diff --git a/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile b/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile index 38e8c8567..88e9c070d 100644 --- a/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile +++ b/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # -# Copyright (C) 2021 ImmortalWrt.org +# Copyright (C) 2022 ImmortalWrt.org include $(TOPDIR)/rules.mk @@ -9,9 +9,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git -PKG_SOURCE_DATE:=2021-06-01 -PKG_SOURCE_VERSION:=7d631e0d5b2d373b54d4533580d08fb9bd2eaad4 -PKG_MIRROR_HASH:=3a4794d1d00890401b032a573fca3121935ea036468a67228f203d68b007d916 +PKG_SOURCE_DATE:=2022-08-01 +PKG_SOURCE_VERSION:=b0c100f1a260d807df450019774993c761beb79d +PKG_MIRROR_HASH:=17723ac8f6ec446c759444ee29ba4fe544cebb3785e26d8e10c91c54b9df3f1a PKG_MAINTAINER:=Tianling Shen @@ -37,6 +37,18 @@ define Package/arm-trusted-firmware-rk3399 VARIANT:=rk3399 endef +define Package/arm-trusted-firmware-rk3568 + $(Package/arm-trusted-firmware-rockchip-vendor) + DEPENDS:=@TARGET_rockchip_armv8 + VARIANT:=rk3568 +endef + +define Package/arm-trusted-firmware-rk3588 + $(Package/arm-trusted-firmware-rockchip-vendor) + DEPENDS:=@TARGET_rockchip_armv8 + VARIANT:=rk3588 +endef + define Build/Configure $(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini $(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini @@ -57,5 +69,13 @@ endef define Package/arm-trusted-firmware-rk3399/install endef +define Package/arm-trusted-firmware-rk3568/install +endef + +define Package/arm-trusted-firmware-rk3588/install +endef + $(eval $(call BuildPackage,arm-trusted-firmware-rk3328)) $(eval $(call BuildPackage,arm-trusted-firmware-rk3399)) +$(eval $(call BuildPackage,arm-trusted-firmware-rk3568)) +$(eval $(call BuildPackage,arm-trusted-firmware-rk3588)) diff --git a/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh b/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh index 6bc9faf33..6dfb89172 100755 --- a/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh +++ b/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh @@ -8,15 +8,23 @@ STAGING_DIR_IMAGE="$4" case "$VARIANT" in "rk3328") - ATF="rk33/rk322xh_bl31_v1.46.elf" - DDR="rk33/rk3328_ddr_333MHz_v1.17.bin" + ATF="rk33/rk322xh_bl31_v1.49.elf" + DDR="rk33/rk3328_ddr_333MHz_v1.19.bin" LOADER="rk33/rk322xh_miniloader_v2.50.bin" ;; "rk3399") ATF="rk33/rk3399_bl31_v1.35.elf" - DDR="rk33/rk3399_ddr_800MHz_v1.25.bin" + DDR="rk33/rk3399_ddr_800MHz_v1.27.bin" LOADER="rk33/rk3399_miniloader_v1.26.bin" ;; +"rk3568") + ATF="rk35/rk3568_bl31_v1.28.elf" + DDR="rk35/rk3568_ddr_1560MHz_v1.13.bin" + ;; +"rk3588") + ATF="rk35/rk3588_bl31_v1.27.elf" + DDR="rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin" + ;; *) echo -e "Not compatible with your platform: $VARIANT." exit 1 @@ -25,15 +33,26 @@ esac set -x if [ "$ACTION" == "build" ]; then - mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" - cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" - "$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini" + case "$VARIANT" in + rk33*) + "$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" + cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" + "$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini" + ;; + esac elif [ "$ACTION" == "install" ]; then mkdir -p "$STAGING_DIR_IMAGE" cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/ - cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/ - cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/ - cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/ + case "$VARIANT" in + rk33*) + cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/ + cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/ + cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/ + ;; + rk35*) + cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/ + ;; + esac else echo -e "Unknown operation: $ACTION." exit 1 diff --git a/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf b/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf new file mode 100644 index 000000000..459d06627 Binary files /dev/null and b/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf differ diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 2e30b87ce..7093fc834 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -1,6 +1,6 @@ # # This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. +# See /LICENSE for more information. # include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk @@ -31,8 +31,7 @@ define U-Boot/nanopi-r2c-rk3328 friendlyarm_nanopi-r2c DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328 PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.46.elf - OF_PLATDATA:=$(1) + ATF:=rk322xh_bl31_v1.49.elf USE_RKBIN:=1 endef @@ -44,32 +43,7 @@ define U-Boot/nanopi-r2s-rk3328 friendlyarm_nanopi-neo3 DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328 PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.46.elf - OF_PLATDATA:=$(1) - USE_RKBIN:=1 -endef - -define U-Boot/orangepi-r1-plus-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=Orange Pi R1 Plus - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus - DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.46.elf - OF_PLATDATA:=$(1) - USE_RKBIN:=1 -endef - -define U-Boot/orangepi-r1-plus-lts-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=Orange Pi R1 Plus LTS - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus-lts - DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.46.elf - OF_PLATDATA:=$(1) + ATF:=rk322xh_bl31_v1.49.elf USE_RKBIN:=1 endef @@ -80,33 +54,12 @@ define U-Boot/doornet1-rk3328 embedfire_doornet1 DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328 PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.46.elf - OF_PLATDATA:=$(1) + ATF:=rk322xh_bl31_v1.49.elf USE_RKBIN:=1 endef # RK3399 boards -define U-Boot/doornet2-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=DoorNet2 - BUILD_DEVICES:= \ - embedfire_doornet2 - DEPENDS:=+PACKAGE_u-boot-doornet2-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf -endef - -define U-Boot/guangmiao-g4c-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=GuangMiao G4C - BUILD_DEVICES:= \ - sharevdi_guangmiao-g4c - DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - define U-Boot/nanopi-r4s-rk3399 BUILD_SUBTARGET:=armv8 NAME:=NanoPi R4S @@ -129,38 +82,72 @@ define U-Boot/nanopi-r4se-rk3399 USE_RKBIN:=1 endef -define U-Boot/rock-pi-4-rk3399 +define U-Boot/doornet2-rk3399 BUILD_SUBTARGET:=armv8 - NAME:=Rock Pi 4 + NAME:=DoorNet2 BUILD_DEVICES:= \ - radxa_rock-pi-4 - DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf + embedfire_doornet2 + DEPENDS:=+PACKAGE_u-boot-doornet2-rk3399:arm-trusted-firmware-rk3399 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3399_bl31_v1.35.elf endef -define U-Boot/rockpro64-rk3399 +# RK3568 boards + +define U-Boot/nanopi-r5s-rk3568 BUILD_SUBTARGET:=armv8 - NAME:=RockPro64 + NAME:=NanoPi R5S BUILD_DEVICES:= \ - pine64_rockpro64 - DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf + friendlyarm_nanopi-r5s + DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3568_bl31_v1.28.elf + DDR:=rk3568_ddr_1560MHz_v1.13.bin +endef + +define U-Boot/mrkaio-m68s-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=Mrkaio M68S + BUILD_DEVICES:= \ + ezpro_mrkaio-m68s + DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3568_bl31_v1.28.elf + DDR:=rk3568_ddr_1560MHz_v1.13.bin +endef + +define U-Boot/opc-h68k-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=OPC-H68K Board + BUILD_DEVICES:= \ + hinlink_opc-h68k + DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3568_bl31_v1.28.elf + DDR:=rk3568_ddr_1560MHz_v1.13.bin +endef + +define U-Boot/station-p2-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=StationP2 + BUILD_DEVICES:= \ + firefly_station-p2 + DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3568_bl31_v1.28.elf + DDR:=rk3568_ddr_1560MHz_v1.13.bin endef UBOOT_TARGETS := \ - doornet2-rk3399 \ - guangmiao-g4c-rk3399 \ - nanopi-r4s-rk3399 \ - nanopi-r4se-rk3399 \ - rock-pi-4-rk3399 \ - rockpro64-rk3399 \ - doornet1-rk3328 \ nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 \ - orangepi-r1-plus-rk3328 \ - orangepi-r1-plus-lts-rk3328 + doornet1-rk3328 \ + nanopi-r4s-rk3399 \ + nanopi-r4se-rk3399 \ + doornet2-rk3399 \ + nanopi-r5s-rk3568 \ + opc-h68k-rk3568 \ + station-p2-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes @@ -170,17 +157,12 @@ UBOOT_MAKE_FLAGS += \ define Build/Configure $(call Build/Configure/U-Boot) -ifneq ($(OF_PLATDATA),) - mkdir -p $(PKG_BUILD_DIR)/tpl/dts - mkdir -p $(PKG_BUILD_DIR)/include/generated - - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h -endif - + $(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config +ifneq ($(DDR),) + $(CP) $(STAGING_DIR_IMAGE)/$(DDR) $(PKG_BUILD_DIR)/ram_init.bin +endif endef define Build/InstallDev diff --git a/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch b/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch index 7a6aea701..4f38e6951 100644 --- a/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch +++ b/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch @@ -17,9 +17,6 @@ Signed-off-by: Marty Jones 9 files changed, 692 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts - create mode 100644 board/radxa/rock-3a-rk3568/Kconfig - create mode 100644 board/radxa/rock-3a-rk3568/Makefile - create mode 100644 board/radxa/rock-3a-rk3568/rock-3a-rk3568.c create mode 100644 configs/rock-3a-rk3568_defconfig create mode 100644 include/configs/rock-3a-rk3568.h @@ -37,7 +34,7 @@ Signed-off-by: Marty Jones rv1108-elgin-r1.dtb \ --- /dev/null +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi -@@ -0,0 +1,25 @@ +@@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd @@ -54,13 +51,12 @@ Signed-off-by: Marty Jones + +&sdmmc0 { + bus-width = <4>; -+ u-boot,dm-spl; + u-boot,spl-fifo-mode; +}; + +&uart2 { -+ clock-frequency = <24000000>; + u-boot,dm-spl; ++ clock-frequency = <24000000>; + status = "okay"; +}; --- /dev/null @@ -591,59 +587,9 @@ Signed-off-by: Marty Jones +&usb_host1_ohci { + status = "okay"; +}; ---- a/arch/arm/mach-rockchip/rk3568/Kconfig -+++ b/arch/arm/mach-rockchip/rk3568/Kconfig -@@ -18,6 +18,11 @@ config TARGET_QUARTZ64_A_RK3566 - help - Quartz64 Model A RK3566 is a development board from Pine64. - -+config TARGET_ROCK_3A_RK3568 -+ bool "ROCK3 Model A RK3568 development board" -+ help -+ ROCK3 Model A RK3568 is a development board from Radxa. -+ - endchoice - - config ROCKCHIP_BOOT_MODE_REG -@@ -35,5 +40,6 @@ config SYS_MALLOC_F_LEN - source "board/rockchip/bpi-r2-pro-rk3568/Kconfig" - source "board/rockchip/evb_rk3568/Kconfig" - source "board/pine64/quartz64-a-rk3566/Kconfig" -+source "board/radxa/rock-3a-rk3568/Kconfig" - - endif ---- /dev/null -+++ b/board/radxa/rock-3a-rk3568/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_ROCK_3A_RK3568 -+ -+config SYS_BOARD -+ default "rock-3a-rk3568" -+ -+config SYS_VENDOR -+ default "radxa" -+ -+config SYS_CONFIG_NAME -+ default "rock-3a-rk3568" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/radxa/rock-3a-rk3568/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += rock-3a-rk3568.o ---- /dev/null -+++ b/board/radxa/rock-3a-rk3568/rock-3a-rk3568.c -@@ -0,0 +1 @@ -+// SPDX-License-Identifier: GPL-2.0+ --- /dev/null +++ b/configs/rock-3a-rk3568_defconfig -@@ -0,0 +1,97 @@ +@@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_ROCKCHIP=y @@ -658,7 +604,7 @@ Signed-off-by: Marty Jones +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_ROCK_3A_RK3568=y ++CONFIG_TARGET_EVB_RK3568=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y @@ -670,6 +616,7 @@ Signed-off-by: Marty Jones +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" +# CONFIG_SYS_DEVICE_NULLDEV is not set ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -741,23 +688,3 @@ Signed-off-by: Marty Jones +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/include/configs/rock-3a-rk3568.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __ROCK_3A_RK3568_H -+#define __ROCK_3A_RK3568_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ -+#endif diff --git a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch b/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch index 47ff38964..b527a261e 100644 --- a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch +++ b/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch @@ -129,7 +129,7 @@ Signed-off-by: Marty Jones + */ --- /dev/null +++ b/configs/nanopi-r5s-rk3568_defconfig -@@ -0,0 +1,97 @@ +@@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_ROCKCHIP=y @@ -149,6 +149,7 @@ Signed-off-by: Marty Jones +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_API=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y @@ -229,7 +230,7 @@ Signed-off-by: Marty Jones +CONFIG_ERRNO_STR=y --- /dev/null +++ b/include/configs/nanopi-r5s-rk3568.h -@@ -0,0 +1,17 @@ +@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __NANOPI_R5S_RK3568_H @@ -243,7 +244,4 @@ Signed-off-by: Marty Jones + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ +#endif diff --git a/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch b/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch new file mode 100644 index 000000000..ff5a97f33 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch @@ -0,0 +1,282 @@ +From cd6a45a41fb2c19884ac87afade87b4d53601929 Mon Sep 17 00:00:00 2001 +From: Tom Rini +Date: Sat, 25 Jun 2022 11:02:31 -0400 +Subject: [PATCH] Convert CONFIG_USB_OHCI_NEW et al to Kconfig + +This converts the following to Kconfig: + CONFIG_SYS_OHCI_SWAP_REG_ACCESS + CONFIG_SYS_USB_OHCI_CPU_INIT + CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS + CONFIG_SYS_USB_OHCI_SLOT_NAME + CONFIG_USB_ATMEL + CONFIG_USB_ATMEL_CLK_SEL_PLLB + CONFIG_USB_ATMEL_CLK_SEL_UPLL + CONFIG_USB_OHCI_LPC32XX + CONFIG_USB_OHCI_NEW + +Signed-off-by: Tom Rini +--- + +diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig +index 4d6d235cb125..c81437300c74 100644 +--- a/configs/evb-rk3328_defconfig ++++ b/configs/evb-rk3328_defconfig +@@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 + CONFIG_USB_DWC2=y + CONFIG_USB_DWC3=y + # CONFIG_USB_DWC3_GADGET is not set +diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig +index 41793ca7e486..15c2e1698c20 100644 +--- a/configs/nanopi-r2s-rk3328_defconfig ++++ b/configs/nanopi-r2s-rk3328_defconfig +@@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 + CONFIG_USB_DWC2=y + CONFIG_USB_DWC3=y + # CONFIG_USB_DWC3_GADGET is not set +diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig +index ab25abc1a031..43b90c7879b7 100644 +--- a/configs/roc-cc-rk3328_defconfig ++++ b/configs/roc-cc-rk3328_defconfig +@@ -108,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 + CONFIG_USB_DWC2=y + CONFIG_USB_DWC3=y + # CONFIG_USB_DWC3_GADGET is not set +diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig +index 1d51a267b93a..7d95e171f7f4 100644 +--- a/configs/rock-pi-e-rk3328_defconfig ++++ b/configs/rock-pi-e-rk3328_defconfig +@@ -109,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 + CONFIG_USB_DWC2=y + CONFIG_USB_DWC3=y + # CONFIG_USB_DWC3_GADGET is not set +diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig +index 640fe558d414..bc333a5e2a6a 100644 +--- a/configs/rock64-rk3328_defconfig ++++ b/configs/rock64-rk3328_defconfig +@@ -106,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 + CONFIG_USB_DWC2=y + CONFIG_USB_DWC3=y + # CONFIG_USB_DWC3_GADGET is not set +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index 78e50dbfbcb7..bb5b2143691d 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -74,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 + CONFIG_USB_DWC3=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index 4d2a5b32e31c..ef28fe6a937a 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -87,6 +87,7 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_KEYBOARD=y +diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig +index 0b82c2fdaf71..31ae9f74e7ac 100644 +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -297,10 +297,17 @@ config USB_EHCI_TXFIFO_THRESH + Enables support for the on-chip EHCI controller on FSL chips. + endif # USB_EHCI_HCD + ++config USB_OHCI_NEW ++ bool ++ ++config SYS_USB_OHCI_CPU_INIT ++ bool ++ + config USB_OHCI_HCD + bool "OHCI HCD (USB 1.1) support" + depends on DM && OF_CONTROL + select USB_HOST ++ select USB_OHCI_NEW + ---help--- + The Open Host Controller Interface (OHCI) is a standard for accessing + USB 1.1 host controller hardware. It does more in hardware than Intel's +@@ -332,6 +339,19 @@ config USB_OHCI_DA8XX + + endif # USB_OHCI_HCD + ++config SYS_USB_OHCI_SLOT_NAME ++ string "Display name for the OHCI controller" ++ depends on USB_OHCI_NEW && !DM_USB ++ ++config SYS_USB_OHCI_MAX_ROOT_PORTS ++ int "Maximal number of ports of the root hub" ++ depends on USB_OHCI_NEW ++ default 1 if ARCH_SUNXI ++ ++config SYS_OHCI_SWAP_REG_ACCESS ++ bool "Perform byte swapping on OHCI controller register accesses" ++ depends on USB_OHCI_NEW ++ + config USB_UHCI_HCD + bool "UHCI HCD (most Intel and VIA) support" + select USB_HOST +@@ -381,3 +401,27 @@ config USB_R8A66597_HCD + ---help--- + This enables support for the on-chip Renesas R8A66597 USB 2.0 + controller, present in various RZ and SH SoCs. ++ ++config USB_ATMEL ++ bool "AT91 OHCI USB support" ++ depends on ARCH_AT91 ++ select SYS_USB_OHCI_CPU_INIT ++ select USB_OHCI_NEW ++ ++choice ++ prompt "Clock for OHCI" ++ depends on USB_ATMEL ++ ++config USB_ATMEL_CLK_SEL_PLLB ++ bool "PLLB" ++ ++config USB_ATMEL_CLK_SEL_UPLL ++ bool "UPLL" ++ ++endchoice ++ ++config USB_OHCI_LPC32XX ++ bool "LPC32xx USB OHCI support" ++ depends on ARCH_LPC32XX ++ select SYS_USB_OHCI_CPU_INIT ++ select USB_OHCI_NEW +diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c +index 8ceabaf45c1b..9b955c1bd678 100644 +--- a/drivers/usb/host/ohci-at91.c ++++ b/drivers/usb/host/ohci-at91.c +@@ -5,9 +5,6 @@ + */ + + #include +- +-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +- + #include + + int usb_cpu_init(void) +@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void) + { + return usb_cpu_stop(); + } +- +-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ +diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c +index 163f0ef17b11..5d23058aaf6a 100644 +--- a/drivers/usb/host/ohci-generic.c ++++ b/drivers/usb/host/ohci-generic.c +@@ -14,10 +14,6 @@ + #include + #include "ohci.h" + +-#if !defined(CONFIG_USB_OHCI_NEW) +-# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW" +-#endif +- + struct generic_ohci { + ohci_t ohci; + struct clk *clocks; /* clock list */ +diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h +index a38cd25eb85f..7699f2e6b15a 100644 +--- a/drivers/usb/host/ohci.h ++++ b/drivers/usb/host/ohci.h +@@ -151,7 +151,7 @@ struct ohci_hcca { + * Maximum number of root hub ports. + */ + #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS +-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + #endif + + /* +diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h +index 492b7b4df128..b7e850370b31 100644 +--- a/include/configs/evb_rk3399.h ++++ b/include/configs/evb_rk3399.h +@@ -15,7 +15,4 @@ + + #define SDRAM_BANK_SIZE (2UL << 30) + +-#define CONFIG_USB_OHCI_NEW +-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +- + #endif +diff --git a/include/configs/gru.h b/include/configs/gru.h +index b1084bb21d4d..be2dc79968c0 100644 +--- a/include/configs/gru.h ++++ b/include/configs/gru.h +@@ -13,7 +13,4 @@ + + #include + +-#define CONFIG_USB_OHCI_NEW +-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +- + #endif +diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h +index 90183579202d..165b78ff3309 100644 +--- a/include/configs/rk3328_common.h ++++ b/include/configs/rk3328_common.h +@@ -30,8 +30,4 @@ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +-/* rockchip ohci host driver */ +-#define CONFIG_USB_OHCI_NEW +-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +- + #endif +diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h +index 2edad710284f..6099d2fa55a6 100644 +--- a/include/configs/rock960_rk3399.h ++++ b/include/configs/rock960_rk3399.h +@@ -14,7 +14,4 @@ + #include + + #define SDRAM_BANK_SIZE (2UL << 30) +- +-#define CONFIG_USB_OHCI_NEW +-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif +diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h +index 903e9df527c1..9195b9b99e41 100644 +--- a/include/configs/rockpro64_rk3399.h ++++ b/include/configs/rockpro64_rk3399.h +@@ -14,7 +14,4 @@ + #include + + #define SDRAM_BANK_SIZE (2UL << 30) +- +-#define CONFIG_USB_OHCI_NEW +-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif diff --git a/package/boot/uboot-rockchip/patches/103-tools-disable-TOOLS_LIBCRYPTO.patch b/package/boot/uboot-rockchip/patches/103-tools-disable-TOOLS_LIBCRYPTO.patch deleted file mode 100644 index a65ead68f..000000000 --- a/package/boot/uboot-rockchip/patches/103-tools-disable-TOOLS_LIBCRYPTO.patch +++ /dev/null @@ -1,21 +0,0 @@ -From d585719ad3f737ca5e5186fe55be964340ecfcc7 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Mon, 4 Oct 2021 16:46:32 -0400 -Subject: [PATCH] tools:disable TOOLS_LIBCRYPTO - -Signed-off-by: Marty Jones ---- - tools/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/tools/Kconfig -+++ b/tools/Kconfig -@@ -16,7 +16,7 @@ config TOOLS_CRC32 - - config TOOLS_LIBCRYPTO - bool "Use OpenSSL's libcrypto library for host tools" -- default y -+ default n - help - Cryptographic signature, verification, and encryption of images is - provided by host tools using OpenSSL's libcrypto. Select 'n' here if diff --git a/package/boot/uboot-rockchip/patches/201-scripts-remove-dependency-on-swig.patch b/package/boot/uboot-rockchip/patches/201-scripts-remove-dependency-on-swig.patch deleted file mode 100644 index 050558938..000000000 --- a/package/boot/uboot-rockchip/patches/201-scripts-remove-dependency-on-swig.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 13 Jul 2020 23:37:37 +0200 -Subject: [PATCH] scripts: remove dependency on swig - -Don't build the libfdt tool, as it has a dependency on swig (which -OpenWrt does not ship). - -This requires more hacks, as of-platdata generation does not work -without it. - -Signed-off-by: David Bauer ---- - scripts/dtc/Makefile | 2 -- - 1 file changed, 2 deletions(-) - ---- a/scripts/dtc/Makefile -+++ b/scripts/dtc/Makefile -@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src) - # dependencies on generated files need to be listed explicitly - $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h - --# Added for U-Boot --subdir-$(CONFIG_PYLIBFDT) += pylibfdt diff --git a/package/boot/uboot-rockchip/patches/202-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/202-spl-remove-dtoc-of-pdata-generation.patch deleted file mode 100644 index 14bcbfb63..000000000 --- a/package/boot/uboot-rockchip/patches/202-spl-remove-dtoc-of-pdata-generation.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Tue, 14 Jul 2020 22:44:22 +0200 -Subject: [PATCH] spl: remove dtoc of-pdata generation - -Remove the dtoc of-pdata generation. This generation is dependant on -libpython-dev. As OpenWrt does not ship with this dependency, use -pre-generated pdata files and remove the generation from the -build-process. - -This only affects RK3328 boards. - -Signed-off-by: David Bauer ---- - scripts/Makefile.spl | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/scripts/Makefile.spl -+++ b/scripts/Makefile.spl -@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) - @# of OF_PLATDATA_INST and this might change between builds. Leaving old - @# ones around is confusing and it is possible that switching the - @# setting again will use the old one instead of regenerating it. -- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) -- $(call if_changed,dtoc) - - ifdef CONFIG_SAMSUNG - ifdef CONFIG_VAR_SIZE_SPL diff --git a/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch b/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch deleted file mode 100644 index fae269b71..000000000 --- a/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch +++ /dev/null @@ -1,740 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-ficus.dtb \ - rk3399-firefly.dtb \ - rk3399-gru-bob.dtb \ -+ rk3399-guangmiao-g4c.dtb \ - rk3399-gru-kevin.dtb \ - rk3399-khadas-edge.dtb \ - rk3399-khadas-edge-captain.dtb \ ---- /dev/null -+++ b/configs/guangmiao-g4c-rk3399_defconfig -@@ -0,0 +1,57 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/arch/arm/dts/rk3399-guangmiao-g4c-u-boot.dtsi -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+}; -+ -+&sdmmc { -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; -+}; -+ -+&vdd_log { -+ regulator-init-microvolt = <950000>; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3399-guangmiao-g4c.dts -@@ -0,0 +1,646 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "SHAREVDI GuangMiao G4C"; -+ compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399"; -+ -+ /delete-node/ display-subsystem; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc_sys"; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_0v9: vcc-0v9 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcc_0v9"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc5v0_host0: vcc5v0-host0 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc5v0_host0"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-name = "vdd_log"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&reset_button_pin>; -+ -+ reset { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>; -+ -+ lan_led: led-lan { -+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ status_led: led-status { -+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ label = "green:status"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc3v3_s3>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ reg = <1>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <30000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ vcc8-supply = <&vcc_3v0>; -+ vcc9-supply = <&vcc_sys>; -+ vcc10-supply = <&vcc_sys>; -+ vcc11-supply = <&vcc_sys>; -+ vcc12-supply = <&vcc_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_vldo1: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_vldo1"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_vldo2: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_vldo2"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc3v0_sd: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_clkreqnb_cpm>; -+ vpcie0v9-supply = <&vcc_0v9>; -+ vpcie1v8-supply = <&vcca_1v8>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ status_led_pin: status-led-pin { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gmac { -+ phy_intb: phy-intb { -+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_pmeb: phy-pmeb { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_rstb: phy-rstb { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "active"; -+ pinctrl-0 = <&pwm2_pin_pull_down>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; diff --git a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch b/package/boot/uboot-rockchip/patches/301-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch similarity index 95% rename from package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch rename to package/boot/uboot-rockchip/patches/301-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch index a4214f1ca..e5e5b93ec 100644 --- a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch +++ b/package/boot/uboot-rockchip/patches/301-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch @@ -1,549 +1,550 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - rk3308-roc-cc.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ -+ rk3328-doornet1.dtb \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-roc-cc.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3328-doornet1-u-boot.dtsi -@@ -0,0 +1,46 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * Copyright (c) 2021 EmbedFire -+ */ -+ -+#include "rk3328-u-boot.dtsi" -+#include "rk3328-sdram-ddr4-666.dtsi" -+/ { -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &emmc; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; -+ }; -+}; -+ -+&gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&pinctrl { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc0m1_pin { -+ u-boot,dm-spl; -+}; -+ -+&pcfg_pull_up_4ma { -+ u-boot,dm-spl; -+}; -+ -+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -+&vcc_sd { -+ u-boot,dm-spl; -+}; -+ -+&gmac2io { -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3328-doornet1.dts -@@ -0,0 +1,385 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 David Bauer -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet1"; -+ compatible = "embedfire,doornet1", "rockchip,rk3328"; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&reset_button_pin>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ lan_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:wan"; -+ }; -+ }; -+ -+ vcc_io_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_io_sdio"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ startup-delay-us = <2000>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211f>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io_33>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ rx_delay = <0x54>; -+ snps,aal; -+ tx_delay = <0x20>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211f: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vdd_5v>; -+ vcc2-supply = <&vdd_5v>; -+ vcc3-supply = <&vdd_5v>; -+ vcc4-supply = <&vdd_5v>; -+ vcc5-supply = <&vcc_io_33>; -+ vcc6-supply = <&vdd_5v>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io_33: DCDC_REG4 { -+ regulator-name = "vcc_io_33"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io_33>; -+ vccio1-supply = <&vcc_io_33>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io_sdio>; -+ vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io_33>; -+ vccio6-supply = <&vcc_io_33>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ button { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sd { -+ sdio_vcc_pin: sdio-vcc-pin { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io_33>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ ---- /dev/null -+++ b/configs/doornet1-rk3328_defconfig -@@ -0,0 +1,99 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-doornet1.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-doornet1" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + rk3308-roc-cc.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ ++ rk3328-doornet1.dtb \ + rk3328-evb.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-roc-cc.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3328-doornet1-u-boot.dtsi +@@ -0,0 +1,46 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ * Copyright (c) 2021 EmbedFire ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr4-666.dtsi" ++/ { ++ aliases { ++ mmc0 = &sdmmc; ++ mmc1 = &emmc; ++ }; ++ ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&gpio0 { ++ u-boot,dm-spl; ++}; ++ ++&pinctrl { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc0m1_pin { ++ u-boot,dm-spl; ++}; ++ ++&pcfg_pull_up_4ma { ++ u-boot,dm-spl; ++}; ++ ++/* Need this and all the pinctrl/gpio stuff above to set pinmux */ ++&vcc_sd { ++ u-boot,dm-spl; ++}; ++ ++&gmac2io { ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++}; ++ +--- /dev/null ++++ b/arch/arm/dts/rk3328-doornet1.dts +@@ -0,0 +1,385 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "EmbedFire DoorNet1"; ++ compatible = "embedfire,doornet1", "rockchip,rk3328"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; ++ pinctrl-names = "default"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ lan_led: led-0 { ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "doornet1:green:lan"; ++ }; ++ ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "doornet1:red:sys"; ++ }; ++ ++ wan_led: led-2 { ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "doornet1:green:wan"; ++ }; ++ }; ++ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211f>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io_33>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ rx_delay = <0x54>; ++ snps,aal; ++ tx_delay = <0x20>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211f: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c916", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io_sdio>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdio_vcc_pin: sdio-vcc-pin { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_io_sdio>; ++ status = "okay"; ++}; ++ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <150000000>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io_33>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ +--- /dev/null ++++ b/configs/doornet1-rk3328_defconfig +@@ -0,0 +1,100 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYSINFO=y ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-doornet1.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-doornet1" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch similarity index 98% rename from package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch rename to package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch index f2cb109a4..d7940c960 100644 --- a/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch +++ b/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch @@ -71,7 +71,7 @@ M: Chen-Yu Tsai --- /dev/null +++ b/configs/orangepi-r1-plus-rk3328_defconfig -@@ -0,0 +1,99 @@ +@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 @@ -163,6 +163,7 @@ +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set diff --git a/package/boot/uboot-rockchip/patches/306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch b/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch similarity index 98% rename from package/boot/uboot-rockchip/patches/306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch rename to package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch index abc5bdc65..0f3f17f7b 100644 --- a/package/boot/uboot-rockchip/patches/306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch +++ b/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch @@ -41,7 +41,7 @@ new file mode 100644 index 00000000..3cb3b5c3 --- /dev/null +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig -@@ -0,0 +1,99 @@ +@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 @@ -133,6 +133,7 @@ index 00000000..3cb3b5c3 +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set diff --git a/package/boot/uboot-rockchip/patches/305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch similarity index 98% rename from package/boot/uboot-rockchip/patches/305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch rename to package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index da4a1005b..39022fddf 100644 --- a/package/boot/uboot-rockchip/patches/305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -81,7 +81,7 @@ new file mode 100644 index 0000000000..7bc7a3274f --- /dev/null +++ b/configs/nanopi-r2c-rk3328_defconfig -@@ -0,0 +1,99 @@ +@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 @@ -173,6 +173,7 @@ index 0000000000..7bc7a3274f +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set diff --git a/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 000000000..ca6f80958 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,113 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -157,6 +157,7 @@ + rk3399-nanopi-m4b.dtb \ + rk3399-nanopi-neo4.dtb \ + rk3399-nanopi-r4s.dtb \ ++ rk3399-nanopi-r4se.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4se.dts +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * FriendlyElec NanoPC-T4 board device tree source ++ * ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2018 Collabora Ltd. ++ * ++ * Copyright (c) 2020 Jensen Huang ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi-r4s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R4SE"; ++ compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++&sdmmc { ++ pinctrl-0 = <&sdmmc_cd>; ++}; +--- /dev/null ++++ b/configs/nanopi-r4se-rk3399_defconfig +@@ -0,0 +1,65 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch similarity index 95% rename from package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch rename to package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch index e5ac06111..f5daeeba0 100644 --- a/package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch +++ b/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch @@ -1,985 +1,985 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -121,6 +121,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \ - rk3368-px5-evb.dtb \ - - dtb-$(CONFIG_ROCKCHIP_RK3399) += \ -+ rk3399-doornet2.dtb \ - rk3399-evb.dtb \ - rk3399-ficus.dtb \ - rk3399-firefly.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Jagan Teki -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" -+#include "rk3399-sdram-ddr3-1866.dtsi" -+ -+/{ -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; -+ }; -+}; -+ -+&sdmmc { -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2.dts -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3399-doornet2.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet2"; -+ compatible = "embedfire,doornet2", "rockchip,rk3399"; -+ -+ /delete-node/ display-subsystem; -+ -+ gpio-leds { -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ -+ /delete-node/ status; -+ -+ lan_led: led-lan { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ sys_led: led-sys { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "red:sys"; -+ default-state = "on"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+ -+ gpio-keys { -+ pinctrl-0 = <&reset_button_pin>; -+ -+ /delete-node/ power; -+ -+ reset { -+ debounce-interval = <50>; -+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ }; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ status = "disabled"; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ /delete-node/ leds-gpio; -+ -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rockchip-key { -+ /delete-node/ power-key; -+ -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&sdhci { -+ status = "okay"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&uart0 { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2.dtsi -@@ -0,0 +1,750 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc5v0_sys"; -+ vin-supply = <&vdd_5v>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_s3"; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* -+ * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only -+ * drives the enable pin, but we can't quite model that. -+ */ -+ vcca0v9_s3: vcca0v9-s3 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcca0v9_s3"; -+ vin-supply = <&vcc1v8_s3>; -+ }; -+ -+ /* As above, actually supplied by vcc3v3_sys */ -+ vcca1v8_s3: vcca1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_s3"; -+ vin-supply = <&vcc1v8_s3>; -+ }; -+ -+ vbus_typec: vbus-typec { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vbus_typec"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_key>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&leds_gpio>; -+ -+ status { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; -+ phy-handle = <&rtl8211f>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc3v3_s3>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211f: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <30000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c7>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "xin32k", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_cam: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_cam"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_touch"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmupll: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_pmupll"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <3000000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcca3v0_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <200000>; -+ i2c-scl-rising-time-ns = <150>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ vbus-supply = <&vbus_typec>; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <2>; -+ num-lanes = <2>; -+ vpcie0v9-supply = <&vcca0v9_s3>; -+ vpcie1v8-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-leds { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ phy { -+ phy_intb: phy-intb { -+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_rstb: phy-rstb { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ power_key: power-key { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_reg_on_h: wifi-reg_on-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "active"; -+ pinctrl-0 = <&pwm2_pin_pull_down>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <4000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -+ ---- /dev/null -+++ b/configs/doornet2-rk3399_defconfig -@@ -0,0 +1,66 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_TARGET_DOORNET2_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-doornet2" -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-doornet2.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -+ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -121,6 +121,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \ + rk3368-px5-evb.dtb \ + + dtb-$(CONFIG_ROCKCHIP_RK3399) += \ ++ rk3399-doornet2.dtb \ + rk3399-evb.dtb \ + rk3399-ficus.dtb \ + rk3399-firefly.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3399-doornet2-u-boot.dtsi +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" ++#include "rk3399-sdram-ddr3-1866.dtsi" ++ ++/{ ++ aliases { ++ mmc0 = &sdmmc; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; ++ }; ++}; ++ ++&sdmmc { ++ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; ++}; ++ +--- /dev/null ++++ b/arch/arm/dts/rk3399-doornet2.dts +@@ -0,0 +1,122 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include "rk3399-doornet2.dtsi" ++ ++/ { ++ model = "EmbedFire DoorNet2"; ++ compatible = "embedfire,doornet2", "rockchip,rk3399"; ++ ++ /delete-node/ display-subsystem; ++ ++ gpio-leds { ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ ++ /delete-node/ status; ++ ++ lan_led: led-lan { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "green:lan"; ++ }; ++ ++ sys_led: led-sys { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "red:sys"; ++ default-state = "on"; ++ }; ++ ++ wan_led: led-wan { ++ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; ++ }; ++ }; ++ ++ gpio-keys { ++ pinctrl-0 = <&reset_button_pin>; ++ ++ /delete-node/ power; ++ ++ reset { ++ debounce-interval = <50>; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ max-link-speed = <1>; ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ /delete-node/ leds-gpio; ++ ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rockchip-key { ++ /delete-node/ power-key; ++ ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ status = "okay"; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&u2phy1_host { ++ status = "disabled"; ++}; ++ ++&uart0 { ++ status = "disabled"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; ++ +--- /dev/null ++++ b/arch/arm/dts/rk3399-doornet2.dtsi +@@ -0,0 +1,750 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++ ++/dts-v1/; ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_sys"; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_sys"; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_s3"; ++ vin-supply = <&vcc_1v8>; ++ }; ++ ++ vcc3v0_sd: vcc3v0-sd { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_pwr_h>; ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc3v0_sd"; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ /* ++ * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only ++ * drives the enable pin, but we can't quite model that. ++ */ ++ vcca0v9_s3: vcca0v9-s3 { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcca0v9_s3"; ++ vin-supply = <&vcc1v8_s3>; ++ }; ++ ++ /* As above, actually supplied by vcc3v3_sys */ ++ vcca1v8_s3: vcca1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_s3"; ++ vin-supply = <&vcc1v8_s3>; ++ }; ++ ++ vbus_typec: vbus-typec { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vbus_typec"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_key>; ++ ++ power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "GPIO Key Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_gpio>; ++ ++ status { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "status_led"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clock-parents = <&clkin_gmac>; ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ clock_in_out = "input"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; ++ phy-handle = <&rtl8211f>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc3v3_s3>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211f: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c916", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <30000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c7>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpu_b_sleep>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-ramp-delay = <1000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpu_sleep>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vdd_gpu"; ++ regulator-ramp-delay = <1000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ clock-output-names = "xin32k", "rtc_clko_wifi"; ++ #clock-cells = <1>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_3v0>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-name = "vdd_center"; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-name = "vdd_cpu_l"; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_ddr"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_cam: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_cam"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc3v0_touch"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmupll: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_pmupll"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <3000000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_sdio"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcca3v0_codec"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc_1v5"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_codec"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_3v0"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ clock-frequency = <200000>; ++ i2c-scl-rising-time-ns = <150>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ vbus-supply = <&vbus_typec>; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc_1v8>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vcc_sdio>; ++ gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; ++ assigned-clock-rates = <100000000>; ++ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; ++ max-link-speed = <2>; ++ num-lanes = <2>; ++ vpcie0v9-supply = <&vcca0v9_s3>; ++ vpcie1v8-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ phy { ++ phy_intb: phy-intb { ++ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ phy_rstb: phy-rstb { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ cpu_b_sleep: cpu-b-sleep { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ gpu_sleep: gpu-sleep { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ power_key: power-key { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio { ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_reg_on_h: bt-reg-on-h { ++ /* external pullup to VCC1V8_PMUPLL */ ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_reg_on_h: wifi-reg_on-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc { ++ sdmmc0_det_l: sdmmc0-det-l { ++ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "active"; ++ pinctrl-0 = <&pwm2_pin_pull_down>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v0_sd>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ clocks = <&rk808 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ max-speed = <4000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; ++ +--- /dev/null ++++ b/configs/doornet2-rk3399_defconfig +@@ -0,0 +1,66 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-doornet2" ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-doornet2.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y ++ diff --git a/package/boot/uboot-rockchip/patches/307-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch b/package/boot/uboot-rockchip/patches/307-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch new file mode 100644 index 000000000..f780ecb67 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/307-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch @@ -0,0 +1,406 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-bpi-r2-pro.dtb \ + rk3568-evb.dtb \ ++ rk3568-mrkaio-m68s.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3566-quartz64-a.dtb \ + rk3568-rock-3a.dtb +--- /dev/null ++++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3568-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ u-boot,spl-fifo-mode; ++}; ++ ++&uart2 { ++ u-boot,dm-spl; ++ clock-frequency = <24000000>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts +@@ -0,0 +1,268 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3568-evb.dts" ++ ++/ { ++ model = "EZPRO Mrkaio M68S"; ++ compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568"; ++ ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/configs/mrkaio-m68s-rk3568_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_API=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb" ++# CONFIG_SYS_DEVICE_NULLDEV is not set ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SEPARATE_BSS=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_LOAD_IMAGE_V2=y ++CONFIG_CMD_BIND=y ++CONFIG_CMD_CLK=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_ROCKCHIP_GPIO_V2=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ROCKCHIP_USB2_PHY=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_LAN75XX=y ++CONFIG_USB_ETHER_LAN78XX=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/308-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch b/package/boot/uboot-rockchip/patches/308-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch new file mode 100644 index 000000000..69a685d34 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/308-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch @@ -0,0 +1,415 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-bpi-r2-pro.dtb \ + rk3568-evb.dtb \ ++ rk3568-opc-h68k.dtb \ + rk3568-mrkaio-m68s.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3566-quartz64-a.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3568-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ u-boot,spl-fifo-mode; ++}; ++ ++&uart2 { ++ u-boot,dm-spl; ++ clock-frequency = <24000000>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-opc-h68k.dts +@@ -0,0 +1,277 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3568-evb.dts" ++ ++/ { ++ model = "HINLINK OPC-H68K Board"; ++ compatible = "hinlink,opc-h68k", "rockchip,rk3568"; ++ ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; ++ rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ codec { ++ mic-in-differential; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/configs/opc-h68k-rk3568_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_API=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb" ++# CONFIG_SYS_DEVICE_NULLDEV is not set ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SEPARATE_BSS=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_LOAD_IMAGE_V2=y ++CONFIG_CMD_BIND=y ++CONFIG_CMD_CLK=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_ROCKCHIP_GPIO_V2=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ROCKCHIP_USB2_PHY=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_LAN75XX=y ++CONFIG_USB_ETHER_LAN78XX=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/309-rockchip-rk3568-Add-support-for-Station-P2.patch b/package/boot/uboot-rockchip/patches/309-rockchip-rk3568-Add-support-for-Station-P2.patch new file mode 100644 index 000000000..3df47445f --- /dev/null +++ b/package/boot/uboot-rockchip/patches/309-rockchip-rk3568-Add-support-for-Station-P2.patch @@ -0,0 +1,77 @@ +From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001 +From: huangjf +Date: Thu, 7 Apr 2022 16:22:56 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for Station P2 + +--- + configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + create mode 100644 configs/station-p2-rk3568_defconfig + +diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig +new file mode 100644 +index 0000000000..435be99edf +--- /dev/null ++++ b/configs/station-p2-rk3568_defconfig +@@ -0,0 +1,59 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SEPARATE_BSS=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++# CONFIG_CMD_SETEXPR is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_ERRNO_STR=y +-- +2.20.1 diff --git a/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch b/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch similarity index 95% rename from package/boot/uboot-rockchip/patches/307-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch rename to package/boot/uboot-rockchip/patches/310-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch index 4b74d36e2..13d064ce3 100644 --- a/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch +++ b/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch @@ -1,696 +1,696 @@ ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -109,6 +109,21 @@ config TARGET_ROC_PC_RK3399 - * wide voltage input(5V-15V), dual cell battery - * Wifi/BT accessible via expansion board M.2 - -+config TARGET_DOORNET2_RK3399 -+ bool "EmbedFire DoorNet2 board" -+ help -+ DoorNet2 is SBC produced by EmbedFire. Key features: -+ -+ * Rockchip RK3399 -+ * 1-4GB DDR3 or LPDDR4 -+ * SD card slot and 8-32GB eMMC -+ * Gigabit ethernet -+ * PCIe -+ * USB 3.0, 2.0 -+ * USB Type C power -+ * GPIO expansion ports -+ * USB 2.0 Wifi module -+ - endchoice - - config ROCKCHIP_BOOT_MODE_REG -@@ -151,6 +166,7 @@ config SYS_BOOTCOUNT_ADDR - - endif # BOOTCOUNT_LIMIT - -+source "board/embedfire/doornet2/Kconfig" - source "board/firefly/roc-pc-rk3399/Kconfig" - source "board/google/gru/Kconfig" - source "board/pine64/pinebook-pro-rk3399/Kconfig" ---- /dev/null -+++ b/board/embedfire/doornet2/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_DOORNET2_RK3399 -+ -+config SYS_BOARD -+ default "doornet2" -+ -+config SYS_VENDOR -+ default "embedfire" -+ -+config SYS_CONFIG_NAME -+ default "doornet2" -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/embedfire/doornet2/Makefile -@@ -0,0 +1,6 @@ -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += doornet2.o hwrev.o -+ ---- /dev/null -+++ b/board/embedfire/doornet2/doornet2.c -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "hwrev.h" -+ -+#ifdef CONFIG_MISC_INIT_R -+static void setup_iodomain(void) -+{ -+ struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ -+ /* BT565 and AUDIO is in 1.8v domain */ -+ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1)); -+} -+ -+static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr) -+{ -+ struct udevice *i2c_dev; -+ int ret; -+ -+ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */ -+ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev); -+ if (!ret) -+ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6); -+ -+ return ret; -+} -+ -+static void setup_macaddr(void) -+{ -+#if CONFIG_IS_ENABLED(CMD_NET) -+ int ret; -+ const char *cpuid = env_get("cpuid#"); -+ u8 hash[SHA256_SUM_LEN]; -+ int size = sizeof(hash); -+ u8 mac_addr[6]; -+ int from_eeprom = 0; -+ int lockdown = 0; -+ -+#ifndef CONFIG_ENV_IS_NOWHERE -+ lockdown = env_get_yesno("lockdown") == 1; -+#endif -+ if (lockdown && env_get("ethaddr")) -+ return; -+ -+ ret = mac_read_from_generic_eeprom(mac_addr); -+ if (!ret && is_valid_ethaddr(mac_addr)) { -+ eth_env_set_enetaddr("ethaddr", mac_addr); -+ from_eeprom = 1; -+ } -+ -+ if (!cpuid) { -+ debug("%s: could not retrieve 'cpuid#'\n", __func__); -+ return; -+ } -+ -+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); -+ if (ret) { -+ debug("%s: failed to calculate SHA256\n", __func__); -+ return; -+ } -+ -+ /* Copy 6 bytes of the hash to base the MAC address on */ -+ memcpy(mac_addr, hash, 6); -+ -+ /* Make this a valid MAC address and set it */ -+ mac_addr[0] &= 0xfe; /* clear multicast bit */ -+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ -+ -+ if (from_eeprom) { -+ eth_env_set_enetaddr("eth1addr", mac_addr); -+ } else { -+ eth_env_set_enetaddr("ethaddr", mac_addr); -+ -+ if (lockdown && env_get("eth1addr")) -+ return; -+ -+ /* Ugly, copy another 4 bytes to generate a similar address */ -+ memcpy(mac_addr + 2, hash + 8, 4); -+ if (!memcmp(hash + 2, hash + 8, 4)) -+ mac_addr[5] ^= 0xff; -+ -+ eth_env_set_enetaddr("eth1addr", mac_addr); -+ } -+#endif -+ -+ return; -+} -+ -+int misc_init_r(void) -+{ -+ const u32 cpuid_offset = 0x7; -+ const u32 cpuid_length = 0x10; -+ u8 cpuid[cpuid_length]; -+ int ret; -+ -+ setup_iodomain(); -+ -+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); -+ if (ret) -+ return ret; -+ -+ ret = rockchip_cpuid_set(cpuid, cpuid_length); -+ if (ret) -+ return ret; -+ -+ setup_macaddr(); -+ bd_hwrev_init(); -+ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_SERIAL_TAG -+void get_board_serial(struct tag_serialnr *serialnr) -+{ -+ char *serial_string; -+ u64 serial = 0; -+ -+ serial_string = env_get("serial#"); -+ -+ if (serial_string) -+ serial = simple_strtoull(serial_string, NULL, 16); -+ -+ serialnr->high = (u32)(serial >> 32); -+ serialnr->low = (u32)(serial & 0xffffffff); -+} -+#endif -+ ---- /dev/null -+++ b/board/embedfire/doornet2/hwrev.c -@@ -0,0 +1,171 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * ID info: -+ * ID : Volts : ADC value : Bucket -+ * == ===== ========= =========== -+ * 0 : 0.102V: 58 : 0 - 81 -+ * 1 : 0.211V: 120 : 82 - 150 -+ * 2 : 0.319V: 181 : 151 - 211 -+ * 3 : 0.427V: 242 : 212 - 274 -+ * 4 : 0.542V: 307 : 275 - 342 -+ * 5 : 0.666V: 378 : 343 - 411 -+ * 6 : 0.781V: 444 : 412 - 477 -+ * 7 : 0.900V: 511 : 478 - 545 -+ * 8 : 1.023V: 581 : 546 - 613 -+ * 9 : 1.137V: 646 : 614 - 675 -+ * 10 : 1.240V: 704 : 676 - 733 -+ * 11 : 1.343V: 763 : 734 - 795 -+ * 12 : 1.457V: 828 : 796 - 861 -+ * 13 : 1.576V: 895 : 862 - 925 -+ * 14 : 1.684V: 956 : 926 - 989 -+ * 15 : 1.800V: 1023 : 990 - 1023 -+ */ -+static const int id_readings[] = { -+ 81, 150, 211, 274, 342, 411, 477, 545, -+ 613, 675, 733, 795, 861, 925, 989, 1023 -+}; -+ -+static int cached_board_id = -1; -+ -+#define SARADC_BASE 0xFF100000 -+#define SARADC_DATA (SARADC_BASE + 0) -+#define SARADC_CTRL (SARADC_BASE + 8) -+ -+static u32 get_saradc_value(int chn) -+{ -+ int timeout = 0; -+ u32 adc_value = 0; -+ -+ writel(0, SARADC_CTRL); -+ udelay(2); -+ -+ writel(0x28 | chn, SARADC_CTRL); -+ udelay(50); -+ -+ timeout = 0; -+ do { -+ if (readl(SARADC_CTRL) & 0x40) { -+ adc_value = readl(SARADC_DATA) & 0x3FF; -+ goto stop_adc; -+ } -+ -+ udelay(10); -+ } while (timeout++ < 100); -+ -+stop_adc: -+ writel(0, SARADC_CTRL); -+ -+ return adc_value; -+} -+ -+static uint32_t get_adc_index(int chn) -+{ -+ int i; -+ int adc_reading; -+ -+ if (cached_board_id != -1) -+ return cached_board_id; -+ -+ adc_reading = get_saradc_value(chn); -+ for (i = 0; i < ARRAY_SIZE(id_readings); i++) { -+ if (adc_reading <= id_readings[i]) { -+ debug("ADC reading %d, ID %d\n", adc_reading, i); -+ cached_board_id = i; -+ return i; -+ } -+ } -+ -+ /* should die for impossible value */ -+ return 0; -+} -+ -+/* -+ * Extended by ADC_IN4 -+ * 0x06 - SOC-RK3399 -+ * 0x09 - DoorNet2 DDR3 -+ * 0x0a - DoorNet2 LPDDR4 -+ */ -+static int pcb_rev = -1; -+ -+void bd_hwrev_init(void) -+{ -+#define GPIO4_BASE 0xff790000 -+ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE; -+ -+#ifdef CONFIG_SPL_BUILD -+ struct udevice *dev; -+ -+ if (uclass_get_device_by_driver(UCLASS_CLK, -+ DM_DRIVER_GET(clk_rk3399), &dev)) -+ return; -+#endif -+ -+ if (pcb_rev >= 0) -+ return; -+ -+ /* D1, D0: input mode */ -+ clrbits_le32(®s->swport_ddr, (0x3 << 24)); -+ pcb_rev = (readl(®s->ext_port) >> 24) & 0x3; -+ -+ if (pcb_rev == 0x3) { -+ /* Revision group A: 0x04 ~ 0x13 */ -+ pcb_rev = 0x4 + get_adc_index(4); -+ -+ } else if (pcb_rev == 0x1) { -+ int idx = get_adc_index(4); -+ -+ /* Revision group B: 0x21 ~ 0x2f */ -+ if (idx > 0) { -+ pcb_rev = 0x20 + idx; -+ } -+ } -+} -+ -+#ifdef CONFIG_SPL_BUILD -+static struct board_ddrtype { -+ int rev; -+ const char *type; -+} ddrtypes[] = { -+ { 0x00, "lpddr3-samsung-4GB-1866" }, -+ { 0x01, "lpddr3-samsung-4GB-1866" }, -+ { 0x04, "ddr3-1866" }, -+ { 0x06, "ddr3-1866" }, -+ { 0x07, "lpddr4-100" }, -+ { 0x09, "ddr3-1866" }, -+ { 0x0a, "lpddr4-100" }, -+ { 0x21, "lpddr4-100" }, -+ { 0x22, "ddr3-1866" }, -+}; -+ -+const char *rk3399_get_ddrtype(void) { -+ int i; -+ -+ bd_hwrev_init(); -+ printf("Board: rev%02x\n", pcb_rev); -+ -+ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) { -+ if (ddrtypes[i].rev == pcb_rev) -+ return ddrtypes[i].type; -+ } -+ -+ /* fallback to first subnode (ie, first included dtsi) */ -+ return NULL; -+} -+#endif -+ -+/* To override __weak symbols */ -+u32 get_board_rev(void) -+{ -+ return pcb_rev; -+} -+ -+ ---- /dev/null -+++ b/board/embedfire/doornet2/MAINTAINERS -@@ -0,0 +1,5 @@ -+DoorNet2 Series -+M: embedfire -+S: Maintained -+F: board/embedfire/doornet2/ -+F: include/configs/doornet2.h ---- /dev/null -+++ b/board/embedfire/doornet2/hwrev.h -@@ -0,0 +1,25 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, you can access it online at -+ * http://www.gnu.org/licenses/gpl-2.0.html. -+ */ -+ -+#ifndef __BD_HW_REV_H__ -+#define __BD_HW_REV_H__ -+ -+extern void bd_hwrev_config_gpio(void); -+extern void bd_hwrev_init(void); -+extern u32 get_board_rev(void); -+ -+#endif /* __BD_HW_REV_H__ */ -+ ---- a/drivers/clk/rockchip/clk_rk3399.c -+++ b/drivers/clk/rockchip/clk_rk3399.c -@@ -1372,6 +1372,8 @@ static void rkclk_init(struct rockchip_c - pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | - hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | - HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); -+ -+ rk3399_saradc_set_clk(cru, 1000000); - } - - static int rk3399_clk_probe(struct udevice *dev) ---- /dev/null -+++ b/include/configs/doornet2.h -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd -+ */ -+ -+#ifndef __CONFIG_DOORNET2_H__ -+#define __CONFIG_DOORNET2_H__ -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdin=serial,usbkbd\0" \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#include -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#define CONFIG_SERIAL_TAG -+#define CONFIG_REVISION_TAG -+ -+#endif -+ ---- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi -+++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi -@@ -4,7 +4,9 @@ - */ - - &dmc { -- rockchip,sdram-params = < -+ ddr3-1333 { -+ u-boot,dm-pre-reloc; -+ rockchip,sdram-params = < - 0x1 - 0xa - 0x3 -@@ -1536,5 +1538,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; -- ---- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi -+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi -@@ -4,7 +4,9 @@ - */ - - &dmc { -- rockchip,sdram-params = < -+ ddr3-1600 { -+ u-boot,dm-pre-reloc; -+ rockchip,sdram-params = < - 0x1 - 0xa - 0x3 -@@ -1536,4 +1538,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; ---- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi -+++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi -@@ -4,7 +4,9 @@ - */ - - &dmc { -- rockchip,sdram-params = < -+ ddr3-1866 { -+ u-boot,dm-pre-reloc; -+ rockchip,sdram-params = < - 0x1 - 0xa - 0x3 -@@ -1536,5 +1538,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; -- ---- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi -+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi -@@ -5,6 +5,8 @@ - */ - - &dmc { -+ lpddr3-2GB-1600 { -+ u-boot,dm-pre-reloc; - rockchip,sdram-params = < - 0x1 - 0xa -@@ -1537,4 +1539,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; ---- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi -+++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi -@@ -4,6 +4,8 @@ - */ - - &dmc { -+ lpddr3-4GB-1600 { -+ u-boot,dm-pre-reloc; - rockchip,sdram-params = < - 0x2 - 0xa -@@ -1536,4 +1538,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; ---- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi -+++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi -@@ -4,6 +4,8 @@ - */ - - &dmc { -+ lpddr3-samsung-4GB-1866 { -+ u-boot,dm-pre-reloc; - rockchip,sdram-params = < - 0x2 - 0xa -@@ -1543,4 +1545,5 @@ - 0x01010000 /* DENALI_PHY_957_DATA */ - 0x00000000 /* DENALI_PHY_958_DATA */ - >; -+ }; - }; ---- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi -+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi -@@ -6,6 +6,8 @@ - */ - - &dmc { -+ lpddr4-100 { -+ u-boot,dm-pre-reloc; - rockchip,sdram-params = < - 0x2 - 0xa -@@ -1538,4 +1540,5 @@ - 0x01010000 - 0x00000000 - >; -+ }; - }; ---- a/drivers/ram/rockchip/sdram_rk3399.c -+++ b/drivers/ram/rockchip/sdram_rk3399.c -@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) - rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); - } - --#if !defined(CONFIG_RAM_RK3399_LPDDR4) - static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, - struct rk3399_sdram_params *params) - { -@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info *chan, - clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); - clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); - } --#else - -+#if defined(CONFIG_RAM_RK3399_LPDDR4) - struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { - #include "sdram-rk3399-lpddr4-400.inc" - #include "sdram-rk3399-lpddr4-800.inc" -@@ -3011,22 +3010,43 @@ static int sdram_init(struct dram_info *dram, - return 0; - } - -+__weak const char *rk3399_get_ddrtype(void) -+{ -+ return NULL; -+} -+ - static int rk3399_dmc_of_to_plat(struct udevice *dev) - { - struct rockchip_dmc_plat *plat = dev_get_plat(dev); -+ ofnode node = { .np = NULL }; -+ const char *name; - int ret; - - if (!CONFIG_IS_ENABLED(OF_REAL)) - return 0; - -- ret = dev_read_u32_array(dev, "rockchip,sdram-params", -- (u32 *)&plat->sdram_params, -- sizeof(plat->sdram_params) / sizeof(u32)); -+ name = rk3399_get_ddrtype(); -+ if (name) -+ node = dev_read_subnode(dev, name); -+ if (!ofnode_valid(node)) { -+ debug("Failed to read subnode %s\n", name); -+ node = dev_read_first_subnode(dev); -+ } -+ -+ /* fallback to current node */ -+ if (!ofnode_valid(node)) -+ node = dev_ofnode(dev); -+ -+ ret = ofnode_read_u32_array(node, "rockchip,sdram-params", -+ (u32 *)&plat->sdram_params, -+ sizeof(plat->sdram_params) / sizeof(u32)); -+ - if (ret) { - printf("%s: Cannot read rockchip,sdram-params %d\n", - __func__, ret); - return ret; - } -+ - ret = regmap_init_mem(dev_ofnode(dev), &plat->map); - if (ret) - printf("%s: regmap failed %d\n", __func__, ret); -@@ -3051,18 +3071,21 @@ static int conv_of_plat(struct udevice *dev) - #endif - - static const struct sdram_rk3399_ops rk3399_ops = { --#if !defined(CONFIG_RAM_RK3399_LPDDR4) -+ - .data_training_first = data_training_first, - .set_rate_index = switch_to_phy_index1, - .modify_param = modify_param, - .get_phy_index_params = get_phy_index_params, --#else -+}; -+ -+#if defined(CONFIG_RAM_RK3399_LPDDR4) -+static const struct sdram_rk3399_ops lpddr4_ops = { - .data_training_first = lpddr4_mr_detect, - .set_rate_index = lpddr4_set_rate, - .modify_param = lpddr4_modify_param, -- .get_phy_index_params = lpddr4_get_phy_index_params, --#endif -+ .get_phy_index_params = lpddr4_get_phy_index_params, - }; -+#endif - - static int rk3399_dmc_init(struct udevice *dev) - { -@@ -3081,7 +3104,17 @@ static int rk3399_dmc_init(struct udevice *dev) - return ret; - #endif - -- priv->ops = &rk3399_ops; -+ if (params->base.dramtype == LPDDR4) { -+#if defined(CONFIG_RAM_RK3399_LPDDR4) -+ priv->ops = &lpddr4_ops; -+#else -+ printf("LPDDR4 support is disable\n"); -+ return -EINVAL; -+#endif -+ } else { -+ priv->ops = &rk3399_ops; -+ } -+ - priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -109,6 +109,21 @@ config TARGET_ROC_PC_RK3399 + * wide voltage input(5V-15V), dual cell battery + * Wifi/BT accessible via expansion board M.2 + ++config TARGET_DOORNET2_RK3399 ++ bool "EmbedFire DoorNet2 board" ++ help ++ DoorNet2 is SBC produced by EmbedFire. Key features: ++ ++ * Rockchip RK3399 ++ * 1-4GB DDR3 or LPDDR4 ++ * SD card slot and 8-32GB eMMC ++ * Gigabit ethernet ++ * PCIe ++ * USB 3.0, 2.0 ++ * USB Type C power ++ * GPIO expansion ports ++ * USB 2.0 Wifi module ++ + endchoice + + config ROCKCHIP_BOOT_MODE_REG +@@ -151,6 +166,7 @@ config SYS_BOOTCOUNT_ADDR + + endif # BOOTCOUNT_LIMIT + ++source "board/embedfire/doornet2/Kconfig" + source "board/firefly/roc-pc-rk3399/Kconfig" + source "board/google/gru/Kconfig" + source "board/pine64/pinebook-pro-rk3399/Kconfig" +--- /dev/null ++++ b/board/embedfire/doornet2/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_DOORNET2_RK3399 ++ ++config SYS_BOARD ++ default "doornet2" ++ ++config SYS_VENDOR ++ default "embedfire" ++ ++config SYS_CONFIG_NAME ++ default "doornet2" ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ ++endif +--- /dev/null ++++ b/board/embedfire/doornet2/Makefile +@@ -0,0 +1,6 @@ ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += doornet2.o hwrev.o ++ +--- /dev/null ++++ b/board/embedfire/doornet2/doornet2.c +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "hwrev.h" ++ ++#ifdef CONFIG_MISC_INIT_R ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ ++ /* BT565 and AUDIO is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1)); ++} ++ ++static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr) ++{ ++ struct udevice *i2c_dev; ++ int ret; ++ ++ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */ ++ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev); ++ if (!ret) ++ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6); ++ ++ return ret; ++} ++ ++static void setup_macaddr(void) ++{ ++#if CONFIG_IS_ENABLED(CMD_NET) ++ int ret; ++ const char *cpuid = env_get("cpuid#"); ++ u8 hash[SHA256_SUM_LEN]; ++ int size = sizeof(hash); ++ u8 mac_addr[6]; ++ int from_eeprom = 0; ++ int lockdown = 0; ++ ++#ifndef CONFIG_ENV_IS_NOWHERE ++ lockdown = env_get_yesno("lockdown") == 1; ++#endif ++ if (lockdown && env_get("ethaddr")) ++ return; ++ ++ ret = mac_read_from_generic_eeprom(mac_addr); ++ if (!ret && is_valid_ethaddr(mac_addr)) { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ from_eeprom = 1; ++ } ++ ++ if (!cpuid) { ++ debug("%s: could not retrieve 'cpuid#'\n", __func__); ++ return; ++ } ++ ++ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); ++ if (ret) { ++ debug("%s: failed to calculate SHA256\n", __func__); ++ return; ++ } ++ ++ /* Copy 6 bytes of the hash to base the MAC address on */ ++ memcpy(mac_addr, hash, 6); ++ ++ /* Make this a valid MAC address and set it */ ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ ++ if (from_eeprom) { ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } else { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ ++ if (lockdown && env_get("eth1addr")) ++ return; ++ ++ /* Ugly, copy another 4 bytes to generate a similar address */ ++ memcpy(mac_addr + 2, hash + 8, 4); ++ if (!memcmp(hash + 2, hash + 8, 4)) ++ mac_addr[5] ^= 0xff; ++ ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } ++#endif ++ ++ return; ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ setup_macaddr(); ++ bd_hwrev_init(); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_SERIAL_TAG ++void get_board_serial(struct tag_serialnr *serialnr) ++{ ++ char *serial_string; ++ u64 serial = 0; ++ ++ serial_string = env_get("serial#"); ++ ++ if (serial_string) ++ serial = simple_strtoull(serial_string, NULL, 16); ++ ++ serialnr->high = (u32)(serial >> 32); ++ serialnr->low = (u32)(serial & 0xffffffff); ++} ++#endif ++ +--- /dev/null ++++ b/board/embedfire/doornet2/hwrev.c +@@ -0,0 +1,171 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * ID info: ++ * ID : Volts : ADC value : Bucket ++ * == ===== ========= =========== ++ * 0 : 0.102V: 58 : 0 - 81 ++ * 1 : 0.211V: 120 : 82 - 150 ++ * 2 : 0.319V: 181 : 151 - 211 ++ * 3 : 0.427V: 242 : 212 - 274 ++ * 4 : 0.542V: 307 : 275 - 342 ++ * 5 : 0.666V: 378 : 343 - 411 ++ * 6 : 0.781V: 444 : 412 - 477 ++ * 7 : 0.900V: 511 : 478 - 545 ++ * 8 : 1.023V: 581 : 546 - 613 ++ * 9 : 1.137V: 646 : 614 - 675 ++ * 10 : 1.240V: 704 : 676 - 733 ++ * 11 : 1.343V: 763 : 734 - 795 ++ * 12 : 1.457V: 828 : 796 - 861 ++ * 13 : 1.576V: 895 : 862 - 925 ++ * 14 : 1.684V: 956 : 926 - 989 ++ * 15 : 1.800V: 1023 : 990 - 1023 ++ */ ++static const int id_readings[] = { ++ 81, 150, 211, 274, 342, 411, 477, 545, ++ 613, 675, 733, 795, 861, 925, 989, 1023 ++}; ++ ++static int cached_board_id = -1; ++ ++#define SARADC_BASE 0xFF100000 ++#define SARADC_DATA (SARADC_BASE + 0) ++#define SARADC_CTRL (SARADC_BASE + 8) ++ ++static u32 get_saradc_value(int chn) ++{ ++ int timeout = 0; ++ u32 adc_value = 0; ++ ++ writel(0, SARADC_CTRL); ++ udelay(2); ++ ++ writel(0x28 | chn, SARADC_CTRL); ++ udelay(50); ++ ++ timeout = 0; ++ do { ++ if (readl(SARADC_CTRL) & 0x40) { ++ adc_value = readl(SARADC_DATA) & 0x3FF; ++ goto stop_adc; ++ } ++ ++ udelay(10); ++ } while (timeout++ < 100); ++ ++stop_adc: ++ writel(0, SARADC_CTRL); ++ ++ return adc_value; ++} ++ ++static uint32_t get_adc_index(int chn) ++{ ++ int i; ++ int adc_reading; ++ ++ if (cached_board_id != -1) ++ return cached_board_id; ++ ++ adc_reading = get_saradc_value(chn); ++ for (i = 0; i < ARRAY_SIZE(id_readings); i++) { ++ if (adc_reading <= id_readings[i]) { ++ debug("ADC reading %d, ID %d\n", adc_reading, i); ++ cached_board_id = i; ++ return i; ++ } ++ } ++ ++ /* should die for impossible value */ ++ return 0; ++} ++ ++/* ++ * Extended by ADC_IN4 ++ * 0x06 - SOC-RK3399 ++ * 0x09 - DoorNet2 DDR3 ++ * 0x0a - DoorNet2 LPDDR4 ++ */ ++static int pcb_rev = -1; ++ ++void bd_hwrev_init(void) ++{ ++#define GPIO4_BASE 0xff790000 ++ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE; ++ ++#ifdef CONFIG_SPL_BUILD ++ struct udevice *dev; ++ ++ if (uclass_get_device_by_driver(UCLASS_CLK, ++ DM_DRIVER_GET(clk_rk3399), &dev)) ++ return; ++#endif ++ ++ if (pcb_rev >= 0) ++ return; ++ ++ /* D1, D0: input mode */ ++ clrbits_le32(®s->swport_ddr, (0x3 << 24)); ++ pcb_rev = (readl(®s->ext_port) >> 24) & 0x3; ++ ++ if (pcb_rev == 0x3) { ++ /* Revision group A: 0x04 ~ 0x13 */ ++ pcb_rev = 0x4 + get_adc_index(4); ++ ++ } else if (pcb_rev == 0x1) { ++ int idx = get_adc_index(4); ++ ++ /* Revision group B: 0x21 ~ 0x2f */ ++ if (idx > 0) { ++ pcb_rev = 0x20 + idx; ++ } ++ } ++} ++ ++#ifdef CONFIG_SPL_BUILD ++static struct board_ddrtype { ++ int rev; ++ const char *type; ++} ddrtypes[] = { ++ { 0x00, "lpddr3-samsung-4GB-1866" }, ++ { 0x01, "lpddr3-samsung-4GB-1866" }, ++ { 0x04, "ddr3-1866" }, ++ { 0x06, "ddr3-1866" }, ++ { 0x07, "lpddr4-100" }, ++ { 0x09, "ddr3-1866" }, ++ { 0x0a, "lpddr4-100" }, ++ { 0x21, "lpddr4-100" }, ++ { 0x22, "ddr3-1866" }, ++}; ++ ++const char *rk3399_get_ddrtype(void) { ++ int i; ++ ++ bd_hwrev_init(); ++ printf("Board: rev%02x\n", pcb_rev); ++ ++ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) { ++ if (ddrtypes[i].rev == pcb_rev) ++ return ddrtypes[i].type; ++ } ++ ++ /* fallback to first subnode (ie, first included dtsi) */ ++ return NULL; ++} ++#endif ++ ++/* To override __weak symbols */ ++u32 get_board_rev(void) ++{ ++ return pcb_rev; ++} ++ ++ +--- /dev/null ++++ b/board/embedfire/doornet2/MAINTAINERS +@@ -0,0 +1,5 @@ ++DoorNet2 Series ++M: embedfire ++S: Maintained ++F: board/embedfire/doornet2/ ++F: include/configs/doornet2.h +--- /dev/null ++++ b/board/embedfire/doornet2/hwrev.h +@@ -0,0 +1,25 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, you can access it online at ++ * http://www.gnu.org/licenses/gpl-2.0.html. ++ */ ++ ++#ifndef __BD_HW_REV_H__ ++#define __BD_HW_REV_H__ ++ ++extern void bd_hwrev_config_gpio(void); ++extern void bd_hwrev_init(void); ++extern u32 get_board_rev(void); ++ ++#endif /* __BD_HW_REV_H__ */ ++ +--- a/drivers/clk/rockchip/clk_rk3399.c ++++ b/drivers/clk/rockchip/clk_rk3399.c +@@ -1372,6 +1372,8 @@ static void rkclk_init(struct rockchip_c + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); ++ ++ rk3399_saradc_set_clk(cru, 1000000); + } + + static int rk3399_clk_probe(struct udevice *dev) +--- /dev/null ++++ b/include/configs/doornet2.h +@@ -0,0 +1,25 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ */ ++ ++#ifndef __CONFIG_DOORNET2_H__ ++#define __CONFIG_DOORNET2_H__ ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdin=serial,usbkbd\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#define CONFIG_SERIAL_TAG ++#define CONFIG_REVISION_TAG ++ ++#endif ++ +--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1333 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1600 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1866 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +@@ -5,6 +5,8 @@ + */ + + &dmc { ++ lpddr3-2GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x1 + 0xa +@@ -1537,4 +1539,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-4GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-samsung-4GB-1866 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1543,4 +1545,5 @@ + 0x01010000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi +@@ -6,6 +6,8 @@ + */ + + &dmc { ++ lpddr4-100 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1538,4 +1540,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/drivers/ram/rockchip/sdram_rk3399.c ++++ b/drivers/ram/rockchip/sdram_rk3399.c +@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) + rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); + } + +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) + static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) + { +@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info *chan, + clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); + } +-#else + ++#if defined(CONFIG_RAM_RK3399_LPDDR4) + struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { + #include "sdram-rk3399-lpddr4-400.inc" + #include "sdram-rk3399-lpddr4-800.inc" +@@ -3011,22 +3010,43 @@ static int sdram_init(struct dram_info *dram, + return 0; + } + ++__weak const char *rk3399_get_ddrtype(void) ++{ ++ return NULL; ++} ++ + static int rk3399_dmc_of_to_plat(struct udevice *dev) + { + struct rockchip_dmc_plat *plat = dev_get_plat(dev); ++ ofnode node = { .np = NULL }; ++ const char *name; + int ret; + + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + +- ret = dev_read_u32_array(dev, "rockchip,sdram-params", +- (u32 *)&plat->sdram_params, +- sizeof(plat->sdram_params) / sizeof(u32)); ++ name = rk3399_get_ddrtype(); ++ if (name) ++ node = dev_read_subnode(dev, name); ++ if (!ofnode_valid(node)) { ++ debug("Failed to read subnode %s\n", name); ++ node = dev_read_first_subnode(dev); ++ } ++ ++ /* fallback to current node */ ++ if (!ofnode_valid(node)) ++ node = dev_ofnode(dev); ++ ++ ret = ofnode_read_u32_array(node, "rockchip,sdram-params", ++ (u32 *)&plat->sdram_params, ++ sizeof(plat->sdram_params) / sizeof(u32)); ++ + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } ++ + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); +@@ -3051,18 +3071,21 @@ static int conv_of_plat(struct udevice *dev) + #endif + + static const struct sdram_rk3399_ops rk3399_ops = { +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) ++ + .data_training_first = data_training_first, + .set_rate_index = switch_to_phy_index1, + .modify_param = modify_param, + .get_phy_index_params = get_phy_index_params, +-#else ++}; ++ ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++static const struct sdram_rk3399_ops lpddr4_ops = { + .data_training_first = lpddr4_mr_detect, + .set_rate_index = lpddr4_set_rate, + .modify_param = lpddr4_modify_param, +- .get_phy_index_params = lpddr4_get_phy_index_params, +-#endif ++ .get_phy_index_params = lpddr4_get_phy_index_params, + }; ++#endif + + static int rk3399_dmc_init(struct udevice *dev) + { +@@ -3081,7 +3104,17 @@ static int rk3399_dmc_init(struct udevice *dev) + return ret; + #endif + +- priv->ops = &rk3399_ops; ++ if (params->base.dramtype == LPDDR4) { ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++ priv->ops = &lpddr4_ops; ++#else ++ printf("LPDDR4 support is disable\n"); ++ return -EINVAL; ++#endif ++ } else { ++ priv->ops = &rk3399_ops; ++ } ++ + priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); diff --git a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch deleted file mode 100644 index 0c80d9131..000000000 --- a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -157,6 +157,7 @@ - rk3399-nanopi-m4b.dtb \ - rk3399-nanopi-neo4.dtb \ - rk3399-nanopi-r4s.dtb \ -+ rk3399-nanopi-r4se.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-puma-haikou.dtb \ diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts deleted file mode 100644 index b8f863b2d..000000000 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPC-T4 board device tree source - * - * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * - * Copyright (c) 2020 Jensen Huang - * Copyright (c) 2020 Marty Jones - * Copyright (c) 2021 Tianling Shen - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi R4SE"; - compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; - - /delete-node/ display-subsystem; - - gpio-leds { - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - - /delete-node/ led-0; - - lan_led: led-lan { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; - }; - - sys_led: led-sys { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:power"; - default-state = "on"; - }; - - wan_led: led-wan { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - }; - }; - - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - - /delete-node/ power; - - reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c4 { - status = "disabled"; -}; - -&pcie0 { - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; -}; - -&pinctrl { - gpio-leds { - /delete-node/ status-led-pin; - - lan_led_pin: lan-led-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - /delete-node/ power-key; - - reset_button_pin: reset-button-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdmmc { - pinctrl-0 = <&sdmmc_cd>; -}; - -&sdio0 { - status = "disabled"; -}; - -&u2phy0_host { - phy-supply = <&vdd_5v>; -}; - -&u2phy1_host { - status = "disabled"; -}; - -&uart0 { - status = "disabled"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_sys>; -}; diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig deleted file mode 100644 index e92fb5e88..000000000 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=24000000 -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" -CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y -CONFIG_DEBUG_UART_BASE=0xFF1A0000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_DEBUG_UART=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_TPL=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM_RK3399_LPDDR4=y -CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_ASIX88179=y -CONFIG_USB_ETHER_MCS7830=y -CONFIG_USB_ETHER_RTL8152=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_DM_VIDEO=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_ROCKCHIP=y -CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed5..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-plat.c deleted file mode 100644 index 1818461ec..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-plat.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* Node /clock-controller@ff440000 index 0 */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* Node /dmc index 1 */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* Node /mmc@ff500000 index 2 */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* Node /serial@ff130000 index 3 */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /syscon@ff100000 index 4 */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a92..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/doornet1-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed5..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a92..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed5..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a92..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h deleted file mode 100644 index 06889b0b4..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); \ No newline at end of file diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c deleted file mode 100644 index 42468f38a..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h deleted file mode 100644 index 364d416f7..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; \ No newline at end of file diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed5..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a92..000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -};