From cdebdc900ae5cb29dc1cce1c26865001534ab77d Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Thu, 4 Oct 2018 09:38:34 +0530
Subject: [PATCH] staging: fsl_ppfe/eth: replace magic numbers

Replace magic numbers and some cosmetic changes.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
 drivers/staging/fsl_ppfe/pfe_eth.c | 83 ++++++++++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 22 deletions(-)

--- a/drivers/staging/fsl_ppfe/pfe_eth.c
+++ b/drivers/staging/fsl_ppfe/pfe_eth.c
@@ -66,6 +66,36 @@ static void pfe_eth_flush_tx(struct pfe_
 static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
 				from_tx, int n_desc);
 
+/* MDIO registers */
+#define MDIO_SGMII_CR			0x00
+#define MDIO_SGMII_SR			0x01
+#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
+#define MDIO_SGMII_LINK_TMR_L		0x12
+#define MDIO_SGMII_LINK_TMR_H		0x13
+#define MDIO_SGMII_IF_MODE		0x14
+
+/* SGMII Control defines */
+#define SGMII_CR_RST			0x8000
+#define SGMII_CR_AN_EN			0x1000
+#define SGMII_CR_RESTART_AN		0x0200
+#define SGMII_CR_FD			0x0100
+#define SGMII_CR_SPEED_SEL1_1G		0x0040
+#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
+					 SGMII_CR_SPEED_SEL1_1G)
+
+/* SGMII IF Mode */
+#define SGMII_DUPLEX_HALF		0x10
+#define SGMII_SPEED_10MBPS		0x00
+#define SGMII_SPEED_100MBPS		0x04
+#define SGMII_SPEED_1GBPS		0x08
+#define SGMII_USE_SGMII_AN		0x02
+#define SGMII_EN			0x01
+
+/* SGMII Device Ability for SGMII */
+#define SGMII_DEV_ABIL_ACK		0x4000
+#define SGMII_DEV_ABIL_EEE_CLK_STP_EN	0x0100
+#define SGMII_DEV_ABIL_SGMII		0x0001
+
 unsigned int gemac_regs[] = {
 	0x0004, /* Interrupt event */
 	0x0008, /* Interrupt mask */
@@ -1042,6 +1072,10 @@ static int pfe_get_phydev_speed(struct p
 #define SCFG_RGMIIPCR_SETSP_10M         (0x00000002)
 #define SCFG_RGMIIPCR_SETFD             (0x00000001)
 
+#define MDIOSELCR	0x484
+#define MDIOSEL_SERDES	0x0
+#define MDIOSEL_EXTPHY  0x80000000
+
 static void pfe_set_rgmii_speed(struct phy_device *phydev)
 {
 	u32 rgmii_pcr;
@@ -1187,25 +1221,34 @@ static void ls1012a_configure_serdes(str
 	netif_info(priv, drv, ndev, "%s\n", __func__);
 	/* PCS configuration done with corresponding GEMAC */
 
-	pfe_eth_mdio_read(bus, 0, 0);
-	pfe_eth_mdio_read(bus, 0, 1);
+	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
+	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
+
+	pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
 
-       /*These settings taken from validtion team */
-	pfe_eth_mdio_write(bus, 0, 0x0, 0x8000);
 	if (sgmii_2500) {
-		pfe_eth_mdio_write(bus, 0, 0x14, 0x9);
-		pfe_eth_mdio_write(bus, 0, 0x4, 0x4001);
-		pfe_eth_mdio_write(bus, 0, 0x12, 0xa120);
-		pfe_eth_mdio_write(bus, 0, 0x13, 0x7);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
+							       | SGMII_EN);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
+				   SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
 		/* Autonegotiation need to be disabled for 2.5G SGMII mode*/
-		value = 0x0140;
-		pfe_eth_mdio_write(bus, 0, 0x0, value);
+		value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
 	} else {
-		pfe_eth_mdio_write(bus, 0, 0x14, 0xb);
-		pfe_eth_mdio_write(bus, 0, 0x4, 0x1a1);
-		pfe_eth_mdio_write(bus, 0, 0x12, 0x400);
-		pfe_eth_mdio_write(bus, 0, 0x13, 0x0);
-		pfe_eth_mdio_write(bus, 0, 0x0, 0x1140);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
+				   SGMII_SPEED_1GBPS
+				   | SGMII_USE_SGMII_AN
+				   | SGMII_EN);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
+				   SGMII_DEV_ABIL_EEE_CLK_STP_EN
+				   | 0xa0
+				   | SGMII_DEV_ABIL_SGMII);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
+		value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
 	}
 }
 
@@ -1235,15 +1278,15 @@ static int pfe_phy_init(struct net_devic
 	    (interface == PHY_INTERFACE_MODE_2500SGMII)) {
 		/*Configure SGMII PCS */
 		if (pfe->scfg) {
-			/*Config MDIO from serdes */
-			regmap_write(pfe->scfg, 0x484, 0x00000000);
+			/* Config MDIO from serdes */
+			regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
 		}
 		ls1012a_configure_serdes(ndev);
 	}
 
 	if (pfe->scfg) {
 		/*Config MDIO from PAD */
-		regmap_write(pfe->scfg, 0x484, 0x80000000);
+		regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
 	}
 
 	priv->oldlink = 0;
@@ -2339,10 +2382,6 @@ static int pfe_eth_init_one(struct pfe *
 	priv->PHY_baseaddr = cbus_emac_base[0];
 	priv->GPI_baseaddr = cbus_gpi_base[id];
 
-#define HIF_GEMAC_TMUQ_BASE	6
-	priv->low_tmu_q	=  HIF_GEMAC_TMUQ_BASE + (id * 2);
-	priv->high_tmu_q	=  priv->low_tmu_q + 1;
-
 	spin_lock_init(&priv->lock);
 
 	pfe_eth_fast_tx_timeout_init(priv);
