From 8d4209ee0613dfea700bcfc2ecb6052dc9dc9956 Mon Sep 17 00:00:00 2001
From: CanYang He <hcy@rock-chips.com>
Date: Tue, 26 Dec 2017 10:19:46 +0800
Subject: [PATCH] PM / devfreq: event: add support for rk3328 dfi

This adds the necessary data for handling dfi on the rk3328.

Change-Id: Id870f78dad3ddd6cb5771674a4e8905322f9e8ef
Signed-off-by: CanYang He <hcy@rock-chips.com>
---
 .../bindings/devfreq/event/rockchip-dfi.txt   |  1 +
 drivers/devfreq/event/rockchip-dfi.c          | 40 ++++++++++++++++++-
 2 files changed, 39 insertions(+), 2 deletions(-)

--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
@@ -5,6 +5,7 @@ Required properties:
 - compatible: Should be one of the following.
   - "rockchip,rk3128-dfi" - for RK3128 SoCs.
   - "rockchip,rk3288-dfi" - for RK3288 SoCs.
+  - "rockchip,rk3328-dfi" - for RK3328 SoCs.
   - "rockchip,rk3368-dfi" - for RK3368 SoCs.
   - "rockchip,rk3399-dfi" - for RK3399 SoCs.
 
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -36,6 +36,8 @@
 #define RK3288_LPDDR_SEL		(0x10001 << 13)
 #define RK3288_DDR3_SEL			(0x10000 << 13)
 
+#define RK3328_GRF_OS_REG2		0x5d0
+
 #define RK3368_GRF_DDRC0_CON0		0x600
 #define RK3368_GRF_SOC_STATUS5		0x494
 #define RK3368_GRF_SOC_STATUS6		0x498
@@ -48,10 +50,10 @@
 #define MAX_DMC_NUM_CH			2
 #define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
 #define READ_CH_INFO(n)			(((n) >> 28) & 0x3)
-
 /* DDRMON_CTRL */
 #define DDRMON_CTRL			0x04
-#define CLR_DDRMON_CTRL			(0x1f0000 << 0)
+#define CLR_DDRMON_CTRL			(0x3f0000 << 0)
+#define DDR4_EN				(0x10001 << 5)
 #define LPDDR4_EN			(0x10001 << 4)
 #define HARDWARE_EN			(0x10001 << 3)
 #define LPDDR3_EN			(0x10001 << 2)
@@ -68,6 +70,7 @@
 #define PMUGRF_OS_REG2			0x308
 
 enum {
+	DDR4 = 0,
 	DDR3 = 3,
 	LPDDR3 = 6,
 	LPDDR4 = 7,
@@ -339,6 +342,8 @@ static void rockchip_dfi_start_hardware_
 		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
 	else if (info->dram_type == LPDDR4)
 		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+	else if (info->dram_type == DDR4)
+		writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
 
 	/* enable count, use software mode */
 	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
@@ -547,9 +552,40 @@ static __init int rockchip_dfi_init(stru
 	return 0;
 }
 
+static __init int rk3328_dfi_init(struct platform_device *pdev,
+				  struct rockchip_dfi *data,
+				  struct devfreq_event_desc *desc)
+{
+	struct device_node *np = pdev->dev.of_node, *node;
+	struct resource *res;
+	u32 val;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(data->regs))
+		return PTR_ERR(data->regs);
+
+	node = of_parse_phandle(np, "rockchip,grf", 0);
+	if (node) {
+		data->regmap_grf = syscon_node_to_regmap(node);
+		if (IS_ERR(data->regmap_grf))
+			return PTR_ERR(data->regmap_grf);
+	}
+
+	regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
+	data->dram_type = READ_DRAMTYPE_INFO(val);
+	data->ch_msk = 1;
+	data->clk = NULL;
+
+	desc->ops = &rockchip_dfi_ops;
+
+	return 0;
+}
+
 static const struct of_device_id rockchip_dfi_id_match[] = {
 	{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
 	{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
+	{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
 	{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
 	{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
 	{ },
