From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Wed, 30 Mar 2022 21:24:21 -0500
Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI

D1's HDMI controller contains some platform integration changes.
It now has no external TMDS clock. The controller also supports HDCP
without an external clock or reset.

While the maximum HDMI frequency is not explicity stated, the BSP PHY
driver provides PLL configurations only up to 297 MHz, so use that as
the max frequency.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev
 		return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
 				     "Could not get ctrl reset control\n");
 
-	hdmi->clk_tmds = devm_clk_get(dev, "tmds");
+	hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds");
 	if (IS_ERR(hdmi->clk_tmds))
 		return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
 				     "Couldn't get the tmds clock\n");
@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks
 	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
 };
 
+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = {
+	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
+	.use_drm_infoframe = true,
+};
+
 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
 	.mode_valid = sun8i_dw_hdmi_mode_valid_h6,
 	.use_drm_infoframe = true,
@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d
 		.data = &sun8i_a83t_quirks,
 	},
 	{
+		.compatible = "allwinner,sun20i-d1-dw-hdmi",
+		.data = &sun20i_d1_quirks,
+	},
+	{
 		.compatible = "allwinner,sun50i-h6-dw-hdmi",
 		.data = &sun50i_h6_quirks,
 	},
