diff --git a/config/Config-build.in b/config/Config-build.in index 24c2bcf130..9768878572 100644 --- a/config/Config-build.in +++ b/config/Config-build.in @@ -228,6 +228,7 @@ menu "Global build settings" config STRIP_KERNEL_EXPORTS bool "Strip unnecessary exports from the kernel image" + depends on !LINUX_6_6 help Reduces kernel size by stripping unused kernel exports from the kernel image. Note that this might make the kernel incompatible with any kernel diff --git a/config/Config-kernel.in b/config/Config-kernel.in index 292675c464..2d93ffbfcd 100644 --- a/config/Config-kernel.in +++ b/config/Config-kernel.in @@ -50,6 +50,11 @@ config KERNEL_ARM_PMU default y if TARGET_armsr_armv8 depends on (arm || aarch64) +config KERNEL_ARM_PMUV3 + bool + default y if TARGET_armsr_armv8 + depends on (arm_v7 || aarch64) && LINUX_6_6 + config KERNEL_RISCV_PMU bool select KERNEL_RISCV_PMU_SBI @@ -79,6 +84,7 @@ config KERNEL_X86_VSYSCALL_EMULATION config KERNEL_PERF_EVENTS bool "Compile the kernel with performance events and counters" select KERNEL_ARM_PMU if (arm || aarch64) + select KERNEL_ARM_PMUV3 if (arm_v7 || aarch64) && LINUX_6_6 select KERNEL_RISCV_PMU if riscv64 config KERNEL_PROFILING diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 4a82b9c9b3..71d13ebc5f 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .155 -LINUX_KERNEL_HASH-5.15.155 = c85859b86d2e6d1fc91ca1be8b44f24a9b5bb9f86869b04a8665a3a6559126e4 +LINUX_VERSION-5.15 = .158 +LINUX_KERNEL_HASH-5.15.158 = f9071c83a4fd8b80af026b48cfc1869bfa25883f9148b92b5dc1e1e1e26dd5c6 diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 567bf9824d..4a6e7e4d0a 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -20,10 +20,7 @@ alfa-network,n5q|\ alfa-network,pi-wifi4|\ alfa-network,r36a|\ alfa-network,tube-2hq|\ -allnet,all-wap02860ac|\ araknis,an-300-ap-i-n|\ -araknis,an-500-ap-i-ac|\ -araknis,an-700-ap-i-ac|\ arduino,yun|\ asus,rt-ac59u|\ asus,rt-ac59u-v2|\ @@ -31,8 +28,6 @@ asus,zenwifi-cd6n|\ asus,zenwifi-cd6r|\ buffalo,bhr-4grv2|\ devolo,magic-2-wifi|\ -engenius,eap1200h|\ -engenius,eap1750h|\ engenius,eap300-v2|\ engenius,eap350-v1|\ engenius,eap600|\ @@ -42,8 +37,6 @@ engenius,ecb350-v1|\ engenius,ecb600|\ engenius,enh202-v1|\ engenius,ens202ext-v1|\ -engenius,enstationac-v1|\ -engenius,ews660ap|\ etactica,eg200|\ glinet,gl-ar750s-nor|\ glinet,gl-ar750s-nor-nand|\ @@ -84,7 +77,6 @@ ubnt,powerbridge-m|\ ubnt,rocket-m|\ watchguard,ap100|\ watchguard,ap200|\ -watchguard,ap300|\ yuncore,a770|\ yuncore,a782|\ yuncore,a930|\ diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq807x b/package/boot/uboot-envtools/files/qualcommax_ipq807x index f570fa3e69..b3f94254de 100644 --- a/package/boot/uboot-envtools/files/qualcommax_ipq807x +++ b/package/boot/uboot-envtools/files/qualcommax_ipq807x @@ -32,7 +32,8 @@ zte,mf269) ;; linksys,mx4200v1|\ linksys,mx4200v2|\ -linksys,mx5300) +linksys,mx5300|\ +linksys,mx8500) idx="$(find_mtd_index u_env)" [ -n "$idx" ] && \ ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2" diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 68448a6ec1..2ffd2e014c 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -37,6 +37,7 @@ ALLWIFIBOARDS:= \ edimax_cax1800 \ linksys_mx4200 \ linksys_mx5300 \ + linksys_mx8500 \ netgear_lbr20 \ netgear_rax120v2 \ netgear_wax214 \ @@ -157,6 +158,7 @@ $(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102)) $(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800)) $(eval $(call generate-ipq-wifi-package,linksys_mx4200,Linksys MX4200)) $(eval $(call generate-ipq-wifi-package,linksys_mx5300,Linksys MX5300)) +$(eval $(call generate-ipq-wifi-package,linksys_mx8500,Linksys MX8500)) $(eval $(call generate-ipq-wifi-package,netgear_lbr20,Netgear LBR20)) $(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2)) $(eval $(call generate-ipq-wifi-package,netgear_wax214,Netgear WAX214)) diff --git a/package/firmware/linux-firmware/realtek.mk b/package/firmware/linux-firmware/realtek.mk index e077c796be..cd64d79d63 100644 --- a/package/firmware/linux-firmware/realtek.mk +++ b/package/firmware/linux-firmware/realtek.mk @@ -87,6 +87,14 @@ define Package/rtl8723au-firmware/install endef $(eval $(call BuildPackage,rtl8723au-firmware)) +Package/rtl8723be-firmware = $(call Package/firmware-default,RealTek RTL8723BE firmware,,LICENCE.rtlwifi_firmware.txt) +define Package/rtl8723be-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/rtlwifi + $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw_36.bin $(1)/lib/firmware/rtlwifi + $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw.bin $(1)/lib/firmware/rtlwifi +endef +$(eval $(call BuildPackage,rtl8723be-firmware)) + Package/rtl8723bu-firmware = $(call Package/firmware-default,RealTek RTL8723BU firmware,,LICENCE.rtlwifi_firmware.txt) define Package/rtl8723bu-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/rtlwifi diff --git a/package/kernel/gpio-nct5104d/src/gpio-nct5104d.c b/package/kernel/gpio-nct5104d/src/gpio-nct5104d.c index 5343d6e3a8..eb1cf8494a 100644 --- a/package/kernel/gpio-nct5104d/src/gpio-nct5104d.c +++ b/package/kernel/gpio-nct5104d/src/gpio-nct5104d.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c index 8ccfb443ed..b5e7f07319 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c +++ b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c @@ -61,8 +61,6 @@ #define IFXMIPS_FUSE_BASE_ADDR IFX_FUSE_BASE_ADDR #define IFXMIPS_ICU_IM0_IER IFX_ICU_IM0_IER #define IFXMIPS_ICU_IM2_IER IFX_ICU_IM2_IER -#define LTQ_MEI_INT IFX_MEI_INT -#define LTQ_MEI_DYING_GASP_INT IFX_MEI_DYING_GASP_INT #define LTQ_MEI_BASE_ADDR IFX_MEI_SPACE_ACCESS #define IFXMIPS_PMU_PWDCR IFX_PMU_PWDCR #define IFXMIPS_MPS_CHIPID IFX_MPS_CHIPID @@ -86,28 +84,6 @@ #define LTQ_PMU_BASE_ADDR 0x1F102000 -#ifdef CONFIG_DANUBE -# define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) -# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) -# define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) -#endif - -#ifdef CONFIG_AMAZON_SE -# define LTQ_MEI_INT (INT_NUM_IM2_IRL0 + 9) -# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM2_IRL0 + 11) -# define LTQ_USB_OC_INT (INT_NUM_IM2_IRL0 + 20) -#endif - -#ifdef CONFIG_AR9 -# define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) -# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) -# define LTQ_USB_OC_INT (INT_NUM_IM1_IRL0 + 28) -#endif - -#ifndef LTQ_MEI_INT -#error "Unknown Lantiq ARCH!" -#endif - #define LTQ_RCU_RST_REQ_DFE (1 << 7) #define LTQ_RCU_RST_REQ_AFE (1 << 11) @@ -1350,14 +1326,14 @@ IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev) im2_register = (*LTQ_ICU_IM2_IER) & (1 << 20); /* Turn off irq */ - disable_irq (LTQ_USB_OC_INT); + disable_irq (pDev->nIrq[IFX_USB_OC]); disable_irq (pDev->nIrq[IFX_DYING_GASP]); IFX_MEI_RunArc (pDev); MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000); - MEI_MASK_AND_ACK_IRQ (LTQ_USB_OC_INT); + MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_USB_OC]); MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]); /* Re-enable irq */ @@ -2304,8 +2280,6 @@ IFX_MEI_InitDevice (int num) sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS); if (num == 0) { - pDev->nIrq[IFX_DFEIR] = LTQ_MEI_INT; - pDev->nIrq[IFX_DYING_GASP] = LTQ_MEI_DYING_GASP_INT; pDev->base_address = KSEG1 + LTQ_MEI_BASE_ADDR; /* Power up MEI */ @@ -2759,10 +2733,31 @@ static int ltq_mei_probe(struct platform_device *pdev) { int i = 0; static struct class *dsl_class; + DSL_DEV_Device_t *pDev; pr_info("IFX MEI Version %ld.%02ld.%02ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); for (i = 0; i < BSP_MAX_DEVICES; i++) { + pDev = &dsl_devices[i]; + + pDev->nIrq[IFX_DFEIR] = platform_get_irq(pdev, 0); + if (pDev->nIrq[IFX_DFEIR] < 0) { + IFX_MEI_EMSG("Failed to get DFEIR irq!\n"); + return pDev->nIrq[IFX_DFEIR]; + } + + pDev->nIrq[IFX_DYING_GASP] = platform_get_irq(pdev, 1); + if (pDev->nIrq[IFX_DYING_GASP] < 0) { + IFX_MEI_EMSG("Failed to get DYING_GASP irq!\n"); + return pDev->nIrq[IFX_DYING_GASP]; + } + + pDev->nIrq[IFX_USB_OC] = platform_get_irq(pdev, 2); + if (pDev->nIrq[IFX_USB_OC] < 0) { + IFX_MEI_EMSG("Failed to get USB_OC irq!\n"); + return pDev->nIrq[IFX_USB_OC]; + } + if (IFX_MEI_InitDevice (i) != 0) { IFX_MEI_EMSG("Init device fail!\n"); return -EIO; diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/ifxmips_mei_interface.h b/package/kernel/lantiq/ltq-adsl-mei/src/ifxmips_mei_interface.h index e5089c43a3..c591bdfb22 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/ifxmips_mei_interface.h +++ b/package/kernel/lantiq/ltq-adsl-mei/src/ifxmips_mei_interface.h @@ -515,9 +515,10 @@ typedef struct DSL_DEV_Device DSL_int_t nInUse; /* modem state, update by bsp driver, */ DSL_void_t *pPriv; DSL_uint32_t base_address; /* mei base address */ - DSL_int_t nIrq[2]; /* irq number */ + DSL_int_t nIrq[3]; /* irq number */ #define IFX_DFEIR 0 #define IFX_DYING_GASP 1 +#define IFX_USB_OC 2 DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */ struct module *owner; } DSL_DEV_Device_t; /* ifx_adsl_device_t */ diff --git a/package/kernel/lantiq/ltq-adsl/patches/201-fix-compilation-warning-fallthrough.patch b/package/kernel/lantiq/ltq-adsl/patches/201-fix-compilation-warning-fallthrough.patch index dfaf29f449..17dfd0f25d 100644 --- a/package/kernel/lantiq/ltq-adsl/patches/201-fix-compilation-warning-fallthrough.patch +++ b/package/kernel/lantiq/ltq-adsl/patches/201-fix-compilation-warning-fallthrough.patch @@ -25,7 +25,7 @@ nErrCode = DSL_DRV_PM_HistoryDelete(pContext, EpData.pHistShowtime ); --- a/src/device/drv_dsl_cpe_device_danube.c +++ b/src/device/drv_dsl_cpe_device_danube.c -@@ -3193,7 +3193,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTraining( +@@ -3193,7 +3193,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTr DSL_DEV_NUM(pContext))); } #endif /* INCLUDE_DSL_DELT*/ diff --git a/package/kernel/lantiq/ltq-adsl/patches/202-g997_danube-dynamically-allocate-hlogdata.patch b/package/kernel/lantiq/ltq-adsl/patches/202-g997_danube-dynamically-allocate-hlogdata.patch index c3b1047a2a..1dd0f21693 100644 --- a/package/kernel/lantiq/ltq-adsl/patches/202-g997_danube-dynamically-allocate-hlogdata.patch +++ b/package/kernel/lantiq/ltq-adsl/patches/202-g997_danube-dynamically-allocate-hlogdata.patch @@ -1,6 +1,6 @@ --- a/src/g997/drv_dsl_cpe_api_g997_danube.c +++ b/src/g997/drv_dsl_cpe_api_g997_danube.c -@@ -1984,41 +1984,53 @@ DSL_Error_t DSL_DRV_DEV_G997_DeltHlogGet( +@@ -1984,41 +1984,53 @@ DSL_Error_t DSL_DRV_DEV_G997_DeltHlogGet { if (nDirection == DSL_DOWNSTREAM) { diff --git a/package/kernel/lantiq/ltq-adsl/patches/203-g997_danube-fix-compilation-warning.patch b/package/kernel/lantiq/ltq-adsl/patches/203-g997_danube-fix-compilation-warning.patch index c6a0e70f1f..b86ecf84a4 100644 --- a/package/kernel/lantiq/ltq-adsl/patches/203-g997_danube-fix-compilation-warning.patch +++ b/package/kernel/lantiq/ltq-adsl/patches/203-g997_danube-fix-compilation-warning.patch @@ -1,6 +1,6 @@ --- a/src/g997/drv_dsl_cpe_api_g997_danube.c +++ b/src/g997/drv_dsl_cpe_api_g997_danube.c -@@ -2512,6 +2524,7 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManagementStateForcedTrigger( +@@ -2524,6 +2524,7 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManage else { /* read L3 request failure reason */ @@ -8,7 +8,7 @@ nErrCode = DSL_DRV_DANUBE_CmvRead(pContext, DSL_CMV_GROUP_STAT, DSL_CMV_ADDRESS_STAT_L3_FAILURE_REASON, 0, 1, &nVal); DSL_DEBUG(DSL_DBG_MSG, -@@ -2525,11 +2538,13 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManagementStateForcedTrigger( +@@ -2537,11 +2538,13 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManage nErrCode = DSL_ERR_MSG_EXCHANGE; break; } diff --git a/package/kernel/lantiq/ltq-adsl/patches/400-kernel-6.1.patch b/package/kernel/lantiq/ltq-adsl/patches/400-kernel-6.1.patch new file mode 100644 index 0000000000..2179f355bb --- /dev/null +++ b/package/kernel/lantiq/ltq-adsl/patches/400-kernel-6.1.patch @@ -0,0 +1,14 @@ +--- a/src/common/drv_dsl_cpe_os_linux.c ++++ b/src/common/drv_dsl_cpe_os_linux.c +@@ -556,7 +556,11 @@ static int DSL_DRV_KernelThreadStartup(v + retVal = pThrCntrl->pThrFct(&pThrCntrl->thrParams); + pThrCntrl->thrParams.bRunning = 0; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0)) + complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal); ++#else ++ kthread_complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal); ++#endif + + DSL_DEBUG( DSL_DBG_MSG, + (DSL_NULL, "EXIT - Kernel Thread Startup <%s>" DSL_DRV_CRLF, diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_core.h b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_core.h index 31b80cf86f..20aa14445a 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_core.h +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_core.h @@ -25,8 +25,6 @@ #define IFXMIPS_ATM_CORE_H -#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) -#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) #define CONFIG_IFXMIPS_DSL_CPE_MEI #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) #define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) @@ -239,6 +237,8 @@ struct atm_priv_data { void *oam_buf_base; void *tx_desc_base; void *tx_skb_base; + + int irq; }; #include "ifxmips_atm_ppe_common.h" diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h index 412f605b2b..a8520300a0 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h @@ -111,11 +111,6 @@ #define EMA_ALIGNMENT 4 -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13 - #endif // IFXMIPS_ATM_PPE_AMAZON_SE_H diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_ar9.h b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_ar9.h index fae0252c31..ff5602aa61 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_ar9.h +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_ar9.h @@ -178,11 +178,6 @@ #define EMA_ALIGNMENT 4 -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - #endif // IFXMIPS_ATM_PPE_AR9_H diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_danube.h b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_danube.h index 7aaaa8db1e..eff1a98819 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_danube.h +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_danube.h @@ -119,11 +119,6 @@ #define EMA_ALIGNMENT 4 -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - #endif // IFXMIPS_ATM_PPE_DANUBE_H diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_vr9.h b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_vr9.h index 144c39656c..943350a1b4 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_vr9.h +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_vr9.h @@ -182,11 +182,6 @@ #define PDMA_ALIGNMENT 4 #define EMA_ALIGNMENT PDMA_ALIGNMENT -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - #endif // IFXMIPS_ATM_PPE_VR9_H diff --git a/package/kernel/lantiq/ltq-atm/src/ltq_atm.c b/package/kernel/lantiq/ltq-atm/src/ltq_atm.c index 5d23b5ec48..bf2a4a50ec 100644 --- a/package/kernel/lantiq/ltq-atm/src/ltq_atm.c +++ b/package/kernel/lantiq/ltq-atm/src/ltq_atm.c @@ -435,7 +435,7 @@ static int ppe_open(struct atm_vcc *vcc) *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); - enable_irq(PPE_MAILBOX_IGU1_INT); + enable_irq(g_atm_priv_data.irq); } /* set port */ @@ -481,7 +481,7 @@ static void ppe_close(struct atm_vcc *vcc) /* disable irq */ if ( g_atm_priv_data.conn_table == 0 ) - disable_irq(PPE_MAILBOX_IGU1_INT); + disable_irq(g_atm_priv_data.irq); /* release bandwidth */ switch ( vcc->qos.txtp.traffic_class ) @@ -1022,7 +1022,7 @@ static void do_ppe_tasklet(unsigned long data) else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */ tasklet_schedule(&g_dma_tasklet); else - enable_irq(PPE_MAILBOX_IGU1_INT); + enable_irq(g_atm_priv_data.irq); } static irqreturn_t mailbox_irq_handler(int irq, void *dev_id) @@ -1030,7 +1030,7 @@ static irqreturn_t mailbox_irq_handler(int irq, void *dev_id) if ( !*MBOX_IGU1_ISR ) return IRQ_HANDLED; - disable_irq_nosync(PPE_MAILBOX_IGU1_INT); + disable_irq_nosync(g_atm_priv_data.irq); tasklet_schedule(&g_dma_tasklet); return IRQ_HANDLED; @@ -1805,17 +1805,23 @@ static int ltq_atm_probe(struct platform_device *pdev) } } + g_atm_priv_data.irq = platform_get_irq(pdev, 0); + if (g_atm_priv_data.irq < 0) { + pr_err("platform_get_irq fail"); + goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; + } + /* register interrupt handler */ - ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data); + ret = request_irq(g_atm_priv_data.irq, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data); if ( ret ) { if ( ret == -EBUSY ) { pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n"); } else { - pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT); + pr_err("request_irq fail irq:%d\n", g_atm_priv_data.irq); } goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; } - disable_irq(PPE_MAILBOX_IGU1_INT); + disable_irq(g_atm_priv_data.irq); ret = ops->start(0); @@ -1845,7 +1851,7 @@ static int ltq_atm_probe(struct platform_device *pdev) return 0; PP32_START_FAIL: - free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); + free_irq(g_atm_priv_data.irq, &g_atm_priv_data); REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL: ATM_DEV_REGISTER_FAIL: while ( port_num-- > 0 ) @@ -1868,7 +1874,7 @@ static int ltq_atm_remove(struct platform_device *pdev) ops->stop(0); - free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); + free_irq(g_atm_priv_data.irq, &g_atm_priv_data); for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) atm_dev_deregister(g_atm_priv_data.port[port_num].dev); diff --git a/package/kernel/lantiq/ltq-ptm/patches/101-fix-more-compilation-warning-debugfs.patch b/package/kernel/lantiq/ltq-ptm/patches/101-fix-more-compilation-warning-debugfs.patch index f854662a07..55551ad91d 100644 --- a/package/kernel/lantiq/ltq-ptm/patches/101-fix-more-compilation-warning-debugfs.patch +++ b/package/kernel/lantiq/ltq-ptm/patches/101-fix-more-compilation-warning-debugfs.patch @@ -1,6 +1,6 @@ --- a/ifxmips_ptm_adsl.c +++ b/ifxmips_ptm_adsl.c -@@ -180,7 +180,7 @@ static int proc_read_version(char *, char **, off_t, int, int *, void *); +@@ -180,7 +180,7 @@ static int proc_read_version(char *, cha static int proc_read_wanmib(char *, char **, off_t, int, int *, void *); static int proc_write_wanmib(struct file *, const char *, unsigned long, void *); #endif @@ -9,7 +9,7 @@ static int proc_read_genconf(char *, char **, off_t, int, int *, void *); #endif #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC -@@ -191,8 +191,8 @@ static int proc_write_wanmib(struct file *, const char *, unsigned long, void *) +@@ -191,8 +191,8 @@ static int proc_write_wanmib(struct file /* * Proc Help Functions */ @@ -19,7 +19,7 @@ static INLINE int strincmp(const char *, const char *, int); #endif static INLINE int ifx_ptm_version(char *); -@@ -1159,8 +1159,6 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun +@@ -1159,8 +1159,6 @@ static int proc_write_dbg(struct file *f return count; } @@ -28,7 +28,7 @@ static INLINE int stricmp(const char *p1, const char *p2) { int c1, c2; -@@ -1178,7 +1176,6 @@ static INLINE int stricmp(const char *p1, const char *p2) +@@ -1178,7 +1176,6 @@ static INLINE int stricmp(const char *p1 return *p1 - *p2; } diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c index 5ee966c014..8c829f9c6b 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c @@ -277,6 +277,8 @@ static int g_showtime = 0; static void ptm_setup(struct net_device *dev, int ndev) { + u8 addr[ETH_ALEN]; + #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) netif_carrier_off(dev); #endif @@ -285,15 +287,20 @@ static void ptm_setup(struct net_device *dev, int ndev) dev->netdev_ops = &g_ptm_netdev_ops; /* Allow up to 1508 bytes, for RFC4638 */ dev->max_mtu = ETH_DATA_LEN + 8; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)) netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25); +#else + netif_napi_add_weight(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25); +#endif dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT; - dev->dev_addr[0] = 0x00; - dev->dev_addr[1] = 0x20; - dev->dev_addr[2] = 0xda; - dev->dev_addr[3] = 0x86; - dev->dev_addr[4] = 0x23; - dev->dev_addr[5] = 0x75 + ndev; + addr[0] = 0x00; + addr[1] = 0x20; + addr[2] = 0xda; + addr[3] = 0x86; + addr[4] = 0x23; + addr[5] = 0x75 + ndev; + eth_hw_addr_set(dev, addr); } static struct net_device_stats *ptm_get_stats(struct net_device *dev) @@ -1484,8 +1491,14 @@ static int ltq_ptm_probe(struct platform_device *pdev) goto REGISTER_NETDEV_FAIL; } + g_ptm_priv_data.irq = platform_get_irq(pdev, 0); + if (g_ptm_priv_data.irq < 0) { + err("platform_get_irq fail"); + goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; + } + /* register interrupt handler */ - ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data); + ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data); if ( ret ) { if ( ret == -EBUSY ) { err("IRQ may be occupied by other driver, please reconfig to disable it."); @@ -1495,7 +1508,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) } goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; } - disable_irq(PPE_MAILBOX_IGU1_INT); + disable_irq(g_ptm_priv_data.irq); ret = ifx_pp32_start(0); if ( ret ) { @@ -1505,7 +1518,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) IFX_REG_W32(0, MBOX_IGU1_IER); IFX_REG_W32(~0, MBOX_IGU1_ISRC); - enable_irq(PPE_MAILBOX_IGU1_INT); + enable_irq(g_ptm_priv_data.irq); proc_file_create(); @@ -1527,7 +1540,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) return 0; PP32_START_FAIL: - free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data); + free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data); REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL: i = ARRAY_SIZE(g_net_dev); REGISTER_NETDEV_FAIL: @@ -1565,7 +1578,7 @@ static int ltq_ptm_remove(struct platform_device *pdev) ifx_pp32_stop(0); - free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data); + free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data); for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) unregister_netdev(g_net_dev[i]); diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h index 6d1cbc7ea3..dd8a2fddca 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h @@ -35,7 +35,6 @@ #include "ifxmips_ptm_fw_regs_adsl.h" #define CONFIG_IFXMIPS_DSL_CPE_MEI -#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) #define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) @@ -104,6 +103,7 @@ struct ptm_itf { struct ptm_priv_data { struct ptm_itf itf[MAX_ITF_NUMBER]; + int irq; void *rx_desc_base; void *tx_desc_base; diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h index f912039c38..be68d7894f 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h @@ -176,11 +176,6 @@ #define EMA_ALIGNMENT 4 -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13 - #endif // IFXMIPS_PTM_PPE_AMAZON_SE_H diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h index 9355747af6..4d730499ba 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h @@ -203,11 +203,5 @@ #define SW_P2_CTL SW_REG(0x00C) -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - - #endif // IFXMIPS_PTM_PPE_AR9_H diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h index 5f896e60c2..f03aae8251 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h @@ -125,11 +125,6 @@ #define EMA_ALIGNMENT 4 -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - #endif // IFXMIPS_PTM_PPE_DANUBE_H diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h index 4a8c2f7bc9..52fa286933 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h @@ -195,11 +195,6 @@ #define PDMA_ALIGNMENT 32 // same as Central DMA because of descriptor swap #define EMA_ALIGNMENT PDMA_ALIGNMENT -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - #endif // IFXMIPS_PTM_PPE_VR9_H diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c index dfb57787b9..9cd9cd5986 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c @@ -153,7 +153,11 @@ static void ptm_setup(struct net_device *dev, int ndev) dev->netdev_ops = &g_ptm_netdev_ops; /* Allow up to 1508 bytes, for RFC4638 */ dev->max_mtu = ETH_DATA_LEN + 8; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)) netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16); +#else + netif_napi_add_weight(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16); +#endif dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT; addr[0] = 0x00; @@ -1009,8 +1013,14 @@ static int ltq_ptm_probe(struct platform_device *pdev) goto REGISTER_NETDEV_FAIL; } + g_ptm_priv_data.irq = platform_get_irq(pdev, 0); + if (g_ptm_priv_data.irq < 0) { + err("platform_get_irq fail"); + goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; + } + /* register interrupt handler */ - ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data); + ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data); if ( ret ) { if ( ret == -EBUSY ) { err("IRQ may be occupied by other driver, please reconfig to disable it."); @@ -1020,7 +1030,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) } goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; } - disable_irq(PPE_MAILBOX_IGU1_INT); + disable_irq(g_ptm_priv_data.irq); ret = ifx_pp32_start(0); if ( ret ) { @@ -1030,7 +1040,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt IFX_REG_W32(~0, MBOX_IGU1_ISRC); - enable_irq(PPE_MAILBOX_IGU1_INT); + enable_irq(g_ptm_priv_data.irq); ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr); if ( g_showtime ) { @@ -1048,7 +1058,7 @@ static int ltq_ptm_probe(struct platform_device *pdev) return 0; PP32_START_FAIL: - free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data); + free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data); REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL: i = ARRAY_SIZE(g_net_dev); REGISTER_NETDEV_FAIL: @@ -1076,7 +1086,7 @@ static int ltq_ptm_remove(struct platform_device *pdev) ifx_pp32_stop(0); - free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data); + free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data); for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) unregister_netdev(g_net_dev[i]); diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h index b12c354fe0..90ed9d9021 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h @@ -31,8 +31,6 @@ #include "ifxmips_ptm_ppe_common.h" #include "ifxmips_ptm_fw_regs_vdsl.h" -#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) - #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) #define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) #define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) @@ -99,6 +97,7 @@ struct ptm_itf { struct ptm_priv_data { struct ptm_itf itf[MAX_ITF_NUMBER]; + int irq; }; diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/300-fix-simple-compilation-warning.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/300-fix-simple-compilation-warning.patch index e9f1931227..c1d3aa8b41 100644 --- a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/300-fix-simple-compilation-warning.patch +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/300-fix-simple-compilation-warning.patch @@ -9,7 +9,7 @@ #endif /* add MEI CPE debug/printout part */ -@@ -1718,8 +1718,8 @@ static void MEI_MeminfoProcPerDevGet(struct seq_file *s) +@@ -1718,8 +1718,8 @@ static void MEI_MeminfoProcPerDevGet(str ", CRC = 0x%08X" #endif MEI_DRV_CRLF, @@ -22,7 +22,7 @@ #if (MEI_SUPPORT_OPTIMIZED_FW_DL == 1) --- a/src/drv_mei_cpe_download_vrx.c +++ b/src/drv_mei_cpe_download_vrx.c -@@ -3139,9 +3139,9 @@ IFX_int32_t MEI_DEV_IoctlFirmwareDownload( +@@ -3139,9 +3139,9 @@ IFX_int32_t MEI_DEV_IoctlFirmwareDownloa { IFX_int32_t ret = 0; MEI_DEV_T *pMeiDev = pMeiDynCntrl->pMeiDev; diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/400-kernel-6.1.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/400-kernel-6.1.patch new file mode 100644 index 0000000000..a1efdb7b48 --- /dev/null +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/400-kernel-6.1.patch @@ -0,0 +1,28 @@ +--- a/src/drv_mei_cpe_linux.c ++++ b/src/drv_mei_cpe_linux.c +@@ -1873,7 +1873,11 @@ static int mei_seq_single_show(struct se + + static int mei_proc_single_open(struct inode *inode, struct file *file) + { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0)) + return single_open(file, mei_seq_single_show, PDE_DATA(inode)); ++#else ++ return single_open(file, mei_seq_single_show, pde_data(inode)); ++#endif + } + + static void mei_proc_entry_create(struct proc_dir_entry *parent_node, +--- a/src/drv_mei_cpe_linux_proc_config.c ++++ b/src/drv_mei_cpe_linux_proc_config.c +@@ -1036,7 +1036,11 @@ static int mei_seq_single_show(struct se + + static int mei_proc_single_open(struct inode *inode, struct file *file) + { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0)) + return single_open(file, mei_seq_single_show, PDE_DATA(inode)); ++#else ++ return single_open(file, mei_seq_single_show, pde_data(inode)); ++#endif + } + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)) diff --git a/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/401-use-unsafe_memcpy-for-intentional-field-spanning-write.patch b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/401-use-unsafe_memcpy-for-intentional-field-spanning-write.patch new file mode 100644 index 0000000000..1542ace44f --- /dev/null +++ b/package/kernel/lantiq/ltq-vdsl-vr9-mei/patches/401-use-unsafe_memcpy-for-intentional-field-spanning-write.patch @@ -0,0 +1,15 @@ +--- a/src/drv_mei_cpe_msg_process.c ++++ b/src/drv_mei_cpe_msg_process.c +@@ -3524,7 +3524,12 @@ IFX_int32_t MEI_IoctlCmdMsgWrite( + { + if (bInternCall) + { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)) + memcpy(pDestPtr, pUserMsg->pPayload, pUserMsg->paylSize_byte); ++#else ++ unsafe_memcpy(pDestPtr, pUserMsg->pPayload, pUserMsg->paylSize_byte, ++ /* field-spanning writing is used here intentionally */); ++#endif + } + else + { diff --git a/package/kernel/lantiq/ltq-vmmc/patches/602-remove-ABS.patch b/package/kernel/lantiq/ltq-vmmc/patches/602-remove-ABS.patch new file mode 100644 index 0000000000..e09989be8a --- /dev/null +++ b/package/kernel/lantiq/ltq-vmmc/patches/602-remove-ABS.patch @@ -0,0 +1,20 @@ +--- a/src/drv_vmmc_api.h ++++ b/src/drv_vmmc_api.h +@@ -149,17 +149,6 @@ DECLARE_TRACE_GROUP(VMMC); + return code; \ + }while(0) + +-/******************************************************************************* +-Description: +- always returns the absolute value of argument given +-Arguments: +- x - argument +-Return: +- absolute value of x +-*******************************************************************************/ +-/* define ABS */ +-#define ABS(x) (((x) < 0) ? -(x) : (x)) +- + /* regular format macros */ + /******************************************************************************* + Description: diff --git a/package/kernel/lantiq/ltq-vmmc/patches/603-fix-signature.patch b/package/kernel/lantiq/ltq-vmmc/patches/603-fix-signature.patch new file mode 100644 index 0000000000..b99255692b --- /dev/null +++ b/package/kernel/lantiq/ltq-vmmc/patches/603-fix-signature.patch @@ -0,0 +1,37 @@ +--- a/src/drv_vmmc_init.c ++++ b/src/drv_vmmc_init.c +@@ -202,11 +202,20 @@ IFX_int32_t VMMC_GetDevice (IFX_uint16_t + /** + Wrapper for the voice buffer get function that sets the FW as owner. + */ +-static IFX_void_t* vmmc_WrapperVoiceBufferGet (IFX_void_t) ++static IFX_void_t* vmmc_WrapperVoiceBufferGet (IFX_size_t size, ++ IFX_int32_t priority) + { + return IFX_TAPI_VoiceBufferGetWithOwnerId (IFX_TAPI_BUFFER_OWNER_FW); + } + ++/** ++ Wrapper for the voice buffer get function that sets the FW as owner. ++*/ ++static IFX_void_t vmmc_WrapperVoiceBufferPut (const IFX_void_t *ptr) ++{ ++ IFX_TAPI_VoiceBufferPut ((IFX_void_t *)ptr); ++} ++ + + /** + Wrapper for the voice buffer free all function freeing all buffers that +@@ -263,10 +272,8 @@ IFX_int32_t VMMC_ChipAccessInit(VMMC_DEV + + /* Register the buffer handler. */ + #ifdef USE_BUFFERPOOL +- ifx_mps_bufman_register((IFX_void_t* (*)(IFX_size_t, IFX_int32_t)) +- vmmc_WrapperVoiceBufferGet, +- (IFX_void_t (*)(const IFX_void_t*)) +- IFX_TAPI_VoiceBufferPut, ++ ifx_mps_bufman_register(vmmc_WrapperVoiceBufferGet, ++ vmmc_WrapperVoiceBufferPut, + sizeof(PACKET), POBX_BUFFER_THRESHOLD); + ifx_mps_register_bufman_freeall_callback (vmmc_WrapperVoiceBufferFreeAll); + #else diff --git a/package/kernel/lantiq/ltq-vmmc/patches/604-fix-write-beyond-size-of-field.patch b/package/kernel/lantiq/ltq-vmmc/patches/604-fix-write-beyond-size-of-field.patch new file mode 100644 index 0000000000..a7343914ac --- /dev/null +++ b/package/kernel/lantiq/ltq-vmmc/patches/604-fix-write-beyond-size-of-field.patch @@ -0,0 +1,66 @@ +--- a/src/drv_vmmc_fw_commands.h ++++ b/src/drv_vmmc_fw_commands.h +@@ -4628,26 +4628,28 @@ struct RES_DTMFATG_COEF + struct CDM_RES_DTMFATG_DATA + { + CMD_HEAD_BE; +- /** Frequency 1 1st Tone or Dual Tone Control Word 1 */ +- IFX_uint16_t FREQ11_DTC1; +- /** Frequency 2 1st Tone or Dual Tone Control Word 2 */ +- IFX_uint16_t FREQ21_DTC2; +- /** Frequency 1 2nd Tone */ +- IFX_uint16_t FREQ12_DTC3; +- /** Frequency 2 2nd Tone */ +- IFX_uint16_t FREQ22_DTC4; +- /** Frequency 1 3rd Tone */ +- IFX_uint16_t FREQ13_DTC5; +- /** Frequency 2 3nd Tone */ +- IFX_uint16_t FREQ23_DTC6; +- /** Frequency 1 4th Tone */ +- IFX_uint16_t FREQ14_DTC7; +- /** Frequency 2 4th Tone */ +- IFX_uint16_t FREQ24_DTC8; +- /** Frequency 1 5th Tone */ +- IFX_uint16_t FREQ15_DTC9; +- /** Frequency 2 5th Tone */ +- IFX_uint16_t FREQ25_DTC10; ++ struct_group(FREQS, ++ /** Frequency 1 1st Tone or Dual Tone Control Word 1 */ ++ IFX_uint16_t FREQ11_DTC1; ++ /** Frequency 2 1st Tone or Dual Tone Control Word 2 */ ++ IFX_uint16_t FREQ21_DTC2; ++ /** Frequency 1 2nd Tone */ ++ IFX_uint16_t FREQ12_DTC3; ++ /** Frequency 2 2nd Tone */ ++ IFX_uint16_t FREQ22_DTC4; ++ /** Frequency 1 3rd Tone */ ++ IFX_uint16_t FREQ13_DTC5; ++ /** Frequency 2 3nd Tone */ ++ IFX_uint16_t FREQ23_DTC6; ++ /** Frequency 1 4th Tone */ ++ IFX_uint16_t FREQ14_DTC7; ++ /** Frequency 2 4th Tone */ ++ IFX_uint16_t FREQ24_DTC8; ++ /** Frequency 1 5th Tone */ ++ IFX_uint16_t FREQ15_DTC9; ++ /** Frequency 2 5th Tone */ ++ IFX_uint16_t FREQ25_DTC10; ++ ); + } __PACKED__ ; + + +--- a/src/drv_vmmc_sig_dtmfg.c ++++ b/src/drv_vmmc_sig_dtmfg.c +@@ -742,10 +742,8 @@ IFX_int32_t irq_VMMC_SIG_DtmfOnRequest(V + /* Get a pointer to the data area which is behind the header of the cmd */ + pAtgCmd = &pDtmfAtgData->FREQ11_DTC1; + +- /* Wipe the data area in the command. The size of this area is +- command size - header size. */ +- /*lint -e(419) */ +- memset (pAtgCmd, 0x00, sizeof(CDM_RES_DTMFATG_DATA_t) - CMD_HDR_CNT); ++ /* Wipe the data area in the command. */ ++ memset (&pDtmfAtgData->FREQS, 0x00, sizeof(pDtmfAtgData->FREQS)); + + /* Fill the data area */ + if (pDtmf->bByteMode == IFX_TRUE) diff --git a/package/kernel/lantiq/ltq-vmmc/patches/605-get-irqs-from-kernel-in-tree-vmmc-driver.patch b/package/kernel/lantiq/ltq-vmmc/patches/605-get-irqs-from-kernel-in-tree-vmmc-driver.patch new file mode 100644 index 0000000000..0ebaef3b9d --- /dev/null +++ b/package/kernel/lantiq/ltq-vmmc/patches/605-get-irqs-from-kernel-in-tree-vmmc-driver.patch @@ -0,0 +1,89 @@ +--- a/src/mps/drv_mps_vmmc_linux.c ++++ b/src/mps/drv_mps_vmmc_linux.c +@@ -104,6 +104,10 @@ extern irqreturn_t ifx_mps_vc_irq (IFX_i + extern IFX_void_t ifx_mps_shutdown (IFX_void_t); + extern IFX_int32_t ifx_mps_event_activation_poll (mps_devices type, + MbxEventRegs_s * act); ++extern unsigned int ltq_get_mps_ad0_irq(void); ++extern unsigned int ltq_get_mps_ad1_irq(void); ++extern unsigned int ltq_get_mps_vc_irq(int idx); ++ + mps_mbx_dev *ifx_mps_get_device (mps_devices type); + + #ifdef CONFIG_PROC_FS +@@ -2260,7 +2264,7 @@ IFX_int32_t __init ifx_mps_init_module ( + /* reset the device before initializing the device driver */ + ifx_mps_reset (); + +- result = request_irq (INT_NUM_IM4_IRL18, ++ result = request_irq (ltq_get_mps_ad0_irq(), + #ifdef LINUX_2_6 + ifx_mps_ad0_irq, 0x0 + #else /* */ +@@ -2270,7 +2274,7 @@ IFX_int32_t __init ifx_mps_init_module ( + , "mps_mbx ad0", &ifx_mps_dev); + if (result) + return result; +- result = request_irq (INT_NUM_IM4_IRL19, ++ result = request_irq (ltq_get_mps_ad1_irq(), + #ifdef LINUX_2_6 + ifx_mps_ad1_irq, 0x0 + #else /* */ +@@ -2285,7 +2289,7 @@ IFX_int32_t __init ifx_mps_init_module ( + for (i = 0; i < 4; ++i) + { + sprintf (&voice_channel_int_name[i][0], "mps_mbx vc%d", i); +- result = request_irq (INT_NUM_IM4_IRL14 + i, ++ result = request_irq (ltq_get_mps_vc_irq(i), + #ifdef LINUX_2_6 + ifx_mps_vc_irq, 0x0 + #else /* */ +@@ -2446,13 +2450,13 @@ ifx_mps_cleanup_module (IFX_void_t) + ifx_mps_release_structures (&ifx_mps_dev); + + /* release all interrupts at the system */ +- free_irq (INT_NUM_IM4_IRL18, &ifx_mps_dev); +- free_irq (INT_NUM_IM4_IRL19, &ifx_mps_dev); ++ free_irq (ltq_get_mps_ad0_irq(), &ifx_mps_dev); ++ free_irq (ltq_get_mps_ad1_irq(), &ifx_mps_dev); + + /* register status interrupts for voice channels */ + for (i = 0; i < 4; ++i) + { +- free_irq (INT_NUM_IM4_IRL14 + i, &ifx_mps_dev); ++ free_irq (ltq_get_mps_vc_irq(i), &ifx_mps_dev); + } + #ifdef CONFIG_PROC_FS + #if CONFIG_MPS_HISTORY_SIZE > 0 +--- a/src/mps/drv_mps_vmmc_common.c ++++ b/src/mps/drv_mps_vmmc_common.c +@@ -134,6 +134,8 @@ extern IFX_void_t mask_and_ack_danube_ir + + #endif /* */ + ++extern unsigned int ltq_get_mps_vc_irq(int idx); ++ + extern void sys_hw_setup (void); + + extern IFXOS_event_t fw_ready_evt; +@@ -2979,7 +2981,7 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t + */ + irqreturn_t ifx_mps_vc_irq (IFX_int32_t irq, mps_comm_dev * pDev) + { +- IFX_uint32_t chan = irq - INT_NUM_IM4_IRL14; ++ IFX_uint32_t chan = irq - ltq_get_mps_vc_irq(0); + mps_mbx_dev *mbx_dev = (mps_mbx_dev *) & (pMPSDev->voice_mb[chan]); + MPS_VCStatReg_u MPS_VCStatusReg; + MbxEventRegs_s events; +--- a/src/mps/drv_mps_vmmc_device.h ++++ b/src/mps/drv_mps_vmmc_device.h +@@ -69,9 +69,6 @@ + # define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR + # define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR + /* interrupt vectors */ +-# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) +-# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) +-# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) + # define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER + + /* ============================= */ diff --git a/package/kernel/mac80211/realtek.mk b/package/kernel/mac80211/realtek.mk index 04057b3106..28ea6a6571 100644 --- a/package/kernel/mac80211/realtek.mk +++ b/package/kernel/mac80211/realtek.mk @@ -1,6 +1,6 @@ PKG_DRIVERS += \ rtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \ - rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723bs rtl8821ae \ + rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \ rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \ rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \ rtw88-8822ce rtw88-8822cu rtw88-8723de @@ -20,6 +20,9 @@ config-$(CONFIG_PACKAGE_RTLWIFI_DEBUG) += RTLWIFI_DEBUG config-$(call config_package,rtl8xxxu) += RTL8XXXU config-y += RTL8XXXU_UNTESTED +config-$(call config_package,rtl8723-common) += RTL8723_COMMON +config-$(call config_package,rtl8723be) += RTL8723BE + config-$(call config_package,rtl8723bs) += RTL8723BS config-y += STAGING @@ -299,6 +302,22 @@ define KernelPackage/rtw88-8723de AUTOLOAD:=$(call AutoProbe,rtw88_8723) endef +define KernelPackage/rtl8723-common + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8723AE/RTL8723BE common support module + DEPENDS+= +kmod-rtlwifi + FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.ko + HIDDEN:=1 +endef + +define KernelPackage/rtl8723be + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8723AE/RTL8723BE support + DEPENDS+= +kmod-rtlwifi-btcoexist +kmod-rtlwifi-pci +kmod-rtl8723-common +rtl8723be-firmware + FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.ko + AUTOLOAD:=$(call AutoProbe,rtl8723be) +endef + define KernelPackage/rtl8723bs $(call KernelPackage/mac80211/Default) TITLE:=Realtek RTL8723BS SDIO Wireless LAN NIC driver (staging) diff --git a/package/kernel/qca-ssdk/Makefile b/package/kernel/qca-ssdk/Makefile index ed18f17504..de262e6578 100644 --- a/package/kernel/qca-ssdk/Makefile +++ b/package/kernel/qca-ssdk/Makefile @@ -1,7 +1,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qca-ssdk -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git PKG_SOURCE_PROTO:=git @@ -45,6 +45,7 @@ MAKE_FLAGS+= \ GCC_VERSION=$(GCC_VERSION) \ EXTRA_CFLAGS="-fno-stack-protector -I$(STAGING_DIR)/usr/include" \ SoC=$(CONFIG_TARGET_SUBTARGET) \ + SHELL="$(BASH)" \ PTP_FEATURE=disable SWCONFIG_FEATURE=disable \ ISISC_ENABLE=disable IN_QCA803X_PHY=FALSE \ IN_QCA808X_PHY=FALSE IN_MALIBU_PHY=FALSE \ diff --git a/package/kernel/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch b/package/kernel/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch new file mode 100644 index 0000000000..d93cf0978c --- /dev/null +++ b/package/kernel/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch @@ -0,0 +1,33 @@ +From ab3b663842f66d0ed290696cee9edb9070a36e8f Mon Sep 17 00:00:00 2001 +From: Paweł Owoc +Date: Wed, 7 May 2024 10:37:44 +0100 +Subject: [PATCH] hsl_phy: add support for AQR114C-B0 PHY + +Add support for AQR114C-B0 PHY. + +Signed-off-by: Paweł Owoc +--- + include/hsl/phy/hsl_phy.h | 1 + + src/hsl/phy/hsl_phy.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/include/hsl/phy/hsl_phy.h ++++ b/include/hsl/phy/hsl_phy.h +@@ -612,6 +612,7 @@ typedef struct { + #define AQUANTIA_PHY_113C_B0 0x31c31C12 + #define AQUANTIA_PHY_113C_B1 0x31c31C13 + #define AQUANTIA_PHY_112C 0x03a1b792 ++#define AQUANTIA_PHY_114C_B0 0x31c31c22 + #define MVL_PHY_X3410 0x31c31DD3 + + #define PHY_805XV2 0x004DD082 +--- a/src/hsl/phy/hsl_phy.c ++++ b/src/hsl/phy/hsl_phy.c +@@ -271,6 +271,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_uint32_t dev_id, a_uint32_t phy_id) + case AQUANTIA_PHY_113C_B0: + case AQUANTIA_PHY_113C_B1: + case AQUANTIA_PHY_112C: ++ case AQUANTIA_PHY_114C_B0: + case MVL_PHY_X3410: + phytype = AQUANTIA_PHY_CHIP; + break; diff --git a/package/kernel/ubnt-ledbar/src/leds-ubnt-ledbar.c b/package/kernel/ubnt-ledbar/src/leds-ubnt-ledbar.c index ee9d34601c..e0516322dc 100644 --- a/package/kernel/ubnt-ledbar/src/leds-ubnt-ledbar.c +++ b/package/kernel/ubnt-ledbar/src/leds-ubnt-ledbar.c @@ -9,7 +9,6 @@ #include #include #include -#include /** * Driver for the Ubiquiti RGB LED controller (LEDBAR). @@ -167,9 +166,7 @@ static int ubnt_ledbar_init_led(struct device_node *np, struct ubnt_ledbar *ledb return ret; } - -static int ubnt_ledbar_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int ubnt_ledbar_probe(struct i2c_client *client) { struct device_node *np = client->dev.of_node; struct ubnt_ledbar *ledbar; @@ -219,19 +216,11 @@ static int ubnt_ledbar_probe(struct i2c_client *client, return ubnt_ledbar_apply_state(ledbar); } -#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0) -static int ubnt_ledbar_remove(struct i2c_client *client) -#else static void ubnt_ledbar_remove(struct i2c_client *client) -#endif { struct ubnt_ledbar *ledbar = i2c_get_clientdata(client); mutex_destroy(&ledbar->lock); - -#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0) - return 0; -#endif } static const struct i2c_device_id ubnt_ledbar_id[] = { diff --git a/package/system/mtd/src/trx.c b/package/system/mtd/src/trx.c index d7c5d832c4..494cc3c91e 100644 --- a/package/system/mtd/src/trx.c +++ b/package/system/mtd/src/trx.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -165,7 +166,7 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size) size_t block_offset; if (quiet < 2) - fprintf(stderr, "Trying to fix trx header in %s at 0x%x...\n", mtd, offset); + fprintf(stderr, "Trying to fix trx header in %s at 0x%zx...\n", mtd, offset); fd = mtd_check_open(mtd); if(fd < 0) { @@ -246,7 +247,7 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size) trx->crc32 = STORE32_LE(crc32buf(buf, data_size)); if (mtd_erase_block(fd, block_offset)) { - fprintf(stderr, "Can't erease block at 0x%x (%s)\n", block_offset, strerror(errno)); + fprintf(stderr, "Can't erease block at 0x%zx (%s)\n", block_offset, strerror(errno)); exit(1); } diff --git a/package/system/opkg/files/20_migrate-feeds b/package/system/opkg/files/20_migrate-feeds index 38cc57c467..a4bd725758 100644 --- a/package/system/opkg/files/20_migrate-feeds +++ b/package/system/opkg/files/20_migrate-feeds @@ -1,6 +1,6 @@ #!/bin/sh -[ -f /etc/opkg.conf ] && grep -q "src\/" /etc/opkg.conf || exit 0 +[ -f /etc/opkg.conf ] && grep -q "src/" /etc/opkg.conf || exit 0 echo -e "# Old feeds from previous image\n# Uncomment to reenable\n" >> /etc/opkg/customfeeds.conf sed -n "s/.*\(src\/.*\)/# \1/p" /etc/opkg.conf >> /etc/opkg/customfeeds.conf diff --git a/package/utils/audit/Makefile b/package/utils/audit/Makefile index e36e3ebd53..50c4729b84 100644 --- a/package/utils/audit/Makefile +++ b/package/utils/audit/Makefile @@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=audit-userspace PKG_VERSION:=3.1.4 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/linux-audit/audit-userspace/archive/refs/tags/v$(PKG_VERSION).tar.gz? PKG_HASH:=aec501760acd13ebbe00e78b9b59f795d16a430b1d673628e346cd18905c594b diff --git a/package/utils/audit/patches/0001-Implicit-builtin-functions.patch b/package/utils/audit/patches/0001-Implicit-builtin-functions.patch new file mode 100644 index 0000000000..3cb275bd35 --- /dev/null +++ b/package/utils/audit/patches/0001-Implicit-builtin-functions.patch @@ -0,0 +1,615 @@ +From 429d031edd52566eeba03c3b3af32ad6e103fd94 Mon Sep 17 00:00:00 2001 +From: Steve Grubb +Date: Fri, 3 May 2024 17:33:39 -0400 +Subject: [PATCH] Implicit builtin functions + +Correct a number of places where printf is being used without a prototype. +All cases are in libraries which should not be using printf. Change them +to return an error rather than communicate the problem. + +This is a backport of 8c7eaa7 +--- + audisp/audispd-llist.c | 10 +++++----- + audisp/audispd-llist.h | 4 ++-- + auparse/normalize-llist.c | 12 ++++++------ + auparse/normalize-llist.h | 4 ++-- + auparse/normalize.c | 14 +++++++++----- + src/auditctl-llist.c | 18 +++++++++--------- + src/auditctl-llist.h | 4 ++-- + src/ausearch-avc.c | 16 ++++++++-------- + src/ausearch-avc.h | 4 ++-- + src/ausearch-int.c | 12 ++++++------ + src/ausearch-int.h | 4 ++-- + src/ausearch-llist.c | 14 +++++++------- + src/ausearch-llist.h | 2 +- + src/ausearch-nvpair.c | 12 ++++++------ + src/ausearch-nvpair.h | 4 ++-- + src/ausearch-string.c | 10 +++++----- + src/ausearch-string.h | 2 +- + tools/aulastlog/aulastlog-llist.c | 18 +++++++++--------- + tools/aulastlog/aulastlog-llist.h | 4 ++-- + 19 files changed, 86 insertions(+), 82 deletions(-) + +--- a/audisp/audispd-llist.c ++++ b/audisp/audispd-llist.c +@@ -69,15 +69,13 @@ unsigned int plist_count_active(const co + return cnt; + } + +-void plist_append(conf_llist *l, plugin_conf_t *p) ++int plist_append(conf_llist *l, plugin_conf_t *p) + { + lnode* newnode; + + newnode = malloc(sizeof(lnode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + if (p) { + void *pp = malloc(sizeof(struct plugin_conf)); +@@ -98,6 +96,8 @@ void plist_append(conf_llist *l, plugin_ + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + void plist_clear(conf_llist* l) +--- a/audisp/audispd-llist.h ++++ b/audisp/audispd-llist.h +@@ -1,6 +1,6 @@ + /* + * audispd-llist.h - Header file for ausearch-conf_llist.c +-* Copyright (c) 2007,2013 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2007,2013 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -51,7 +51,7 @@ unsigned int plist_count_active(const co + void plist_last(conf_llist *l); + lnode *plist_next(conf_llist *l); + static inline lnode *plist_get_cur(conf_llist *l) { return l->cur; } +-void plist_append(conf_llist *l, plugin_conf_t *p); ++int plist_append(conf_llist *l, plugin_conf_t *p); + void plist_clear(conf_llist* l); + void plist_mark_all_unchecked(conf_llist* l); + lnode *plist_find_unchecked(conf_llist* l); +--- a/auparse/normalize-llist.c ++++ b/auparse/normalize-llist.c +@@ -1,6 +1,6 @@ + /* + * normalize-llist.c - Minimal linked list library +- * Copyright (c) 2016-17 Red Hat Inc., Durham, North Carolina. ++ * Copyright (c) 2016-17 Red Hat Inc. + * All Rights Reserved. + * + * This library is free software; you can redistribute it and/or +@@ -61,15 +61,14 @@ data_node *cllist_next(cllist *l) + return l->cur; + } + +-void cllist_append(cllist *l, uint32_t num, void *data) ++// Returns 0 on success and 1 on error ++int cllist_append(cllist *l, uint32_t num, void *data) + { + data_node *newnode; + + newnode = malloc(sizeof(data_node)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + newnode->num = num; + newnode->data = data; +@@ -84,5 +83,6 @@ void cllist_append(cllist *l, uint32_t n + // make newnode current + l->cur = newnode; + l->cnt++; ++ return 0; + } + +--- a/auparse/normalize-llist.h ++++ b/auparse/normalize-llist.h +@@ -1,6 +1,6 @@ + /* + * normalize-llist.h - Header file for normalize-llist.c +- * Copyright (c) 2016-17 Red Hat Inc., Durham, North Carolina. ++ * Copyright (c) 2016-17 Red Hat Inc. + * All Rights Reserved. + * + * This library is free software; you can redistribute it and/or +@@ -53,7 +53,7 @@ AUDIT_HIDDEN_START + void cllist_create(cllist *l, void (*cleanup)(void *)); + void cllist_clear(cllist* l); + data_node *cllist_next(cllist *l); +-void cllist_append(cllist *l, uint32_t num, void *data); ++int cllist_append(cllist *l, uint32_t num, void *data); + + AUDIT_HIDDEN_END + +--- a/auparse/normalize.c ++++ b/auparse/normalize.c +@@ -179,7 +179,8 @@ static unsigned int add_subj_attr(aupars + if ((auparse_find_field(au, str))) { + attr = set_record(0, rnum); + attr = set_field(attr, auparse_get_field_num(au)); +- cllist_append(&D.actor.attr, attr, NULL); ++ if (cllist_append(&D.actor.attr, attr, NULL)) ++ return 1; + return 0; + } else + auparse_goto_record_num(au, rnum); +@@ -224,7 +225,8 @@ static unsigned int add_obj_attr(auparse + if ((auparse_find_field(au, str))) { + attr = set_record(0, rnum); + attr = set_field(attr, auparse_get_field_num(au)); +- cllist_append(&D.thing.attr, attr, NULL); ++ if (cllist_append(&D.thing.attr, attr, NULL)) ++ return 1; + return 0; + } else + auparse_goto_record_num(au, rnum); +@@ -360,21 +362,23 @@ static void collect_id_obj2(auparse_stat + } + } + +-static void collect_path_attrs(auparse_state_t *au) ++static int collect_path_attrs(auparse_state_t *au) + { + value_t attr; + unsigned int rnum = auparse_get_record_num(au); + + auparse_first_field(au); + if (add_obj_attr(au, "mode", rnum)) +- return; // Failed opens don't have anything else ++ return 1; // Failed opens don't have anything else + + // All the rest of the fields matter + while ((auparse_next_field(au))) { + attr = set_record(0, rnum); + attr = set_field(attr, auparse_get_field_num(au)); +- cllist_append(&D.thing.attr, attr, NULL); ++ if (cllist_append(&D.thing.attr, attr, NULL)) ++ return 1; + } ++ return 0; + } + + static void collect_cwd_attrs(auparse_state_t *au) +--- a/src/auditctl-llist.c ++++ b/src/auditctl-llist.c +@@ -1,7 +1,7 @@ + /* + * ausearch-llist.c - Minimal linked list library +-* Copyright (c) 2005 Red Hat Inc., Durham, North Carolina. +-* All Rights Reserved. ++* Copyright (c) 2005 Red Hat Inc. ++* All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the + * terms of the GNU General Public License as published by the Free +@@ -15,7 +15,7 @@ + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to the +-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor ++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor + * Boston, MA 02110-1335, USA. + * + * Authors: +@@ -59,19 +59,17 @@ lnode *list_next(llist *l) + return l->cur; + } + +-void list_append(llist *l, struct audit_rule_data *r, size_t sz) ++int list_append(llist *l, struct audit_rule_data *r, size_t sz) + { + lnode* newnode; + + newnode = malloc(sizeof(lnode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + if (r) { + void *rr = malloc(sz); +- if (rr) ++ if (rr) + memcpy(rr, r, sz); + newnode->r = rr; + } else +@@ -89,6 +87,8 @@ void list_append(llist *l, struct audit_ + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + void list_clear(llist* l) +--- a/src/auditctl-llist.h ++++ b/src/auditctl-llist.h +@@ -1,6 +1,6 @@ + /* + * auditctl-llist.h - Header file for ausearch-llist.c +-* Copyright (c) 2005 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2005 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -50,7 +50,7 @@ void list_first(llist *l); + void list_last(llist *l); + lnode *list_next(llist *l); + static inline lnode *list_get_cur(llist *l) { return l->cur; } +-void list_append(llist *l, struct audit_rule_data *r, size_t sz); ++int list_append(llist *l, struct audit_rule_data *r, size_t sz); + void list_clear(llist* l); + + #endif +--- a/src/ausearch-avc.c ++++ b/src/ausearch-avc.c +@@ -1,7 +1,7 @@ + /* + * ausearch-avc.c - Minimal linked list library for avcs +-* Copyright (c) 2006,2008,2014 Red Hat Inc., Durham, North Carolina. +-* All Rights Reserved. ++* Copyright (c) 2006,2008,2014 Red Hat Inc. ++* All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the + * terms of the GNU General Public License as published by the Free +@@ -15,7 +15,7 @@ + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to the +-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor ++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor + * Boston, MA 02110-1335, USA. + * + * Authors: +@@ -62,15 +62,13 @@ static void alist_last(alist *l) + l->cur = cur; + } + +-void alist_append(alist *l, anode *node) ++int alist_append(alist *l, anode *node) + { + anode* newnode; + + newnode = malloc(sizeof(anode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + if (node->scontext) + newnode->scontext = node->scontext; +@@ -108,6 +106,8 @@ void alist_append(alist *l, anode *node) + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + int alist_find_subj(alist *l) +--- a/src/ausearch-avc.h ++++ b/src/ausearch-avc.h +@@ -1,6 +1,6 @@ + /* + * ausearch-avc.h - Header file for ausearch-string.c +-* Copyright (c) 2006,2008 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2006,2008 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -54,7 +54,7 @@ void alist_create(alist *l); + static inline void alist_first(alist *l) { l->cur = l->head; } + anode *alist_next(alist *l); + static inline anode *alist_get_cur(alist *l) { return l->cur; } +-void alist_append(alist *l, anode *node); ++int alist_append(alist *l, anode *node); + void anode_init(anode *an); + void anode_clear(anode *an); + void alist_clear(alist* l); +--- a/src/ausearch-int.c ++++ b/src/ausearch-int.c +@@ -1,6 +1,6 @@ + /* + * ausearch-int.c - Minimal linked list library for integers +-* Copyright (c) 2005,2008 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2005,2008 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -41,15 +41,13 @@ int_node *ilist_next(ilist *l) + return l->cur; + } + +-void ilist_append(ilist *l, int num, unsigned int hits, int aux) ++int ilist_append(ilist *l, int num, unsigned int hits, int aux) + { + int_node* newnode; + + newnode = malloc(sizeof(int_node)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + newnode->num = num; + newnode->hits = hits; +@@ -65,6 +63,8 @@ void ilist_append(ilist *l, int num, uns + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + void ilist_clear(ilist* l) +--- a/src/ausearch-int.h ++++ b/src/ausearch-int.h +@@ -1,6 +1,6 @@ + /* + * ausearch-int.h - Header file for ausearch-int.c +-* Copyright (c) 2005,2008 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2005,2008 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -48,7 +48,7 @@ void ilist_create(ilist *l); + static inline void ilist_first(ilist *l) { l->cur = l->head; } + int_node *ilist_next(ilist *l); + static inline int_node *ilist_get_cur(ilist *l) { return l->cur; } +-void ilist_append(ilist *l, int num, unsigned int hits, int aux); ++int ilist_append(ilist *l, int num, unsigned int hits, int aux); + void ilist_clear(ilist* l); + + /* append a number if its not already on the list */ +--- a/src/ausearch-llist.c ++++ b/src/ausearch-llist.c +@@ -1,6 +1,6 @@ + /* + * ausearch-llist.c - Minimal linked list library +-* Copyright (c) 2005-2008,2011,2016 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2005-2008,2011,2016 Red Hat Inc. + * Copyright (c) 2011 IBM Corp. + * All Rights Reserved. + * +@@ -102,15 +102,13 @@ lnode *list_prev(llist *l) + return l->cur; + } + +-void list_append(llist *l, lnode *node) ++int list_append(llist *l, lnode *node) + { + lnode* newnode; + + newnode = malloc(sizeof(lnode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + if (node->message) + newnode->message = node->message; +@@ -123,7 +121,7 @@ void list_append(llist *l, lnode *node) + newnode->type = node->type; + newnode->a0 = node->a0; + newnode->a1 = node->a1; +- newnode->item = l->cnt; ++ newnode->item = l->cnt; + newnode->next = NULL; + + // if we are at top, fix this up +@@ -135,6 +133,8 @@ void list_append(llist *l, lnode *node) + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + int list_find_item(llist *l, unsigned int i) +--- a/src/ausearch-llist.h ++++ b/src/ausearch-llist.h +@@ -107,7 +107,7 @@ void list_last(llist *l); + lnode *list_next(llist *l); + lnode *list_prev(llist *l); + static inline lnode *list_get_cur(llist *l) { return l->cur; } +-void list_append(llist *l, lnode *node); ++int list_append(llist *l, lnode *node); + void list_clear(llist* l); + int list_get_event(llist* l, event *e); + +--- a/src/ausearch-nvpair.c ++++ b/src/ausearch-nvpair.c +@@ -1,6 +1,6 @@ + /* + * ausearch-nvpair.c - Minimal linked list library for name-value pairs +-* Copyright (c) 2006-08 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2006-08 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -42,13 +42,11 @@ nvnode *search_list_next(nvlist *l) + return l->cur; + } + +-void search_list_append(nvlist *l, nvnode *node) ++int search_list_append(nvlist *l, nvnode *node) + { + nvnode* newnode = malloc(sizeof(nvnode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + newnode->name = node->name; + newnode->val = node->val; +@@ -66,6 +64,8 @@ void search_list_append(nvlist *l, nvnod + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + int search_list_find_val(nvlist *l, long val) +--- a/src/ausearch-nvpair.h ++++ b/src/ausearch-nvpair.h +@@ -1,6 +1,6 @@ + /* + * ausearch-nvpair.h - Header file for ausearch-nvpair.c +-* Copyright (c) 2006-08 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2006-08 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -48,7 +48,7 @@ void search_list_create(nvlist *l); + static inline void search_list_first(nvlist *l) { l->cur = l->head; } + nvnode *search_list_next(nvlist *l); + static inline nvnode *search_list_get_cur(nvlist *l) { return l->cur; } +-void search_list_append(nvlist *l, nvnode *node); ++int search_list_append(nvlist *l, nvnode *node); + void search_list_clear(nvlist* l); + + /* Given a numeric index, find that record. */ +--- a/src/ausearch-string.c ++++ b/src/ausearch-string.c +@@ -44,15 +44,13 @@ snode *slist_next(slist *l) + return l->cur; + } + +-void slist_append(slist *l, snode *node) ++int slist_append(slist *l, snode *node) + { + snode* newnode; + + newnode = malloc(sizeof(snode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + if (node->str) + newnode->str = node->str; +@@ -79,6 +77,8 @@ void slist_append(slist *l, snode *node) + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + void slist_clear(slist* l) +--- a/src/ausearch-string.h ++++ b/src/ausearch-string.h +@@ -49,7 +49,7 @@ void slist_create(slist *l); + static inline void slist_first(slist *l) { l->cur = l->head; } + snode *slist_next(slist *l); + static inline snode *slist_get_cur(slist *l) { return l->cur; } +-void slist_append(slist *l, snode *node); ++int slist_append(slist *l, snode *node); + void slist_clear(slist* l); + + /* append a string if its not already on the list */ +--- a/tools/aulastlog/aulastlog-llist.c ++++ b/tools/aulastlog/aulastlog-llist.c +@@ -1,7 +1,7 @@ + /* + * aulastlog-llist.c - Minimal linked list library +-* Copyright (c) 2008 Red Hat Inc., Durham, North Carolina. +-* All Rights Reserved. ++* Copyright (c) 2008 Red Hat Inc.. ++* All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the + * terms of the GNU General Public License as published by the Free +@@ -15,7 +15,7 @@ + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to the +-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor ++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor + * Boston, MA 02110-1335, USA. + * + * Authors: +@@ -41,15 +41,13 @@ lnode *list_next(llist *l) + return l->cur; + } + +-void list_append(llist *l, lnode *node) ++int list_append(llist *l, lnode *node) + { + lnode* newnode; + + newnode = malloc(sizeof(lnode)); +- if (newnode == NULL) { +- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__); +- return; +- } ++ if (newnode == NULL) ++ return 1; + + newnode->sec = node->sec; + newnode->uid = node->uid; +@@ -62,7 +60,7 @@ void list_append(llist *l, lnode *node) + newnode->term = strdup(node->term); + else + newnode->term = NULL; +- newnode->item = l->cnt; ++ newnode->item = l->cnt; + newnode->next = NULL; + + // if we are at top, fix this up +@@ -74,6 +72,8 @@ void list_append(llist *l, lnode *node) + // make newnode current + l->cur = newnode; + l->cnt++; ++ ++ return 0; + } + + void list_clear(llist* l) +--- a/tools/aulastlog/aulastlog-llist.h ++++ b/tools/aulastlog/aulastlog-llist.h +@@ -1,6 +1,6 @@ + /* + * aulastlog-llist.h - Header file for aulastlog-llist.c +-* Copyright (c) 2008 Red Hat Inc., Durham, North Carolina. ++* Copyright (c) 2008 Red Hat Inc. + * All Rights Reserved. + * + * This software may be freely redistributed and/or modified under the +@@ -53,7 +53,7 @@ static inline void list_first(llist *l) + lnode *list_next(llist *l); + static inline lnode *list_get_cur(llist *l) { return l->cur; } + static inline unsigned int list_get_cnt(llist *l) { return l->cnt; } +-void list_append(llist *l, lnode *node); ++int list_append(llist *l, lnode *node); + void list_clear(llist* l); + int list_update_login(llist* l, time_t t); + int list_update_host(llist* l, const char *h); diff --git a/target/linux/airoha/Makefile b/target/linux/airoha/Makefile index 0a66ef839c..50c871edaa 100644 --- a/target/linux/airoha/Makefile +++ b/target/linux/airoha/Makefile @@ -7,6 +7,7 @@ CPU_TYPE:=cortex-a7 FEATURES:=dt squashfs nand ramdisk gpio source-only KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/airoha/config-6.6 b/target/linux/airoha/config-6.6 new file mode 100644 index 0000000000..ce93f7d9ff --- /dev/null +++ b/target/linux/airoha/config-6.6 @@ -0,0 +1,303 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AIROHA=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_EN7523=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DMA_OPS=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_EN7523=y +CONFIG_GPIO_GENERIC=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PINCTRL=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_AIROHA_EN7523=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_STACKTRACE=y +# CONFIG_SWAP is not set +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch new file mode 100644 index 0000000000..30ba1ab412 --- /dev/null +++ b/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch @@ -0,0 +1,341 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -353,6 +353,12 @@ config SPI_DLN2 + This driver can also be built as a module. If so, the module + will be called spi-dln2. + ++config SPI_AIROHA_EN7523 ++ bool "Airoha EN7523 SPI controller support" ++ depends on ARCH_AIROHA ++ help ++ This enables SPI controller support for the Airoha EN7523 SoC. ++ + config SPI_EP93XX + tristate "Cirrus Logic EP93xx SPI controller" + depends on ARCH_EP93XX || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1. + obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o + obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o + obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o ++obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o + obj-$(CONFIG_SPI_FALCON) += spi-falcon.o + obj-$(CONFIG_SPI_FSI) += spi-fsi.o + obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o +--- /dev/null ++++ b/drivers/spi/spi-en7523.c +@@ -0,0 +1,313 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++ ++ ++#define ENSPI_READ_IDLE_EN 0x0004 ++#define ENSPI_MTX_MODE_TOG 0x0014 ++#define ENSPI_RDCTL_FSM 0x0018 ++#define ENSPI_MANUAL_EN 0x0020 ++#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024 ++#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028 ++#define ENSPI_MANUAL_OPFIFO_FULL 0x002C ++#define ENSPI_MANUAL_OPFIFO_WR 0x0030 ++#define ENSPI_MANUAL_DFIFO_FULL 0x0034 ++#define ENSPI_MANUAL_DFIFO_WDATA 0x0038 ++#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C ++#define ENSPI_MANUAL_DFIFO_RD 0x0040 ++#define ENSPI_MANUAL_DFIFO_RDATA 0x0044 ++#define ENSPI_IER 0x0090 ++#define ENSPI_NFI2SPI_EN 0x0130 ++ ++// TODO not in spi block ++#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4) ++ ++#define OP_CSH 0x00 ++#define OP_CSL 0x01 ++#define OP_CK 0x02 ++#define OP_OUTS 0x08 ++#define OP_OUTD 0x09 ++#define OP_OUTQ 0x0A ++#define OP_INS 0x0C ++#define OP_INS0 0x0D ++#define OP_IND 0x0E ++#define OP_INQ 0x0F ++#define OP_OS2IS 0x10 ++#define OP_OS2ID 0x11 ++#define OP_OS2IQ 0x12 ++#define OP_OD2IS 0x13 ++#define OP_OD2ID 0x14 ++#define OP_OD2IQ 0x15 ++#define OP_OQ2IS 0x16 ++#define OP_OQ2ID 0x17 ++#define OP_OQ2IQ 0x18 ++#define OP_OSNIS 0x19 ++#define OP_ODNID 0x1A ++ ++#define MATRIX_MODE_AUTO 1 ++#define CONF_MTX_MODE_AUTO 0 ++#define MANUALEN_AUTO 0 ++#define MATRIX_MODE_MANUAL 0 ++#define CONF_MTX_MODE_MANUAL 9 ++#define MANUALEN_MANUAL 1 ++ ++#define _ENSPI_MAX_XFER 0x1ff ++ ++#define REG(x) (iobase + x) ++ ++ ++static void __iomem *iobase; ++ ++ ++static void opfifo_write(u32 cmd, u32 len) ++{ ++ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff); ++ ++ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA)); ++ ++ /* Wait for room in OPFIFO */ ++ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL))) ++ ; ++ ++ /* Shift command into OPFIFO */ ++ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR)); ++ ++ /* Wait for command to finish */ ++ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY))) ++ ; ++} ++ ++static void set_cs(int state) ++{ ++ if (state) ++ opfifo_write(OP_CSH, 1); ++ else ++ opfifo_write(OP_CSL, 1); ++} ++ ++static void manual_begin_cmd(void) ++{ ++ /* Disable read idle state */ ++ writel(0, REG(ENSPI_READ_IDLE_EN)); ++ ++ /* Wait for FSM to reach idle state */ ++ while (readl(REG(ENSPI_RDCTL_FSM))) ++ ; ++ ++ /* Set SPI core to manual mode */ ++ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN)); ++} ++ ++static void manual_end_cmd(void) ++{ ++ /* Set SPI core to auto mode */ ++ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN)); ++ ++ /* Enable read idle state */ ++ writel(1, REG(ENSPI_READ_IDLE_EN)); ++} ++ ++static void dfifo_read(u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for requested data to show up in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY))) ++ ; ++ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA)); ++ /* Queue up next byte */ ++ writel(1, REG(ENSPI_MANUAL_DFIFO_RD)); ++ } ++} ++ ++static void dfifo_write(const u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for room in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL))) ++ ; ++ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA)); ++ } ++} ++ ++#if 0 ++static void set_spi_clock_speed(int freq_mhz) ++{ ++ u32 tmp, val; ++ ++ tmp = readl(ENSPI_CLOCK_DIVIDER); ++ tmp &= 0xffff0000; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++ ++ val = (400 / (freq_mhz * 2)); ++ tmp |= (val << 8) | 1; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++} ++#endif ++ ++static void init_hw(void) ++{ ++ /* Disable manual/auto mode clash interrupt */ ++ writel(0, REG(ENSPI_IER)); ++ ++ // TODO via clk framework ++ // set_spi_clock_speed(50); ++ ++ /* Disable DMA */ ++ writel(0, REG(ENSPI_NFI2SPI_EN)); ++} ++ ++static int xfer_read(struct spi_transfer *xfer) ++{ ++ int opcode; ++ uint8_t *buf = xfer->rx_buf; ++ ++ switch (xfer->rx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_INS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_IND; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_INQ; ++ break; ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_read(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx) ++{ ++ int opcode; ++ const uint8_t *buf = xfer->tx_buf; ++ ++ if (next_xfer_is_rx) { ++ /* need to use Ox2Ix opcode to set the core to input afterwards */ ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OS2IS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OS2ID; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OS2IQ; ++ break; ++ } ++ } else { ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OUTS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OUTD; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OUTQ; ++ break; ++ } ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_write(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++size_t max_transfer_size(struct spi_device *spi) ++{ ++ return _ENSPI_MAX_XFER; ++} ++ ++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg) ++{ ++ struct spi_transfer *xfer; ++ int next_xfer_is_rx = 0; ++ ++ manual_begin_cmd(); ++ set_cs(0); ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (xfer->tx_buf) { ++ if (!list_is_last(&xfer->transfer_list, &msg->transfers) ++ && list_next_entry(xfer, transfer_list)->rx_buf != NULL) ++ next_xfer_is_rx = 1; ++ else ++ next_xfer_is_rx = 0; ++ msg->actual_length += xfer_write(xfer, next_xfer_is_rx); ++ } else if (xfer->rx_buf) { ++ msg->actual_length += xfer_read(xfer); ++ } ++ } ++ set_cs(1); ++ manual_end_cmd(); ++ ++ msg->status = 0; ++ spi_finalize_current_message(ctrl); ++ ++ return 0; ++} ++ ++static int spi_probe(struct platform_device *pdev) ++{ ++ struct spi_controller *ctrl; ++ int err; ++ ++ ctrl = devm_spi_alloc_master(&pdev->dev, 0); ++ if (!ctrl) { ++ dev_err(&pdev->dev, "Error allocating SPI controller\n"); ++ return -ENOMEM; ++ } ++ ++ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); ++ if (IS_ERR(iobase)) { ++ dev_err(&pdev->dev, "Could not map SPI register address"); ++ return -ENOMEM; ++ } ++ ++ init_hw(); ++ ++ ctrl->dev.of_node = pdev->dev.of_node; ++ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; ++ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL; ++ ctrl->max_transfer_size = max_transfer_size; ++ ctrl->transfer_one_message = transfer_one_message; ++ err = devm_spi_register_controller(&pdev->dev, ctrl); ++ if (err) { ++ dev_err(&pdev->dev, "Could not register SPI controller\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id spi_of_ids[] = { ++ { .compatible = "airoha,en7523-spi" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spi_of_ids); ++ ++static struct platform_driver spi_driver = { ++ .probe = spi_probe, ++ .driver = { ++ .name = "airoha-en7523-spi", ++ .of_match_table = spi_of_ids, ++ }, ++}; ++ ++module_platform_driver(spi_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Bert Vermeulen "); ++MODULE_DESCRIPTION("Airoha EN7523 SPI driver"); diff --git a/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi b/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi new file mode 100644 index 0000000000..1f8a4a2364 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca955x_senao_loader.dtsi" + +&partitions { + partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + eee-broken-100tx; + eee-broken-1000t; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + eee-broken-100tx; + eee-broken-1000t; + at803x-override-sgmii-link-check; + }; +}; + +ð0 { + status = "okay"; + + nvmem-cells = <&macaddr_art_0 0>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + pll-data = <0x82000000 0x80000101 0x80001313>; +}; + +ð1 { + status = "okay"; + + nvmem-cells = <&macaddr_art_0 1>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&phy2>; + + pll-data = <0x03000000 0x00000101 0x00001313>; + + qca955x-sgmii-fixup; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&ath10k_1 { + nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/target/linux/ath79/dts/qca9558_engenius_ens1750.dts b/target/linux/ath79/dts/qca9558_engenius_ens1750.dts new file mode 100644 index 0000000000..45215d31b5 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_engenius_ens1750.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9558_engenius_dual_ap.dtsi" + +#include +#include +#include + +/ { + compatible = "engenius,ens1750", "qca,qca9558"; + model = "EnGenius ENS1750"; + + aliases { + label-mac-device = ð0; + led-boot = &led_wifi5g; + led-failsafe = &led_wifi5g; + led-upgrade = &led_wifi5g; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 21 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + wifi2g { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_wifi5g: wifi5g { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; diff --git a/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts b/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts index 9fa1927c1d..01a3804fcb 100644 --- a/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts +++ b/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qca955x_senao_loader.dtsi" +#include "qca9558_engenius_dual_ap.dtsi" #include #include +#include / { compatible = "engenius,ews660ap", "qca,qca9558"; @@ -31,103 +32,17 @@ compatible = "gpio-leds"; wifi2g { - label = "green:wifi2g"; + color = ; + function = LED_FUNCTION_WLAN_2GHZ; gpios = <&gpio 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy1tpt"; }; led_wifi5g: wifi5g { - label = "green:wifi5g"; + color = ; + function = LED_FUNCTION_WLAN_5GHZ; gpios = <&gpio 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy0tpt"; }; }; }; - -&partitions { - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x010000>; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - compatible = "mac-base"; - reg = <0x0 0x6>; - #nvmem-cell-cells = <1>; - }; - - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; - - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x844>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - eee-broken-100tx; - eee-broken-1000t; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - eee-broken-100tx; - eee-broken-1000t; - at803x-override-sgmii-link-check; - }; -}; - -ð0 { - status = "okay"; - - nvmem-cells = <&macaddr_art_0 0>; - nvmem-cell-names = "mac-address"; - - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - - pll-data = <0x82000000 0x80000101 0x80001313>; -}; - -ð1 { - status = "okay"; - - nvmem-cells = <&macaddr_art_0 1>; - nvmem-cell-names = "mac-address"; - - phy-handle = <&phy2>; - - pll-data = <0x03000000 0x00000101 0x00001313>; - - qca955x-sgmii-fixup; -}; - -&wmac { - status = "okay"; - - nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>; - nvmem-cell-names = "mac-address", "calibration"; -}; - -&ath10k_1 { - status = "okay"; - - nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>; - nvmem-cell-names = "mac-address", "calibration"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/target/linux/ath79/dts/qca955x_senao_loader.dtsi b/target/linux/ath79/dts/qca955x_senao_loader.dtsi index 31e00ce063..7cf64bd965 100644 --- a/target/linux/ath79/dts/qca955x_senao_loader.dtsi +++ b/target/linux/ath79/dts/qca955x_senao_loader.dtsi @@ -59,6 +59,7 @@ }; partition@40000 { + compatible = "u-boot,env"; label = "u-boot-env"; reg = <0x040000 0x010000>; }; diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index 8132849a9a..8f2a9c7723 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -1319,7 +1319,6 @@ static int ag71xx_rx_packets(struct ag71xx *ag, int limit) int ring_mask = BIT(ring->order) - 1; int ring_size = BIT(ring->order); struct list_head rx_list; - struct sk_buff *next; struct sk_buff *skb; int done = 0; @@ -1379,7 +1378,7 @@ next: ag71xx_ring_rx_refill(ag); - list_for_each_entry_safe(skb, next, &rx_list, list) + list_for_each_entry(skb, &rx_list, list) skb->protocol = eth_type_trans(skb, dev); netif_receive_skb_list(&rx_list); diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 6823c333b6..bf93dc8ba8 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -146,6 +146,7 @@ ath79_setup_interfaces() elecom,wab-i1750-ps|\ elecom,wab-s1167-ps|\ elecom,wab-s600-ps|\ + engenius,ens1750|\ engenius,enstationac-v1|\ engenius,ews511ap|\ engenius,ews660ap|\ diff --git a/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh b/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh index cb93c1b5ab..076a785cbf 100644 --- a/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh +++ b/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh @@ -40,6 +40,7 @@ platform_do_upgrade() { engenius,eap300-v2|\ engenius,eap600|\ engenius,ecb600|\ + engenius,ens1750|\ engenius,ens202ext-v1|\ engenius,enstationac-v1|\ engenius,ews660ap|\ diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index bdfaa74a38..d53140f664 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1529,18 +1529,29 @@ define Device/engenius_ews511ap endef TARGET_DEVICES += engenius_ews511ap -define Device/engenius_ews660ap +define Device/engenius_ews_dual_ap $(Device/senao_loader_okli) SOC := qca9558 DEVICE_VENDOR := EnGenius - DEVICE_MODEL := EWS660AP DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct IMAGE_SIZE := 11584k LOADER_FLASH_OFFS := 0x220000 +endef + +define Device/engenius_ews660ap + $(Device/engenius_ews_dual_ap) + DEVICE_MODEL := EWS660AP SENAO_IMGNAME := ar71xx-generic-ews660ap endef TARGET_DEVICES += engenius_ews660ap +define Device/engenius_ens1750 + $(Device/engenius_ews_dual_ap) + DEVICE_MODEL := ENS1750 + SENAO_IMGNAME := ar71xx-generic-ens1750 +endef +TARGET_DEVICES += engenius_ens1750 + define Device/enterasys_ws-ap3705i SOC := ar9344 DEVICE_VENDOR := Enterasys diff --git a/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch index 772e905ecb..ddf9d0dfb9 100644 --- a/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch +++ b/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch @@ -19,7 +19,7 @@ Subject: [PATCH 210/210] b44: register adm switch #include #include -@@ -2245,6 +2247,69 @@ static void b44_adjust_link(struct net_d +@@ -2247,6 +2249,69 @@ static void b44_adjust_link(struct net_d } } @@ -89,7 +89,7 @@ Subject: [PATCH 210/210] b44: register adm switch static int b44_register_phy_one(struct b44 *bp) { __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; -@@ -2281,6 +2346,9 @@ static int b44_register_phy_one(struct b +@@ -2283,6 +2348,9 @@ static int b44_register_phy_one(struct b if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) && (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) { @@ -99,7 +99,7 @@ Subject: [PATCH 210/210] b44: register adm switch dev_info(sdev->dev, "could not find PHY at %i, use fixed one\n", bp->phy_addr); -@@ -2475,6 +2543,7 @@ static void b44_remove_one(struct ssb_de +@@ -2477,6 +2545,7 @@ static void b44_remove_one(struct ssb_de unregister_netdev(dev); if (bp->flags & B44_FLAG_EXTERNAL_PHY) b44_unregister_phy_one(bp); diff --git a/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch index ca7123f2a3..9c16da4f57 100644 --- a/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch +++ b/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch @@ -43,7 +43,7 @@ if (bp->flags & B44_FLAG_EXTERNAL_PHY) return 0; -@@ -2175,6 +2200,8 @@ static int b44_get_invariants(struct b44 +@@ -2177,6 +2202,8 @@ static int b44_get_invariants(struct b44 * valid PHY address. */ bp->phy_addr &= 0x1F; diff --git a/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch index 2ea2e2497a..8e4de36db0 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch @@ -73,7 +73,7 @@ Signed-off-by: Andrew Morton --- a/arch/Kconfig +++ b/arch/Kconfig -@@ -1299,6 +1299,14 @@ config ARCH_HAS_ELFCORE_COMPAT +@@ -1307,6 +1307,14 @@ config ARCH_HAS_ELFCORE_COMPAT config ARCH_HAS_PARANOID_L1D_FLUSH bool @@ -90,7 +90,7 @@ Signed-off-by: Andrew Morton source "scripts/gcc-plugins/Kconfig" --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig -@@ -85,6 +85,7 @@ config X86 +@@ -86,6 +86,7 @@ config X86 select ARCH_HAS_PMEM_API if X86_64 select ARCH_HAS_PTE_DEVMAP if X86_64 select ARCH_HAS_PTE_SPECIAL diff --git a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch index 85710eb79b..ff4bb4df3e 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch @@ -552,7 +552,7 @@ Signed-off-by: Andrew Morton --- a/kernel/bounds.c +++ b/kernel/bounds.c @@ -22,6 +22,11 @@ int main(void) - DEFINE(NR_CPUS_BITS, bits_per(CONFIG_NR_CPUS)); + DEFINE(NR_CPUS_BITS, order_base_2(CONFIG_NR_CPUS)); #endif DEFINE(SPINLOCK_SIZE, sizeof(spinlock_t)); +#ifdef CONFIG_LRU_GEN diff --git a/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch b/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch index f56a968589..8e5c718042 100644 --- a/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch +++ b/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch @@ -124,7 +124,7 @@ Signed-off-by: David S. Miller list_del(&dst->list); kfree(dst); } -@@ -805,7 +809,7 @@ static int dsa_switch_setup_tag_protocol +@@ -827,7 +831,7 @@ static int dsa_switch_setup_tag_protocol int port, err; if (tag_ops->proto == dst->default_proto) @@ -133,7 +133,7 @@ Signed-off-by: David S. Miller for (port = 0; port < ds->num_ports; port++) { if (!dsa_is_cpu_port(ds, port)) -@@ -821,6 +825,17 @@ static int dsa_switch_setup_tag_protocol +@@ -843,6 +847,17 @@ static int dsa_switch_setup_tag_protocol } } @@ -151,7 +151,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1132,6 +1147,46 @@ static void dsa_tree_teardown(struct dsa +@@ -1154,6 +1169,46 @@ static void dsa_tree_teardown(struct dsa dst->setup = false; } @@ -198,7 +198,7 @@ Signed-off-by: David S. Miller /* Since the dsa/tagging sysfs device attribute is per master, the assumption * is that all DSA switches within a tree share the same tagger, otherwise * they would have formed disjoint trees (different "dsa,member" values). -@@ -1164,12 +1219,15 @@ int dsa_tree_change_tag_proto(struct dsa +@@ -1186,12 +1241,15 @@ int dsa_tree_change_tag_proto(struct dsa goto out_unlock; } @@ -216,7 +216,7 @@ Signed-off-by: David S. Miller rtnl_unlock(); -@@ -1257,6 +1315,7 @@ static int dsa_port_parse_cpu(struct dsa +@@ -1279,6 +1337,7 @@ static int dsa_port_parse_cpu(struct dsa struct dsa_switch *ds = dp->ds; struct dsa_switch_tree *dst = ds->dst; enum dsa_tag_protocol default_proto; @@ -224,7 +224,7 @@ Signed-off-by: David S. Miller /* Find out which protocol the switch would prefer. */ default_proto = dsa_get_tag_protocol(dp, master); -@@ -1311,6 +1370,12 @@ static int dsa_port_parse_cpu(struct dsa +@@ -1333,6 +1392,12 @@ static int dsa_port_parse_cpu(struct dsa */ dsa_tag_driver_put(tag_ops); } else { diff --git a/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch b/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch index 0c50ae6fb9..8c81ebc7f5 100644 --- a/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch +++ b/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch @@ -101,7 +101,7 @@ Signed-off-by: David S. Miller list_del(&dst->list); kfree(dst); } -@@ -826,17 +822,29 @@ static int dsa_switch_setup_tag_protocol +@@ -848,17 +844,29 @@ static int dsa_switch_setup_tag_protocol } connect: @@ -132,7 +132,7 @@ Signed-off-by: David S. Miller } static int dsa_switch_setup(struct dsa_switch *ds) -@@ -1156,13 +1164,6 @@ static int dsa_tree_bind_tag_proto(struc +@@ -1178,13 +1186,6 @@ static int dsa_tree_bind_tag_proto(struc dst->tag_ops = tag_ops; @@ -146,7 +146,7 @@ Signed-off-by: David S. Miller /* Notify the switches from this tree about the connection * to the new tagger */ -@@ -1172,16 +1173,14 @@ static int dsa_tree_bind_tag_proto(struc +@@ -1194,16 +1195,14 @@ static int dsa_tree_bind_tag_proto(struc goto out_disconnect; /* Notify the old tagger about the disconnection from this tree */ @@ -167,7 +167,7 @@ Signed-off-by: David S. Miller dst->tag_ops = old_tag_ops; return err; -@@ -1315,7 +1314,6 @@ static int dsa_port_parse_cpu(struct dsa +@@ -1337,7 +1336,6 @@ static int dsa_port_parse_cpu(struct dsa struct dsa_switch *ds = dp->ds; struct dsa_switch_tree *dst = ds->dst; enum dsa_tag_protocol default_proto; @@ -175,7 +175,7 @@ Signed-off-by: David S. Miller /* Find out which protocol the switch would prefer. */ default_proto = dsa_get_tag_protocol(dp, master); -@@ -1370,12 +1368,6 @@ static int dsa_port_parse_cpu(struct dsa +@@ -1392,12 +1390,6 @@ static int dsa_port_parse_cpu(struct dsa */ dsa_tag_driver_put(tag_ops); } else { diff --git a/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch b/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch deleted file mode 100644 index 9f2512a1d0..0000000000 --- a/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Felix Fietkau -Date: Mon, 7 Feb 2022 10:27:22 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent - DMA - -It improves performance by eliminating the need for a cache flush on rx and tx - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -357,7 +357,7 @@ - }; - - cci_control2: slave-if@5000 { -- compatible = "arm,cci-400-ctrl-if"; -+ compatible = "arm,cci-400-ctrl-if", "syscon"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; -@@ -938,6 +938,8 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; -+ mediatek,cci-control = <&cci_control2>; -+ dma-coherent; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; diff --git a/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch b/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch deleted file mode 100644 index 2c6e3fd3cd..0000000000 --- a/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch +++ /dev/null @@ -1,62 +0,0 @@ -From: Felix Fietkau -Date: Sat, 5 Feb 2022 18:36:36 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for - Wireless Ethernet Dispatch - -Introduce wed0 and wed1 nodes in order to enable offloading forwarding -between ethernet and wireless devices on the mt7622 chipset. - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -894,6 +894,11 @@ - }; - }; - -+ hifsys: syscon@1af00000 { -+ compatible = "mediatek,mt7622-hifsys", "syscon"; -+ reg = <0 0x1af00000 0 0x70>; -+ }; -+ - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7622-ethsys", - "syscon"; -@@ -912,6 +917,26 @@ - #dma-cells = <1>; - }; - -+ pcie_mirror: pcie-mirror@10000400 { -+ compatible = "mediatek,mt7622-pcie-mirror", -+ "syscon"; -+ reg = <0 0x10000400 0 0x10>; -+ }; -+ -+ wed0: wed@1020a000 { -+ compatible = "mediatek,mt7622-wed", -+ "syscon"; -+ reg = <0 0x1020a000 0 0x1000>; -+ interrupts = ; -+ }; -+ -+ wed1: wed@1020b000 { -+ compatible = "mediatek,mt7622-wed", -+ "syscon"; -+ reg = <0 0x1020b000 0 0x1000>; -+ interrupts = ; -+ }; -+ - eth: ethernet@1b100000 { - compatible = "mediatek,mt7622-eth", - "mediatek,mt2701-eth", -@@ -939,6 +964,9 @@ - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; - mediatek,cci-control = <&cci_control2>; -+ mediatek,wed = <&wed0>, <&wed1>; -+ mediatek,pcie-mirror = <&pcie_mirror>; -+ mediatek,hifsys = <&hifsys>; - dma-coherent; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch b/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch index 70d46c16cd..22125a4546 100644 --- a/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch +++ b/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch @@ -13,7 +13,7 @@ Signed-off-by: David S. Miller --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -963,7 +963,7 @@ +@@ -957,7 +957,7 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; mediatek,ethsys = <ðsys>; mediatek,sgmiisys = <&sgmiisys>; diff --git a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch index 3f7f328247..f65b0cafa8 100644 --- a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch +++ b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1243,27 +1243,31 @@ static int +@@ -1425,27 +1425,31 @@ static int mt7530_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *bridge) { @@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski } /* Add the all other ports to this port matrix. */ -@@ -1368,24 +1372,28 @@ static void +@@ -1550,24 +1554,28 @@ static void mt7530_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *bridge) { diff --git a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch index c3902bb9c5..e04bb11e80 100644 --- a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch +++ b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch @@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2499,6 +2499,32 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2687,6 +2687,32 @@ mt7531_setup(struct dsa_switch *ds) return 0; } @@ -56,7 +56,7 @@ Signed-off-by: Paolo Abeni static bool mt7530_phy_mode_supported(struct dsa_switch *ds, int port, const struct phylink_link_state *state) -@@ -2535,6 +2561,37 @@ static bool mt7531_is_rgmii_port(struct +@@ -2723,6 +2749,37 @@ static bool mt7531_is_rgmii_port(struct return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); } @@ -94,7 +94,7 @@ Signed-off-by: Paolo Abeni static bool mt7531_phy_mode_supported(struct dsa_switch *ds, int port, const struct phylink_link_state *state) -@@ -3011,6 +3068,18 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3199,6 +3256,18 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni static void mt7530_mac_port_validate(struct dsa_switch *ds, int port, unsigned long *supported) -@@ -3246,6 +3315,7 @@ static const struct dsa_switch_ops mt753 +@@ -3435,6 +3504,7 @@ static const struct dsa_switch_ops mt753 .port_vlan_del = mt7530_port_vlan_del, .port_mirror_add = mt753x_port_mirror_add, .port_mirror_del = mt753x_port_mirror_del, @@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni .phylink_validate = mt753x_phylink_validate, .phylink_mac_link_state = mt753x_phylink_mac_link_state, .phylink_mac_config = mt753x_phylink_mac_config, -@@ -3263,6 +3333,7 @@ static const struct mt753x_info mt753x_t +@@ -3452,6 +3522,7 @@ static const struct mt753x_info mt753x_t .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, @@ -129,7 +129,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7530_phy_mode_supported, .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, -@@ -3274,6 +3345,7 @@ static const struct mt753x_info mt753x_t +@@ -3463,6 +3534,7 @@ static const struct mt753x_info mt753x_t .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, @@ -137,7 +137,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7530_phy_mode_supported, .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, -@@ -3286,6 +3358,7 @@ static const struct mt753x_info mt753x_t +@@ -3475,6 +3547,7 @@ static const struct mt753x_info mt753x_t .phy_write = mt7531_ind_phy_write, .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, @@ -145,7 +145,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7531_phy_mode_supported, .mac_port_validate = mt7531_mac_port_validate, .mac_port_get_state = mt7531_phylink_mac_link_state, -@@ -3348,6 +3421,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3537,6 +3610,7 @@ mt7530_probe(struct mdio_device *mdiodev */ if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || @@ -155,7 +155,7 @@ Signed-off-by: Paolo Abeni !priv->info->mac_port_get_state || !priv->info->mac_port_config) --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -796,6 +796,8 @@ struct mt753x_info { +@@ -807,6 +807,8 @@ struct mt753x_info { int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); diff --git a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch index d1d56f5aa8..31be0e7be3 100644 --- a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch +++ b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch @@ -21,7 +21,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2525,37 +2525,6 @@ static void mt7530_mac_port_get_caps(str +@@ -2713,37 +2713,6 @@ static void mt7530_mac_port_get_caps(str } } @@ -59,7 +59,7 @@ Signed-off-by: Paolo Abeni static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) { return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); -@@ -2592,44 +2561,6 @@ static void mt7531_mac_port_get_caps(str +@@ -2780,44 +2749,6 @@ static void mt7531_mac_port_get_caps(str } } @@ -104,7 +104,7 @@ Signed-off-by: Paolo Abeni static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2884,9 +2815,6 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -3072,9 +3003,6 @@ mt753x_phylink_mac_config(struct dsa_swi struct mt7530_priv *priv = ds->priv; u32 mcr_cur, mcr_new; @@ -114,7 +114,7 @@ Signed-off-by: Paolo Abeni switch (port) { case 0 ... 4: /* Internal phy */ if (state->interface != PHY_INTERFACE_MODE_GMII) -@@ -3102,12 +3030,6 @@ mt753x_phylink_validate(struct dsa_switc +@@ -3290,12 +3218,6 @@ mt753x_phylink_validate(struct dsa_switc __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; struct mt7530_priv *priv = ds->priv; @@ -127,7 +127,7 @@ Signed-off-by: Paolo Abeni phylink_set_port_modes(mask); if (state->interface != PHY_INTERFACE_MODE_TRGMII && -@@ -3334,7 +3256,6 @@ static const struct mt753x_info mt753x_t +@@ -3523,7 +3445,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -135,7 +135,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, -@@ -3346,7 +3267,6 @@ static const struct mt753x_info mt753x_t +@@ -3535,7 +3456,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, -@@ -3359,7 +3279,6 @@ static const struct mt753x_info mt753x_t +@@ -3548,7 +3468,6 @@ static const struct mt753x_info mt753x_t .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, @@ -151,7 +151,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7531_mac_port_validate, .mac_port_get_state = mt7531_phylink_mac_link_state, .mac_port_config = mt7531_mac_config, -@@ -3422,7 +3341,6 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3611,7 +3530,6 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || @@ -161,7 +161,7 @@ Signed-off-by: Paolo Abeni return -EINVAL; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -798,8 +798,6 @@ struct mt753x_info { +@@ -809,8 +809,6 @@ struct mt753x_info { int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); diff --git a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch index 19b44d35ed..2a5d5ae9d9 100644 --- a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch +++ b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3054,11 +3054,6 @@ mt753x_phylink_validate(struct dsa_switc +@@ -3242,11 +3242,6 @@ mt753x_phylink_validate(struct dsa_switc linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); diff --git a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch index 5e55f92fc7..ad672312e4 100644 --- a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch +++ b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch @@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2632,12 +2632,13 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2820,12 +2820,13 @@ static int mt7531_rgmii_setup(struct mt7 } static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, @@ -38,7 +38,7 @@ Signed-off-by: Paolo Abeni phylink_set(supported, 2500baseX_Full); phylink_set(supported, 2500baseT_Full); } -@@ -3010,16 +3011,18 @@ static void mt753x_phylink_get_caps(stru +@@ -3198,16 +3199,18 @@ static void mt753x_phylink_get_caps(stru static void mt7530_mac_port_validate(struct dsa_switch *ds, int port, @@ -58,7 +58,7 @@ Signed-off-by: Paolo Abeni } static void -@@ -3042,12 +3045,13 @@ mt753x_phylink_validate(struct dsa_switc +@@ -3230,12 +3233,13 @@ mt753x_phylink_validate(struct dsa_switc } /* This switch only supports 1G full-duplex. */ @@ -76,7 +76,7 @@ Signed-off-by: Paolo Abeni phylink_set(mask, Asym_Pause); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -799,6 +799,7 @@ struct mt753x_info { +@@ -810,6 +810,7 @@ struct mt753x_info { void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); void (*mac_port_validate)(struct dsa_switch *ds, int port, diff --git a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch index ddf368fa1a..8d9802f1ee 100644 --- a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch +++ b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2631,19 +2631,6 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2819,19 +2819,6 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni static void mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, -@@ -3010,51 +2997,21 @@ static void mt753x_phylink_get_caps(stru +@@ -3198,51 +3185,21 @@ static void mt753x_phylink_get_caps(stru } static void @@ -97,7 +97,7 @@ Signed-off-by: Paolo Abeni linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); -@@ -3255,7 +3212,6 @@ static const struct mt753x_info mt753x_t +@@ -3444,7 +3401,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -105,7 +105,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, }, -@@ -3266,7 +3222,6 @@ static const struct mt753x_info mt753x_t +@@ -3455,7 +3411,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, }, -@@ -3278,7 +3233,6 @@ static const struct mt753x_info mt753x_t +@@ -3467,7 +3422,6 @@ static const struct mt753x_info mt753x_t .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, @@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7531_phylink_mac_link_state, .mac_port_config = mt7531_mac_config, .mac_pcs_an_restart = mt7531_sgmii_restart_an, -@@ -3340,7 +3294,6 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3529,7 +3483,6 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || diff --git a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch index 7f69ea2fb4..149c12c1fb 100644 --- a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch +++ b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch @@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni /* String, offset, and register size in bytes if different from 4 bytes */ static const struct mt7530_mib_desc mt7530_mib[] = { MIB_DESC(1, 0x00, "TxDrop"), -@@ -2631,12 +2636,11 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2819,12 +2824,11 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -50,7 +50,7 @@ Signed-off-by: Paolo Abeni unsigned int val; /* For adjusting speed and duplex of SGMII force mode. */ -@@ -2662,6 +2666,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw +@@ -2850,6 +2854,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw /* MT7531 SGMII 1G force mode can only work in full duplex mode, * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. @@ -60,7 +60,7 @@ Signed-off-by: Paolo Abeni */ if ((speed == SPEED_10 || speed == SPEED_100) && duplex != DUPLEX_FULL) -@@ -2737,9 +2744,10 @@ static int mt7531_sgmii_setup_mode_an(st +@@ -2925,9 +2932,10 @@ static int mt7531_sgmii_setup_mode_an(st return 0; } @@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni u32 val; /* Only restart AN when AN is enabled */ -@@ -2796,6 +2804,24 @@ mt753x_mac_config(struct dsa_switch *ds, +@@ -2984,6 +2992,24 @@ mt753x_mac_config(struct dsa_switch *ds, return priv->info->mac_port_config(ds, port, mode, state->interface); } @@ -98,7 +98,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) -@@ -2857,17 +2883,6 @@ unsupported: +@@ -3045,17 +3071,6 @@ unsupported: mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); } @@ -116,7 +116,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) -@@ -2877,16 +2892,13 @@ static void mt753x_phylink_mac_link_down +@@ -3065,16 +3080,13 @@ static void mt753x_phylink_mac_link_down mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); } @@ -139,7 +139,7 @@ Signed-off-by: Paolo Abeni } static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, -@@ -2899,8 +2911,6 @@ static void mt753x_phylink_mac_link_up(s +@@ -3087,8 +3099,6 @@ static void mt753x_phylink_mac_link_up(s struct mt7530_priv *priv = ds->priv; u32 mcr; @@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; /* MT753x MAC works in 1G full duplex mode for all up-clocked -@@ -2978,6 +2988,8 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3166,6 +3176,8 @@ mt7531_cpu_port_config(struct dsa_switch return ret; mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPU_PORT_SETTING(priv->id)); @@ -157,7 +157,7 @@ Signed-off-by: Paolo Abeni mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, speed, DUPLEX_FULL, true, true); -@@ -3017,16 +3029,13 @@ mt753x_phylink_validate(struct dsa_switc +@@ -3205,16 +3217,13 @@ mt753x_phylink_validate(struct dsa_switc linkmode_and(state->advertising, state->advertising, mask); } @@ -178,7 +178,7 @@ Signed-off-by: Paolo Abeni pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); state->link = (pmsr & PMSR_LINK); -@@ -3053,8 +3062,6 @@ mt7530_phylink_mac_link_state(struct dsa +@@ -3241,8 +3250,6 @@ mt7530_phylink_mac_link_state(struct dsa state->pause |= MLO_PAUSE_RX; if (pmsr & PMSR_TX_FC) state->pause |= MLO_PAUSE_TX; @@ -187,7 +187,7 @@ Signed-off-by: Paolo Abeni } static int -@@ -3096,32 +3103,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -3284,32 +3291,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 return 0; } @@ -249,7 +249,7 @@ Signed-off-by: Paolo Abeni if (ret) return ret; -@@ -3134,6 +3158,13 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3322,6 +3346,13 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -263,7 +263,7 @@ Signed-off-by: Paolo Abeni return ret; } -@@ -3195,9 +3226,8 @@ static const struct dsa_switch_ops mt753 +@@ -3384,9 +3415,8 @@ static const struct dsa_switch_ops mt753 .port_mirror_del = mt753x_port_mirror_del, .phylink_get_caps = mt753x_phylink_get_caps, .phylink_validate = mt753x_phylink_validate, @@ -274,7 +274,7 @@ Signed-off-by: Paolo Abeni .phylink_mac_link_down = mt753x_phylink_mac_link_down, .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, -@@ -3207,36 +3237,34 @@ static const struct dsa_switch_ops mt753 +@@ -3396,36 +3426,34 @@ static const struct dsa_switch_ops mt753 static const struct mt753x_info mt753x_table[] = { [ID_MT7621] = { .id = ID_MT7621, @@ -314,7 +314,7 @@ Signed-off-by: Paolo Abeni }, }; -@@ -3294,7 +3322,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3483,7 +3511,7 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || @@ -325,7 +325,7 @@ Signed-off-by: Paolo Abeni priv->id = priv->info->id; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -768,6 +768,12 @@ static const char *p5_intf_modes(unsigne +@@ -779,6 +779,12 @@ static const char *p5_intf_modes(unsigne struct mt7530_priv; @@ -338,7 +338,7 @@ Signed-off-by: Paolo Abeni /* struct mt753x_info - This is the main data structure for holding the specific * part for each supported device * @sw_setup: Holding the handler to a device initialization -@@ -779,18 +785,14 @@ struct mt7530_priv; +@@ -790,18 +796,14 @@ struct mt7530_priv; * port * @mac_port_validate: Holding the way to set addition validate type for a * certan MAC port @@ -359,7 +359,7 @@ Signed-off-by: Paolo Abeni int (*sw_setup)(struct dsa_switch *ds); int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); -@@ -801,15 +803,9 @@ struct mt753x_info { +@@ -812,15 +814,9 @@ struct mt753x_info { void (*mac_port_validate)(struct dsa_switch *ds, int port, phy_interface_t interface, unsigned long *supported); @@ -375,7 +375,7 @@ Signed-off-by: Paolo Abeni }; /* struct mt7530_priv - This is the main data structure for holding the state -@@ -851,6 +847,7 @@ struct mt7530_priv { +@@ -862,6 +858,7 @@ struct mt7530_priv { u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch index 565a5d0bc5..6e406ace0d 100644 --- a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch +++ b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3008,25 +3008,16 @@ static void mt753x_phylink_get_caps(stru +@@ -3196,25 +3196,16 @@ static void mt753x_phylink_get_caps(stru priv->info->mac_port_get_caps(ds, port, config); } @@ -55,7 +55,7 @@ Signed-off-by: Paolo Abeni } static void mt7530_pcs_get_state(struct phylink_pcs *pcs, -@@ -3128,12 +3119,14 @@ static void mt7530_pcs_an_restart(struct +@@ -3316,12 +3307,14 @@ static void mt7530_pcs_an_restart(struct } static const struct phylink_pcs_ops mt7530_pcs_ops = { @@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni .pcs_get_state = mt7531_pcs_get_state, .pcs_config = mt753x_pcs_config, .pcs_an_restart = mt7531_pcs_an_restart, -@@ -3225,7 +3218,6 @@ static const struct dsa_switch_ops mt753 +@@ -3414,7 +3407,6 @@ static const struct dsa_switch_ops mt753 .port_mirror_add = mt753x_port_mirror_add, .port_mirror_del = mt753x_port_mirror_del, .phylink_get_caps = mt753x_phylink_get_caps, diff --git a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch index da9fe699e3..afcfcaba34 100644 --- a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch +++ b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch @@ -19,7 +19,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3005,6 +3005,12 @@ static void mt753x_phylink_get_caps(stru +@@ -3193,6 +3193,12 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; diff --git a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch index eea598a7f4..bf2938d03b 100644 --- a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch +++ b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch @@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3143,9 +3143,16 @@ static int +@@ -3331,9 +3331,16 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski if (ret) return ret; -@@ -3157,13 +3164,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3345,13 +3352,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch index c0dce51a2a..320b5c1ef9 100644 --- a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch +++ b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1589,11 +1589,11 @@ static void +@@ -1771,11 +1771,11 @@ static void mt7530_hw_vlan_add(struct mt7530_priv *priv, struct mt7530_hw_vlan_entry *entry) { @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski /* Validate the entry with independent learning, create egress tag per * VLAN and joining the port as one of the port members. -@@ -1604,22 +1604,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p +@@ -1786,22 +1786,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p /* Decide whether adding tag or not for those outgoing packets from the * port inside the VLAN. @@ -72,7 +72,7 @@ Signed-off-by: Jakub Kicinski } static void -@@ -1638,11 +1636,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p +@@ -1820,11 +1818,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p return; } diff --git a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch index 7a4ee56cf9..eef19b4cb5 100644 --- a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch +++ b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1093,6 +1093,7 @@ static int +@@ -1275,6 +1275,7 @@ static int mt7530_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy) { @@ -29,7 +29,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1101,7 +1102,11 @@ mt7530_port_enable(struct dsa_switch *ds +@@ -1283,7 +1284,11 @@ mt7530_port_enable(struct dsa_switch *ds * restore the port matrix if the port is the member of a certain * bridge. */ @@ -42,7 +42,7 @@ Signed-off-by: Jakub Kicinski priv->ports[port].enable = true; mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, priv->ports[port].pm); -@@ -1249,7 +1254,8 @@ mt7530_port_bridge_join(struct dsa_switc +@@ -1431,7 +1436,8 @@ mt7530_port_bridge_join(struct dsa_switc struct net_device *bridge) { struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; @@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1326,9 +1332,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ +@@ -1508,9 +1514,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ * the CPU port get out of VLAN filtering mode. */ if (all_user_ports_removed) { @@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); } } -@@ -1378,6 +1387,7 @@ mt7530_port_bridge_leave(struct dsa_swit +@@ -1560,6 +1569,7 @@ mt7530_port_bridge_leave(struct dsa_swit struct net_device *bridge) { struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; @@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1406,8 +1416,8 @@ mt7530_port_bridge_leave(struct dsa_swit +@@ -1588,8 +1598,8 @@ mt7530_port_bridge_leave(struct dsa_swit */ if (priv->ports[port].enable) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, @@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski /* When a port is removed from the bridge, the port would be set up * back to the default as is at initial boot which is a VLAN-unaware -@@ -1570,6 +1580,9 @@ static int +@@ -1752,6 +1762,9 @@ static int mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { @@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski if (vlan_filtering) { /* The port is being kept as VLAN-unaware port when bridge is * set up with vlan_filtering not being set, Otherwise, the -@@ -1577,7 +1590,7 @@ mt7530_port_vlan_filtering(struct dsa_sw +@@ -1759,7 +1772,7 @@ mt7530_port_vlan_filtering(struct dsa_sw * for becoming a VLAN-aware port. */ mt7530_port_set_vlan_aware(ds, port); diff --git a/target/linux/generic/backport-5.15/741-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch b/target/linux/generic/backport-5.15/741-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch deleted file mode 100644 index 02407da8a8..0000000000 --- a/target/linux/generic/backport-5.15/741-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch +++ /dev/null @@ -1,85 +0,0 @@ -From: Pablo Neira Ayuso -Date: Thu, 11 Apr 2024 13:28:59 +0200 -Subject: [PATCH] netfilter: flowtable: validate pppoe header - -Ensure there is sufficient room to access the protocol field of the -PPPoe header. Validate it once before the flowtable lookup, then use a -helper function to access protocol field. - -Reported-by: syzbot+b6f07e1c07ef40199081@syzkaller.appspotmail.com -Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support") -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -318,7 +318,7 @@ int nf_flow_rule_route_ipv6(struct net * - int nf_flow_table_offload_init(void); - void nf_flow_table_offload_exit(void); - --static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb) -+static inline __be16 __nf_flow_pppoe_proto(const struct sk_buff *skb) - { - __be16 proto; - -@@ -334,4 +334,14 @@ static inline __be16 nf_flow_pppoe_proto - return 0; - } - -+static inline bool nf_flow_pppoe_proto(struct sk_buff *skb, __be16 *inner_proto) -+{ -+ if (!pskb_may_pull(skb, PPPOE_SES_HLEN)) -+ return false; -+ -+ *inner_proto = __nf_flow_pppoe_proto(skb); -+ -+ return true; -+} -+ - #endif /* _NF_FLOW_TABLE_H */ ---- a/net/netfilter/nf_flow_table_inet.c -+++ b/net/netfilter/nf_flow_table_inet.c -@@ -21,7 +21,8 @@ nf_flow_offload_inet_hook(void *priv, st - proto = veth->h_vlan_encapsulated_proto; - break; - case htons(ETH_P_PPP_SES): -- proto = nf_flow_pppoe_proto(skb); -+ if (!nf_flow_pppoe_proto(skb, &proto)) -+ return NF_ACCEPT; - break; - default: - proto = skb->protocol; ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -246,10 +246,11 @@ static unsigned int nf_flow_xmit_xfrm(st - return NF_STOLEN; - } - --static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto, -+static bool nf_flow_skb_encap_protocol(struct sk_buff *skb, __be16 proto, - u32 *offset) - { - struct vlan_ethhdr *veth; -+ __be16 inner_proto; - - switch (skb->protocol) { - case htons(ETH_P_8021Q): -@@ -260,7 +261,8 @@ static bool nf_flow_skb_encap_protocol(c - } - break; - case htons(ETH_P_PPP_SES): -- if (nf_flow_pppoe_proto(skb) == proto) { -+ if (nf_flow_pppoe_proto(skb, &inner_proto) && -+ inner_proto == proto) { - *offset += PPPOE_SES_HLEN; - return true; - } -@@ -289,7 +291,7 @@ static void nf_flow_encap_pop(struct sk_ - skb_reset_network_header(skb); - break; - case htons(ETH_P_PPP_SES): -- skb->protocol = nf_flow_pppoe_proto(skb); -+ skb->protocol = __nf_flow_pppoe_proto(skb); - skb_pull(skb, PPPOE_SES_HLEN); - skb_reset_network_header(skb); - break; diff --git a/target/linux/generic/backport-5.15/741-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch b/target/linux/generic/backport-5.15/741-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch deleted file mode 100644 index 3b822b169d..0000000000 --- a/target/linux/generic/backport-5.15/741-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Pablo Neira Ayuso -Date: Thu, 11 Apr 2024 13:29:00 +0200 -Subject: [PATCH] netfilter: flowtable: incorrect pppoe tuple - -pppoe traffic reaching ingress path does not match the flowtable entry -because the pppoe header is expected to be at the network header offset. -This bug causes a mismatch in the flow table lookup, so pppoe packets -enter the classical forwarding path. - -Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support") -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -156,7 +156,7 @@ static void nf_flow_tuple_encap(struct s - tuple->encap[i].proto = skb->protocol; - break; - case htons(ETH_P_PPP_SES): -- phdr = (struct pppoe_hdr *)skb_mac_header(skb); -+ phdr = (struct pppoe_hdr *)skb_network_header(skb); - tuple->encap[i].id = ntohs(phdr->sid); - tuple->encap[i].proto = skb->protocol; - break; diff --git a/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch b/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch index e331226fc4..dbc28efc94 100644 --- a/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch +++ b/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch @@ -30,7 +30,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c -@@ -1034,6 +1034,8 @@ static int dsa_tree_setup_master(struct +@@ -1056,6 +1056,8 @@ static int dsa_tree_setup_master(struct struct dsa_port *dp; int err; @@ -39,7 +39,7 @@ Signed-off-by: David S. Miller list_for_each_entry(dp, &dst->ports, list) { if (dsa_port_is_cpu(dp)) { err = dsa_master_setup(dp->master, dp); -@@ -1042,6 +1044,8 @@ static int dsa_tree_setup_master(struct +@@ -1064,6 +1066,8 @@ static int dsa_tree_setup_master(struct } } @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1049,9 +1053,13 @@ static void dsa_tree_teardown_master(str +@@ -1071,9 +1075,13 @@ static void dsa_tree_teardown_master(str { struct dsa_port *dp; diff --git a/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch b/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch index e6472c61da..fbb9c94ec1 100644 --- a/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch +++ b/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch @@ -27,7 +27,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c -@@ -999,23 +999,28 @@ static void dsa_tree_teardown_switches(s +@@ -1021,23 +1021,28 @@ static void dsa_tree_teardown_switches(s dsa_switch_teardown(dp->ds); } @@ -66,7 +66,7 @@ Signed-off-by: David S. Miller } } -@@ -1024,7 +1029,21 @@ static int dsa_tree_setup_switches(struc +@@ -1046,7 +1051,21 @@ static int dsa_tree_setup_switches(struc teardown: dsa_tree_teardown_ports(dst); @@ -89,7 +89,7 @@ Signed-off-by: David S. Miller return err; } -@@ -1111,10 +1130,14 @@ static int dsa_tree_setup(struct dsa_swi +@@ -1133,10 +1152,14 @@ static int dsa_tree_setup(struct dsa_swi if (err) goto teardown_cpu_ports; @@ -105,7 +105,7 @@ Signed-off-by: David S. Miller err = dsa_tree_setup_lags(dst); if (err) goto teardown_master; -@@ -1127,8 +1150,9 @@ static int dsa_tree_setup(struct dsa_swi +@@ -1149,8 +1172,9 @@ static int dsa_tree_setup(struct dsa_swi teardown_master: dsa_tree_teardown_master(dst); diff --git a/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch b/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch index 93cad0c98a..a46e06ef8b 100644 --- a/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch +++ b/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch @@ -43,7 +43,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c -@@ -545,6 +545,7 @@ static void dsa_port_teardown(struct dsa +@@ -567,6 +567,7 @@ static void dsa_port_teardown(struct dsa struct devlink_port *dlp = &dp->devlink_port; struct dsa_switch *ds = dp->ds; struct dsa_mac_addr *a, *tmp; @@ -51,7 +51,7 @@ Signed-off-by: David S. Miller if (!dp->setup) return; -@@ -566,9 +567,11 @@ static void dsa_port_teardown(struct dsa +@@ -588,9 +589,11 @@ static void dsa_port_teardown(struct dsa dsa_port_link_unregister_of(dp); break; case DSA_PORT_TYPE_USER: @@ -65,7 +65,7 @@ Signed-off-by: David S. Miller } break; } -@@ -1130,17 +1133,17 @@ static int dsa_tree_setup(struct dsa_swi +@@ -1152,17 +1155,17 @@ static int dsa_tree_setup(struct dsa_swi if (err) goto teardown_cpu_ports; @@ -87,7 +87,7 @@ Signed-off-by: David S. Miller dst->setup = true; -@@ -1148,10 +1151,10 @@ static int dsa_tree_setup(struct dsa_swi +@@ -1170,10 +1173,10 @@ static int dsa_tree_setup(struct dsa_swi return 0; @@ -100,7 +100,7 @@ Signed-off-by: David S. Miller teardown_switches: dsa_tree_teardown_switches(dst); teardown_cpu_ports: -@@ -1169,10 +1172,10 @@ static void dsa_tree_teardown(struct dsa +@@ -1191,10 +1194,10 @@ static void dsa_tree_teardown(struct dsa dsa_tree_teardown_lags(dst); diff --git a/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch b/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch index bffdcb2881..15122950ce 100644 --- a/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch +++ b/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch @@ -68,7 +68,7 @@ Signed-off-by: David S. Miller static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p) { return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED; -@@ -949,6 +959,13 @@ struct dsa_switch_ops { +@@ -957,6 +967,13 @@ struct dsa_switch_ops { int (*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid, u16 flags); int (*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid); @@ -84,7 +84,7 @@ Signed-off-by: David S. Miller #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes) \ --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c -@@ -1275,6 +1275,52 @@ out_unlock: +@@ -1297,6 +1297,52 @@ out_unlock: return err; } diff --git a/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch b/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch index 6478d580c0..c55c5271d4 100644 --- a/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch +++ b/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch @@ -44,7 +44,7 @@ Signed-off-by: David S. Miller #include "dsa_priv.h" -@@ -1060,9 +1061,18 @@ static int dsa_tree_setup_master(struct +@@ -1082,9 +1083,18 @@ static int dsa_tree_setup_master(struct list_for_each_entry(dp, &dst->ports, list) { if (dsa_port_is_cpu(dp)) { @@ -64,7 +64,7 @@ Signed-off-by: David S. Miller } } -@@ -1077,9 +1087,19 @@ static void dsa_tree_teardown_master(str +@@ -1099,9 +1109,19 @@ static void dsa_tree_teardown_master(str rtnl_lock(); diff --git a/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch index 7b89dbc206..7f16b936cd 100644 --- a/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch +++ b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2791,9 +2791,6 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2979,9 +2979,6 @@ mt7531_mac_config(struct dsa_switch *ds, case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: @@ -29,7 +29,7 @@ Signed-off-by: David S. Miller return mt7531_sgmii_setup_mode_force(priv, port, interface); default: return -EINVAL; -@@ -2869,13 +2866,6 @@ unsupported: +@@ -3057,13 +3054,6 @@ unsupported: return; } @@ -43,7 +43,7 @@ Signed-off-by: David S. Miller mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); mcr_new = mcr_cur; mcr_new &= ~PMCR_LINK_SETTINGS_MASK; -@@ -3012,6 +3002,9 @@ static void mt753x_phylink_get_caps(stru +@@ -3200,6 +3190,9 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; @@ -53,7 +53,7 @@ Signed-off-by: David S. Miller /* This driver does not make use of the speed, duplex, pause or the * advertisement in its mac_config, so it is safe to mark this driver * as non-legacy. -@@ -3077,6 +3070,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -3265,6 +3258,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); state->link = !!(status & MT7531_SGMII_LINK_STATUS); @@ -61,7 +61,7 @@ Signed-off-by: David S. Miller if (state->interface == PHY_INTERFACE_MODE_SGMII && (status & MT7531_SGMII_AN_ENABLE)) { val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); -@@ -3107,16 +3101,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -3295,16 +3289,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 return 0; } @@ -109,7 +109,7 @@ Signed-off-by: David S. Miller } static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, -@@ -3157,6 +3179,8 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3345,6 +3367,8 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -120,7 +120,7 @@ Signed-off-by: David S. Miller ret = priv->info->sw_setup(ds); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -400,6 +400,7 @@ enum mt7530_vlan_port_acc_frm { +@@ -410,6 +410,7 @@ enum mt7530_vlan_port_acc_frm { #define MT7531_SGMII_LINK_STATUS BIT(18) #define MT7531_SGMII_AN_ENABLE BIT(12) #define MT7531_SGMII_AN_RESTART BIT(9) diff --git a/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch b/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch index b9d3018f11..8060ad5afc 100644 --- a/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch +++ b/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch @@ -81,7 +81,7 @@ Tested-by: Frank Wunderlich #include #include #include -@@ -2643,128 +2644,11 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2831,128 +2832,11 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -210,7 +210,7 @@ Tested-by: Frank Wunderlich static int mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) -@@ -2787,11 +2671,11 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2975,11 +2859,11 @@ mt7531_mac_config(struct dsa_switch *ds, phydev = dp->slave->phydev; return mt7531_rgmii_setup(priv, port, interface, phydev); case PHY_INTERFACE_MODE_SGMII: @@ -224,7 +224,7 @@ Tested-by: Frank Wunderlich default: return -EINVAL; } -@@ -2816,11 +2700,11 @@ mt753x_phylink_mac_select_pcs(struct dsa +@@ -3004,11 +2888,11 @@ mt753x_phylink_mac_select_pcs(struct dsa switch (interface) { case PHY_INTERFACE_MODE_TRGMII: @@ -238,7 +238,7 @@ Tested-by: Frank Wunderlich default: return NULL; } -@@ -3061,86 +2945,6 @@ static void mt7530_pcs_get_state(struct +@@ -3249,86 +3133,6 @@ static void mt7530_pcs_get_state(struct state->pause |= MLO_PAUSE_TX; } @@ -325,7 +325,7 @@ Tested-by: Frank Wunderlich static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, phy_interface_t interface, const unsigned long *advertising, -@@ -3160,18 +2964,57 @@ static const struct phylink_pcs_ops mt75 +@@ -3348,18 +3152,57 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -389,7 +389,7 @@ Tested-by: Frank Wunderlich int i, ret; /* Initialise the PCS devices */ -@@ -3179,8 +3022,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3367,8 +3210,6 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -398,7 +398,7 @@ Tested-by: Frank Wunderlich } ret = priv->info->sw_setup(ds); -@@ -3195,6 +3036,16 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3383,6 +3224,16 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -415,7 +415,7 @@ Tested-by: Frank Wunderlich return ret; } -@@ -3286,7 +3137,7 @@ static const struct mt753x_info mt753x_t +@@ -3475,7 +3326,7 @@ static const struct mt753x_info mt753x_t }, [ID_MT7531] = { .id = ID_MT7531, @@ -424,7 +424,7 @@ Tested-by: Frank Wunderlich .sw_setup = mt7531_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, -@@ -3394,7 +3245,7 @@ static void +@@ -3583,7 +3434,7 @@ static void mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); @@ -433,7 +433,7 @@ Tested-by: Frank Wunderlich if (!priv) return; -@@ -3413,6 +3264,10 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3602,6 +3453,10 @@ mt7530_remove(struct mdio_device *mdiode mt7530_free_irq(priv); dsa_unregister_switch(priv->ds); @@ -446,7 +446,7 @@ Tested-by: Frank Wunderlich dev_set_drvdata(&mdiodev->dev, NULL); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm { CCR_TX_OCT_CNT_BAD) /* MT7531 SGMII register group */ @@ -496,7 +496,7 @@ Tested-by: Frank Wunderlich /* Register for system reset */ #define MT7530_SYS_CTRL 0x7000 -@@ -730,13 +691,13 @@ struct mt7530_fdb { +@@ -741,13 +702,13 @@ struct mt7530_fdb { * @pm: The matrix used to show all connections with the port. * @pvid: The VLAN specified is to be considered a PVID at ingress. Any * untagged frames will be assigned to the related VLAN. diff --git a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch index 34db4fce0b..62d9c78cca 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2996,26 +2996,56 @@ static const struct regmap_bus mt7531_re +@@ -3184,26 +3184,56 @@ static const struct regmap_bus mt7531_re .reg_update_bits = mt7530_regmap_update_bits, }; @@ -88,7 +88,7 @@ Signed-off-by: David S. Miller int i, ret; /* Initialise the PCS devices */ -@@ -3037,15 +3067,11 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3225,15 +3255,11 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch index 04060b48ba..e9f69a8777 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2969,7 +2969,7 @@ static int mt7530_regmap_read(void *cont +@@ -3157,7 +3157,7 @@ static int mt7530_regmap_read(void *cont { struct mt7530_priv *priv = context; @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller return 0; }; -@@ -2977,23 +2977,25 @@ static int mt7530_regmap_write(void *con +@@ -3165,23 +3165,25 @@ static int mt7530_regmap_write(void *con { struct mt7530_priv *priv = context; @@ -62,7 +62,7 @@ Signed-off-by: David S. Miller }; static int -@@ -3019,6 +3021,9 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -3207,6 +3209,9 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->reg_stride = 4; mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); mt7531_pcs_config[i]->max_register = 0x17c; diff --git a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch index 48854fd234..a2dcc08b02 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch @@ -133,7 +133,7 @@ Signed-off-by: David S. Miller } static void -@@ -2965,22 +2986,6 @@ static const struct phylink_pcs_ops mt75 +@@ -3153,22 +3174,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -156,7 +156,7 @@ Signed-off-by: David S. Miller static void mt7530_mdio_regmap_lock(void *mdio_lock) { -@@ -2993,7 +2998,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc +@@ -3181,7 +3186,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc mutex_unlock(mdio_lock); } @@ -165,7 +165,7 @@ Signed-off-by: David S. Miller .reg_write = mt7530_regmap_write, .reg_read = mt7530_regmap_read, }; -@@ -3026,7 +3031,7 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -3214,7 +3219,7 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; regmap = devm_regmap_init(priv->dev, @@ -174,7 +174,7 @@ Signed-off-by: David S. Miller mt7531_pcs_config[i]); if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); -@@ -3191,6 +3196,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) +@@ -3380,6 +3385,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) static int mt7530_probe(struct mdio_device *mdiodev) { @@ -182,7 +182,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv; struct device_node *dn; -@@ -3270,6 +3276,21 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3459,6 +3465,21 @@ mt7530_probe(struct mdio_device *mdiodev mutex_init(&priv->reg_mutex); dev_set_drvdata(&mdiodev->dev, priv); @@ -206,7 +206,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -774,6 +774,7 @@ struct mt753x_info { +@@ -785,6 +785,7 @@ struct mt753x_info { * @dev: The device pointer * @ds: The pointer to the dsa core structure * @bus: The bus used for the device and built-in PHY @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller * @rstc: The pointer to reset control used by MCM * @core_pwr: The power supplied into the core * @io_pwr: The power supplied into the I/O -@@ -794,6 +795,7 @@ struct mt7530_priv { +@@ -805,6 +806,7 @@ struct mt7530_priv { struct device *dev; struct dsa_switch *ds; struct mii_bus *bus; diff --git a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch index b4bcdd0c9d..abbecd5e40 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3077,12 +3077,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3265,12 +3265,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -31,7 +31,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -3199,6 +3193,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3388,6 +3382,7 @@ mt7530_probe(struct mdio_device *mdiodev static struct regmap_config *regmap_config; struct mt7530_priv *priv; struct device_node *dn; @@ -39,7 +39,7 @@ Signed-off-by: David S. Miller dn = mdiodev->dev.of_node; -@@ -3291,6 +3286,12 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3480,6 +3475,12 @@ mt7530_probe(struct mdio_device *mdiodev if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch index b9507e6d9b..ef02d46938 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch @@ -114,7 +114,7 @@ Signed-off-by: David S. Miller } static void -@@ -646,14 +650,13 @@ static int +@@ -660,14 +664,13 @@ static int mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, int regnum) { @@ -130,7 +130,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -686,7 +689,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr +@@ -700,7 +703,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr ret = val & MT7531_MDIO_RW_DATA_MASK; out: @@ -139,7 +139,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -695,14 +698,13 @@ static int +@@ -709,14 +712,13 @@ static int mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, int regnum, u32 data) { @@ -155,7 +155,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -734,7 +736,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p +@@ -748,7 +750,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p } out: @@ -164,7 +164,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -742,14 +744,13 @@ out: +@@ -756,14 +758,13 @@ out: static int mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) { @@ -180,7 +180,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -772,7 +773,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr +@@ -786,7 +787,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr ret = val & MT7531_MDIO_RW_DATA_MASK; out: @@ -189,7 +189,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -781,14 +782,13 @@ static int +@@ -795,14 +796,13 @@ static int mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 data) { @@ -205,7 +205,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, !(reg & MT7531_PHY_ACS_ST), 20, 100000); -@@ -810,7 +810,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p +@@ -824,7 +824,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p } out: @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -1162,7 +1162,6 @@ static int +@@ -1344,7 +1344,6 @@ static int mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct mt7530_priv *priv = ds->priv; @@ -222,7 +222,7 @@ Signed-off-by: David S. Miller int length; u32 val; -@@ -1173,7 +1172,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1355,7 +1354,7 @@ mt7530_port_change_mtu(struct dsa_switch if (!dsa_is_cpu_port(ds, port)) return 0; @@ -231,7 +231,7 @@ Signed-off-by: David S. Miller val = mt7530_mii_read(priv, MT7530_GMACCR); val &= ~MAX_RX_PKT_LEN_MASK; -@@ -1194,7 +1193,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1376,7 +1375,7 @@ mt7530_port_change_mtu(struct dsa_switch mt7530_mii_write(priv, MT7530_GMACCR, val); @@ -240,7 +240,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1990,10 +1989,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ +@@ -2172,10 +2171,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ u32 val; int p; @@ -253,7 +253,7 @@ Signed-off-by: David S. Miller for (p = 0; p < MT7530_NUM_PHYS; p++) { if (BIT(p) & val) { -@@ -2029,7 +2028,7 @@ mt7530_irq_bus_lock(struct irq_data *d) +@@ -2211,7 +2210,7 @@ mt7530_irq_bus_lock(struct irq_data *d) { struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); @@ -262,7 +262,7 @@ Signed-off-by: David S. Miller } static void -@@ -2038,7 +2037,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da +@@ -2220,7 +2219,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch index b04a84965b..2e1ed2e652 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch @@ -21,7 +21,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -951,6 +951,24 @@ mt7530_set_ageing_time(struct dsa_switch +@@ -965,6 +965,24 @@ mt7530_set_ageing_time(struct dsa_switch return 0; } @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv = ds->priv; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -709,24 +709,6 @@ enum p5_interface_select { +@@ -720,24 +720,6 @@ enum p5_interface_select { P5_INTF_SEL_GMAC5_SGMII, }; diff --git a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch index 3f656c7a67..c9ff26ff20 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3205,44 +3205,21 @@ static const struct of_device_id mt7530_ +@@ -3394,44 +3394,21 @@ static const struct of_device_id mt7530_ MODULE_DEVICE_TABLE(of, mt7530_of_match); static int @@ -67,7 +67,7 @@ Signed-off-by: David S. Miller if (!priv->info) return -EINVAL; -@@ -3256,23 +3233,53 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3445,23 +3422,53 @@ mt7530_probe(struct mdio_device *mdiodev return -EINVAL; priv->id = priv->info->id; @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(priv->reset)) { -@@ -3281,12 +3288,15 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3470,12 +3477,15 @@ mt7530_probe(struct mdio_device *mdiodev } } diff --git a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch index efbabf668c..7c1c80e7bc 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3323,6 +3323,17 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3512,6 +3512,17 @@ mt7530_probe(struct mdio_device *mdiodev } static void @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); -@@ -3341,16 +3352,11 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3530,16 +3541,11 @@ mt7530_remove(struct mdio_device *mdiode dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch index ee944a6fc5..84883147ac 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch @@ -416,7 +416,7 @@ Signed-off-by: David S. Miller static u32 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) { -@@ -3003,72 +2954,6 @@ static const struct phylink_pcs_ops mt75 +@@ -3191,72 +3142,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -489,7 +489,7 @@ Signed-off-by: David S. Miller static int mt753x_setup(struct dsa_switch *ds) { -@@ -3127,7 +3012,7 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3315,7 +3200,7 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -497,8 +497,8 @@ Signed-off-by: David S. Miller +const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, - .get_strings = mt7530_get_strings, -@@ -3161,8 +3046,9 @@ static const struct dsa_switch_ops mt753 + .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, +@@ -3350,8 +3235,9 @@ static const struct dsa_switch_ops mt753 .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, }; @@ -509,7 +509,7 @@ Signed-off-by: David S. Miller [ID_MT7621] = { .id = ID_MT7621, .pcs_ops = &mt7530_pcs_ops, -@@ -3195,16 +3081,9 @@ static const struct mt753x_info mt753x_t +@@ -3384,16 +3270,9 @@ static const struct mt753x_info mt753x_t .mac_port_config = mt7531_mac_config, }, }; @@ -528,7 +528,7 @@ Signed-off-by: David S. Miller mt7530_probe_common(struct mt7530_priv *priv) { struct device *dev = priv->dev; -@@ -3241,88 +3120,9 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3430,88 +3309,9 @@ mt7530_probe_common(struct mt7530_priv * return 0; } @@ -619,7 +619,7 @@ Signed-off-by: David S. Miller mt7530_remove_common(struct mt7530_priv *priv) { if (priv->irq) -@@ -3333,57 +3133,6 @@ mt7530_remove_common(struct mt7530_priv +@@ -3522,57 +3322,6 @@ mt7530_remove_common(struct mt7530_priv mutex_destroy(&priv->reg_mutex); } @@ -679,7 +679,7 @@ Signed-off-by: David S. Miller MODULE_LICENSE("GPL"); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -834,4 +834,10 @@ static inline void INIT_MT7530_DUMMY_POL +@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL p->reg = reg; } diff --git a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch index e6c1b941dd..c8417091f9 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -184,7 +184,7 @@ Signed-off-by: David S. Miller +MODULE_LICENSE("GPL"); --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2037,6 +2037,47 @@ static const struct irq_domain_ops mt753 +@@ -2219,6 +2219,47 @@ static const struct irq_domain_ops mt753 }; static void @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller mt7530_setup_mdio_irq(struct mt7530_priv *priv) { struct dsa_switch *ds = priv->ds; -@@ -2070,8 +2111,15 @@ mt7530_setup_irq(struct mt7530_priv *pri +@@ -2252,8 +2293,15 @@ mt7530_setup_irq(struct mt7530_priv *pri return priv->irq ? : -EINVAL; } @@ -250,7 +250,7 @@ Signed-off-by: David S. Miller if (!priv->irq_domain) { dev_err(dev, "failed to create IRQ domain\n"); return -ENOMEM; -@@ -2566,6 +2614,25 @@ static void mt7531_mac_port_get_caps(str +@@ -2754,6 +2802,25 @@ static void mt7531_mac_port_get_caps(str } } @@ -276,7 +276,7 @@ Signed-off-by: David S. Miller static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2642,6 +2709,17 @@ static bool mt753x_is_mac_port(u32 port) +@@ -2830,6 +2897,17 @@ static bool mt753x_is_mac_port(u32 port) } static int @@ -294,7 +294,7 @@ Signed-off-by: David S. Miller mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2711,7 +2789,8 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2899,7 +2977,8 @@ mt753x_phylink_mac_config(struct dsa_swi switch (port) { case 0 ... 4: /* Internal phy */ @@ -304,7 +304,7 @@ Signed-off-by: David S. Miller goto unsupported; break; case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ -@@ -2789,7 +2868,8 @@ static void mt753x_phylink_mac_link_up(s +@@ -2977,7 +3056,8 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ @@ -314,7 +314,7 @@ Signed-off-by: David S. Miller (phy_interface_mode_is_8023z(interface))) { speed = SPEED_1000; duplex = DUPLEX_FULL; -@@ -2869,6 +2949,21 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3057,6 +3137,21 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -336,7 +336,7 @@ Signed-off-by: David S. Miller static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -3014,6 +3109,27 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3202,6 +3297,27 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -364,7 +364,7 @@ Signed-off-by: David S. Miller const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -3082,6 +3198,17 @@ const struct mt753x_info mt753x_table[] +@@ -3271,6 +3387,17 @@ const struct mt753x_info mt753x_table[] .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, }, @@ -392,9 +392,9 @@ Signed-off-by: David S. Miller }; #define NUM_TRGMII_CTRL 5 -@@ -54,11 +55,11 @@ enum mt753x_id { - #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) +@@ -59,11 +60,11 @@ enum mt753x_id { #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) + #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) -#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ +#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ @@ -407,7 +407,7 @@ Signed-off-by: David S. Miller MT7531_MIRROR_MASK : MIRROR_MASK) /* Registers for BPDU and PAE frame control*/ -@@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm { MT7531_FORCE_DPX | \ MT7531_FORCE_RX_FC | \ MT7531_FORCE_TX_FC) diff --git a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch index 071680f100..2689647319 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch @@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski } --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3076,6 +3076,12 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3264,6 +3264,12 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -88,7 +88,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -768,10 +768,10 @@ struct mt753x_info { +@@ -779,10 +779,10 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski */ struct mt7530_priv { struct device *dev; -@@ -790,7 +790,6 @@ struct mt7530_priv { +@@ -801,7 +801,6 @@ struct mt7530_priv { unsigned int p5_intf_sel; u8 mirror_rx; u8 mirror_tx; @@ -108,7 +108,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_port ports[MT7530_NUM_PORTS]; struct mt753x_pcs pcs[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ -@@ -798,6 +797,7 @@ struct mt7530_priv { +@@ -809,6 +808,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; diff --git a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch index 698e524c35..b2af169b92 100644 --- a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch +++ b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller ax88179_reset(dev); -@@ -1507,17 +1508,19 @@ ax88179_tx_fixup(struct usbnet *dev, str +@@ -1502,17 +1503,19 @@ ax88179_tx_fixup(struct usbnet *dev, str { u32 tx_hdr1, tx_hdr2; int frame_size = dev->maxpacket; @@ -57,7 +57,7 @@ Signed-off-by: David S. Miller if ((skb_header_cloned(skb) || headroom < 0) && pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { dev_kfree_skb_any(skb); -@@ -1528,6 +1531,8 @@ ax88179_tx_fixup(struct usbnet *dev, str +@@ -1523,6 +1526,8 @@ ax88179_tx_fixup(struct usbnet *dev, str put_unaligned_le32(tx_hdr1, ptr); put_unaligned_le32(tx_hdr2, ptr + 4); diff --git a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch index 725af4b52c..4a63b89f57 100644 --- a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch +++ b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch @@ -17,7 +17,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2287,6 +2287,23 @@ struct btmtk_section_map { +@@ -2289,6 +2289,23 @@ struct btmtk_section_map { }; } __packed; @@ -41,7 +41,7 @@ Signed-off-by: Marcel Holtmann static void btusb_mtk_wmt_recv(struct urb *urb) { struct hci_dev *hdev = urb->context; -@@ -3941,6 +3958,7 @@ static int btusb_probe(struct usb_interf +@@ -3943,6 +3960,7 @@ static int btusb_probe(struct usb_interf hdev->shutdown = btusb_mtk_shutdown; hdev->manufacturer = 70; hdev->cmd_timeout = btusb_mtk_cmd_timeout; diff --git a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch index d72866eabf..d21adada97 100644 --- a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch +++ b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch @@ -18,7 +18,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2292,7 +2292,7 @@ static int btusb_set_bdaddr_mtk(struct h +@@ -2294,7 +2294,7 @@ static int btusb_set_bdaddr_mtk(struct h struct sk_buff *skb; long ret; diff --git a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch index ebb6cc4717..30492ac48d 100644 --- a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch +++ b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch @@ -58,7 +58,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -476,6 +476,9 @@ static const struct usb_device_id blackl +@@ -478,6 +478,9 @@ static const struct usb_device_id blackl { USB_DEVICE(0x13d3, 0x3564), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH | BTUSB_VALID_LE_STATES }, diff --git a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch index a8c7ca003a..6bcd81c3b8 100644 --- a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch +++ b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch @@ -56,7 +56,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -467,6 +467,9 @@ static const struct usb_device_id blackl +@@ -469,6 +469,9 @@ static const struct usb_device_id blackl BTUSB_VALID_LE_STATES }, /* Additional MediaTek MT7921 Bluetooth devices */ diff --git a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch index b46e6926d1..b6b76f64fc 100644 --- a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch +++ b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch @@ -54,7 +54,7 @@ Signed-off-by: Luiz Augusto von Dentz --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -485,6 +485,9 @@ static const struct usb_device_id blackl +@@ -487,6 +487,9 @@ static const struct usb_device_id blackl { USB_DEVICE(0x0489, 0xe0cd), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH | BTUSB_VALID_LE_STATES }, diff --git a/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch b/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch new file mode 100644 index 0000000000..714ef49872 --- /dev/null +++ b/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch @@ -0,0 +1,69 @@ +From c278ec644377249aba5b1e1ca2b5705fd1c0132c Mon Sep 17 00:00:00 2001 +From: Paweł Owoc +Date: Mon, 1 Apr 2024 16:51:06 +0200 +Subject: [PATCH net-next v2] net: phy: aquantia: add support for AQR114C PHY ID + +Add support for AQR114C PHY ID. This PHY advertise 10G speed: +SPEED(0x04): 0x6031 + capabilities: -400g +5g +2.5g -200g -25g -10g-xr -100g -40g -10g/1g -10 + +100 +1000 -10-ts -2-tl +10g +EXTABLE(0x0B): 0x40fc + capabilities: -10g-cx4 -10g-lrm +10g-t +10g-kx4 +10g-kr +1000-t +1000-kx + +100-tx -10-t -p2mp -40g/100g -1000/100-t1 -25g -200g/400g + +2.5g/5g -1000-h + +but supports only up to 5G speed (as with AQR111/111B0). +AQR111 init config is used to set max speed 5G. + +Signed-off-by: Paweł Owoc +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240401145114.1699451-1-frut3k7@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -28,6 +28,7 @@ + #define PHY_ID_AQR412 0x03a1b712 + #define PHY_ID_AQR113 0x31c31c40 + #define PHY_ID_AQR113C 0x31c31c12 ++#define PHY_ID_AQR114C 0x31c31c22 + #define PHY_ID_AQR813 0x31c31cb2 + + #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 +@@ -880,6 +881,25 @@ static struct phy_driver aqr_driver[] = + .link_change_notify = aqr107_link_change_notify, + }, + { ++ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), ++ .name = "Aquantia AQR114C", ++ .probe = aqr107_probe, ++ .get_rate_matching = aqr107_get_rate_matching, ++ .config_init = aqr111_config_init, ++ .config_aneg = aqr_config_aneg, ++ .config_intr = aqr_config_intr, ++ .handle_interrupt = aqr_handle_interrupt, ++ .read_status = aqr107_read_status, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr107_suspend, ++ .resume = aqr107_resume, ++ .get_sset_count = aqr107_get_sset_count, ++ .get_strings = aqr107_get_strings, ++ .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++}, ++{ + PHY_ID_MATCH_MODEL(PHY_ID_AQR813), + .name = "Aquantia AQR813", + .probe = aqr107_probe, +@@ -916,6 +936,7 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, ++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, + { } + }; diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index be9454629e..c4e34e932d 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -4347,6 +4347,7 @@ CONFIG_NF_CONNTRACK_PROCFS=y # CONFIG_NF_DUP_IPV4 is not set # CONFIG_NF_DUP_IPV6 is not set # CONFIG_NF_FLOW_TABLE is not set +# CONFIG_NF_FLOW_TABLE_PROCFS is not set # CONFIG_NF_LOG_ARP is not set # CONFIG_NF_LOG_BRIDGE is not set # CONFIG_NF_LOG_IPV4 is not set diff --git a/target/linux/generic/hack-5.15/250-netfilter_depends.patch b/target/linux/generic/hack-5.15/250-netfilter_depends.patch index d9a2b81d74..1f8af6dbe8 100644 --- a/target/linux/generic/hack-5.15/250-netfilter_depends.patch +++ b/target/linux/generic/hack-5.15/250-netfilter_depends.patch @@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau depends on NETFILTER_ADVANCED help H.323 is a VoIP signalling protocol from ITU-T. As one of the most -@@ -1105,7 +1104,6 @@ config NETFILTER_XT_TARGET_SECMARK +@@ -1114,7 +1113,6 @@ config NETFILTER_XT_TARGET_SECMARK config NETFILTER_XT_TARGET_TCPMSS tristate '"TCPMSS" target support' diff --git a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch index 49f339bddc..d22b9f909b 100644 --- a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch +++ b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch @@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau help This option adds the flow table core infrastructure. -@@ -1010,6 +1009,15 @@ config NETFILTER_XT_TARGET_NOTRACK +@@ -1019,6 +1018,15 @@ config NETFILTER_XT_TARGET_NOTRACK depends on NETFILTER_ADVANCED select NETFILTER_XT_TARGET_CT @@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau depends on NETFILTER_ADVANCED --- a/net/netfilter/Makefile +++ b/net/netfilter/Makefile -@@ -143,6 +143,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF +@@ -144,6 +144,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch index 75c2e41fb6..b4ed6c9910 100644 --- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1152,6 +1157,11 @@ static const struct usb_device_id option +@@ -1156,6 +1161,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1193,6 +1203,11 @@ static const struct usb_device_id option +@@ -1197,6 +1207,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/hack-6.6/221-module_exports.patch b/target/linux/generic/hack-6.6/221-module_exports.patch deleted file mode 100644 index 294944a34b..0000000000 --- a/target/linux/generic/hack-6.6/221-module_exports.patch +++ /dev/null @@ -1,102 +0,0 @@ -From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:05:53 +0200 -Subject: add an optional config option for stripping all unnecessary symbol exports from the kernel image - -lede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc -Signed-off-by: Felix Fietkau ---- - include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++--- - include/linux/export.h | 9 ++++++++- - scripts/Makefile.build | 2 +- - 3 files changed, 24 insertions(+), 5 deletions(-) - ---- a/include/asm-generic/vmlinux.lds.h -+++ b/include/asm-generic/vmlinux.lds.h -@@ -81,6 +81,16 @@ - #define RO_EXCEPTION_TABLE - #endif - -+#ifndef SYMTAB_KEEP -+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) -+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) -+#endif -+ -+#ifndef SYMTAB_DISCARD -+#define SYMTAB_DISCARD -+#define SYMTAB_DISCARD_GPL -+#endif -+ - /* Align . function alignment. */ - #define ALIGN_FUNCTION() . = ALIGN(CONFIG_FUNCTION_ALIGNMENT) - -@@ -486,14 +496,14 @@ - /* Kernel symbol table: Normal symbols */ \ - __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ - __start___ksymtab = .; \ -- KEEP(*(SORT(___ksymtab+*))) \ -+ SYMTAB_KEEP \ - __stop___ksymtab = .; \ - } \ - \ - /* Kernel symbol table: GPL-only symbols */ \ - __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ - __start___ksymtab_gpl = .; \ -- KEEP(*(SORT(___ksymtab_gpl+*))) \ -+ SYMTAB_KEEP_GPL \ - __stop___ksymtab_gpl = .; \ - } \ - \ -@@ -513,7 +523,7 @@ - \ - /* Kernel symbol table: strings */ \ - __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ -- *(__ksymtab_strings) \ -+ *(__ksymtab_strings+*) \ - } \ - \ - /* __*init sections */ \ -@@ -1000,6 +1010,8 @@ - #define COMMON_DISCARDS \ - SANITIZER_DISCARDS \ - PATCHABLE_DISCARDS \ -+ SYMTAB_DISCARD \ -+ SYMTAB_DISCARD_GPL \ - *(.discard) \ - *(.discard.*) \ - *(.export_symbol) \ ---- a/include/linux/export-internal.h -+++ b/include/linux/export-internal.h -@@ -26,6 +26,12 @@ - #define __KSYM_REF(sym) ".long " #sym - #endif - -+#ifdef MODULE -+#define __EXPORT_SUFFIX(sym) -+#else -+#define __EXPORT_SUFFIX(sym) "+" #sym -+#endif -+ - /* - * For every exported symbol, do the following: - * -@@ -38,7 +44,7 @@ - * former apparently works on all arches according to the binutils source. - */ - #define __KSYMTAB(name, sym, sec, ns) \ -- asm(" .section \"__ksymtab_strings\",\"aMS\",%progbits,1" "\n" \ -+ asm(" .section \"__ksymtab_strings" __EXPORT_SUFFIX(sym) "\",\"aMS\",%progbits,1" "\n" \ - "__kstrtab_" #name ":" "\n" \ - " .asciz \"" #name "\"" "\n" \ - "__kstrtabns_" #name ":" "\n" \ ---- a/scripts/Makefile.build -+++ b/scripts/Makefile.build -@@ -366,7 +366,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa - # Linker scripts preprocessor (.lds.S -> .lds) - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds_S = LDS $@ -- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \ -+ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \ - -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< - - $(obj)/%.lds: $(src)/%.lds.S FORCE diff --git a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch index 1232c664ed..ff2038d6f7 100644 --- a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch +++ b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch @@ -15,7 +15,7 @@ Signed-off-by: Alex Marginean --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -101,6 +101,29 @@ +@@ -102,6 +102,29 @@ #define AQR107_OP_IN_PROG_SLEEP 1000 #define AQR107_OP_IN_PROG_TIMEOUT 100000 @@ -45,7 +45,7 @@ Signed-off-by: Alex Marginean struct aqr107_hw_stat { const char *name; int reg; -@@ -232,6 +255,51 @@ static int aqr_config_aneg(struct phy_de +@@ -233,6 +256,51 @@ static int aqr_config_aneg(struct phy_de return genphy_c45_check_and_restart_aneg(phydev, changed); } @@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean static int aqr_config_intr(struct phy_device *phydev) { bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -@@ -809,7 +877,7 @@ static struct phy_driver aqr_driver[] = +@@ -810,7 +878,7 @@ static struct phy_driver aqr_driver[] = PHY_ID_MATCH_MODEL(PHY_ID_AQR112), .name = "Aquantia AQR112", .probe = aqr107_probe, @@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean .config_intr = aqr_config_intr, .handle_interrupt = aqr_handle_interrupt, .get_tunable = aqr107_get_tunable, -@@ -827,7 +895,7 @@ static struct phy_driver aqr_driver[] = +@@ -828,7 +896,7 @@ static struct phy_driver aqr_driver[] = PHY_ID_MATCH_MODEL(PHY_ID_AQR412), .name = "Aquantia AQR412", .probe = aqr107_probe, diff --git a/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch index 72a70ebc14..614003a5d8 100644 --- a/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch +++ b/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch @@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru +@@ -289,10 +289,16 @@ static int aqr_config_aneg_set_prot(stru phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, aquantia_syscfg[if_type].start_rate); diff --git a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch index ee7d0c57b0..4a72b1bd2b 100644 --- a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch +++ b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch @@ -12,16 +12,16 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -29,6 +29,8 @@ - #define PHY_ID_AQR113 0x31c31c40 +@@ -30,6 +30,8 @@ #define PHY_ID_AQR113C 0x31c31c12 + #define PHY_ID_AQR114C 0x31c31c22 #define PHY_ID_AQR813 0x31c31cb2 +#define PHY_ID_AQR112C 0x03a1b790 +#define PHY_ID_AQR112R 0x31c31d12 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) -@@ -972,6 +974,30 @@ static struct phy_driver aqr_driver[] = +@@ -992,6 +994,30 @@ static struct phy_driver aqr_driver[] = .get_stats = aqr107_get_stats, .link_change_notify = aqr107_link_change_notify, }, @@ -52,9 +52,9 @@ Signed-off-by: Daniel Golle }; module_phy_driver(aqr_driver); -@@ -991,6 +1017,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, +@@ -1012,6 +1038,8 @@ static struct mdio_device_id __maybe_unu { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) }, diff --git a/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch index 9968a79699..a64d3021d4 100644 --- a/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch +++ b/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c -@@ -204,6 +204,9 @@ static void __br_handle_local_finish(str +@@ -209,6 +209,9 @@ static void __br_handle_local_finish(str /* note: already called with rcu_read_lock */ static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { @@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau __br_handle_local_finish(skb); /* return 1 to signal the okfn() was called so it's ok to use the skb */ -@@ -369,6 +372,17 @@ static rx_handler_result_t br_handle_fra +@@ -376,6 +379,17 @@ static rx_handler_result_t br_handle_fra forward: switch (p->state) { diff --git a/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch index b17196d3a9..8b1e70bd0e 100644 --- a/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch +++ b/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau for (i = sizeof(struct ipt_entry); i < e->target_offset; i += m->u.match_size) { -@@ -1224,12 +1261,15 @@ compat_copy_entry_to_user(struct ipt_ent +@@ -1226,12 +1263,15 @@ compat_copy_entry_to_user(struct ipt_ent compat_uint_t origsize; const struct xt_entry_match *ematch; int ret = 0; diff --git a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch index 66fd6efed5..6eb72abaa7 100644 --- a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch +++ b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -136,14 +136,14 @@ Signed-off-by: Felix Fietkau /** * eth_type_trans - determine the packet's protocol ID. * @skb: received socket data -@@ -173,6 +185,10 @@ __be16 eth_type_trans(struct sk_buff *sk - } else { - skb->pkt_type = PACKET_OTHERHOST; - } -+ -+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, -+ dev->local_addr_mask)) -+ skb->gro_skip = 1; - } +@@ -165,6 +177,10 @@ __be16 eth_type_trans(struct sk_buff *sk + eth_skb_pkt_type(skb, dev); + ++ if (unlikely(!ether_addr_equal_64bits(eth->h_dest, dev->dev_addr)) && ++ eth_check_local_mask(eth->h_dest, dev->dev_addr, dev->local_addr_mask)) ++ skb->gro_skip = 1; ++ /* + * Some variants of DSA tagging don't have an ethertype field + * at all, so we check here whether one of those tagging diff --git a/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch index 8c75554033..ba75e4a0f1 100644 --- a/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch +++ b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch @@ -10,9 +10,9 @@ Signed-off-by: Pablo Neira Ayuso --- a/net/netfilter/nf_flow_table_core.c +++ b/net/netfilter/nf_flow_table_core.c -@@ -606,13 +606,41 @@ void nf_flow_table_free(struct nf_flowta - } - EXPORT_SYMBOL_GPL(nf_flow_table_free); +@@ -651,6 +651,23 @@ static struct pernet_operations nf_flow_ + .exit_batch = nf_flow_table_pernet_exit, + }; +static int nf_flow_table_netdev_event(struct notifier_block *this, + unsigned long event, void *ptr) @@ -33,26 +33,30 @@ Signed-off-by: Pablo Neira Ayuso + static int __init nf_flow_table_module_init(void) { -- return nf_flow_table_offload_init(); -+ int ret; -+ -+ ret = nf_flow_table_offload_init(); -+ if (ret) -+ return ret; -+ + int ret; +@@ -663,8 +680,14 @@ static int __init nf_flow_table_module_i + if (ret) + goto out_offload; + + ret = register_netdevice_notifier(&flow_offload_netdev_notifier); + if (ret) -+ nf_flow_table_offload_exit(); ++ goto out_offload_init; + -+ return ret; - } + return 0; + ++out_offload_init: ++ nf_flow_table_offload_exit(); + out_offload: + unregister_pernet_subsys(&nf_flow_table_net_ops); + return ret; +@@ -672,6 +695,7 @@ out_offload: static void __exit nf_flow_table_module_exit(void) { + unregister_netdevice_notifier(&flow_offload_netdev_notifier); nf_flow_table_offload_exit(); + unregister_pernet_subsys(&nf_flow_table_net_ops); } - --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c @@ -455,47 +455,14 @@ static struct nft_expr_type nft_flow_off diff --git a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index 2f1b3ed793..3037a724bf 100644 --- a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -7803,7 +7803,7 @@ static int nft_register_flowtable_net_ho +@@ -7811,7 +7811,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch index bbbebefdd5..fd1b79cdfe 100644 --- a/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch +++ b/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch @@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev) --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c -@@ -326,6 +326,8 @@ static rx_handler_result_t br_handle_fra +@@ -331,6 +331,8 @@ static rx_handler_result_t br_handle_fra fwd_mask |= p->group_fwd_mask; switch (dest[5]) { case 0x00: /* Bridge Group Address */ diff --git a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch index f10fa057d5..792135b0d2 100644 --- a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch +++ b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch @@ -15,16 +15,7 @@ Signed-off-by: Alexander Couzens --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2467,7 +2467,7 @@ mt7531_setup(struct dsa_switch *ds) - struct mt7530_priv *priv = ds->priv; - struct mt7530_dummy_poll p; - u32 val, id; -- int ret; -+ int ret, i; - - /* Reset whole chip through gpio pin or memory-mapped registers for - * different type of hardware -@@ -2499,6 +2499,10 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2680,6 +2680,10 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } diff --git a/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch index b1e7a35a55..e3edfa47c6 100644 --- a/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch +++ b/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch @@ -13,7 +13,15 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -744,6 +744,38 @@ static int rtl8226_match_phy_device(stru +@@ -79,6 +79,7 @@ + #define RTLGEN_SPEED_MASK 0x0630 + + #define RTL_GENERIC_PHYID 0x001cc800 ++#define RTL_8221B_VB_CG_PHYID 0x001cc849 + + MODULE_DESCRIPTION("Realtek PHY driver"); + MODULE_AUTHOR("Johnson Leung"); +@@ -744,6 +745,38 @@ static int rtl8226_match_phy_device(stru rtlgen_supports_2_5gbps(phydev); } @@ -46,13 +54,13 @@ Signed-off-by: Daniel Golle + id |= val; + } + -+ return (id == 0x001cc849); ++ return (id == RTL_8221B_VB_CG_PHYID); +} + static int rtl822x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; -@@ -1082,7 +1114,7 @@ static struct phy_driver realtek_drvs[] +@@ -1082,7 +1115,7 @@ static struct phy_driver realtek_drvs[] .write_page = rtl821x_write_page, .soft_reset = genphy_soft_reset, }, { diff --git a/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch index bf0e0aa66d..07d46d8daa 100644 --- a/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch +++ b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -971,6 +971,51 @@ static int rtl8221b_config_init(struct p +@@ -972,6 +972,51 @@ static int rtl8221b_config_init(struct p return 0; } @@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), -@@ -1119,6 +1164,8 @@ static struct phy_driver realtek_drvs[] +@@ -1120,6 +1165,8 @@ static struct phy_driver realtek_drvs[] .get_features = rtl822x_get_features, .config_init = rtl8221b_config_init, .config_aneg = rtl822x_config_aneg, diff --git a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch index b0c0185335..609e03d964 100644 --- a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch +++ b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2174,10 +2174,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2356,10 +2356,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr { struct dsa_switch *ds = priv->ds; struct device *dev = priv->dev; @@ -30,7 +30,7 @@ Signed-off-by: David Bauer bus = devm_mdiobus_alloc(dev); if (!bus) return -ENOMEM; -@@ -2194,7 +2197,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2376,7 +2379,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr if (priv->irq) mt7530_setup_mdio_irq(priv); diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch index 0f97033db6..1697347b53 100644 --- a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch +++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch @@ -33,7 +33,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2877,8 +2877,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -3065,8 +3065,7 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ diff --git a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch index a8c084b980..b127d76e00 100644 --- a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch +++ b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch @@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz /* * We need to store the untouched command line for future reference. * We also need to store the touched command line since the parameter -@@ -958,6 +981,7 @@ asmlinkage __visible void __init __no_sa +@@ -960,6 +983,7 @@ asmlinkage __visible void __init __no_sa pr_notice("%s", linux_banner); early_security_init(); setup_arch(&command_line); diff --git a/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch index f5987109f6..05edcc8bf4 100644 --- a/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch @@ -13,7 +13,15 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -754,6 +754,38 @@ static int rtl8226_match_phy_device(stru +@@ -80,6 +80,7 @@ + + #define RTL_GENERIC_PHYID 0x001cc800 + #define RTL_8211FVD_PHYID 0x001cc878 ++#define RTL_8221B_VB_CG_PHYID 0x001cc849 + + MODULE_DESCRIPTION("Realtek PHY driver"); + MODULE_AUTHOR("Johnson Leung"); +@@ -754,6 +755,38 @@ static int rtl8226_match_phy_device(stru rtlgen_supports_2_5gbps(phydev); } @@ -46,13 +54,13 @@ Signed-off-by: Daniel Golle + id |= val; + } + -+ return (id == 0x001cc849); ++ return (id == RTL_8221B_VB_CG_PHYID); +} + static int rtl822x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; -@@ -1104,7 +1136,7 @@ static struct phy_driver realtek_drvs[] +@@ -1104,7 +1137,7 @@ static struct phy_driver realtek_drvs[] .write_page = rtl821x_write_page, .soft_reset = genphy_soft_reset, }, { diff --git a/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch index 82cd419a7e..249ba5c496 100644 --- a/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -981,6 +981,51 @@ static int rtl8221b_config_init(struct p +@@ -982,6 +982,51 @@ static int rtl8221b_config_init(struct p return 0; } @@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), -@@ -1141,6 +1186,8 @@ static struct phy_driver realtek_drvs[] +@@ -1142,6 +1187,8 @@ static struct phy_driver realtek_drvs[] .get_features = rtl822x_get_features, .config_init = rtl8221b_config_init, .config_aneg = rtl822x_config_aneg, diff --git a/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch index 1d30a19654..0e9affd16a 100644 --- a/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch @@ -1,4 +1,4 @@ -From e52faf1564a8bcaf866f9a6c7bf0e8a8748afb15 Mon Sep 17 00:00:00 2001 +From 0de82310d2b32e78ff79d42c08b1122a6ede3778 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 30 Apr 2023 00:15:41 +0100 Subject: [PATCH] net: phy: realtek: detect early version of RTL8221B @@ -10,9 +10,6 @@ Implement custom identify function using the PKGID instead of iterating over the implemented MMDs. Signed-off-by: Daniel Golle ---- - drivers/net/phy/realtek.c | 50 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 49 insertions(+), 1 deletion(-) --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -20,12 +17,12 @@ Signed-off-by: Daniel Golle #define RTL_GENERIC_PHYID 0x001cc800 #define RTL_8211FVD_PHYID 0x001cc878 -+#define RTL_8221B_VB_CG 0x001cc849 ++#define RTL_8221B_VB_CG_PHYID 0x001cc849 MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); -@@ -801,6 +802,54 @@ static int rtl822x_probe(struct phy_devi - return 0; +@@ -782,6 +783,38 @@ static int rtl8226_match_phy_device(stru + rtlgen_supports_2_5gbps(phydev); } +static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev) @@ -33,14 +30,6 @@ Signed-off-by: Daniel Golle + int val; + u32 id; + -+ if (phydev->is_c45) { -+ if (phydev->c45_ids.device_ids[1]) -+ return phydev->c45_ids.device_ids[1] == RTL_8221B_VB_CG; -+ } else { -+ if (phydev->phy_id) -+ return phydev->phy_id == RTL_8221B_VB_CG; -+ } -+ + if (phydev->mdio.bus->read_c45) { + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PKGID1); + if (val < 0) @@ -65,21 +54,13 @@ Signed-off-by: Daniel Golle + id |= val; + } + -+ if (id != RTL_8221B_VB_CG) -+ return 0; -+ -+ if (phydev->is_c45) -+ phydev->c45_ids.device_ids[1] = id; -+ else -+ phydev->phy_id = id; -+ -+ return 1; ++ return (id == RTL_8221B_VB_CG_PHYID); +} + - static int rtlgen_resume(struct phy_device *phydev) + static int rtl822x_probe(struct phy_device *phydev) { - int ret = genphy_resume(phydev); -@@ -1134,7 +1183,7 @@ static struct phy_driver realtek_drvs[] + struct device *dev = &phydev->mdio.dev; +@@ -1134,7 +1167,7 @@ static struct phy_driver realtek_drvs[] .write_page = rtl821x_write_page, .soft_reset = genphy_soft_reset, }, { diff --git a/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch index e4fbf1f870..726f66cf64 100644 --- a/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1026,6 +1026,51 @@ static int rtl8221b_config_init(struct p +@@ -1010,6 +1010,51 @@ static int rtl8221b_config_init(struct p return 0; } @@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), -@@ -1188,6 +1233,8 @@ static struct phy_driver realtek_drvs[] +@@ -1172,6 +1217,8 @@ static struct phy_driver realtek_drvs[] .get_features = rtl822x_get_features, .config_init = rtl8221b_config_init, .config_aneg = rtl822x_config_aneg, diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts index b3eb610b32..a5b55ff421 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts @@ -243,6 +243,18 @@ &mdio { status = "okay"; + + ar8035: ethernet-phy@0 { + reg = <0>; + }; +}; + +&qca807x { + status = "disabled"; +}; + +ðphy0 { + status = "disabled"; }; ðphy1 { @@ -279,6 +291,6 @@ status = "okay"; label = "lan"; - phy-handle = <ðphy0>; + phy-handle = <&ar8035>; phy-mode = "rgmii-id"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi index 8c56c7d2f1..7f8f9be795 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi @@ -232,6 +232,10 @@ phy-mode = "rgmii-id"; }; +&qca807x { + status = "disabled"; +}; + ðphy0 { status = "disabled"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi index da22d4a671..3637b96d24 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi @@ -401,6 +401,10 @@ status = "okay"; pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; + + ar8035: ethernet-phy@1 { + reg = <1>; + }; }; &gmac { @@ -419,14 +423,22 @@ status = "okay"; label = "lan"; - phy-handle = <ðphy1>; + phy-handle = <&ar8035>; phy-mode = "rgmii-rxid"; }; +&qca807x { + status = "disabled"; +}; + ðphy0 { status = "disabled"; }; +ðphy1 { + status = "disabled"; +}; + ðphy2 { status = "disabled"; }; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts index 12f15bd147..f10fa367f1 100644 --- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts @@ -14,10 +14,10 @@ }; aliases { - led-boot = &ledctrl3; + led-boot = &ledctrl1; led-failsafe = &ledctrl1; - led-running = &ledctrl2; - led-upgrade = &ledctrl3; + led-running = &ledctrl3; + led-upgrade = &ledctrl1; }; chosen { @@ -55,6 +55,7 @@ ledctrl2: ledctrl2 { label = "ledctrl2"; gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; }; ledctrl3: ledctrl3 { diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi index a8f43591f9..2e71575331 100644 --- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi @@ -73,10 +73,6 @@ &pcie0 { status = "okay"; - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - bridge@0,0 { reg = <0x0 0 0 0 0>; #address-cells = <3>; @@ -94,10 +90,6 @@ &pcie1 { status = "okay"; - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - bridge@0,0 { reg = <0x0 0 0 0 0>; #address-cells = <3>; @@ -115,10 +107,6 @@ &pcie2 { status = "okay"; - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - bridge@0,0 { reg = <0x0 0 0 0 0>; #address-cells = <3>; diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index 2e166a5f37..d900416d3a 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -10,6 +10,7 @@ FEATURES:=squashfs SUBTARGETS:=xrx200 xway xway_legacy falcon ase KERNEL_PATCHVER:=5.15 +KERNEL_TESTING_PATCHVER:=6.1 define Target/Description Build firmware images for Lantiq SoC diff --git a/target/linux/lantiq/ase/config-5.15 b/target/linux/lantiq/ase/config-5.15 index 195e49df69..c4d8e575eb 100644 --- a/target/linux/lantiq/ase/config-5.15 +++ b/target/linux/lantiq/ase/config-5.15 @@ -3,7 +3,6 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set CONFIG_CPU_MIPSR1=y CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_GENERIC_ALLOCATOR=y @@ -15,7 +14,7 @@ CONFIG_LANTIQ_ETOP=y CONFIG_NLS=y CONFIG_SGL_ALLOC=y CONFIG_SOC_AMAZON_SE=y -CONFIG_SOC_TYPE_XWAY=y +# CONFIG_SOC_XWAY is not set CONFIG_SWCONFIG=y CONFIG_TARGET_ISA_REV=1 CONFIG_USB=y diff --git a/target/linux/lantiq/ase/config-6.1 b/target/linux/lantiq/ase/config-6.1 new file mode 100644 index 0000000000..c4d8e575eb --- /dev/null +++ b/target/linux/lantiq/ase/config-6.1 @@ -0,0 +1,24 @@ +CONFIG_ADM6996_PHY=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HW_RANDOM=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_NLS=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AMAZON_SE=y +# CONFIG_SOC_XWAY is not set +CONFIG_SWCONFIG=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-5.15 b/target/linux/lantiq/config-5.15 index 90d48fff04..39862948e2 100644 --- a/target/linux/lantiq/config-5.15 +++ b/target/linux/lantiq/config-5.15 @@ -1,30 +1,15 @@ CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_CPU_BIG_ENDIAN=y CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y @@ -32,6 +17,7 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y @@ -42,20 +28,18 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 CONFIG_CRYPTO_RNG2=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y CONFIG_DTC=y # CONFIG_DT_EASY50712 is not set CONFIG_EARLY_PRINTK=y -CONFIG_EFI_EARLYCON=y CONFIG_FIXED_PHY=y -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_FONT_SUPPORT=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IRQ_CHIP=y @@ -71,6 +55,7 @@ CONFIG_GENERIC_PHY=y CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_CDEV=y CONFIG_GPIO_MM_LANTIQ=y CONFIG_GPIO_STP_XWAY=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -78,46 +63,10 @@ CONFIG_HARDWARE_WATCHPOINTS=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y @@ -139,19 +88,16 @@ CONFIG_MIGRATION=y CONFIG_MIPS=y CONFIG_MIPS_ASID_BITS=8 CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set # CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_EBPF_JIT=y CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_MIPS_LD_CAN_LINK_VDSO=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_NO_APPENDED_DTB is not set CONFIG_MIPS_RAW_APPENDED_DTB=y CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_MODULES_USE_ELF_REL=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_GEOMETRY=y @@ -166,8 +112,10 @@ CONFIG_MTD_SPLIT_TPLINK_FW=y CONFIG_MTD_SPLIT_UIMAGE_FW=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_SELFTESTS=y CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y @@ -176,8 +124,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -# CONFIG_PCIE_LANTIQ is not set CONFIG_PCI_DRIVERS_LEGACY=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 @@ -190,6 +136,7 @@ CONFIG_PINCTRL_LANTIQ=y CONFIG_PINCTRL_XWAY=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y CONFIG_RESET_CONTROLLER=y @@ -199,7 +146,8 @@ CONFIG_SERIAL_LANTIQ=y CONFIG_SERIAL_LANTIQ_CONSOLE=y # CONFIG_SOC_AMAZON_SE is not set # CONFIG_SOC_FALCON is not set -# CONFIG_SOC_XWAY is not set +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y CONFIG_SPI=y CONFIG_SPI_LANTIQ_SSC=y CONFIG_SPI_MASTER=y diff --git a/target/linux/lantiq/config-6.1 b/target/linux/lantiq/config-6.1 new file mode 100644 index 0000000000..e037a63068 --- /dev/null +++ b/target/linux/lantiq/config-6.1 @@ -0,0 +1,182 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +# CONFIG_DT_EASY50712 is not set +CONFIG_EARLY_PRINTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_DT_NONE=y +# CONFIG_LANTIQ_ETOP is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_SELFTESTS=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHY_LANTIQ_RCU_USB2=y +# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_LANTIQ=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +CONFIG_SERIAL_LANTIQ_CONSOLE=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SPI=y +CONFIG_SPI_LANTIQ_SSC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/lantiq/falcon/config-5.15 b/target/linux/lantiq/falcon/config-5.15 index 3041c65dbd..d5c5c61505 100644 --- a/target/linux/lantiq/falcon/config-5.15 +++ b/target/linux/lantiq/falcon/config-5.15 @@ -1,4 +1,3 @@ -CONFIG_CPU_HAS_DIEI=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y @@ -6,4 +5,5 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" CONFIG_PINCTRL_FALCON=y CONFIG_SOC_FALCON=y +# CONFIG_SOC_XWAY is not set CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/falcon/config-6.1 b/target/linux/lantiq/falcon/config-6.1 new file mode 100644 index 0000000000..d5c5c61505 --- /dev/null +++ b/target/linux/lantiq/falcon/config-6.1 @@ -0,0 +1,9 @@ +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_PINCTRL_FALCON=y +CONFIG_SOC_FALCON=y +# CONFIG_SOC_XWAY is not set +CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi index 5c608dab63..6ae7ab6188 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi @@ -197,7 +197,7 @@ compatible = "lantiq,mei-xway"; reg = <0xe116000 0x400>; interrupt-parent = <&icu0>; - interrupts = <81>; + interrupts = <81 83 92>; }; usb: usb@e101000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi index b12005ff6b..789ca67002 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi @@ -376,7 +376,7 @@ compatible = "lantiq,mei-xway"; reg = <0xe116000 0x9c>; interrupt-parent = <&icu0>; - interrupts = <63>; + interrupts = <63 61 68>; }; gsw: etop@e180000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi index c19ce2af7e..5fe6699ac2 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi @@ -291,7 +291,7 @@ compatible = "lantiq,mei-xway"; reg = <0xe116000 0x400>; interrupt-parent = <&icu0>; - interrupts = <63>; + interrupts = <63 61 159>; }; gsw: etop@e180000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi index e4c9be8f87..e0e49f377a 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -528,7 +528,7 @@ reg = <0xd900000 0x1000>; interrupt-parent = <&icu0>; - interrupts = <161 144>; + interrupts = <161 144 145 146 147>; phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>; phy-names = "pcie"; diff --git a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch index 16b87ed0a5..3e6c267685 100644 --- a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch +++ b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -186,7 +186,7 @@ Signed-off-by: John Crispin obj-y += vmmc.o --- /dev/null +++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,852 @@ +@@ -0,0 +1,887 @@ +#ifndef CONFIG_SOC_AMAZON_SE + +#include @@ -203,6 +203,8 @@ Signed-off-by: John Crispin +#include +#include + ++#include ++ +#include +#include +#include "../clk.h" @@ -978,10 +980,10 @@ Signed-off-by: John Crispin + return 0; +} + -+int __init lq_gptu_init(void) ++static int gptu_probe(struct platform_device *pdev) +{ + int ret; -+ unsigned int i; ++ int i; + + ltq_w32(0, LQ_GPTU_IRNEN); + ltq_w32(0xfff, LQ_GPTU_IRNCR); @@ -1005,15 +1007,24 @@ Signed-off-by: John Crispin + } + + for (i = 0; i < timer_dev.number_of_timers; i++) { -+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ for (; i >= 0; i--) -+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ int irq = platform_get_irq(pdev, i); ++ if (irq < 0) { ++ printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq); ++ for (i--; i >= 0; i--) ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); + misc_deregister(&gptu_miscdev); ++ return irq; ++ } ++ ++ ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ for (i--; i >= 0; i--) ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); + return ret; + } else { -+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ timer_dev.timer[i].irq = irq; + disable_irq(timer_dev.timer[i].irq); + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); + } @@ -1022,6 +1033,30 @@ Signed-off-by: John Crispin + return 0; +} + ++static const struct of_device_id gptu_match[] = { ++ { .compatible = "lantiq,gptu-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, gptu_match); ++ ++static struct platform_driver gptu_driver = { ++ .probe = gptu_probe, ++ .driver = { ++ .name = "gptu-xway", ++ .owner = THIS_MODULE, ++ .of_match_table = gptu_match, ++ }, ++}; ++ ++int __init lq_gptu_init(void) ++{ ++ int ret = platform_driver_register(&gptu_driver); ++ ++ if (ret) ++ pr_info("gptu: Error registering platform driver\n"); ++ return ret; ++} ++ +void __exit lq_gptu_exit(void) +{ + unsigned int i; diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch index a11ec3ec98..93108cac3a 100644 --- a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch +++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch @@ -39,7 +39,19 @@ Signed-off-by: Eddi De Pieri #include "ifxmips_pcie.h" #include "ifxmips_pcie_reg.h" -@@ -40,6 +47,11 @@ +@@ -25,11 +32,6 @@ + #define IFX_PCIE_ERROR_INT + #define IFX_PCIE_IO_32BIT + +-#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) +-#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) +-#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) +-#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) +-#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) + #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) + #define SM(_v, _f) (((_v) << _f##_S) & (_f)) + #define IFX_REG_SET_BIT(_f, _r) \ +@@ -40,30 +42,30 @@ static DEFINE_SPINLOCK(ifx_pcie_lock); u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); @@ -51,7 +63,31 @@ Signed-off-by: Eddi De Pieri static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { { -@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ... + .ir_irq = { +- .irq = IFX_PCIE_IR, + .name = "ifx_pcie_rc0", + }, + + .legacy_irq = { + { + .irq_bit = PCIE_IRN_INTA, +- .irq = IFX_PCIE_INTA, + }, + { + .irq_bit = PCIE_IRN_INTB, +- .irq = IFX_PCIE_INTB, + }, + { + .irq_bit = PCIE_IRN_INTC, +- .irq = IFX_PCIE_INTC, + }, + { + .irq_bit = PCIE_IRN_INTD, +- .irq = IFX_PCIE_INTD, + }, + }, + }, +@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ... printk("%s", buf); } @@ -74,7 +110,17 @@ Signed-off-by: Eddi De Pieri static inline int pcie_ltssm_enable(int pcie_port) { -@@ -988,10 +1016,26 @@ int ifx_pcie_bios_plat_dev_init(struct +@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port) + ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, + pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); + if (ret) +- printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, ++ pcie_irqs[pcie_port].ir_irq.irq); + + return ret; + } +@@ -988,10 +1007,26 @@ int ifx_pcie_bios_plat_dev_init(struct static int pcie_rc_initialize(int pcie_port) { @@ -103,7 +149,7 @@ Signed-off-by: Eddi De Pieri pcie_ep_gpio_rst_init(pcie_port); -@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port) +@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port) * reset PCIe PHY will solve this issue */ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { @@ -140,7 +186,7 @@ Signed-off-by: Eddi De Pieri /* Enable PCIe PHY and Clock */ pcie_core_pmu_setup(pcie_port); -@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port) +@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port) /* Once link is up, break out */ if (pcie_app_loigc_setup(pcie_port) == 0) break; @@ -151,7 +197,7 @@ Signed-off-by: Eddi De Pieri } if (i >= IFX_PCIE_PHY_LOOP_CNT) { printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port) +@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port) return 0; } @@ -193,10 +239,9 @@ Signed-off-by: Eddi De Pieri - + + ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); -+ if (IS_ERR(ltq_pcie_phy)) { -+ dev_err(&pdev->dev, "failed to get the PCIe PHY\n"); -+ return PTR_ERR(ltq_pcie_phy); -+ } ++ if (IS_ERR(ltq_pcie_phy)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy), ++ "failed to get the PCIe PHY\n"); + + ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); + if (IS_ERR(ltq_pcie_reset)) { @@ -228,15 +273,27 @@ Signed-off-by: Eddi De Pieri for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ if (pcie_rc_initialize(pcie_port) == 0) { IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi +@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi + IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); return -ENOMEM; } ++ pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0); ++ if (pcie_irqs[pcie_port].ir_irq.irq < 0) ++ return pcie_irqs[pcie_port].ir_irq.irq; ++ ++ for (int i = 0; i <= 3; i++){ ++ pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1); ++ ++ if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0) ++ return pcie_irqs[pcie_port].legacy_irq[i].irq; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; + pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); /* XXX, clear error status */ -@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi +@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi return 0; } @@ -409,3 +466,21 @@ Signed-off-by: Eddi De Pieri static inline void pcie_core_pmu_setup(int pcie_port) { struct clk *clk; +--- a/arch/mips/pci/ifxmips_pcie.h ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -96,13 +96,13 @@ struct ifx_pci_controller { + }; + + typedef struct ifx_pcie_ir_irq { +- const unsigned int irq; ++ unsigned int irq; + const char name[16]; + }ifx_pcie_ir_irq_t; + + typedef struct ifx_pcie_legacy_irq{ + const u32 irq_bit; +- const int irq; ++ int irq; + }ifx_pcie_legacy_irq_t; + + typedef struct ifx_pcie_irq { diff --git a/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch new file mode 100644 index 0000000000..472a24e66b --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch @@ -0,0 +1,97 @@ +From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Mon, 13 May 2024 10:42:24 +0200 +Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs + from dts + +Let's fetch the irqs from the dts here and expose them to the voice +driver like it is done for the cp1 base memory. + +ToDo: +Maybe it is possible to drop this driver completely and merge this +handling to the voice driver. + +Signed-off-by: Martin Schiller +--- + arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +--- a/arch/mips/lantiq/xway/vmmc.c ++++ b/arch/mips/lantiq/xway/vmmc.c +@@ -13,6 +13,10 @@ + + static unsigned int *cp1_base; + ++static int ad0_irq; ++static int ad1_irq; ++static int vc_irq[4]; ++ + unsigned int *ltq_get_cp1_base(void) + { + if (!cp1_base) +@@ -22,16 +26,65 @@ unsigned int *ltq_get_cp1_base(void) + } + EXPORT_SYMBOL(ltq_get_cp1_base); + ++unsigned int ltq_get_mps_ad0_irq(void) ++{ ++ if (!ad0_irq) ++ panic("no ad0 irq was set\n"); ++ ++ return ad0_irq; ++} ++EXPORT_SYMBOL(ltq_get_mps_ad0_irq); ++ ++unsigned int ltq_get_mps_ad1_irq(void) ++{ ++ if (!ad1_irq) ++ panic("no ad1 irq was set\n"); ++ ++ return ad1_irq; ++} ++EXPORT_SYMBOL(ltq_get_mps_ad1_irq); ++ ++unsigned int ltq_get_mps_vc_irq(int idx) ++{ ++ if (!vc_irq[idx]) ++ panic("no vc%d irq was set\n", idx); ++ ++ return vc_irq[idx]; ++} ++EXPORT_SYMBOL(ltq_get_mps_vc_irq); ++ + static int vmmc_probe(struct platform_device *pdev) + { + #define CP1_SIZE (1 << 20) + int gpio_count; + dma_addr_t dma; ++ int i; + + cp1_base = + (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE, + &dma, GFP_KERNEL)); + ++ ad0_irq = platform_get_irq(pdev, 4); ++ if (ad0_irq < 0) { ++ dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq); ++ return ad0_irq; ++ } ++ ++ ad1_irq = platform_get_irq(pdev, 5); ++ if (ad1_irq < 0) { ++ dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq); ++ return ad1_irq; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ vc_irq[i] = platform_get_irq(pdev, i); ++ if (vc_irq[i] < 0) { ++ dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n", ++ i, vc_irq[i]); ++ return vc_irq[i]; ++ } ++ } ++ + gpio_count = of_gpio_count(pdev->dev.of_node); + while (gpio_count > 0) { + enum of_gpio_flags flags; diff --git a/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch b/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch new file mode 100644 index 0000000000..c6befe05e5 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch @@ -0,0 +1,32 @@ +From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 10 Oct 2022 16:52:25 +0200 +Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing + phy-mode and fixed-link + +The CPU port has to specify a phy-mode and either a phy or a fixed-link. +Since GSWIP is connected using a SoC internal protocol there's no PHY +involved. Add phy-mode = "internal" and a fixed-link to describe the +communication between the PMAC (Ethernet controller) and GSWIP switch. + +Signed-off-by: Martin Blumenstingl +--- + Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt ++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt +@@ -97,7 +97,13 @@ switch@e108000 { + port@6 { + reg = <0x6>; + label = "cpu"; ++ phy-mode = "internal"; + ethernet = <ð0>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + }; + diff --git a/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch b/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch new file mode 100644 index 0000000000..cc94a41cf3 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch @@ -0,0 +1,33 @@ +From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 10 Oct 2022 16:59:35 +0200 +Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode = + "internal" on the CPU port + +Add the CPU port to gswip_xrx200_phylink_get_caps() and +gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus, +so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1513,6 +1513,7 @@ static void gswip_xrx200_phylink_validat + case 2: + case 3: + case 4: ++ case 6: + if (state->interface != PHY_INTERFACE_MODE_INTERNAL) + goto unsupported; + break; +@@ -1552,6 +1553,7 @@ static void gswip_xrx300_phylink_validat + case 2: + case 3: + case 4: ++ case 6: + if (state->interface != PHY_INTERFACE_MODE_INTERNAL) + goto unsupported; + break; diff --git a/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch b/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch new file mode 100644 index 0000000000..b1658e15d8 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch @@ -0,0 +1,145 @@ +From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 31 Jul 2022 22:54:52 +0200 +Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where + appropriate + +dev_err_probe() can be used to simplify the existing code. Also it means +we get rid of the following warning which is seen whenever the PMAC +(Ethernet controller which connects to GSWIP's CPU port) has not been +probed yet: + gswip 1e108000.switch: dsa switch register failed: -517 + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------ + 1 file changed, 25 insertions(+), 28 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1939,11 +1939,9 @@ static int gswip_gphy_fw_load(struct gsw + msleep(200); + + ret = request_firmware(&fw, gphy_fw->fw_name, dev); +- if (ret) { +- dev_err(dev, "failed to load firmware: %s, error: %i\n", +- gphy_fw->fw_name, ret); +- return ret; +- } ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to load firmware: %s\n", ++ gphy_fw->fw_name); + + /* GPHY cores need the firmware code in a persistent and contiguous + * memory area with a 16 kB boundary aligned start address. +@@ -1956,9 +1954,9 @@ static int gswip_gphy_fw_load(struct gsw + dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); + memcpy(fw_addr, fw->data, fw->size); + } else { +- dev_err(dev, "failed to alloc firmware memory\n"); + release_firmware(fw); +- return -ENOMEM; ++ return dev_err_probe(dev, -ENOMEM, ++ "failed to alloc firmware memory\n"); + } + + release_firmware(fw); +@@ -1985,8 +1983,8 @@ static int gswip_gphy_fw_probe(struct gs + + gphy_fw->clk_gate = devm_clk_get(dev, gphyname); + if (IS_ERR(gphy_fw->clk_gate)) { +- dev_err(dev, "Failed to lookup gate clock\n"); +- return PTR_ERR(gphy_fw->clk_gate); ++ return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate), ++ "Failed to lookup gate clock\n"); + } + + ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); +@@ -2006,8 +2004,8 @@ static int gswip_gphy_fw_probe(struct gs + gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; + break; + default: +- dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); +- return -EINVAL; ++ return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n", ++ gphy_mode); + } + + gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); +@@ -2060,8 +2058,9 @@ static int gswip_gphy_fw_list(struct gsw + priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; + break; + default: +- dev_err(dev, "unknown GSWIP version: 0x%x", version); +- return -ENOENT; ++ return dev_err_probe(dev, -ENOENT, ++ "unknown GSWIP version: 0x%x", ++ version); + } + } + +@@ -2069,10 +2068,9 @@ static int gswip_gphy_fw_list(struct gsw + if (match && match->data) + priv->gphy_fw_name_cfg = match->data; + +- if (!priv->gphy_fw_name_cfg) { +- dev_err(dev, "GPHY compatible type not supported"); +- return -ENOENT; +- } ++ if (!priv->gphy_fw_name_cfg) ++ return dev_err_probe(dev, -ENOENT, ++ "GPHY compatible type not supported"); + + priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); + if (!priv->num_gphy_fw) +@@ -2171,8 +2169,8 @@ static int gswip_probe(struct platform_d + return -EINVAL; + break; + default: +- dev_err(dev, "unknown GSWIP version: 0x%x", version); +- return -ENOENT; ++ return dev_err_probe(dev, -ENOENT, ++ "unknown GSWIP version: 0x%x", version); + } + + /* bring up the mdio bus */ +@@ -2180,10 +2178,9 @@ static int gswip_probe(struct platform_d + if (gphy_fw_np) { + err = gswip_gphy_fw_list(priv, gphy_fw_np, version); + of_node_put(gphy_fw_np); +- if (err) { +- dev_err(dev, "gphy fw probe failed\n"); +- return err; +- } ++ if (err) ++ return dev_err_probe(dev, err, ++ "gphy fw probe failed\n"); + } + + /* bring up the mdio bus */ +@@ -2191,20 +2188,20 @@ static int gswip_probe(struct platform_d + if (mdio_np) { + err = gswip_mdio(priv, mdio_np); + if (err) { +- dev_err(dev, "mdio probe failed\n"); ++ dev_err_probe(dev, err, "mdio probe failed\n"); + goto put_mdio_node; + } + } + + err = dsa_register_switch(priv->ds); + if (err) { +- dev_err(dev, "dsa switch register failed: %i\n", err); ++ dev_err_probe(dev, err, "dsa switch registration failed\n"); + goto mdio_bus; + } + if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { +- dev_err(dev, "wrong CPU port defined, HW only supports port: %i", +- priv->hw_info->cpu_port); +- err = -EINVAL; ++ err = dev_err_probe(dev, -EINVAL, ++ "wrong CPU port defined, HW only supports port: %i", ++ priv->hw_info->cpu_port); + goto disable_switch; + } + diff --git a/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch b/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch new file mode 100644 index 0000000000..1493826c53 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch @@ -0,0 +1,25 @@ +From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 28 Jul 2022 22:37:11 +0200 +Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call + gswip_port_enable() + +We don't need to manually call gswip_port_enable() from within +gswip_setup() for the CPU port. DSA does this automatically for us. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -874,8 +874,6 @@ static int gswip_setup(struct dsa_switch + + ds->mtu_enforcement_ingress = true; + +- gswip_port_enable(ds, cpu_port, NULL); +- + ds->configure_vlan_while_not_filtering = false; + + return 0; diff --git a/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch b/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch new file mode 100644 index 0000000000..2d95b37358 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch @@ -0,0 +1,70 @@ +From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Fri, 10 May 2024 13:52:10 +0200 +Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port + +Before commit 74be4babe72f ("net: dsa: do not enable or disable non user +ports"), gswip_port_enable/disable() were also executed for the cpu port +in gswip_setup() which disabled the cpu port during initialization. + +Let's restore this by removing the dsa_is_user_port checks. Also, let's +clean up the gswip_port_enable() function so that we only have to check +for the cpu port once. + +Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports") +Signed-off-by: Martin Schiller +--- + drivers/net/dsa/lantiq_gswip.c | 24 ++++++++---------------- + 1 file changed, 8 insertions(+), 16 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -671,13 +671,18 @@ static int gswip_port_enable(struct dsa_ + struct gswip_priv *priv = ds->priv; + int err; + +- if (!dsa_is_user_port(ds, port)) +- return 0; +- + if (!dsa_is_cpu_port(ds, port)) { ++ u32 mdio_phy = 0; ++ + err = gswip_add_single_port_br(priv, port, true); + if (err) + return err; ++ ++ if (phydev) ++ mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; ++ ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); + } + + /* RMON Counter Enable for port */ +@@ -690,16 +695,6 @@ static int gswip_port_enable(struct dsa_ + gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, + GSWIP_SDMA_PCTRLp(port)); + +- if (!dsa_is_cpu_port(ds, port)) { +- u32 mdio_phy = 0; +- +- if (phydev) +- mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; +- +- gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, +- GSWIP_MDIO_PHYp(port)); +- } +- + return 0; + } + +@@ -707,9 +702,6 @@ static void gswip_port_disable(struct ds + { + struct gswip_priv *priv = ds->priv; + +- if (!dsa_is_user_port(ds, port)) +- return; +- + gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, + GSWIP_FDMA_PCTRLp(port)); + gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, diff --git a/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch b/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch new file mode 100644 index 0000000000..26f7c0f414 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch @@ -0,0 +1,30 @@ +From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 18 May 2022 23:53:09 +0200 +Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in + gswip_port_change_mtu() + +Make the check for the CPU port in gswip_port_change_mtu() consistent +with other areas of the driver by using dsa_is_cpu_port(). + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1463,12 +1463,11 @@ static int gswip_port_max_mtu(struct dsa + static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) + { + struct gswip_priv *priv = ds->priv; +- int cpu_port = priv->hw_info->cpu_port; + + /* CPU port always has maximum mtu of user ports, so use it to set + * switch frame size, including 8 byte special header. + */ +- if (port == cpu_port) { ++ if (dsa_is_cpu_port(ds, port)) { + new_mtu += 8; + gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, + GSWIP_MAC_FLEN); diff --git a/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch b/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch new file mode 100644 index 0000000000..0a17d14759 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch @@ -0,0 +1,24 @@ +From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Tue, 17 May 2022 22:39:58 +0200 +Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN + +The addr variable in gswip_port_fdb_dump() stores a mac address. Use +ETH_ALEN to make this consistent across other drivers. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1383,7 +1383,7 @@ static int gswip_port_fdb_dump(struct ds + { + struct gswip_priv *priv = ds->priv; + struct gswip_pce_table_entry mac_bridge = {0,}; +- unsigned char addr[6]; ++ unsigned char addr[ETH_ALEN]; + int i; + int err; + diff --git a/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch b/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch new file mode 100644 index 0000000000..87382876c2 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch @@ -0,0 +1,47 @@ +From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 21:23:49 +0200 +Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for + the mac bridge table + +Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout +the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT() +macro. This makes the driver code easier to understand. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -236,7 +236,8 @@ + #define GSWIP_TABLE_ACTIVE_VLAN 0x01 + #define GSWIP_TABLE_VLAN_MAPPING 0x02 + #define GSWIP_TABLE_MAC_BRIDGE 0x0b +-#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ ++#define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */ ++#define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + +@@ -1279,7 +1280,8 @@ static void gswip_port_fast_age(struct d + if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) + continue; + +- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) ++ if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT, ++ mac_bridge.val[0])) + continue; + + mac_bridge.valid = false; +@@ -1414,7 +1416,8 @@ static int gswip_port_fdb_dump(struct ds + return err; + } + } else { +- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { ++ if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT, ++ mac_bridge.val[0])) { + err = cb(addr, 0, false, data); + if (err) + return err; diff --git a/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch b/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch new file mode 100644 index 0000000000..aafea1ec2e --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch @@ -0,0 +1,26 @@ +From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 22:24:24 +0200 +Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid + gswip_add_single_port_br on the CPU port + +Calling gswip_add_single_port_br() with the CPU port would be a bug +because then only the CPU port could talk to itself. Add the CPU port to +the validation at the beginning of gswip_add_single_port_br(). + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -633,7 +633,7 @@ static int gswip_add_single_port_br(stru + unsigned int max_ports = priv->hw_info->max_ports; + int err; + +- if (port >= max_ports) { ++ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) { + dev_err(priv->dev, "single port for %i supported\n", port); + return -EIO; + } diff --git a/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch b/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch new file mode 100644 index 0000000000..ef8302fe80 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch @@ -0,0 +1,26 @@ +From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 22:26:20 +0200 +Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in + gswip_add_single_port_br() + +The error message is printed when the port cannot be used. Update the +error message to reflect that. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -634,7 +634,8 @@ static int gswip_add_single_port_br(stru + int err; + + if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) { +- dev_err(priv->dev, "single port for %i supported\n", port); ++ dev_err(priv->dev, "single port for %i is not supported\n", ++ port); + return -EIO; + } + diff --git a/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch b/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch new file mode 100644 index 0000000000..6eeed5b27a --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch @@ -0,0 +1,36 @@ +From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 14:06:40 +0200 +Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in + gswip_port_vlan_filtering() + +Update the comments in gswip_port_vlan_filtering() so it's clear that +there are two separate cases, one for "tag based VLAN" and another one +for "port based VLAN". + +Suggested-by: Martin Schiller +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -762,7 +762,7 @@ static int gswip_port_vlan_filtering(str + } + + if (vlan_filtering) { +- /* Use port based VLAN tag */ ++ /* Use tag based VLAN */ + gswip_switch_mask(priv, + GSWIP_PCE_VCTRL_VSR, + GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | +@@ -771,7 +771,7 @@ static int gswip_port_vlan_filtering(str + gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, + GSWIP_PCE_PCTRL_0p(port)); + } else { +- /* Use port based VLAN tag */ ++ /* Use port based VLAN */ + gswip_switch_mask(priv, + GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | + GSWIP_PCE_VCTRL_VEMR, diff --git a/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch b/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch new file mode 100644 index 0000000000..b9912e8735 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch @@ -0,0 +1,33 @@ +From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 14:19:05 +0200 +Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a + GSWIP_TABLE_MAC_BRIDGE_FID macro + +Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a +macro so this becomes obvious when reading the driver code. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -238,6 +238,7 @@ + #define GSWIP_TABLE_MAC_BRIDGE 0x0b + #define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */ + #define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */ ++#define GSWIP_TABLE_MAC_BRIDGE_FID GENMASK(5, 0) /* Filtering identifier */ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + +@@ -1357,7 +1358,7 @@ static int gswip_port_fdb(struct dsa_swi + mac_bridge.key[0] = addr[5] | (addr[4] << 8); + mac_bridge.key[1] = addr[3] | (addr[2] << 8); + mac_bridge.key[2] = addr[1] | (addr[0] << 8); +- mac_bridge.key[3] = fid; ++ mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid); + mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ + mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; + mac_bridge.valid = add; diff --git a/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch b/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch new file mode 100644 index 0000000000..2538a4c856 --- /dev/null +++ b/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch @@ -0,0 +1,26 @@ +From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 16:31:57 +0200 +Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in + gswip_port_fdb() + +Print the port which is not found to be part of a bridge so it's easier +to investigate the underlying issue. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1349,7 +1349,8 @@ static int gswip_port_fdb(struct dsa_swi + } + + if (fid == -1) { +- dev_err(priv->dev, "Port not part of a bridge\n"); ++ dev_err(priv->dev, ++ "Port %d is not known to be part of bridge\n", port); + return -EINVAL; + } + diff --git a/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000000..b8f3116bb4 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5550 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -20,6 +20,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HAVE_PCI ++ select ARCH_SUPPORTS_MSI + select MFD_SYSCON + select MFD_CORE + +@@ -52,4 +53,13 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + endif +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -41,6 +41,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o + obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o + obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -6,12 +6,19 @@ + + #include + #include ++#include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability((struct pci_dev *)dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,53 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#define IFX_PCI_CONST const ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1091 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,131 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,305 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn) ++{ ++ struct pci_dev *dev; ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) { ++ if (dev->devfn == devfn) ++ goto out; ++ } ++ ++ dev = NULL; ++ out: ++ pci_dev_get(dev); ++ return dev; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = ifx_pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,391 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,284 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn) ++{ ++ struct pci_dev *dev; ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) { ++ if (dev->devfn == devfn) ++ goto out; ++ } ++ ++ dev = NULL; ++ out: ++ pci_dev_get(dev); ++ return dev; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = ifx_pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ +--- a/arch/mips/pci/pci-legacy.c ++++ b/arch/mips/pci/pci-legacy.c +@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str) + return pcibios_plat_setup(str); + return str; + } ++ ++int pcibios_host_nr(void) ++{ ++ int count = 0; ++ struct pci_controller *hose; ++ list_for_each_entry(hose, &controllers, list) { ++ count++; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose; ++ ++ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1316 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn) ++{ ++ struct pci_dev *dev; ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) { ++ if (dev->devfn == devfn) ++ goto out; ++ } ++ ++ dev = NULL; ++ out: ++ pci_dev_get(dev); ++ return dev; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = ifx_pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/Kconfig ++++ b/drivers/pci/pcie/Kconfig +@@ -51,6 +51,7 @@ config PCIEAER_INJECT + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1558,6 +1558,8 @@ void pci_walk_bus_locked(struct pci_bus + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1097,6 +1097,12 @@ + #define PCI_DEVICE_ID_SGI_IOC3 0x0003 + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch b/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch new file mode 100644 index 0000000000..6b70f8b9a7 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch @@ -0,0 +1,62 @@ +From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Mon, 6 May 2024 09:41:42 +0200 +Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity + +Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not +only switched to the gpiod API, but also inverted / changed the polarity +of the GPIO. + +According to the PCI specification, the RST# pin is an active-low +signal. However, most of the device trees that have been widely used for +a long time (mainly in the openWrt project) define this GPIO as +active-high and the old driver code inverted the signal internally. + +Apparently there are actually boards where the reset gpio must be +operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH +flag for initialization. Instead, we must explicitly set the gpio to +value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that +may have been set. + +In order to remain compatible with all these existing device trees, we +should therefore keep the logic as it was before the commit. + +Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") +Cc: stable@vger.kernel.org +Signed-off-by: Martin Schiller +--- + arch/mips/pci/pci-lantiq.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo + clk_disable(clk_external); + + /* setup reset gpio used by pci */ +- reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", +- GPIOD_OUT_LOW); ++ reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS); + error = PTR_ERR_OR_ZERO(reset_gpio); + if (error) { + dev_err(&pdev->dev, "failed to request gpio: %d\n", error); + return error; + } + gpiod_set_consumer_name(reset_gpio, "pci_reset"); ++ gpiod_direction_output(reset_gpio, 1); + + /* enable auto-switching between PCI and EBU */ + ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); +@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo + + /* toggle reset pin */ + if (reset_gpio) { +- gpiod_set_value_cansleep(reset_gpio, 1); ++ gpiod_set_value_cansleep(reset_gpio, 0); + wmb(); + mdelay(1); +- gpiod_set_value_cansleep(reset_gpio, 0); ++ gpiod_set_value_cansleep(reset_gpio, 1); + } + return 0; + } diff --git a/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000000..e32e4e2daa --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,482 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 4 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d) + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo + void (*_dma_cache_wback)(unsigned long start, unsigned long size); + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + ++EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); ++ + #endif /* CONFIG_DMA_NONCOHERENT */ + + /* +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -131,8 +131,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000000..3e6c267685 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1076 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,10 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o ++ ++ifdef CONFIG_SOC_AMAZON_SE ++obj-y += gptu.o ++else ++obj-y += timer.o ++endif + + obj-y += vmmc.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,887 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ if (copy_from_user(¶m, (void __user *)arg, sizeof(param))) ++ return -EFAULT; ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok((void __user *)arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value,sizeof(param.value))) ++ ret = -EFAULT; ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret))) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_probe(struct platform_device *pdev) ++{ ++ int ret; ++ int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ int irq = platform_get_irq(pdev, i); ++ if (irq < 0) { ++ printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq); ++ for (i--; i >= 0; i--) ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ return irq; ++ } ++ ++ ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ for (i--; i >= 0; i--) ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = irq; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id gptu_match[] = { ++ { .compatible = "lantiq,gptu-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, gptu_match); ++ ++static struct platform_driver gptu_driver = { ++ .probe = gptu_probe, ++ .driver = { ++ .name = "gptu-xway", ++ .owner = THIS_MODULE, ++ .of_match_table = gptu_match, ++ }, ++}; ++ ++int __init lq_gptu_init(void) ++{ ++ int ret = platform_driver_register(&gptu_driver); ++ ++ if (ret) ++ pr_info("gptu: Error registering platform driver\n"); ++ return ret; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000000..f420d8cde5 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,121 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/raw/xway_nand.c ++++ b/drivers/mtd/nand/raw/xway_nand.c +@@ -61,6 +61,24 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++static __be32 req_mask = 0; ++ + struct xway_nand_data { + struct nand_controller controller; + struct nand_chip chip; +@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } ++ + spin_unlock_irqrestore(&ebu_lock, data->csflags); + break; + case 0: + spin_lock_irqsave(&ebu_lock, data->csflags); ++ ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch + { + struct mtd_info *mtd = nand_to_mtd(chip); + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ ++ } ++ + if (cmd == NAND_CMD_NONE) + return; + +@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch + + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct nand_chip *chip) +@@ -169,6 +222,7 @@ static int xway_nand_probe(struct platfo + int err; + u32 cs; + u32 cs_flag = 0; ++ const __be32 *req_mask_ptr; + + /* Allocate memory for the device structure (and zero it) */ + data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), +@@ -204,6 +258,15 @@ static int xway_nand_probe(struct platfo + if (!err && cs == 1) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); ++ ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(data->nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000000..c1fc59487a --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch new file mode 100644 index 0000000000..fcc760b911 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -0,0 +1,294 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p + XWAY_MDIO_MIICTRL_TXSKEW_MASK, val); + } + ++#if IS_ENABLED(CONFIG_OF_MDIO) ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ u32 tmp; ++ ++ /* store the led values if one was passed by the devicetree */ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); ++ ++ return 0; ++} ++#else ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ return 0; ++} ++#endif /* CONFIG_OF_MDIO */ ++ + static int xway_gphy_config_init(struct phy_device *phydev) + { + int err; +@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct + if (err) + return err; + ++ vr9_gphy_of_reg_init(phydev); + return 0; + } + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt +@@ -0,0 +1,216 @@ ++Lanitq PHY binding ++============================================ ++ ++This devicetree binding controls the lantiq ethernet phys led functionality. ++ ++Example: ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "lantiq,xrx200-mdio"; ++ phy5: ethernet-phy@5 { ++ reg = <0x1>; ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; ++ }; ++ phy11: ethernet-phy@11 { ++ reg = <0x11>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy12: ethernet-phy@12 { ++ reg = <0x12>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ phy13: ethernet-phy@13 { ++ reg = <0x13>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy14: ethernet-phy@14 { ++ reg = <0x14>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ }; ++ ++Register Description ++============================================ ++ ++LEDCH: ++ ++Name Hardware Reset Value ++LEDCH 0x00C5 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| FBF | SBF |RES | NACS | ++========================================= ++ ++Field Bits Type Description ++FBF 7:6 RW Fast Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++SBF 5:4 RW Slow Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++NACS 2:0 RW Inverse of Scan Function ++ --- ++ 0x0 (000b) NONE No Function ++ 0x1 (001b) LINK Complex function enabled when link is up ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running ++ 0x7 (111b) TEST Complex function enabled when test mode is running ++ ++LEDCL: ++ ++Name Hardware Reset Value ++LEDCL 0x0067 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++|RES | SCAN |RES | CBLINK | ++========================================= ++ ++Field Bits Type Description ++SCAN 6:4 RW Complex Scan Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++CBLINK 2:0 RW Complex Blinking Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++LEDxH: ++ ++Name Hardware Reset Value ++LED0H 0x0070 ++LED1H 0x0020 ++LED2H 0x0040 ++LED3H 0x0040 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| CON | BLINKF | ++========================================= ++ ++Field Bits Type Description ++CON 7:4 RW Constant On Configuration ++ --- ++ 0x0 (0000b) NONE LED does not light up constantly ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN LED is on when device is powered-down ++ 0x9 (1001b) EEE LED is on when device is in EEE mode ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running ++ 0xB (1011b) ABIST LED is on when analog self-test is running ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running ++ ++BLINKF 3:0 RW Fast Blinking Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running ++ ++LEDxL: ++ ++Name Hardware Reset Value ++LED0L 0x0003 ++LED1L 0x0000 ++LED2L 0x0000 ++LED3L 0x0020 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| BLINKS | PULSE | ++========================================= ++ ++Field Bits Type Description ++BLINKS 7:4 RW Slow Blinkin Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning ++ ++PULSE 3:0 RW Pulsing Configuration ++ The pulse field is a mask field by which certain events can be combined ++ --- ++ 0x0 (0000b) NONE No pulsing ++ 0x1 (0001b) TXACT Transmit activity ++ 0x2 (0010b) RXACT Receive activity ++ 0x4 (0100b) COL Collision ++ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000000..8ac1097267 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,886 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -20,12 +20,17 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -33,7 +38,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -42,44 +47,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) ((x) == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) ((x) == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -89,26 +141,39 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; + + int tx_burst_len; + int rx_burst_len; + +- spinlock_t lock; ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ phy_interface_t mii_mode; ++ ++ spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = +@@ -143,8 +208,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -152,7 +220,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int work_done = 0; ++ unsigned long flags; + + while (work_done < budget) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -164,7 +234,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (work_done < budget) { + napi_complete_done(&ch->napi, work_done); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return work_done; + } +@@ -176,12 +248,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -194,7 +268,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -202,9 +278,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -216,7 +293,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + + for (desc = 0; desc < LTQ_DESC_NUM; desc++) +@@ -228,80 +305,135 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; +- int err; ++ phy_interface_t mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); + +- switch (priv->pldata->mii_mode) { ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); ++ ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE, +- LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL, +- LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->dma.nr = i; +- ch->idx = ch->dma.nr; +- ch->dma.dev = &priv->pdev->dev; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- if (err) { +- netdev_err(dev, +- "Unable to get Tx DMA IRQ %d\n", +- irq); +- return err; +- } +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); +- if (err) { +- netdev_err(dev, +- "Unable to get Rx DMA IRQ %d\n", +- irq); +- return err; +- } ++ priv->txch.dma.nr = tx; ++ priv->txch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ priv->rxch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -320,6 +452,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -327,9 +492,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -340,12 +505,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -361,7 +526,10 @@ ltq_etop_mdio_probe(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev; + +- phydev = phy_find_first(priv->mii_bus); ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = mdiobus_get_phy(priv->mii_bus, 8); ++ else ++ phydev = mdiobus_get_phy(priv->mii_bus, 0); + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -369,14 +537,17 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, phydev_name(phydev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phy_set_max_speed(phydev, SPEED_100); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_set_max_speed(phydev, SPEED_1000); ++ else ++ phy_set_max_speed(phydev, SPEED_100); + + phy_attached_info(phydev); + +@@ -397,8 +568,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -435,18 +611,21 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_enable_irq(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ ltq_dma_enable_irq(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (dev->phydev) ++ phy_start(dev->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- ltq_dma_enable_irq(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(dev->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -455,18 +634,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(dev->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (dev->phydev) ++ phy_stop(dev->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -476,15 +656,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -492,7 +673,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a burst length value aligned address */ + byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); + +@@ -503,11 +684,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -518,11 +699,14 @@ ltq_etop_change_mtu(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; ++ int max; + + dev->mtu = new_mtu; + ++ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +@@ -575,6 +759,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -592,9 +779,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -614,6 +802,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + netif_trans_update(dev); + netif_wake_queue(dev); + return; +@@ -637,14 +828,18 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -670,19 +865,55 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode); ++ if (err) ++ pr_err("Can't find phy-mode for port\n"); ++ ++ of_get_mac_address(pdev->dev.of_node, priv->mac); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + +@@ -698,15 +929,10 @@ ltq_etop_probe(struct platform_device *p + goto err_free; + } + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add_weight(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add_weight(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -735,31 +961,22 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", ++ .of_match_table = ltq_etop_match, + }, + }; + +-static int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000000..b5f79e95a8 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -795,6 +795,16 @@ config I2C_MICROCHIP_CORE + This driver can also be built as a module. If so, the module will be + called i2c-microchip-core. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MICROCHIP_CORE) += i2c-microchip-corei2c.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ adap->dev.parent = &pdev->dev; ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); ++ if (IS_ERR(priv->membase)) ++ return PTR_ERR(priv->membase); ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ 0x0, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ 0x0, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ 0x0, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ 0x0, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ goto out; ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = ltq_i2c_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000000..aea5716596 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,218 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 25 ++++ + drivers/net/ethernet/lantiq_etop.c | 6 +- + 5 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -8,3 +8,6 @@ obj-y += timer.o + endif + + obj-y += vmmc.o ++ ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath5k_eep.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath5k_eep.c +@@ -0,0 +1,136 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej Vlašić ++ * Copyright (C) 2013 Álvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * Copyright (C) 2015 Vittorio Gambaletta ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++static int ath5k_eep_load; ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ list = of_get_property(np, "ath,eep-flash", &i); ++ if (!list || (i != (2 * sizeof(*list)))) ++ return -ENODEV; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENODEV; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ the_mtd = get_mtd_device_nm(part); ++ if (IS_ERR(the_mtd)) ++ return -ENODEV; ++ ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); ++ ++ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, ++ &flash_readlen, (void *) ath5k_pdata.eeprom_data); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ ++ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) ++ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ eth_random_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++ ++ if (ret) ++ ath5k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath5k_eeprom_init_late(void) ++{ ++ if (!ath5k_eep_load) ++ return 0; ++ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++late_initcall(of_ath5k_eeprom_init_late); ++subsys_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++early_param("ethaddr", setup_ethaddr); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -763,7 +763,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ ++ if (!is_valid_ether_addr(mac.sa_data)) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch new file mode 100644 index 0000000000..c81222af57 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch @@ -0,0 +1,24 @@ +From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jun 2016 13:12:20 +0200 +Subject: [PATCH] arch: mips: increase io_space_limit + +this value comes from x86 and breaks some pci devices + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/spaces.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __ASM_MACH_LANTIQ_SPACES_H_ ++#define __ASM_MACH_LANTIQ_SPACES_H_ ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#include ++#endif diff --git a/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch new file mode 100644 index 0000000000..a3bbda7c33 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch @@ -0,0 +1,80 @@ +From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:55:24 +0100 +Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs + +The size of the internal RAM of the DesignWare USB controller changed +between the different Lantiq SoCs. We have the following sizes: + +Amazon + Danube: 8 KByte +Amazon SE + arx100: 2 KByte +xrx200 + xrx300: 2.5 KByte + +For Danube SoC we do not provide the params and let the driver decide +to use sane defaults, for the Amazon SE and arx100 we use small fifos +and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. +The auto detection of max_transfer_size and max_packet_count should +work, so remove it. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 39 insertions(+), 7 deletions(-) + +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -115,7 +115,15 @@ static void dwc2_set_rk_params(struct dw + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + } + +-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) ++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_caps.hnp_support = false; ++ p->otg_caps.srp_support = false; ++} ++ ++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; + +@@ -124,12 +132,21 @@ static void dwc2_set_ltq_params(struct d + p->host_rx_fifo_size = 288; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 96; +- p->max_transfer_size = 65535; +- p->max_packet_count = 511; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; + } + ++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_caps.hnp_support = false; ++ p->otg_caps.srp_support = false; ++ p->host_rx_fifo_size = 288; ++ p->host_nperio_tx_fifo_size = 128; ++ p->host_perio_tx_fifo_size = 136; ++} ++ + static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -241,8 +258,11 @@ const struct of_device_id dwc2_of_match_ + { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, + { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, + { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, +- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, +- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, ++ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, ++ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, ++ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, + { .compatible = "snps,dwc2" }, + { .compatible = "samsung,s3c6400-hsotg", + .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch new file mode 100644 index 0000000000..dca9880e8f --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch @@ -0,0 +1,49 @@ +From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:40:12 +0100 +Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization + +This adds code to initialize the USB controller and PHY also on Danube, +Amazon SE and AR10. This code is based on the Vendor driver from +different UGW versions and compared to the hardware documentation. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ + 2 files changed, 110 insertions(+), 30 deletions(-) + + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk) + pr_warn("deactivating PMU module failed!"); + } + ++static void usb_set_clock(void) ++{ ++ unsigned int val = ltq_cgu_r32(ifccr); ++ ++ if (of_machine_is_compatible("lantiq,ar10") || ++ of_machine_is_compatible("lantiq,grx390")) { ++ val &= ~0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) { ++ /* TODO: this depends on the XTAL frequency */ ++ val |= 0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ase")) { ++ val |= 0x20; /* from XTAL */ ++ } else if (of_machine_is_compatible("lantiq,danube")) { ++ val |= 0x30; /* 12 MHz, generated from 36 MHz */ ++ } ++ ltq_cgu_w32(val, ifccr); ++} ++ + /* the pci enable helper */ + static int pci_enable(struct clk *clk) + { +@@ -589,4 +608,5 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } ++ usb_set_clock(); + } diff --git a/target/linux/lantiq/patches-6.1/0101-find_active_root.patch b/target/linux/lantiq/patches-6.1/0101-find_active_root.patch new file mode 100644 index 0000000000..99e187a012 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0101-find_active_root.patch @@ -0,0 +1,103 @@ +From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Mon, 2 May 2016 18:50:00 +0000 +Subject: [PATCH] find active root + +Signed-off-by: Mathias Kresin +--- + drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++- + 1 file changed, 48 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/parsers/ofpart_core.c ++++ b/drivers/mtd/parsers/ofpart_core.c +@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, ++ loff_t offset) ++{ ++ static uint8_t root_id; ++ int err, len; ++ ++ err = mtd_read(master, offset, 0x01, &len, &root_id); ++ ++ if (mtd_is_bitflip(err) || !err) ++ return &root_id; ++ ++ return NULL; ++} ++ ++static void brnboot_set_active_root_part(struct mtd_partition *pparts, ++ struct device_node **part_nodes, ++ int nr_parts, ++ uint8_t *root_id) ++{ ++ int i; ++ ++ for (i = 0; i < nr_parts; i++) { ++ int part_root_id; ++ ++ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) ++ && part_root_id == *root_id) { ++ pparts[i].name = "firmware"; ++ break; ++ } ++ } ++} ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct + struct device_node *pp; + int nr_parts, i, ret = 0; + bool dedicated = true; ++ uint8_t *proot_id = NULL; ++ struct device_node **part_nodes; + + /* Pull of_node from the master device node */ + mtd_node = mtd_get_of_node(master); +@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct + return 0; + + parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); +- if (!parts) ++ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); ++ ++ if (!parts || !part_nodes) + return -ENOMEM; + + i = 0; +@@ -166,6 +202,11 @@ static int parse_fixed_partitions(struct + if (of_property_read_bool(pp, "slc-mode")) + parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; + ++ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) ++ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); ++ ++ part_nodes[i] = pp; ++ + i++; + } + +@@ -175,6 +216,11 @@ static int parse_fixed_partitions(struct + if (quirks && quirks->post_parse) + quirks->post_parse(master, parts, nr_parts); + ++ if (proot_id) ++ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); ++ ++ kfree(part_nodes); ++ + *pparts = parts; + return nr_parts; + +@@ -185,6 +231,7 @@ ofpart_fail: + ofpart_none: + of_node_put(pp); + kfree(parts); ++ kfree(part_nodes); + return ret; + } + diff --git a/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000000..b83bf992a6 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,486 @@ +From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001 +From: Eddi De Pieri +Date: Tue, 14 Oct 2014 11:04:00 +0000 +Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of + +Signed-off-by: Eddi De Pieri +--- + arch/mips/pci/Makefile | 2 +- + arch/mips/pci/ifxmips_pcie.c | 151 +++++++++++++++++++++++++++---- + arch/mips/pci/ifxmips_pcie_vr9.h | 105 --------------------- + 3 files changed, 133 insertions(+), 125 deletions(-) + +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -41,7 +41,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o +-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o + obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o + obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -16,8 +16,15 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + #include + ++#include ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -25,11 +32,6 @@ + #define IFX_PCIE_ERROR_INT + #define IFX_PCIE_IO_32BIT + +-#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) +-#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) +-#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) +-#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) +-#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) + #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) + #define SM(_v, _f) (((_v) << _f##_S) & (_f)) + #define IFX_REG_SET_BIT(_f, _r) \ +@@ -40,30 +42,30 @@ + static DEFINE_SPINLOCK(ifx_pcie_lock); + + u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++static int pcie_reset_gpio; ++static struct phy *ltq_pcie_phy; ++static struct reset_control *ltq_pcie_reset; ++static struct regmap *ltq_rcu_regmap; ++static bool switch_pcie_endianess; + + static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { + { + .ir_irq = { +- .irq = IFX_PCIE_IR, + .name = "ifx_pcie_rc0", + }, + + .legacy_irq = { + { + .irq_bit = PCIE_IRN_INTA, +- .irq = IFX_PCIE_INTA, + }, + { + .irq_bit = PCIE_IRN_INTB, +- .irq = IFX_PCIE_INTB, + }, + { + .irq_bit = PCIE_IRN_INTC, +- .irq = IFX_PCIE_INTC, + }, + { + .irq_bit = PCIE_IRN_INTD, +- .irq = IFX_PCIE_INTD, + }, + }, + }, +@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ... + printk("%s", buf); + } + ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ gpio_direction_output(pcie_reset_gpio, 1); ++ gpio_set_value(pcie_reset_gpio, 1); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(pcie_reset_gpio, 0); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(pcie_reset_gpio, 1); ++} + + static inline int pcie_ltssm_enable(int pcie_port) + { +@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port) + ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, + pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); + if (ret) +- printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, ++ pcie_irqs[pcie_port].ir_irq.irq); + + return ret; + } +@@ -988,10 +1007,26 @@ int ifx_pcie_bios_plat_dev_init(struct + static int + pcie_rc_initialize(int pcie_port) + { +- int i; ++ int i, ret; + #define IFX_PCIE_PHY_LOOP_CNT 5 + +- pcie_rcu_endian_setup(pcie_port); ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M, ++ IFX_RCU_AHB_BE_PCIE_M); ++ ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ IFX_RCU_AHB_BE_PCIE_S); ++ if (switch_pcie_endianess) { ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S, ++ IFX_RCU_AHB_BE_XBAR_S); ++ } ++#else ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ 0x0); ++#endif ++ ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M, ++ 0x0); + + pcie_ep_gpio_rst_init(pcie_port); + +@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port) + * reset PCIe PHY will solve this issue + */ + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { +- /* Disable PCIe PHY Analog part for sanity check */ +- pcie_phy_pmu_disable(pcie_port); +- +- pcie_phy_rst_assert(pcie_port); +- pcie_phy_rst_deassert(pcie_port); +- +- /* Make sure PHY PLL is stable */ +- udelay(20); +- +- /* PCIe Core reset enabled, low active, sw programmed */ +- pcie_core_rst_assert(pcie_port); ++ ret = phy_init(ltq_pcie_phy); ++ if (ret) ++ continue; + + /* Put PCIe EP in reset status */ + pcie_device_rst_assert(pcie_port); + +- /* PCI PHY & Core reset disabled, high active, sw programmed */ +- pcie_core_rst_deassert(pcie_port); ++ udelay(1); ++ reset_control_deassert(ltq_pcie_reset); + +- /* Already in a quiet state, program PLL, enable PHY, check ready bit */ +- pcie_phy_clock_mode_setup(pcie_port); ++ ret = phy_power_on(ltq_pcie_phy); ++ if (ret) { ++ phy_exit(ltq_pcie_phy); ++ continue; ++ } + + /* Enable PCIe PHY and Clock */ + pcie_core_pmu_setup(pcie_port); +@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port) + /* Once link is up, break out */ + if (pcie_app_loigc_setup(pcie_port) == 0) + break; ++ ++ phy_power_off(ltq_pcie_phy); ++ reset_control_assert(ltq_pcie_reset); ++ phy_exit(ltq_pcie_phy); + } + if (i >= IFX_PCIE_PHY_LOOP_CNT) { + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); +@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int ifx_pcie_bios_probe(struct platform_device *pdev) + { ++ struct device_node *node = pdev->dev.of_node; + void __iomem *io_map_base; + int pcie_port; + int startup_port; ++ struct device_node *np; ++ struct pci_bus *bus; ++ ++ /* ++ * In case a PCI device is physical present, the Lantiq PCI driver need ++ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them ++ * will work. ++ * ++ * In case the lantiq PCI driver is enabled in the device tree, check if ++ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already ++ * registered. ++ * ++ * It will fail if there is another PCI controller, this controller is ++ * registered before the Lantiq PCIe driver is probe and the lantiq PCI ++ */ ++ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); ++ ++ if (of_device_is_available(np)) { ++ bus = pci_find_next_bus(bus); ++ ++ if (!bus) ++ return -EPROBE_DEFER; ++ } + + /* Enable AHB Master/ Slave */ + pcie_ahb_pmu_setup(); + + startup_port = IFX_PCIE_PORT0; +- ++ ++ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); ++ if (IS_ERR(ltq_pcie_phy)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy), ++ "failed to get the PCIe PHY\n"); ++ ++ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); ++ if (IS_ERR(ltq_pcie_reset)) { ++ dev_err(&pdev->dev, "failed to get the PCIe reset line\n"); ++ return PTR_ERR(ltq_pcie_reset); ++ } ++ ++ if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) { ++ switch_pcie_endianess = true; ++ dev_info(&pdev->dev, "switch pcie endianess requested\n"); ++ } else { ++ switch_pcie_endianess = false; ++ } ++ ++ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu"); ++ if (IS_ERR(ltq_rcu_regmap)) ++ return PTR_ERR(ltq_rcu_regmap); ++ ++ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); ++ if (gpio_is_valid(pcie_reset_gpio)) { ++ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); ++ return ret; ++ } ++ gpio_direction_output(pcie_reset_gpio, 1); ++ } ++ + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ + if (pcie_rc_initialize(pcie_port) == 0) { + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", +@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi + IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); + return -ENOMEM; + } ++ pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0); ++ if (pcie_irqs[pcie_port].ir_irq.irq < 0) ++ return pcie_irqs[pcie_port].ir_irq.irq; ++ ++ for (int i = 0; i <= 3; i++){ ++ pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1); ++ ++ if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0) ++ return pcie_irqs[pcie_port].legacy_irq[i].irq; ++ } ++ + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); + + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); + /* XXX, clear error status */ +@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); +--- a/arch/mips/pci/ifxmips_pcie_vr9.h ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -22,8 +22,6 @@ + #include + #include + +-#define IFX_PCIE_GPIO_RESET 494 +- + #define IFX_REG_R32 ltq_r32 + #define IFX_REG_W32 ltq_w32 + #define CONFIG_IFX_PCIE_HW_SWAP +@@ -54,21 +52,6 @@ + #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) + + +-static inline void pcie_ep_gpio_rst_init(int pcie_port) +-{ +- +- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- +-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ +-} +- + static inline void pcie_ahb_pmu_setup(void) + { + /* Enable AHB bus master/slave */ +@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo + //AHBS_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_rcu_endian_setup(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +-#ifdef CONFIG_IFX_PCIE_HW_SWAP +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg |= IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#else +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg &= ~IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#endif /* CONFIG_IFX_PCIE_HW_SWAP */ +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); +-} +- + static inline void pcie_phy_pmu_enable(int pcie_port) + { + struct clk *clk; +@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable( + // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); + } + +-static inline void pcie_pdi_big_endian(int pcie_port) +-{ +- u32 reg; +- +- /* SRAM2PDI endianness control. */ +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +- /* Config AHB->PCIe and PDI endianness */ +- reg |= IFX_RCU_AHB_BE_PCIE_PDI; +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +-} +- + static inline void pcie_pdi_pmu_enable(int pcie_port) + { + /* Enable PDI to access PCIe PHY register */ +@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i + //PDI_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_core_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- +- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ +- reg |= 0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_core_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- /* Reset PCIe PHY & Core, bit 22 */ +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg |= 0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_device_rst_assert(int pcie_port) +-{ +- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); +-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- +-static inline void pcie_device_rst_deassert(int pcie_port) +-{ +- mdelay(100); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- + static inline void pcie_core_pmu_setup(int pcie_port) + { + struct clk *clk; +--- a/arch/mips/pci/ifxmips_pcie.h ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -96,13 +96,13 @@ struct ifx_pci_controller { + }; + + typedef struct ifx_pcie_ir_irq { +- const unsigned int irq; ++ unsigned int irq; + const char name[16]; + }ifx_pcie_ir_irq_t; + + typedef struct ifx_pcie_legacy_irq{ + const u32 irq_bit; +- const int irq; ++ int irq; + }ifx_pcie_legacy_irq_t; + + typedef struct ifx_pcie_irq { diff --git a/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch new file mode 100644 index 0000000000..51810fe924 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch @@ -0,0 +1,187 @@ +From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001 +From: Stefan Koch +Date: Thu, 20 Oct 2016 21:32:00 +0200 +Subject: [PATCH] lantiq: vpe + +Signed-off-by: Stefan Koch +--- + arch/mips/Kconfig | 6 ++++ + arch/mips/include/asm/mipsmtregs.h | 5 ++++ + arch/mips/include/asm/vpe.h | 9 ++++++ + arch/mips/kernel/vpe-mt.c | 47 ++++++++++++++++++++++++++++++ + arch/mips/kernel/vpe.c | 35 ++++++++++++++++++++++ + arch/mips/lantiq/prom.c | 4 +++ + 6 files changed, 106 insertions(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2306,6 +2306,12 @@ config MIPS_VPE_LOADER + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + ++config IFX_VPE_EXT ++ bool "IFX APRP Extensions" ++ depends on MIPS_VPE_LOADER ++ help ++ IFX included extensions in APRP ++ + config MIPS_VPE_LOADER_CMP + bool + default "y" +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -31,6 +31,9 @@ + #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) + #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +@@ -377,6 +380,8 @@ do { \ + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) + #define read_vpe_c0_vpeconf1() mftc0(1, 3) + #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) +--- a/arch/mips/include/asm/vpe.h ++++ b/arch/mips/include/asm/vpe.h +@@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc); + + int __init vpe_module_init(void); + void __exit vpe_module_exit(void); ++ ++/* For the explanation of the APIs please refer the section "MT APRP Kernel ++ * Programming" in AR9 SW Architecture Specification ++ */ ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); ++int32_t vpe1_sw_stop(uint32_t flags); ++uint32_t vpe1_get_load_addr(uint32_t flags); ++uint32_t vpe1_get_max_mem(uint32_t flags); ++ + #endif /* _ASM_VPE_H */ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -416,6 +416,8 @@ int __init vpe_module_init(void) + } + + v->ntcs = hw_tcs - aprp_cpu_index(); ++ write_tc_c0_tcbind((read_tc_c0_tcbind() & ++ ~TCBIND_CURVPE) | 1); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); +@@ -519,3 +521,47 @@ void __exit vpe_module_exit(void) + release_vpe(v); + } + } ++ ++#ifdef CONFIG_IFX_VPE_EXT ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) ++{ ++ enum vpe_state state; ++ struct vpe *v = get_vpe(tclimit); ++ struct vpe_notifications *not; ++ ++ if (tcmask || flags) { ++ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); ++ return -1; ++ } ++ ++ state = xchg(&v->state, VPE_STATE_INUSE); ++ if (state != VPE_STATE_UNUSED) { ++ vpe_stop(v); ++ ++ list_for_each_entry(not, &v->notify, list) { ++ not->stop(tclimit); ++ } ++ } ++ ++ v->__start = (unsigned long)sw_start_addr; ++ ++ if (!vpe_run(v)) { ++ pr_debug("VPE loader: VPE1 running successfully\n"); ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_start); ++ ++int32_t vpe1_sw_stop(uint32_t flags) ++{ ++ struct vpe *v = get_vpe(tclimit); ++ ++ if (!vpe_free(v)) { ++ pr_debug("RP Stopped\n"); ++ return 0; ++ } else ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_stop); ++#endif +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { + .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) + }; + ++#ifdef CONFIG_IFX_VPE_EXT ++unsigned int vpe1_load_addr; ++ ++static int __init load_address(char *str) ++{ ++ get_option(&str, &vpe1_load_addr); ++ return 1; ++} ++__setup("vpe1_load_addr=", load_address); ++ ++static unsigned int vpe1_mem; ++static int __init vpe1mem(char *str) ++{ ++ vpe1_mem = memparse(str, &str); ++ return 1; ++} ++__setup("vpe1_mem=", vpe1mem); ++ ++uint32_t vpe1_get_load_addr(uint32_t flags) ++{ ++ return vpe1_load_addr; ++} ++EXPORT_SYMBOL(vpe1_get_load_addr); ++ ++uint32_t vpe1_get_max_mem(uint32_t flags) ++{ ++ if (!vpe1_mem) ++ return P_SIZE; ++ else ++ return vpe1_mem; ++} ++EXPORT_SYMBOL(vpe1_get_max_mem); ++ ++#endif ++ + /* get the vpe associated with this minor */ + struct vpe *get_vpe(int minor) + { +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -42,10 +42,14 @@ extern const struct plat_smp_ops vsmp_sm + static struct plat_smp_ops lantiq_smp_ops; + #endif + ++/* for Multithreading (APRP), vpe.c will use it */ ++unsigned long cp0_memsize; ++ + const char *get_system_type(void) + { + return soc_info.sys_type; + } ++EXPORT_SYMBOL(ltq_soc_type); + + int ltq_soc_type(void) + { diff --git a/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch new file mode 100644 index 0000000000..9214f786d7 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch @@ -0,0 +1,32 @@ +From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001 +From: Eddi De Pieri +Date: Tue, 8 Nov 2016 17:38:00 +0100 +Subject: [PATCH] lantiq: pci: bar11mask fix + +Signed-off-by: Eddi De Pieri +--- + arch/mips/pci/pci-lantiq.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -59,6 +59,8 @@ + #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) + #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + ++extern u32 max_low_pfn; ++ + __iomem void *ltq_pci_mapped_cfg; + static __iomem void *ltq_pci_membase; + +@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ +- mem = get_num_physpages() * PAGE_SIZE; +- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; ++ mem = max_low_pfn << PAGE_SHIFT; ++ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; + + return bar11mask; + } diff --git a/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch new file mode 100644 index 0000000000..015acabcfe --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch @@ -0,0 +1,24 @@ +From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001 +From: Stefan Koch +Date: Mon, 13 Mar 2017 23:42:00 +0100 +Subject: [PATCH] lantiq: vpe nosmp + +Signed-off-by: Stefan Koch +--- + arch/mips/kernel/vpe-mt.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -131,7 +131,10 @@ int vpe_run(struct vpe *v) + * kernels need to turn it on, even if that wasn't the pre-dvpe() state. + */ + #ifdef CONFIG_SMP +- evpe(vpeflags); ++ if (!setup_max_cpus) /* nosmp is set */ ++ evpe(EVPE_ENABLE); ++ else ++ evpe(vpeflags); + #else + evpe(EVPE_ENABLE); + #endif diff --git a/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000000..a83325c094 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,230 @@ +From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001 +From: Maikel Bloemendal +Date: Fri, 14 Nov 2014 17:06:00 +0000 +Subject: [PATCH] owrt: lantiq: multiple flash + +Signed-off-by: Maikel Bloemendal +--- + drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++----------- + 1 file changed, 109 insertions(+), 59 deletions(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -36,13 +37,16 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; ++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; + + static map_word + ltq_read16(struct map_info *map, unsigned long adr) +@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); + if (!ltq_mtd) +@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; + } + +- ltq_mtd->mtd->dev.parent = &pdev->dev; +- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ ltq_mtd->cmtd->dev.parent = &pdev->dev; ++ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); + +- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); ++ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch new file mode 100644 index 0000000000..f057ba324e --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch @@ -0,0 +1,99 @@ +From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Mon, 13 May 2024 10:42:24 +0200 +Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs + from dts + +Let's fetch the irqs from the dts here and expose them to the voice +driver like it is done for the cp1 base memory. + +ToDo: +Maybe it is possible to drop this driver completely and merge this +handling to the voice driver. + +Signed-off-by: Martin Schiller +--- + arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +--- a/arch/mips/lantiq/xway/vmmc.c ++++ b/arch/mips/lantiq/xway/vmmc.c +@@ -14,6 +14,10 @@ + + static unsigned int *cp1_base; + ++static int ad0_irq; ++static int ad1_irq; ++static int vc_irq[4]; ++ + unsigned int *ltq_get_cp1_base(void) + { + if (!cp1_base) +@@ -23,6 +27,33 @@ unsigned int *ltq_get_cp1_base(void) + } + EXPORT_SYMBOL(ltq_get_cp1_base); + ++unsigned int ltq_get_mps_ad0_irq(void) ++{ ++ if (!ad0_irq) ++ panic("no ad0 irq was set\n"); ++ ++ return ad0_irq; ++} ++EXPORT_SYMBOL(ltq_get_mps_ad0_irq); ++ ++unsigned int ltq_get_mps_ad1_irq(void) ++{ ++ if (!ad1_irq) ++ panic("no ad1 irq was set\n"); ++ ++ return ad1_irq; ++} ++EXPORT_SYMBOL(ltq_get_mps_ad1_irq); ++ ++unsigned int ltq_get_mps_vc_irq(int idx) ++{ ++ if (!vc_irq[idx]) ++ panic("no vc%d irq was set\n", idx); ++ ++ return vc_irq[idx]; ++} ++EXPORT_SYMBOL(ltq_get_mps_vc_irq); ++ + static int vmmc_probe(struct platform_device *pdev) + { + #define CP1_SIZE (1 << 20) +@@ -30,11 +61,33 @@ static int vmmc_probe(struct platform_de + int gpio_count; + dma_addr_t dma; + int error; ++ int i; + + cp1_base = + (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE, + &dma, GFP_KERNEL)); + ++ ad0_irq = platform_get_irq(pdev, 4); ++ if (ad0_irq < 0) { ++ dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq); ++ return ad0_irq; ++ } ++ ++ ad1_irq = platform_get_irq(pdev, 5); ++ if (ad1_irq < 0) { ++ dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq); ++ return ad1_irq; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ vc_irq[i] = platform_get_irq(pdev, i); ++ if (vc_irq[i] < 0) { ++ dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n", ++ i, vc_irq[i]); ++ return vc_irq[i]; ++ } ++ } ++ + gpio_count = gpiod_count(&pdev->dev, NULL); + while (gpio_count > 0) { + gpio = devm_gpiod_get_index(&pdev->dev, diff --git a/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000000..f62d167078 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,21 @@ +From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001 +From: Matti Laakso +Date: Sat, 14 Feb 2015 20:48:00 +0000 +Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes + +Signed-off-by: Matti Laakso +--- + drivers/mtd/chips/cfi_cmdset_0001.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..e46790b2c3 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,40 @@ +From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Mon, 2 May 2016 18:50:00 +0000 +Subject: [PATCH] xrx200: add gphy clk src device tree binding + +Signed-off-by: Mathias Kresin +--- + arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -609,4 +623,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } diff --git a/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch b/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch new file mode 100644 index 0000000000..c43d9d4b35 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch @@ -0,0 +1,62 @@ +From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001 +From: Aleksander Jan Bajkowski +Date: Sat, 6 May 2023 14:32:00 +0200 +Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if + FORCE_WORD_WRITE is 1 + +Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1. +So the compile warning messages are output if FORCE_WORD_WRITE is 1. To +resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1. + +This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f. + +Signed-off-by: Aleksander Jan Bajkowski +--- + drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -61,8 +61,10 @@ + + static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#if !FORCE_WORD_WRITE + static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); + static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *); ++#endif + static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *); + static void cfi_intelext_sync (struct mtd_info *); + static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); +@@ -304,6 +306,7 @@ static void fixup_use_point(struct mtd_i + } + } + ++#if !FORCE_WORD_WRITE + static void fixup_use_write_buffers(struct mtd_info *mtd) + { + struct map_info *map = mtd->priv; +@@ -314,6 +317,7 @@ static void fixup_use_write_buffers(stru + mtd->_writev = cfi_intelext_writev; + } + } ++#endif /* !FORCE_WORD_WRITE */ + + /* + * Some chips power-up with all sectors locked by default. +@@ -1719,6 +1723,7 @@ static int cfi_intelext_write_words (str + } + + ++#if !FORCE_WORD_WRITE + static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, + unsigned long adr, const struct kvec **pvec, + unsigned long *pvec_seek, int len) +@@ -1947,6 +1952,7 @@ static int cfi_intelext_write_buffers (s + + return cfi_intelext_writev(mtd, &vec, 1, to, retlen); + } ++#endif /* !FORCE_WORD_WRITE */ + + static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, + unsigned long adr, int len, void *thunk) diff --git a/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch b/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch new file mode 100644 index 0000000000..edf0626860 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch @@ -0,0 +1,38 @@ +From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001 +From: Thomas Nixon +Date: Sun, 26 Mar 2023 11:08:49 +0100 +Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock + +The nand driver normally while waiting for the device to become ready; +this is normally fine, but xway_nand holds the ebu_lock spinlock, and +this can cause lockups if other threads which use ebu_lock are +interleaved. Fix this by waiting instead of polling. + +This mainly showed up as crashes in ath9k_pci_owl_loader (see +https://github.com/openwrt/openwrt/issues/9829 ), but turning on +spinlock debugging shows this happening in other places too. + +This doesn't seem to measurably impact boot time. + +Signed-off-by: Thomas Nixon +--- + drivers/mtd/nand/raw/xway_nand.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/raw/xway_nand.c ++++ b/drivers/mtd/nand/raw/xway_nand.c +@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch + + static int xway_dev_ready(struct nand_chip *chip) + { +- return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; ++ /* ++ * wait until ready, as otherwise the driver will yield in nand_wait or ++ * nand_wait_ready, which is a bad idea when we're holding ebu_lock ++ */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ cpu_relax(); ++ return 1; + } + + static unsigned char xway_read_byte(struct nand_chip *chip) diff --git a/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch new file mode 100644 index 0000000000..19c027b9f8 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch @@ -0,0 +1,47 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: Johann Neuhauser +Date: Thu, 17 May 2018 19:12:35 +0200 +Subject: [PATCH] net: lantiq_etop: of mdio + +Signed-off-by: Johann Neuhauser +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + + #include + +@@ -558,7 +559,8 @@ static int + ltq_etop_mdio_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int err; ++ struct device_node *mdio_np = NULL; ++ int err, ret; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -578,7 +580,15 @@ ltq_etop_mdio_init(struct net_device *de + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +- if (mdiobus_register(priv->mii_bus)) { ++ ++ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); ++ ++ if (mdio_np) ++ ret = of_mdiobus_register(priv->mii_bus, mdio_np); ++ else ++ ret = mdiobus_register(priv->mii_bus); ++ ++ if (ret) { + err = -ENXIO; + goto err_out_free_mdiobus; + } diff --git a/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch b/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch new file mode 100644 index 0000000000..c337c564b6 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch @@ -0,0 +1,32 @@ +From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 10 Oct 2022 16:52:25 +0200 +Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing + phy-mode and fixed-link + +The CPU port has to specify a phy-mode and either a phy or a fixed-link. +Since GSWIP is connected using a SoC internal protocol there's no PHY +involved. Add phy-mode = "internal" and a fixed-link to describe the +communication between the PMAC (Ethernet controller) and GSWIP switch. + +Signed-off-by: Martin Blumenstingl +--- + Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt ++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt +@@ -96,7 +96,13 @@ switch@e108000 { + + port@6 { + reg = <0x6>; ++ phy-mode = "internal"; + ethernet = <ð0>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + }; + diff --git a/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch b/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch new file mode 100644 index 0000000000..4800ee1dd2 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch @@ -0,0 +1,33 @@ +From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 10 Oct 2022 16:59:35 +0200 +Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode = + "internal" on the CPU port + +Add the CPU port to gswip_xrx200_phylink_get_caps() and +gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus, +so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1509,6 +1509,7 @@ static void gswip_xrx200_phylink_get_cap + case 2: + case 3: + case 4: ++ case 6: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; +@@ -1540,6 +1541,7 @@ static void gswip_xrx300_phylink_get_cap + case 2: + case 3: + case 4: ++ case 6: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; diff --git a/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch b/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch new file mode 100644 index 0000000000..f30e7ab00c --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch @@ -0,0 +1,145 @@ +From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 31 Jul 2022 22:54:52 +0200 +Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where + appropriate + +dev_err_probe() can be used to simplify the existing code. Also it means +we get rid of the following warning which is seen whenever the PMAC +(Ethernet controller which connects to GSWIP's CPU port) has not been +probed yet: + gswip 1e108000.switch: dsa switch register failed: -517 + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------ + 1 file changed, 25 insertions(+), 28 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1919,11 +1919,9 @@ static int gswip_gphy_fw_load(struct gsw + msleep(200); + + ret = request_firmware(&fw, gphy_fw->fw_name, dev); +- if (ret) { +- dev_err(dev, "failed to load firmware: %s, error: %i\n", +- gphy_fw->fw_name, ret); +- return ret; +- } ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to load firmware: %s\n", ++ gphy_fw->fw_name); + + /* GPHY cores need the firmware code in a persistent and contiguous + * memory area with a 16 kB boundary aligned start address. +@@ -1936,9 +1934,9 @@ static int gswip_gphy_fw_load(struct gsw + dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); + memcpy(fw_addr, fw->data, fw->size); + } else { +- dev_err(dev, "failed to alloc firmware memory\n"); + release_firmware(fw); +- return -ENOMEM; ++ return dev_err_probe(dev, -ENOMEM, ++ "failed to alloc firmware memory\n"); + } + + release_firmware(fw); +@@ -1965,8 +1963,8 @@ static int gswip_gphy_fw_probe(struct gs + + gphy_fw->clk_gate = devm_clk_get(dev, gphyname); + if (IS_ERR(gphy_fw->clk_gate)) { +- dev_err(dev, "Failed to lookup gate clock\n"); +- return PTR_ERR(gphy_fw->clk_gate); ++ return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate), ++ "Failed to lookup gate clock\n"); + } + + ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); +@@ -1986,8 +1984,8 @@ static int gswip_gphy_fw_probe(struct gs + gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; + break; + default: +- dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); +- return -EINVAL; ++ return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n", ++ gphy_mode); + } + + gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); +@@ -2038,8 +2036,9 @@ static int gswip_gphy_fw_list(struct gsw + priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; + break; + default: +- dev_err(dev, "unknown GSWIP version: 0x%x", version); +- return -ENOENT; ++ return dev_err_probe(dev, -ENOENT, ++ "unknown GSWIP version: 0x%x", ++ version); + } + } + +@@ -2047,10 +2046,9 @@ static int gswip_gphy_fw_list(struct gsw + if (match && match->data) + priv->gphy_fw_name_cfg = match->data; + +- if (!priv->gphy_fw_name_cfg) { +- dev_err(dev, "GPHY compatible type not supported"); +- return -ENOENT; +- } ++ if (!priv->gphy_fw_name_cfg) ++ return dev_err_probe(dev, -ENOENT, ++ "GPHY compatible type not supported"); + + priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); + if (!priv->num_gphy_fw) +@@ -2150,8 +2148,8 @@ static int gswip_probe(struct platform_d + return -EINVAL; + break; + default: +- dev_err(dev, "unknown GSWIP version: 0x%x", version); +- return -ENOENT; ++ return dev_err_probe(dev, -ENOENT, ++ "unknown GSWIP version: 0x%x", version); + } + + /* bring up the mdio bus */ +@@ -2159,10 +2157,9 @@ static int gswip_probe(struct platform_d + if (gphy_fw_np) { + err = gswip_gphy_fw_list(priv, gphy_fw_np, version); + of_node_put(gphy_fw_np); +- if (err) { +- dev_err(dev, "gphy fw probe failed\n"); +- return err; +- } ++ if (err) ++ return dev_err_probe(dev, err, ++ "gphy fw probe failed\n"); + } + + /* bring up the mdio bus */ +@@ -2170,20 +2167,20 @@ static int gswip_probe(struct platform_d + if (mdio_np) { + err = gswip_mdio(priv, mdio_np); + if (err) { +- dev_err(dev, "mdio probe failed\n"); ++ dev_err_probe(dev, err, "mdio probe failed\n"); + goto put_mdio_node; + } + } + + err = dsa_register_switch(priv->ds); + if (err) { +- dev_err(dev, "dsa switch register failed: %i\n", err); ++ dev_err_probe(dev, err, "dsa switch registration failed\n"); + goto mdio_bus; + } + if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { +- dev_err(dev, "wrong CPU port defined, HW only supports port: %i", +- priv->hw_info->cpu_port); +- err = -EINVAL; ++ err = dev_err_probe(dev, -EINVAL, ++ "wrong CPU port defined, HW only supports port: %i", ++ priv->hw_info->cpu_port); + goto disable_switch; + } + diff --git a/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch b/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch new file mode 100644 index 0000000000..de8416380a --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch @@ -0,0 +1,25 @@ +From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 28 Jul 2022 22:37:11 +0200 +Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call + gswip_port_enable() + +We don't need to manually call gswip_port_enable() from within +gswip_setup() for the CPU port. DSA does this automatically for us. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -891,8 +891,6 @@ static int gswip_setup(struct dsa_switch + + ds->mtu_enforcement_ingress = true; + +- gswip_port_enable(ds, cpu_port, NULL); +- + ds->configure_vlan_while_not_filtering = false; + + return 0; diff --git a/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch b/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch new file mode 100644 index 0000000000..a653c85841 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch @@ -0,0 +1,70 @@ +From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Fri, 10 May 2024 13:52:10 +0200 +Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port + +Before commit 74be4babe72f ("net: dsa: do not enable or disable non user +ports"), gswip_port_enable/disable() were also executed for the cpu port +in gswip_setup() which disabled the cpu port during initialization. + +Let's restore this by removing the dsa_is_user_port checks. Also, let's +clean up the gswip_port_enable() function so that we only have to check +for the cpu port once. + +Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports") +Signed-off-by: Martin Schiller +--- + drivers/net/dsa/lantiq_gswip.c | 24 ++++++++---------------- + 1 file changed, 8 insertions(+), 16 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -688,13 +688,18 @@ static int gswip_port_enable(struct dsa_ + struct gswip_priv *priv = ds->priv; + int err; + +- if (!dsa_is_user_port(ds, port)) +- return 0; +- + if (!dsa_is_cpu_port(ds, port)) { ++ u32 mdio_phy = 0; ++ + err = gswip_add_single_port_br(priv, port, true); + if (err) + return err; ++ ++ if (phydev) ++ mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; ++ ++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, ++ GSWIP_MDIO_PHYp(port)); + } + + /* RMON Counter Enable for port */ +@@ -707,16 +712,6 @@ static int gswip_port_enable(struct dsa_ + gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, + GSWIP_SDMA_PCTRLp(port)); + +- if (!dsa_is_cpu_port(ds, port)) { +- u32 mdio_phy = 0; +- +- if (phydev) +- mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; +- +- gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, +- GSWIP_MDIO_PHYp(port)); +- } +- + return 0; + } + +@@ -724,9 +719,6 @@ static void gswip_port_disable(struct ds + { + struct gswip_priv *priv = ds->priv; + +- if (!dsa_is_user_port(ds, port)) +- return; +- + gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, + GSWIP_FDMA_PCTRLp(port)); + gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, diff --git a/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch b/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch new file mode 100644 index 0000000000..fd19982264 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch @@ -0,0 +1,30 @@ +From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 18 May 2022 23:53:09 +0200 +Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in + gswip_port_change_mtu() + +Make the check for the CPU port in gswip_port_change_mtu() consistent +with other areas of the driver by using dsa_is_cpu_port(). + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1457,12 +1457,11 @@ static int gswip_port_max_mtu(struct dsa + static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) + { + struct gswip_priv *priv = ds->priv; +- int cpu_port = priv->hw_info->cpu_port; + + /* CPU port always has maximum mtu of user ports, so use it to set + * switch frame size, including 8 byte special header. + */ +- if (port == cpu_port) { ++ if (dsa_is_cpu_port(ds, port)) { + new_mtu += 8; + gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, + GSWIP_MAC_FLEN); diff --git a/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch b/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch new file mode 100644 index 0000000000..74e52d1d18 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch @@ -0,0 +1,24 @@ +From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Tue, 17 May 2022 22:39:58 +0200 +Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN + +The addr variable in gswip_port_fdb_dump() stores a mac address. Use +ETH_ALEN to make this consistent across other drivers. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1406,7 +1406,7 @@ static int gswip_port_fdb_dump(struct ds + { + struct gswip_priv *priv = ds->priv; + struct gswip_pce_table_entry mac_bridge = {0,}; +- unsigned char addr[6]; ++ unsigned char addr[ETH_ALEN]; + int i; + int err; + diff --git a/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch b/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch new file mode 100644 index 0000000000..0ea90db483 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch @@ -0,0 +1,47 @@ +From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 21:23:49 +0200 +Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for + the mac bridge table + +Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout +the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT() +macro. This makes the driver code easier to understand. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -236,7 +236,8 @@ + #define GSWIP_TABLE_ACTIVE_VLAN 0x01 + #define GSWIP_TABLE_VLAN_MAPPING 0x02 + #define GSWIP_TABLE_MAC_BRIDGE 0x0b +-#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ ++#define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */ ++#define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + +@@ -1300,7 +1301,8 @@ static void gswip_port_fast_age(struct d + if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) + continue; + +- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) ++ if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT, ++ mac_bridge.val[0])) + continue; + + mac_bridge.valid = false; +@@ -1438,7 +1440,8 @@ static int gswip_port_fdb_dump(struct ds + return err; + } + } else { +- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { ++ if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT, ++ mac_bridge.val[0])) { + err = cb(addr, 0, false, data); + if (err) + return err; diff --git a/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch b/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch new file mode 100644 index 0000000000..1347a98c5c --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch @@ -0,0 +1,26 @@ +From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 22:24:24 +0200 +Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid + gswip_add_single_port_br on the CPU port + +Calling gswip_add_single_port_br() with the CPU port would be a bug +because then only the CPU port could talk to itself. Add the CPU port to +the validation at the beginning of gswip_add_single_port_br(). + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -650,7 +650,7 @@ static int gswip_add_single_port_br(stru + unsigned int max_ports = priv->hw_info->max_ports; + int err; + +- if (port >= max_ports) { ++ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) { + dev_err(priv->dev, "single port for %i supported\n", port); + return -EIO; + } diff --git a/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch b/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch new file mode 100644 index 0000000000..732588308e --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch @@ -0,0 +1,26 @@ +From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 1 Aug 2022 22:26:20 +0200 +Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in + gswip_add_single_port_br() + +The error message is printed when the port cannot be used. Update the +error message to reflect that. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -651,7 +651,8 @@ static int gswip_add_single_port_br(stru + int err; + + if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) { +- dev_err(priv->dev, "single port for %i supported\n", port); ++ dev_err(priv->dev, "single port for %i is not supported\n", ++ port); + return -EIO; + } + diff --git a/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch b/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch new file mode 100644 index 0000000000..679dd53c47 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch @@ -0,0 +1,36 @@ +From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 14:06:40 +0200 +Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in + gswip_port_vlan_filtering() + +Update the comments in gswip_port_vlan_filtering() so it's clear that +there are two separate cases, one for "tag based VLAN" and another one +for "port based VLAN". + +Suggested-by: Martin Schiller +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -779,7 +779,7 @@ static int gswip_port_vlan_filtering(str + } + + if (vlan_filtering) { +- /* Use port based VLAN tag */ ++ /* Use tag based VLAN */ + gswip_switch_mask(priv, + GSWIP_PCE_VCTRL_VSR, + GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | +@@ -788,7 +788,7 @@ static int gswip_port_vlan_filtering(str + gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, + GSWIP_PCE_PCTRL_0p(port)); + } else { +- /* Use port based VLAN tag */ ++ /* Use port based VLAN */ + gswip_switch_mask(priv, + GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | + GSWIP_PCE_VCTRL_VEMR, diff --git a/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch b/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch new file mode 100644 index 0000000000..3d284c2ea6 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch @@ -0,0 +1,33 @@ +From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 14:19:05 +0200 +Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a + GSWIP_TABLE_MAC_BRIDGE_FID macro + +Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a +macro so this becomes obvious when reading the driver code. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -238,6 +238,7 @@ + #define GSWIP_TABLE_MAC_BRIDGE 0x0b + #define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */ + #define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */ ++#define GSWIP_TABLE_MAC_BRIDGE_FID GENMASK(5, 0) /* Filtering identifier */ + + #define XRX200_GPHY_FW_ALIGN (16 * 1024) + +@@ -1378,7 +1379,7 @@ static int gswip_port_fdb(struct dsa_swi + mac_bridge.key[0] = addr[5] | (addr[4] << 8); + mac_bridge.key[1] = addr[3] | (addr[2] << 8); + mac_bridge.key[2] = addr[1] | (addr[0] << 8); +- mac_bridge.key[3] = fid; ++ mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid); + mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ + mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; + mac_bridge.valid = add; diff --git a/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch b/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch new file mode 100644 index 0000000000..5c756c5a19 --- /dev/null +++ b/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch @@ -0,0 +1,26 @@ +From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 14 Oct 2022 16:31:57 +0200 +Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in + gswip_port_fdb() + +Print the port which is not found to be part of a bridge so it's easier +to investigate the underlying issue. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/dsa/lantiq_gswip.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1370,7 +1370,8 @@ static int gswip_port_fdb(struct dsa_swi + } + + if (fid == -1) { +- dev_err(priv->dev, "Port not part of a bridge\n"); ++ dev_err(priv->dev, ++ "Port %d is not known to be part of bridge\n", port); + return -EINVAL; + } + diff --git a/target/linux/lantiq/xrx200/config-5.15 b/target/linux/lantiq/xrx200/config-5.15 index 4dfd55274a..1b87ad65f0 100644 --- a/target/linux/lantiq/xrx200/config-5.15 +++ b/target/linux/lantiq/xrx200/config-5.15 @@ -1,11 +1,9 @@ CONFIG_AT803X_PHY=y CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_MIPSR2_IRQ_EI=y CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_RMAP=y CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LZO=y @@ -20,8 +18,8 @@ CONFIG_ICPLUS_PHY=y CONFIG_IFX_VPE_EXT=y CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y CONFIG_INTEL_XWAY_PHY=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y # CONFIG_ISDN is not set CONFIG_LANTIQ_XRX200=y CONFIG_LZO_COMPRESS=y @@ -60,6 +58,7 @@ CONFIG_PCIEPORTBUS=y CONFIG_PCIE_LANTIQ=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_LANTIQ=y +CONFIG_PHYLINK=y CONFIG_PHY_LANTIQ_VRX200_PCIE=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_SUPPLY=y @@ -74,8 +73,7 @@ CONFIG_SENSORS_LTQ_CPUTEMP=y CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_SYNC_R4K=y CONFIG_SYS_SUPPORTS_SCHED_SMT=y CONFIG_SYS_SUPPORTS_SMP=y diff --git a/target/linux/lantiq/xrx200/config-6.1 b/target/linux/lantiq/xrx200/config-6.1 new file mode 100644 index 0000000000..dc41fe0ca8 --- /dev/null +++ b/target/linux/lantiq/xrx200/config-6.1 @@ -0,0 +1,96 @@ +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GRO_CELLS=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_ICPLUS_PHY=y +CONFIG_IFX_VPE_EXT=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INTEL_XWAY_PHY=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_XRX200=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_VPE_APSP_API=y +CONFIG_MIPS_VPE_APSP_API_MT=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_MT=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_LANTIQ_GSWIP=y +CONFIG_NET_DSA_TAG_GSWIP=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_PADATA=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_LANTIQ=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PHYLINK=y +CONFIG_PHY_LANTIQ_VRX200_PCIE=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_QCOM_NET_PHYLIB=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SENSORS_LTQ_CPUTEMP=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/config-5.15 b/target/linux/lantiq/xway/config-5.15 index 5a6f15dafd..696ce77860 100644 --- a/target/linux/lantiq/xway/config-5.15 +++ b/target/linux/lantiq/xway/config-5.15 @@ -1,9 +1,7 @@ CONFIG_ADM6996_PHY=y CONFIG_AR8216_PHY=y -CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_AT803X_PHY=y CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_MIPSR2_IRQ_EI=y CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_RMAP=y @@ -13,18 +11,15 @@ CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FWNODE_MDIO=y CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GPIO_CDEV=y CONFIG_HW_RANDOM=y CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y # CONFIG_ISDN is not set CONFIG_LANTIQ_ETOP=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_EBPF_JIT=y CONFIG_MIPS_MT=y CONFIG_MIPS_MT_FPAFF=y CONFIG_MIPS_MT_SMP=y @@ -40,15 +35,14 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SELFTESTS=y CONFIG_NLS=y CONFIG_NR_CPUS=2 CONFIG_PADATA=y CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set CONFIG_PCI_DOMAINS=y CONFIG_PCI_LANTIQ=y CONFIG_PSB6970_PHY=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_REGULATOR=y @@ -64,8 +58,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y CONFIG_SWCONFIG=y CONFIG_SYNC_R4K=y CONFIG_SYS_SUPPORTS_SCHED_SMT=y diff --git a/target/linux/lantiq/xway/config-6.1 b/target/linux/lantiq/xway/config-6.1 new file mode 100644 index 0000000000..1fc821575e --- /dev/null +++ b/target/linux/lantiq/xway/config-6.1 @@ -0,0 +1,81 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_HW_RANDOM=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_PADATA=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PSB6970_PHY=y +CONFIG_QCOM_NET_PHYLIB=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +# CONFIG_SCHED_CORE is not set +CONFIG_SCHED_SMT=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SWCONFIG=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway_legacy/config-5.15 b/target/linux/lantiq/xway_legacy/config-5.15 index c177d2a935..ed3ecd8b4d 100644 --- a/target/linux/lantiq/xway_legacy/config-5.15 +++ b/target/linux/lantiq/xway_legacy/config-5.15 @@ -1,15 +1,13 @@ CONFIG_ADM6996_PHY=y CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_GENERIC_ALLOCATOR=y +# CONFIG_GPIO_CDEV is not set # CONFIG_GPIO_SYSFS is not set CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y # CONFIG_ISDN is not set CONFIG_LANTIQ_ETOP=y # CONFIG_LEDS_TRIGGER_TIMER is not set @@ -17,14 +15,13 @@ CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_NLS=y CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set CONFIG_PCI_DOMAINS=y CONFIG_PCI_LANTIQ=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_RTL8306_PHY=y CONFIG_SGL_ALLOC=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y CONFIG_SWCONFIG=y CONFIG_USB=y CONFIG_USB_COMMON=y diff --git a/target/linux/lantiq/xway_legacy/config-6.1 b/target/linux/lantiq/xway_legacy/config-6.1 new file mode 100644 index 0000000000..ed3ecd8b4d --- /dev/null +++ b/target/linux/lantiq/xway_legacy/config-6.1 @@ -0,0 +1,30 @@ +CONFIG_ADM6996_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +# CONFIG_GPIO_CDEV is not set +# CONFIG_GPIO_SYSFS is not set +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_NLS=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_SGL_ALLOC=y +CONFIG_SWCONFIG=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface index 9351ffd492..6dfa52c291 100644 --- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface +++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface @@ -1,10 +1,6 @@ set_preinit_iface() { case $(board_name) in - smartrg,sdg-8622|\ - smartrg,sdg-8632) - ip link set lan up - ifname=lan - ;; + cudy,m3000-v1|\ cudy,tr3000-v1|\ glinet,gl-mt3000) ip link set eth1 up @@ -16,6 +12,11 @@ set_preinit_iface() { ip link set eth0 up ifname=eth0 ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + ip link set lan up + ifname=lan + ;; xiaomi,mi-router-ax3000t|\ xiaomi,mi-router-ax3000t-ubootmod|\ xiaomi,mi-router-wr30u-stock|\ diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts new file mode 100644 index 0000000000..e700d3728a --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "Cudy M3000 v1"; + compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb"; + + aliases { + ethernet0 = &gmac0; + label-mac-device = &gmac0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: internet-white { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + internet-red { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&rtl8221b_phy>; + + /* the MAC address assignment using nvmem-cells doesn't work, so it's done through 02_network */ + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + }; +}; + +&mdio_bus { + rtl8221b_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <1>; + + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partition@0 { + label = "BL2"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x0180000 0x0200000>; + read-only; + }; + + bdinfo: partition@380000 { + label = "bdinfo"; + reg = <0x0380000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + #nvmem-cell-cells = <1>; + compatible = "mac-base"; + reg = <0xde00 0x6>; + }; + }; + }; + + partition@3c0000 { + label = "FIP"; + reg = <0x03c0000 0x0200000>; + }; + + partition@5c0000 { + label = "ubi"; + reg = <0x05c0000 0x4000000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&wifi { + status = "okay"; + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 5b0423ca36..4488e37a7c 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -63,9 +63,7 @@ mediatek_setup_interfaces() comfast,cf-e393ax) ucidef_set_interfaces_lan_wan "lan1" eth1 ;; - dlink,aquila-pro-ai-m30-a1) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet - ;; + cudy,m3000-v1|\ cudy,tr3000-v1|\ glinet,gl-mt2500|\ glinet,gl-mt3000|\ @@ -74,6 +72,9 @@ mediatek_setup_interfaces() openembed,som7981) ucidef_set_interfaces_lan_wan eth1 eth0 ;; + dlink,aquila-pro-ai-m30-a1) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet + ;; glinet,gl-mt6000|\ tplink,tl-xdr4288|\ tplink,tl-xdr6088) @@ -145,6 +146,9 @@ mediatek_setup_macs() ;; esac ;; + cudy,m3000-v1) + wan_mac=$(macaddr_add $(cat /sys/class/net/eth1/address) 1) + ;; h3c,magic-nx30-pro|\ h3c,magic-nx30-pro-nmbm) wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 5b1bd4a4cb..2617c619b1 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -80,6 +80,7 @@ case "$board" in [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress ;; + cudy,m3000-v1|\ cudy,wr3000-v1) addr=$(mtd_get_mac_binary bdinfo 0xde00) # Originally, phy0 is phy1 mac with LA bit set. However, this would conflict diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index eb0e2d45dd..5938a69fe4 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -537,6 +537,28 @@ define Device/confiabits_mt7981 endef TARGET_DEVICES += confiabits_mt7981 +define Device/cudy_m3000-v1 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := M3000 + DEVICE_VARIANT := v1 + DEVICE_DTS := mt7981b-cudy-m3000-v1 + DEVICE_DTS_DIR := ../dts + SUPPORTED_DEVICES += R37 + DEVICE_DTS_LOADADDR := 0x44000000 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += cudy_m3000-v1 + define Device/cudy_re3000-v1 DEVICE_VENDOR := Cudy DEVICE_MODEL := RE3000 diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile index 26bd4d4240..b279d818ed 100644 --- a/target/linux/mvebu/Makefile +++ b/target/linux/mvebu/Makefile @@ -9,8 +9,7 @@ BOARDNAME:=Marvell EBU Armada FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz SUBTARGETS:=cortexa9 cortexa53 cortexa72 -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/mvebu/config-6.1 b/target/linux/mvebu/config-6.1 deleted file mode 100644 index 88e5fff4d9..0000000000 --- a/target/linux/mvebu/config-6.1 +++ /dev/null @@ -1,447 +0,0 @@ -CONFIG_AHCI_MVEBU=y -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARMADA_370_CLK=y -CONFIG_ARMADA_370_XP_IRQ=y -CONFIG_ARMADA_370_XP_TIMER=y -# CONFIG_ARMADA_37XX_WATCHDOG is not set -CONFIG_ARMADA_38X_CLK=y -CONFIG_ARMADA_THERMAL=y -CONFIG_ARMADA_XP_CLK=y -CONFIG_ARM_APPENDED_DTB=y -# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set -# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1 -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MVEBU_V7_CPUIDLE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_ATA_LEDS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_FEROCEON_L2 is not set -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PJ4B=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_MARVELL=y -CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRYPTO_ESSIV=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MVEBU_UART0=y -# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set -# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0xd0012000 -CONFIG_DEBUG_UART_VIRT=0xfec12000 -CONFIG_DEBUG_USER=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MVEBU=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWBM=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -# CONFIG_I2C_PXA is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_IWMMXT is not set -CONFIG_JBD2=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PCA963X=y -CONFIG_LEDS_TLC591XX=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_ARMADA_370=y -# CONFIG_MACH_ARMADA_375 is not set -CONFIG_MACH_ARMADA_38X=y -# CONFIG_MACH_ARMADA_39X is not set -CONFIG_MACH_ARMADA_XP=y -# CONFIG_MACH_DOVE is not set -CONFIG_MACH_MVEBU_ANY=y -CONFIG_MACH_MVEBU_V7=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANGLE_BOOTARGS=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_I2C=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_MVSDIO=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_PXAV3=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MVEBU_CLK_COMMON=y -CONFIG_MVEBU_CLK_COREDIV=y -CONFIG_MVEBU_CLK_CPU=y -CONFIG_MVEBU_DEVBUS=y -CONFIG_MVEBU_MBUS=y -CONFIG_MVMDIO=y -CONFIG_MVNETA=y -CONFIG_MVNETA_BM=y -CONFIG_MVNETA_BM_ENABLE=y -# CONFIG_MVPP2 is not set -CONFIG_MV_XOR=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_DSA_COMMON=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_ORION_WATCHDOG=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCI_BRIDGE_EMUL=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_MVEBU=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MVEBU_A3700_COMPHY is not set -# CONFIG_PHY_MVEBU_A3700_UTMI is not set -# CONFIG_PHY_MVEBU_A38X_COMPHY is not set -# CONFIG_PHY_MVEBU_CP110_COMPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_ARMADA_370=y -CONFIG_PINCTRL_ARMADA_38X=y -CONFIG_PINCTRL_ARMADA_XP=y -CONFIG_PINCTRL_MVEBU=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PJ4B_ERRATA_4742=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PLAT_ORION=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_ARMADA38X=y -# CONFIG_RTC_DRV_MV is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SATA_HOST=y -CONFIG_SATA_MV=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SENSORS_PWM_FAN=y -CONFIG_SENSORS_TMP421=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MVEBU_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SFP=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_ARMADA_3700 is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ORION=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_ORION=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_PHY=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MVEBU=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mvebu/cortexa53/config-6.1 b/target/linux/mvebu/cortexa53/config-6.1 deleted file mode 100644 index d8dd985365..0000000000 --- a/target/linux/mvebu/cortexa53/config-6.1 +++ /dev/null @@ -1,92 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_37XX_RWTM_MBOX=y -CONFIG_ARMADA_37XX_WATCHDOG=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_AP_CP_HELPER=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_ARM_MHU_V2 is not set -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_FRAME_POINTER=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MVEBU_SEI=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI_AARDVARK=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MVEBU_A3700_COMPHY=y -CONFIG_PHY_MVEBU_A3700_UTMI=y -CONFIG_PINCTRL_AC5=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SWIOTLB=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TURRIS_MOX_RWTM=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/mvebu/cortexa72/config-6.1 b/target/linux/mvebu/cortexa72/config-6.1 deleted file mode 100644 index 3c398dcd8f..0000000000 --- a/target/linux/mvebu/cortexa72/config-6.1 +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_64BIT=y -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_SVE=y -# CONFIG_ARM64_TAGGED_ADDR_ABI is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_AP_CPU_CLK=y -CONFIG_ARMADA_AP_CP_HELPER=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set -CONFIG_ARM_ARMADA_8K_CPUFREQ=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CRC_CCITT=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_EEPROM_AT24=y -CONFIG_FRAME_POINTER=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_HW_RANDOM_OMAP=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LEDS_IEI_WT61P803_PUZZLE=y -CONFIG_LEDS_IS31FL319X=y -CONFIG_MARVELL_10G_PHY=y -CONFIG_MFD_CORE=y -CONFIG_MFD_IEI_WT61P803_PUZZLE=y -CONFIG_MFD_SYSCON=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MVEBU_SEI=y -CONFIG_MVPP2=y -CONFIG_MV_XOR_V2=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_LAYOUT_ONIE_TLV=y -CONFIG_NVMEM_SYSFS=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -# CONFIG_PCI_AARDVARK is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_MVEBU_CP110_UTMI=y -CONFIG_PINCTRL_AC5=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REGULATOR_GPIO=y -# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set -CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SWIOTLB=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/mvebu/cortexa9/config-6.1 b/target/linux/mvebu/cortexa9/config-6.1 deleted file mode 100644 index 7f825a806b..0000000000 --- a/target/linux/mvebu/cortexa9/config-6.1 +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_IRQSTACKS=y -CONFIG_LED_TRIGGER_PHY=y -CONFIG_MTD_SPLIT_SEIL_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_PHY_MVEBU_A38X_COMPHY=y -CONFIG_POWER_RESET_QNAP=y -CONFIG_RTC_DRV_MV=y -CONFIG_THREAD_INFO_IN_TASK=y diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts deleted file mode 100644 index 11be6a4028..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Device Tree file for Buffalo LinkStation LS220DE - * - * Copyright (C) 2023 Daniel González Cabanelas - */ - -/dts-v1/; - -#include "armada-370.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include -#include -#include -#include - -/ { - model = "Buffalo LinkStation LS220DE"; - compatible = "buffalo,ls220de", "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - led-boot = &led_boot; - led-failsafe = &led_failsafe; - led-running = &led_power; - led-upgrade = &led_upgrade; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - append-rootblock = "nullparameter="; /* override the bootloader args */ - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - }; - - system_fan: gpio_fan { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH - &gpio0 14 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - - #cooling-cells = <2>; - }; - - thermal-zones { - hdd-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */ - - trips { - hdd_alert1: trip1 { - temperature = <34000>; - hysteresis = <2000>; - type = "active"; - }; - hdd_alert2: trip2 { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - hdd_alert3: trip3 { - temperature = <45000>; - hysteresis = <2000>; - type = "passive"; - }; - hdd_hot { - temperature = <50000>; - hysteresis = <2000>; - type = "hot"; - }; - hdd_crit { - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&hdd_alert1>; - cooling-device = <&system_fan THERMAL_NO_LIMIT 1>; - }; - map2 { - trip = <&hdd_alert2>; - cooling-device = <&system_fan 2 2>; - }; - map3 { - trip = <&hdd_alert3>; - cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - power { - label = "Power Switch"; - linux,code = ; - linux,input-type = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - function { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_leds1 &pmx_leds2>; - - indicator_red { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - panic-indicator; - }; - - led_power: power_white { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led_failsafe: power_red { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - led_upgrade: power_orange { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - }; - - led_boot: indicator_white { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - hdd1_red { - function = LED_FUNCTION_DISK; - color = ; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ata1"; - function-enumerator = <1>; - }; - - hdd2_red { - function = LED_FUNCTION_DISK; - color = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ata2"; - function-enumerator = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd1 &pmx_power_hdd2>; - pinctrl-names = "default"; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "HDD1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - sata2_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD2"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&coherencyfab { - broken-idle; -}; - -ð1 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - marvell,reg-init = <0x3 0x10 0xf000 0x091A>, /* LED function */ - <0x3 0x11 0x0000 0x4401>, /* LED polarity */ - <0x3 0x12 0x0000 0x4905>; /* LED timer */ - #thermal-sensor-cells = <0>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ubi_kernel"; - reg = <0x00000000 0x02000000>; /* 32 MiB */ - }; - - partition@2000000 { - label = "ubi"; - reg = <0x02000000 0x1df00000>; /* 479 MiB */ - }; - }; - }; -}; - -&sata { - nr-ports = <2>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - hdd0_temp: sata-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; - - hdd1_temp: sata-port@1 { - reg = <1>; - #thermal-sensor-cells = <0>; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000 0xf0000>; /* 960 KiB*/ - label = "u-boot"; - read-only; - }; - partition@f0000 { - reg = <0xf0000 0x10000>; /* 64 KiB */ - label = "u-boot-env"; - }; - }; - }; -}; - -&pmsu { - pinctrl-0 = <&pmx_power_cpu>; - pinctrl-names = "default"; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&pinctrl { - pmx_power_hdd2: pmx-power-hdd2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_power_cpu: pmx-power-cpu { - marvell,pins = "mpp4"; - marvell,function = "vdd"; - }; - - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_hdd_present: pmx-hdd-present { - marvell,pins = "mpp11", "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp15", "mpp16"; - marvell,function = "gpio"; - }; - - pmx_leds1: pmx-leds { - marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61"; - marvell,function = "gpo"; - }; - - pmx_leds2: pmx-leds { - marvell,pins = "mpp55", "mpp57", "mpp62"; - marvell,function = "gpio"; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts deleted file mode 100644 index 59400839a7..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Device Tree file for Buffalo LinkStation LS421DE - * - * Copyright (C) 2020 Daniel González Cabanelas - */ - -/dts-v1/; - -#include "armada-370.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include -#include -#include - -/ { - model = "Buffalo LinkStation LS421DE"; - compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - led-boot = &led_boot; - led-failsafe = &led_failsafe; - led-running = &led_power; - led-upgrade = &led_upgrade; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - append-rootblock = "nullparameter="; /* override the bootloader args */ - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - }; - - system_fan: gpio_fan { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH - &gpio0 14 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - - #cooling-cells = <2>; - }; - - thermal-zones { - hdd-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */ - - trips { - hdd_alert1: trip1 { - temperature = <36000>; - hysteresis = <2000>; - type = "active"; - }; - hdd_alert2: trip2 { - temperature = <44000>; - hysteresis = <2000>; - type = "active"; - }; - hdd_alert3: trip3 { - temperature = <52000>; - hysteresis = <2000>; - type = "passive"; - }; - hdd_crit: trip4 { - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&hdd_alert1>; - cooling-device = <&system_fan THERMAL_NO_LIMIT 1>; - }; - map2 { - trip = <&hdd_alert2>; - cooling-device = <&system_fan 2 2>; - }; - map3 { - trip = <&hdd_alert3>; - cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>; - }; - }; - }; - - ethphy-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <ðphy0>; - - trips { - ethphy_alert1: trip1 { - temperature = <65000>; - hysteresis = <4000>; - type = "passive"; - }; - - ethphy_crit: trip2 { - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <ðphy_alert1>; - cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - power { - label = "Power Switch"; - linux,code = ; - linux,input-type = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - function { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_leds1 &pmx_leds2>; - - system_red { - label = "ls421de:red:system"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - led_power: power_white { - label = "ls421de:white:power"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led_failsafe: power_red { - label = "ls421de:red:power"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - led_upgrade: power_orange { - label = "ls421de:orange:power"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - }; - - led_boot: system_white { - label = "ls421de:white:system"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - hdd1_red { - label = "ls421de:red:hdd1"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ata1"; - }; - - hdd2_red { - label = "ls421de:red:hdd2"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ata2"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>; - pinctrl-names = "default"; - - usb_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "HDD1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - sata2_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD2"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&coherencyfab { - broken-idle; -}; - -ð1 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - wakeup-source; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */ - reg = <0>; - marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */ - <0x3 0x10 0x0000 0x1991>, /* LED function */ - <0x3 0x11 0x0000 0x4401>, /* LED polarity */ - <0x3 0x12 0x0000 0x4905>; /* LED timer */ - #thermal-sensor-cells = <0>; - }; -}; - -&pciec { - status = "okay"; - pinctrl-0 = <&pmx_pcie>; - pinctrl-names = "default"; - - /* Connected to uPD720202 USB 3.0 Host */ - pcie@1,0 { - status = "okay"; - }; -}; - -&pmsu { - pinctrl-0 = <&pmx_power_cpu>; - pinctrl-names = "default"; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - nr-ports = <2>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - hdd0_temp: sata-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; - - hdd1_temp: sata-port@1 { - reg = <1>; - #thermal-sensor-cells = <0>; - }; -}; - -&sdio { - pinctrl-0 = <&sdio_pins2>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x00000000 0x02000000>; /* 32 MiB */ - }; - - partition@2000000 { - label = "ubi"; - reg = <0x02000000 0x1e000000>; /* 480 MiB */ - }; - }; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000 0xf0000>; /* 960 KiB*/ - label = "u-boot"; - read-only; - }; - partition@f0000 { - reg = <0xf0000 0x10000>; /* 64 KiB */ - label = "u-boot-env"; - }; - }; - }; -}; - -&pinctrl { - pmx_power_cpu: pmx-power-cpu { - marvell,pins = "mpp4"; - marvell,function = "vdd"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp5"; - marvell,function = "gpo"; - }; - - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_power_hdd2: pmx-power-hdd2 { - marvell,pins = "mpp9"; - marvell,function = "gpo"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_hdd_present: pmx-hdd-present { - marvell,pins = "mpp11", "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp15", "mpp16"; - marvell,function = "gpio"; - }; - - pmx_leds1: pmx-leds { - marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61"; - marvell,function = "gpo"; - }; - - pmx_leds2: pmx-leds { - marvell,pins = "mpp55", "mpp57", "mpp62"; - marvell,function = "gpio"; - }; - - pmx_pcie: pmx-pcie { - marvell,pins = "mpp56", "mpp60"; - marvell,function = "pcie"; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts deleted file mode 100644 index 0d5ec567ea..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Device Tree file for Ctera C200-V2 - * - * Copyright (C) 2021 Pawel Dembicki - */ - -/dts-v1/; - -#include "armada-370.dtsi" -#include -#include -#include -#include - -/ { - model = "Ctera C200 V2"; - compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - led-boot = &led_status_green; - led-failsafe = &led_status_red; - led-running = &led_status_green; - led-upgrade = &led_status_red; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1024 MB */ - }; - - soc { - ranges = ; - }; - - thermal-zones { - ethphy-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <ðphy0>; - - trips { - ethphy_alert1: trip1 { - temperature = <65000>; - hysteresis = <4000>; - type = "passive"; - }; - - ethphy_crit: trip2 { - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - - usb1 { - label = "USB1 Button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "USB2 Button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds1 &pmx_leds2>; - pinctrl-names = "default"; - - led-0 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - - led-1 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&usb1_port 1>, <&usb2_port 1>; - }; - - led-2 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - led-3 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&usb1_port 2>, <&usb2_port 2>; - }; - - led-4 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata2"; - }; - - led-5 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - led-6 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - }; - - led-7 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - }; - - led-8 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; - - led-9 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - }; - - led_status_red: led-10 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - - led-11 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata1"; - }; - - led_status_green: led-12 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&coherencyfab { - broken-idle; -}; - -ð1 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - - hwmon@2a { - compatible = "nuvoton,nct7802"; - reg = <0x2a>; - }; - - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - #thermal-sensor-cells = <0>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "certificate"; - reg = <0x0200000 0x100000>; - read-only; - }; - - partition@300000 { - label = "preset_cfg"; - reg = <0x0300000 0x100000>; - read-only; - }; - - partition@400000 { - label = "dev_params"; - reg = <0x0400000 0x100000>; - read-only; - }; - partition@500000 { - label = "active_bank"; - reg = <0x0500000 0x0100000>; - }; - - partition@600000 { - label = "magic"; - reg = <0x0600000 0x0100000>; - read-only; - }; - - partition@700000 { - label = "bank1"; - reg = <0x0700000 0x2800000>; - }; - - partition@2f00000 { - label = "bank2"; - reg = <0x2f00000 0x2800000>; - }; - - /* 0x5700000-0x5a00000 undefined in vendor firmware */ - - partition@5a00000 { - label = "reserved"; - reg = <0x5a00000 0x2000000>; - }; - - partition@7a00000 { - label = "ubi"; - reg = <0x7a00000 0x8600000>; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { - pinctrl-0 = <&pmx_pcie>; - pinctrl-names = "default"; - status = "okay"; - reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - - /* -[0000:00]---01.0-[01]----00.0 */ - /* usbport trigger won't work */ - bridge@0,1 { - compatible = "pci11ab,6710"; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - usb@1,0 { - /* Renesas uPD720202 */ - compatible = "pci1912,0015"; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - usb1_port: port@1 { - reg = <1>; - #trigger-source-cells = <1>; - }; - - usb2_port: port@2 { - reg = <2>; - #trigger-source-cells = <1>; - }; - }; - }; - }; -}; - -&pinctrl { - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_power_cpu: pmx-power-cpu { - marvell,pins = "mpp4"; - marvell,function = "vdd"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32"; - marvell,function = "gpio"; - }; - - pmx_leds1: pmx-leds1 { - marvell,pins = "mpp47"; - marvell,function = "gpo"; - }; - - pmx_leds2: pmx-leds2 { - marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51", - "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58"; - marvell,function = "gpio"; - }; - - pmx_pcie: pmx-pcie { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; - - /* this gpio is connected to the pin of buzzer - * leave it as is due lack of proper driver - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; -}; - -&pmsu { - pinctrl-0 = <&pmx_power_cpu>; - pinctrl-names = "default"; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - nr-ports = <2>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - hdd0_temp: sata-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; - - hdd1_temp: sata-port@1 { - reg = <1>; - #thermal-sensor-cells = <0>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts deleted file mode 100644 index 01c1ef675b..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; - -#include -#include -#include -#include "armada-380.dtsi" - -/ { - model = "IIJ SA-W2"; - compatible = "iij,sa-w2", "marvell,armada380"; - - aliases { - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_green; - label-mac-device = &ge0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256MB */ - }; - - soc { - ranges = ; - - pcie { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - - pcie@3,0 { - status = "okay"; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_keys_pins>; - - button-init { - label = "init"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_leds_pins>; - - led-0 { - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN_5GHZ; - linux,default-trigger = "phy0tpt"; - }; - - led-1 { - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN_5GHZ; - }; - - led-2 { - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-3 { - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-4 { - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_MOBILE; - }; - - led-5 { - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_MOBILE; - }; - - led-6 { - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN_2GHZ; - linux,default-trigger = "phy1tpt"; - }; - - led-7 { - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_WLAN_2GHZ; - }; - - led_power_green: led-8 { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_POWER; - }; - - led_power_red: led-9 { - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_POWER; - }; - - led-10 { - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_USB; - function-enumerator = <1>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port2>; - }; - - led-11 { - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_USB; - function-enumerator = <0>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port1>; - }; - }; - - regulator-vbus-usb0 { - compatible = "regulator-fixed"; - regulator-name = "vbus-usb0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - regulator-vbus-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vbus-usb1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&pinctrl { - pmx_usb_pins: usb-pins { - marvell,pins = "mpp2", /* smsc usb2514b reset */ - "mpp48", "mpp49", /* port over current */ - "mpp52", "mpp53"; /* port vbus */ - marvell,function = "gpio"; - }; - - pmx_keys_pins: keys-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_leds_pins: leds-pins { - marvell,pins = "mpp19", "mpp20", "mpp33", "mpp34", "mpp35", - "mpp36", "mpp44", "mpp45", "mpp46", "mpp47", - "mpp54", "mpp55"; - marvell,function = "gpio"; - }; -}; - -&gpio0 { - usb-hub-reset { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pmx_usb_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* SMSC USB2514B on PCB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - hub_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð1 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - - phy-connection-type = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - - nvmem-cells = <&macaddr_bdinfo_6 1>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - /* Marvell 88E6172 */ - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0x0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "ge1_0"; - }; - - port@1 { - reg = <1>; - label = "ge1_1"; - }; - - port@2 { - reg = <2>; - label = "ge1_2"; - }; - - port@3 { - reg = <3>; - label = "ge1_3"; - }; - - ge0: port@4 { - reg = <4>; - label = "ge0"; - nvmem-cells = <&macaddr_bdinfo_6 0>; - nvmem-cell-names = "mac-address"; - }; - - /* - * eth0 is connected to port5 for WAN connection - * on port4 ("GE0") - */ - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <ð1>; - phy-connection-type = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&rtc { - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x100000>; - label = "bootloader"; - read-only; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "bootloader-env"; - read-only; - }; - - partition@110000 { - reg = <0x110000 0xf0000>; - label = "board_info"; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_bdinfo_6: macaddr@6 { - compatible = "mac-base"; - reg = <0x6 0x6>; - #nvmem-cell-cells = <1>; - }; - }; - }; - - partition@200000 { - compatible = "iij,seil-firmware"; - reg = <0x200000 0xf00000>; - label = "firmware"; - iij,bootdev-name = "flash"; - iij,seil-id = <0x5345494c 0x32303135>; - }; - - partition@1100000 { - compatible = "iij,seil-firmware"; - reg = <0x1100000 0xf00000>; - label = "rescue"; - iij,bootdev-name = "rescue"; - iij,seil-id = <0x5345494c 0x32303135>; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts deleted file mode 100644 index dca6fbacf0..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "armada-385-fortinet-fg-x0e.dtsi" - -/ { - model = "Fortinet FortiGate 30E"; - compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1GB */ - }; -}; - -&gpio_leds { - led-14 { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; - }; - - led-15 { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; - }; -}; - -&pinctrl { - pmx_switch_pins: switch-pins { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>; - - /* Marvell 88E6176 */ - switch@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2>; - reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - nvmem-cells = <&macaddr_bdinfo_d880 1>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - nvmem-cells = <&macaddr_bdinfo_d880 5>; - nvmem-cell-names = "mac-address"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - nvmem-cells = <&macaddr_bdinfo_d880 4>; - nvmem-cell-names = "mac-address"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - nvmem-cells = <&macaddr_bdinfo_d880 3>; - nvmem-cell-names = "mac-address"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - nvmem-cells = <&macaddr_bdinfo_d880 2>; - nvmem-cell-names = "mac-address"; - }; - - port@6 { - reg = <6>; - ethernet = <ð0>; - phy-connection-type = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts deleted file mode 100644 index cf13bb5fda..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "armada-385-fortinet-fg-x0e.dtsi" - -/ { - model = "Fortinet FortiGate 50E"; - compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; -}; - -&gpio_leds { - led-14 { - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - function-enumerator = <1>; - linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; - }; - - led-15 { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - function-enumerator = <2>; - linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; - }; - - led-16 { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <5>; - linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; - }; - - led-17 { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <5>; - linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; - }; -}; - -&pinctrl { - pmx_phy_switch_pins: phy-switch-pins { - marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41"; - marvell,function = "gpio"; - }; -}; - -ð1 { - status = "okay"; - - phy-handle = <ðphy0>; - phy-connection-type = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - nvmem-cells = <&macaddr_bdinfo_d880 1>; - nvmem-cell-names = "mac-address"; -}; - -ð2 { - status = "okay"; - - phy-handle = <ðphy1>; - phy-connection-type = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - nvmem-cells = <&macaddr_bdinfo_d880 2>; - nvmem-cell-names = "mac-address"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>; - - /* Marvell 88E1512 */ - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0141,0dd1", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - /* - * LINK/ACT (Green): LED[0], Active Low - * SPEED 100M (Amber): LED[1], Active High - */ - marvell,reg-init = <3 16 0 0x71>, - <3 17 0 0x4>; - }; - - /* Marvell 88E1512 */ - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0141,0dd1", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - /* - * LINK/ACT (Green): LED[0], Active Low - * SPEED 100M (Amber): LED[1], Active High - */ - marvell,reg-init = <3 16 0 0x71>, - <3 17 0 0x4>; - }; - - /* Marvell 88E6176 */ - switch@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2>; - reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - nvmem-cells = <&macaddr_bdinfo_d880 7>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - nvmem-cells = <&macaddr_bdinfo_d880 6>; - nvmem-cell-names = "mac-address"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - nvmem-cells = <&macaddr_bdinfo_d880 5>; - nvmem-cell-names = "mac-address"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - nvmem-cells = <&macaddr_bdinfo_d880 4>; - nvmem-cell-names = "mac-address"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - nvmem-cells = <&macaddr_bdinfo_d880 3>; - nvmem-cell-names = "mac-address"; - }; - - port@6 { - reg = <6>; - ethernet = <ð0>; - phy-connection-type = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi deleted file mode 100644 index 6a5e016d30..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; - -#include -#include -#include -#include "armada-385.dtsi" - -/ { - aliases { - led-boot = &led_status_green; - led-failsafe = &led_status_red; - led-running = &led_status_green; - led-upgrade = &led_status_green; - label-mac-device = ð0; - }; - - chosen { - stdout-path = "serial0:9600n8"; - }; - - soc { - ranges = ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_gpio_keys_pins>; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_gpio_leds_pins>; - - led-0 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_ALARM; - }; - - led-1 { - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - color = ; - function = "ha"; - }; - - led_status_green: led-2 { - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-3 { - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - color = ; - function = "ha"; - }; - - led-4 { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_ALARM; - }; - - led_status_red: led-5 { - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-6 { - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <4>; - linux,default-trigger = "mv88e6xxx-1:01:1Gbps"; - }; - - led-7 { - gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <4>; - linux,default-trigger = "mv88e6xxx-1:01:100Mbps"; - }; - - led-8 { - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <3>; - linux,default-trigger = "mv88e6xxx-1:02:100Mbps"; - }; - - led-9 { - gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <3>; - linux,default-trigger = "mv88e6xxx-1:02:1Gbps"; - }; - - led-10 { - gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <1>; - linux,default-trigger = "mv88e6xxx-1:04:1Gbps"; - }; - - led-11 { - gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <1>; - linux,default-trigger = "mv88e6xxx-1:04:100Mbps"; - }; - - led-12 { - gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <2>; - linux,default-trigger = "mv88e6xxx-1:03:1Gbps"; - }; - - led-13 { - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <2>; - linux,default-trigger = "mv88e6xxx-1:03:100Mbps"; - }; - }; - - reg_usb_vbus: regulator-usb-vbus { - compatible = "fixed-regulator"; - regulator-name = "usb-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - gpio2: gpio@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <0x2>; - }; - - hwmon@28 { - compatible = "nuvoton,nct7802"; - reg = <0x28>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&pinctrl { - pmx_gpio_leds_pins: gpio-leds-pins { - marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35", - "mpp45", "mpp47"; - marvell,function = "gpio"; - }; - - pmx_usb_pins: usb-pins { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - pmx_gpio_keys_pins: gpio-keys-pins { - marvell,pins = "mpp54"; - marvell,function = "gpio"; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - - phy-connection-type = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - nvmem-cells = <&macaddr_bdinfo_d880 0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pmx_usb_pins>; - status = "okay"; - - vbus-supply = <®_usb_vbus>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x1c0000>; - label = "u-boot"; - read-only; - }; - - partition@1c0000 { - reg = <0x1c0000 0x10000>; - label = "firmware-info"; - - /* - * 0x10 - 0x2f : image name (image1) - * 0x30 - 0x4f : image name (image2) - * 0x170 (1byte): active image (0x0/0x1) - * 0x184 - 0x185: kernel block count (image1) - * 0x18c - 0x18d: rootfs block count (image1) - * 0x194 - 0x195: kernel block count (image2) - * 0x19c - 0x19d: rootfs block count (image2) - * 0x1be (1byte): bit7 -> active flag (image1)? - * 0x1ce (1byte): bit7 -> active flag (image2)? - * - * Note: block size --> 0x200 (512 bytes) - */ - }; - - partition@1d0000 { - reg = <0x1d0000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@1e0000 { - reg = <0x1e0000 0x10000>; - label = "u-boot-env"; - read-only; - }; - - partition@1f0000 { - reg = <0x1f0000 0x10000>; - label = "board-info"; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_bdinfo_d880: macaddr@d880 { - compatible = "mac-base"; - reg = <0xd880 0x6>; - #nvmem-cell-cells = <1>; - }; - }; - }; - - partition@200000 { - reg = <0x200000 0x600000>; - label = "kernel"; - }; - - partition@800000 { - reg = <0x800000 0x1800000>; - label = "rootfs"; - }; - - partition@2000000 { - reg = <0x2000000 0x600000>; - label = "kn2"; - read-only; - }; - - partition@2600000 { - reg = <0x2600000 0x1800000>; - label = "rfs2"; - read-only; - }; - - partition@3e00000 { - reg = <0x3e00000 0x1200000>; - label = "part1"; - read-only; - }; - - partition@5000000 { - reg = <0x5000000 0x1200000>; - label = "part2"; - read-only; - }; - - partition@6200000 { - reg = <0x6200000 0x1e00000>; - label = "config"; - read-only; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts deleted file mode 100644 index a2ca3158cf..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Device Tree file for the Linksys WRT32X (Venom) - * - * Copyright (C) 2017 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT32X"; - compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385", - "marvell,armada385", "marvell,armada380"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - append-rootblock = "root=/dev/mtdblock"; - }; -}; - -&expander0 { - wan_amber@0 { - label = "venom:amber:wan"; - reg = <0x0>; - }; - - wan_blue@1 { - label = "venom:blue:wan"; - reg = <0x1>; - }; - - usb2@5 { - label = "venom:blue:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "venom:blue:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "venom:blue:usb3_2"; - reg = <0x7>; - }; - - wps_blue@8 { - label = "venom:blue:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "venom:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - power { - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - label = "venom:blue:power"; - }; - - sata { - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - label = "venom:blue:sata"; - }; - - wlan_2g { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - label = "venom:blue:wlan_2g"; - }; - - wlan_5g { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - label = "venom:blue:wlan_5g"; - }; -}; - -&gpio_leds_pins { - marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; -}; - -&nand { - /* Spansion S34ML02G2 256MiB, OEM Layout */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MB */ - read-only; - }; - - partition@200000 { - label = "u_env"; - reg = <0x200000 0x20000>; /* 128KB */ - }; - - partition@220000 { - label = "s_env"; - reg = <0x220000 0x40000>; /* 256KB */ - }; - - partition@180000 { - label = "unused_area"; - reg = <0x260000 0x5c0000>; /* 5.75MB */ - }; - - partition@7e0000 { - label = "devinfo"; - reg = <0x7e0000 0x40000>; /* 256KB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@900000 { - label = "kernel1"; - reg = <0x900000 0x7b00000>; /* 123MB */ - }; - - partition@f00000 { - label = "rootfs1"; - reg = <0xf00000 0x7500000>; /* 117MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@8400000 { - label = "kernel2"; - reg = <0x8400000 0x7b00000>; /* 123MB */ - }; - - partition@8a00000 { - label = "rootfs2"; - reg = <0x8a00000 0x7500000>; /* 117MB */ - }; - - /* last MB is for the BBT, not writable */ - partition@ff00000 { - label = "BBT"; - reg = <0xff00000 0x100000>; - }; - }; -}; - - -&pcie1 { - mwlwifi { - marvell,chainmask = <4 4>; - }; -}; - -&pcie2 { - mwlwifi { - marvell,chainmask = <4 4>; - }; -}; - -&sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - non-removable; - wp-inverted; - bus-width = <8>; - status = "okay"; -}; - -&usb3_1_vbus { - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; -}; - -&usb3_1_vbus_pins { - marvell,pins = "mpp44"; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts deleted file mode 100644 index f1fd72a93c..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR MIT) -/* - * Device Tree file for ipTIME NAS1dual - * - * Copyright (C) 2020 Sungbo Eo - * - * Based on armada-385-linksys.dtsi - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; - -#include -#include -#include -#include "armada-385.dtsi" - -/ { - model = "ipTIME NAS1dual"; - compatible = "iptime,nas1dual", "marvell,armada385", "marvell,armada380"; - - aliases { - led-boot = &led_ready; - led-failsafe = &led_ready; - led-running = &led_ready; - led-upgrade = &led_ready; - label-mac-device = ð0; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - power { - label = "Power Button"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - copy { - label = "USB Copy Button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds_pins>; - - led_ready: ready { - label = "blue:ready"; - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - - hdd { - label = "blue:hdd"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - - usb { - function = LED_FUNCTION_USB; - color = ; - gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - trigger-sources = <&usb3_0_port1 &usb3_0_port2>; - linux,default-trigger = "usbport"; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_fan_pins>; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>, - <&gpio1 18 GPIO_ACTIVE_HIGH>; - /* We don't know the exact rpm, just use dummy values here. */ - gpio-fan,speed-map = <0 0>, <1 1>, <2 2>; - #cooling-cells = <2>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&pca9536 1 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_power_pins>; - - reg_sata_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "sata-power"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - }; -}; - -&ahci0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata-port@0 { - reg = <0>; - target-supply = <®_sata_power>; - #thermal-sensor-cells = <0>; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - nvmem-cells = <&macaddr_uboot_fffa8>; - nvmem-cell-names = "mac-address"; -}; - -ð1 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - nvmem-cells = <&macaddr_uboot_fffa8>; - nvmem-cell-names = "mac-address"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - pca9536: gpio@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "power-led", "power-board"; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - /* LED1: On - Link, Blink - Activity, Off - No Link */ - - ethphy0: ethernet-phy@0 { - reg = <0>; - marvell,reg-init = <3 16 0 0x1017>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 16 0 0x1017>; - }; -}; - -&pinctrl { - gpio_keys_pins: gpio-keys-pins { - marvell,pins = "mpp24", "mpp26", "mpp48"; - marvell,function = "gpio"; - }; - - gpio_leds_pins: gpio-leds-pins { - marvell,pins = "mpp18", "mpp20", "mpp51"; - marvell,function = "gpio"; - }; - - gpio_fan_pins: gpio-fan-pins { - marvell,pins = "mpp25", "mpp50"; - marvell,function = "gpio"; - }; - - sata_power_pins: sata-power-pins { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - uart1_pins_alt: uart-pins-1-alt { - marvell,pins = "mpp45", "mpp46"; - marvell,function = "ua1"; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_fffa8: macaddr@fffa8 { - reg = <0xfffa8 0x6>; - }; - }; - }; - - partition@100000 { - reg = <0x00100000 0x03ec0000>; - label = "firmware"; - - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000000 0x00600000>; - label = "kernel"; - }; - - partition@600000 { - reg = <0x00600000 0x038c0000>; - label = "rootfs"; - }; - }; - - partition@3fc0000 { - reg = <0x03fc0000 0x00040000>; - label = "config"; - read-only; - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_alt>; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_0_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_0_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts deleted file mode 100644 index 35f107b63b..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "armada-3720-uDPU.dtsi" - -/ { - model = "Methode eDPU Board"; - compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710"; -}; - -/* PHY mode is set to 1000Base-X despite Maxlinear IC being capable of - * 2500Base-X since until 5.15 support for mvebu is available trying to - * use 2500Base-X will cause buffer overruns for which the fix is not - * easily backportable. - */ -ð0 { - phy-mode = "1000base-x"; -}; - -/* - * External MV88E6361 switch is only available on v2 of the board. - * U-Boot will enable the MDIO bus and switch nodes. - */ -&mdio { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&smi_pins>; - - /* Actual device is MV88E6361 */ - switch: switch@0 { - compatible = "marvell,mv88e6190"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - ethernet = <ð0>; - }; - - port@9 { - reg = <9>; - label = "downlink"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - - port@a { - reg = <10>; - label = "uplink"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - sfp = <&sfp_eth1>; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts deleted file mode 100644 index 1a6594e3cd..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for ESPRESSObin-Ultra - * Copyright (C) 2019 Globalscale technologies, Inc. - * - * Jason Hung - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Ultra Board"; - compatible = "globalscale,espressobin-ultra", "marvell,armada3720", - "marvell,armada3710"; - - aliases { - /* for dsa slave device */ - ethernet1 = &switch0port1; - ethernet2 = &switch0port2; - ethernet3 = &switch0port3; - ethernet4 = &switch0port4; - ethernet5 = &switch0port5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>; - }; - - usb3_phy: usb3-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_vbus>; - }; - - leds { - pinctrl-names = "default"; - compatible = "gpio-leds"; - /* No assigned functions to the LEDs by default */ - led1 { - label = "ebin-ultra:blue:led1"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - led2 { - label = "ebin-ultra:green:led2"; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - led3 { - label = "ebin-ultra:red:led3"; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - }; - led4 { - label = "ebin-ultra:yellow:led4"; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x0 0x3e0000>; - }; - partition@3e0000 { - label = "hw-info"; - reg = <0x3e0000 0x10000>; - read-only; - }; - partition@3f0000 { - label = "u-boot-env"; - reg = <0x3f0000 0x10000>; - }; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <100000>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&usb3 { - status = "okay"; - usb-phy = <&usb3_phy>; -}; - -&usb2 { - status = "okay"; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&mdio { - status = "okay"; - - extphy: ethernet-phy@0 { - reg = <1>; - }; - - switch0: switch0@1 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch0port0: port@0 { - reg = <0>; - ethernet = <ð0>; - }; - - switch0port1: port@1 { - reg = <1>; - label = "lan0"; - phy-handle = <&switch0phy1>; - }; - - switch0port2: port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy2>; - }; - - switch0port3: port@3 { - reg = <3>; - label = "lan2"; - phy-handle = <&switch0phy3>; - }; - - switch0port4: port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy4>; - }; - - switch0port5: port@5 { - reg = <5>; - label = "wan"; - phy-handle = <&extphy>; - phy-mode = "sgmii"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy1@11 { - reg = <0x11>; - }; - switch0phy2: switch0phy2@12 { - reg = <0x12>; - }; - switch0phy3: switch0phy3@13 { - reg = <0x13>; - }; - switch0phy4: switch0phy4@14 { - reg = <0x14>; - }; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts deleted file mode 100644 index 07400fce3a..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) - -/dts-v1/; -#include -#include -#include -#include "armada-372x.dtsi" - -/ { - model = "GL.iNet GL-MV1000"; - compatible = "glinet,gl-mv1000", "marvell,armada3720"; - - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - - switch { - label = "switch"; - linux,code = ; - gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - vpn { - label = "green:vpn"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - - wan { - function = LED_FUNCTION_WAN; - color = ; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - - led_power: power { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; - m25p,fast-read; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0 0xf0000>; - read-only; - }; - - partition@f0000 { - label = "u-boot-env"; - reg = <0xf0000 0x8000>; - read-only; - }; - - factory: partition@f8000 { - label = "factory"; - reg = <0xf8000 0x8000>; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_factory_6: macaddr@6 { - reg = <0x6 0x6>; - }; - }; - }; - - partition@100000 { - label = "gl-firmware-dtb"; - reg = <0x100000 0x10000>; - read-only; - }; - - partition@110000 { - label = "gl-firmware"; - reg = <0x110000 0xef0000>; - read-only; - }; - - partition@ef0000 { - label = "gl-firmware-jffs2"; - reg = <0xef0000 0x110000>; - read-only; - }; - }; - }; -}; - -&sdhci1 { - wp-inverted; - bus-width = <4>; - cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>; - marvell,pad-type = "sd"; - no-1-8-v; - vqmmc-supply = <&vcc_sd_reg1>; - status = "okay"; -}; - -&sdhci0 { - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - non-removable; - no-sd; - no-sdio; - marvell,pad-type = "fixed-1-8v"; - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&mdio { - switch0: switch0@1 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - dsa,member = <0 0>; - - ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - ethernet = <ð0>; - }; - - port@1 { - reg = <1>; - label = "wan"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan0"; - phy-handle = <&switch0phy1>; - - nvmem-cells = <&macaddr_factory_6>; - nvmem-cell-names = "mac-address"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - phy-handle = <&switch0phy2>; - - nvmem-cells = <&macaddr_factory_6>; - nvmem-cell-names = "mac-address"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - }; - }; -}; - -ð0 { - nvmem-cells = <&macaddr_factory_0>; - nvmem-cell-names = "mac-address"; - phy-mode = "rgmii-id"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts deleted file mode 100644 index 186a5e7d7d..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "armada-3720-uDPU.dtsi" - -/ { - model = "Methode uDPU Board"; - compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710"; - - sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&pinctrl_nb { - i2c1_recovery_pins: i2c1-recovery-pins { - groups = "i2c1"; - function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_recovery_pins>; - /delete-property/mrvl,i2c-fast-mode; - scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -ð0 { - phy-mode = "2500base-x"; - sfp = <&sfp_eth0>; -}; - -ð1 { - phy-mode = "2500base-x"; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi deleted file mode 100644 index bc8d1f1020..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree for the uDPU board. - * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * Copyright (C) 2019 Methode Electronics - * Copyright (C) 2019 Telus - * - * Vladimir Vid - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - }; - - leds { - compatible = "gpio-leds"; - - led-power1 { - label = "udpu:green:power"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - - led-power2 { - label = "udpu:red:power"; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - - led-network1 { - label = "udpu:green:network"; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - }; - - led-network2 { - label = "udpu:red:network"; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - - led-alarm1 { - label = "udpu:green:alarm"; - gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; - }; - - led-alarm2 { - label = "udpu:red:alarm"; - gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; - }; - }; - - sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - non-removable; - no-sd; - no-sdio; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <54000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x0 0x180000>; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x10000>; - }; - }; - }; -}; - -&pinctrl_nb { - i2c2_recovery_pins: i2c2-recovery-pins { - groups = "i2c2"; - function = "gpio"; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_recovery_pins>; - /delete-property/mrvl,i2c-fast-mode; - scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - temp-sensor@48 { - compatible = "ti,tmp75c"; - reg = <0x48>; - }; - - temp-sensor@49 { - compatible = "ti,tmp75c"; - reg = <0x49>; - }; -}; - -ð0 { - status = "okay"; - managed = "in-band-status"; - phys = <&comphy1 0>; -}; - -ð1 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy0 1>; - sfp = <&sfp_eth1>; -}; - -&usb3 { - status = "okay"; - phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts deleted file mode 100644 index 26804a4875..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree file for Globalscale MOCHAbin - * Copyright (C) 2019 Globalscale technologies, Inc. - * Copyright (C) 2021 Sartura Ltd. - * - */ - -/dts-v1/; - -#include -#include "armada-7040.dtsi" - -/ { - model = "Globalscale MOCHAbin"; - compatible = "globalscale,mochabin", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - ethernet3 = &swport1; - ethernet4 = &swport2; - ethernet5 = &swport3; - ethernet6 = &swport4; - }; - - /* SFP+ 10G */ - sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_i2c1>; - los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - /* SFP 1G */ - sfp_eth2: sfp-eth2 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_i2c0>; - los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; - }; -}; - -/* microUSB UART console */ -&uart0 { - status = "okay"; - - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -/* eMMC */ -&ap_sdhci0 { - status = "okay"; - - bus-width = <4>; - non-removable; - /delete-property/ marvell,xenon-phy-slow-mode; - no-1-8-v; -}; - -&cp0_pinctrl { - cp0_uart0_pins: cp0-uart0-pins { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "uart0"; - }; - - cp0_spi0_pins: cp0-spi0-pins { - marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; - marvell,function = "spi0"; - }; - - cp0_spi1_pins: cp0-spi1-pins { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - - cp0_i2c0_pins: cp0-i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - - cp0_i2c1_pins: cp0-i2c1-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c1"; - }; - - pca9554_int_pins: pca9554-int-pins { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - cp0_rgmii1_pins: cp0-rgmii1-pins { - marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - - is31_sdb_pins: is31-sdb-pins { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - cp0_pcie_reset_pins: cp0-pcie-reset-pins { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - cp0_switch_pins: cp0-switch-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "gpio"; - }; - - cp0_phy_pins: cp0-phy-pins { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; -}; - -/* mikroBUS UART */ -&cp0_uart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_uart0_pins>; -}; - -/* mikroBUS SPI */ -&cp0_spi0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; -}; - -/* SPI-NOR */ -&cp0_spi1{ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi1_pins>; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x3e0000>; - read-only; - }; - - partition@3e0000 { - label = "hw-info"; - reg = <0x3e0000 0x10000>; - read-only; - }; - - partition@3f0000 { - label = "u-boot-env"; - reg = <0x3f0000 0x10000>; - }; - }; - }; -}; - -/* mikroBUS, 1G SFP and GPIO expander */ -&cp0_i2c0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - clock-frequency = <100000>; - - sfp_gpio: pca9554@39 { - compatible = "nxp,pca9554"; - pinctrl-names = "default"; - pinctrl-0 = <&pca9554_int_pins>; - reg = <0x39>; - - interrupt-parent = <&cp0_gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - gpio-controller; - #gpio-cells = <2>; - - /* - * IO0_0: SFP+_TX_FAULT - * IO0_1: SFP+_TX_DISABLE - * IO0_2: SFP+_PRSNT - * IO0_3: SFP+_LOSS - * IO0_4: SFP_TX_FAULT - * IO0_5: SFP_TX_DISABLE - * IO0_6: SFP_PRSNT - * IO0_7: SFP_LOSS - */ - }; -}; - -/* IS31FL3199, mini-PCIe and 10G SFP+ */ -&cp0_i2c1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - clock-frequency = <100000>; - - leds@64 { - compatible = "issi,is31fl3199"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&is31_sdb_pins>; - shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>; - reg = <0x64>; - - led1_red: led@1 { - label = "red:led1"; - reg = <1>; - led-max-microamp = <20000>; - }; - - led1_green: led@2 { - label = "green:led1"; - reg = <2>; - }; - - led1_blue: led@3 { - label = "blue:led1"; - reg = <3>; - }; - - led2_red: led@4 { - label = "red:led2"; - reg = <4>; - }; - - led2_green: led@5 { - label = "green:led2"; - reg = <5>; - }; - - led2_blue: led@6 { - label = "blue:led2"; - reg = <6>; - }; - - led3_red: led@7 { - label = "red:led3"; - reg = <7>; - }; - - led3_green: led@8 { - label = "green:led3"; - reg = <8>; - }; - - led3_blue: led@9 { - label = "blue:led3"; - reg = <9>; - }; - }; -}; - -&cp0_mdio { - status = "okay"; - - /* 88E1512 PHY */ - eth2phy: ethernet-phy@1 { - reg = <1>; - sfp = <&sfp_eth2>; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_phy_pins>; - reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>; - }; - - /* 88E6141 Topaz switch */ - switch: switch@3 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_switch_pins>; - reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&cp0_gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - swport1: port@1 { - reg = <1>; - label = "lan0"; - phy-handle = <&swphy1>; - }; - - swport2: port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&swphy2>; - }; - - swport3: port@3 { - reg = <3>; - label = "lan2"; - phy-handle = <&swphy3>; - }; - - swport4: port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&swphy4>; - }; - - port@5 { - reg = <5>; - ethernet = <&cp0_eth1>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - swphy1: swphy1@17 { - reg = <17>; - }; - - swphy2: swphy2@18 { - reg = <18>; - }; - - swphy3: swphy3@19 { - reg = <19>; - }; - - swphy4: swphy4@20 { - reg = <20>; - }; - }; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* 10G SFP+ */ -&cp0_eth0 { - status = "okay"; - - phy-mode = "10gbase-r"; - phys = <&cp0_comphy4 0>; - managed = "in-band-status"; - sfp = <&sfp_eth0>; -}; - -/* Topaz switch uplink */ -&cp0_eth1 { - status = "okay"; - - phy-mode = "2500base-x"; - phys = <&cp0_comphy0 1>; - - fixed-link { - speed = <2500>; - full-duplex; - }; -}; - -/* 1G SFP or 1G RJ45 */ -&cp0_eth2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_rgmii1_pins>; - - phy = <ð2phy>; - phy-mode = "rgmii-id"; -}; - -/* SMSC USB5434B hub */ -&cp0_usb3_0 { - status = "okay"; - - phys = <&cp0_comphy1 0>; - phy-names = "cp0-usb3h0-comphy"; -}; - -/* miniPCI-E USB */ -&cp0_usb3_1 { - status = "okay"; -}; - -&cp0_sata0 { - status = "okay"; - - /* 7 + 12 SATA connector (J24) */ - sata-port@0 { - phys = <&cp0_comphy2 0>; - phy-names = "cp0-sata0-0-phy"; - }; - - /* M.2-2250 B-key (J39) */ - sata-port@1 { - phys = <&cp0_comphy3 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -/* miniPCI-E (J5) */ -&cp0_pcie2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pcie_reset_pins>; - phys = <&cp0_comphy5 2>; - phy-names = "cp0-pcie2-x1-phy"; - reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; - ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts deleted file mode 100644 index b5cc630781..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts +++ /dev/null @@ -1,513 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright SolidRun Ltd. - * Copyright (C) 2024 Tobias Schramm - * - * Device tree for the CN9130-based ClearFog Pro - */ - -#include "cn9130.dtsi" - -#include -#include - -/ { - model = "SolidRun ClearFog Pro"; - compatible = "solidrun,clearfog-pro", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - i2c0 = &cp0_i2c0; - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - spi1 = &cp0_spi1; - }; - - memory@00000000 { - reg = <0x0 0x0 0x1 0x0>; - device_type = "memory"; - }; - - /* Virtual regulator, root of power tree */ - vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-always-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* Regulators supplied by vin */ - v_5v0: regulator-v_5v0 { - compatible = "regulator-fixed"; - regulator-name = "v_5v0"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vin>; - }; - - v_3v3: regulator-v_3v3 { - compatible = "regulator-fixed"; - regulator-name = "v_3v3"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vin>; - }; - - /* Regulators supplied by v_5v0 */ - v_1v8: regulator-v_1v8 { - compatible = "regulator-fixed"; - regulator-name = "v_1v8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&v_5v0>; - }; - - v_5v0_usb3_hst_vbus: regulator-v_5v0_usb3_hst_vbus { - compatible = "regulator-fixed"; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&expander0 6 GPIO_ACTIVE_LOW>; - vin-supply = <&v_5v0>; - }; - - /* Regulators internal to SOM */ - vqmmc: regulator-vqmmc { - compatible = "regulator-fixed"; - regulator-name = "vqmmc"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&v_5v0>; - }; - - cp0_usb3_0_phy1: cp0_usb3_phy@1 { - compatible = "usb-nop-xceiv"; - vbus-supply = <&v_5v0_usb3_hst_vbus>; - }; - - cp0_sfp_eth0: sfp-eth@0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_i2c1>; - los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_button_pin>; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* on-board eMMC */ -&ap_sdhci0 { - bus-width = <8>; - pinctrl-names = "default"; - vqmmc-supply = <&vqmmc>; - status = "okay"; -}; - -&cp0_crypto { - status = "okay"; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - clock-frequency = <100000>; - - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2-CON2 PERST# - * 3-CON3 W_DISABLE - * 4-CON2 CLKREQ# - * 5-USB3 overcurrent - * 6-USB3 power - * 7-CON2 W_DISABLE - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - expander0: gpio-expander@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&cp0_gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_expander0_pins>; - vcc-supply = <&v_3v3>; - - pcie1_0_clkreq { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie1.0-clkreq"; - }; - - pcie1_0_w_disable { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie1.0-w-disable"; - }; - - pcie2_0_clkreq { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie2.0-clkreq"; - }; - - pcie2_0_w_disable { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie2.0-w-disable"; - }; - - usb3_ilimit { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - input; - line-name = "usb3-current-limit"; - }; - - m2_devslp { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "m.2 devslp"; - }; - }; - - /* ADC only for mikroBUS connector */ - mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; - - /* EEPROM on the SOM */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - read-only; - - nvmem-layout { - compatible = "onie,tlv-layout"; - - onie_tlv_macaddr: mac-address { - #nvmem-cell-cells = <1>; - }; - }; - }; -}; - -/* SMBUS on mini PCIe sockets */ -&cp0_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - clock-frequency = <100000>; -}; - -&cp0_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - /* Green led blinks on activity, orange LED on link */ - marvell,reg-init = <3 16 0 0x0064>; - }; - - switch@4 { - compatible = "marvell,mv88e6085"; - reg = <4>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&cp0_gpio1>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_dsa0_pins>; - reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; - - mdio-external { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - - /* 88E1512 PHY */ - port6_phy: ethernet-phy@1 { - reg = <1>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - ethernet = <&cp0_eth1>; - label = "cpu"; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - phy-handle = <&port6_phy>; - phy-mode = "rgmii-id"; - }; - }; - }; -}; - -/* SRDS #0 - SATA on bottom M.2 B-Key connector */ -&cp0_sata0 { - status = "okay"; - - sata-port@0 { - status = "disabled"; - }; - - sata-port@1 { - phys = <&cp0_comphy0 1>; - target-supply = <&v_3v3>; - }; -}; - -&cp0_utmi { - status = "okay"; -}; - -/* mini PCIe slot far from SOM, USB 2.0 only, SS lanes unused */ -&cp0_usb3_0 { - status = "okay"; - phys = <&cp0_utmi0>; - phy-names = "utmi"; - dr_mode = "host"; -}; - -/* SRDS #1 - USB-A 3.0 host port */ -&cp0_usb3_1 { - status = "okay"; - phys = <&cp0_utmi1>, <&cp0_comphy1 0>; - phy-names = "utmi", "usb"; - usb-phy = <&cp0_usb3_0_phy1>; - dr_mode = "host"; -}; - -/* SRDS #2 - SFP+ 10GE */ -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-r"; - phys = <&cp0_comphy2 0>; - managed = "in-band-status"; - nvmem-cells = <&onie_tlv_macaddr 0>; - nvmem-cell-names = "mac-address"; - sfp = <&cp0_sfp_eth0>; -}; - -/* SRDS #3 - SGMII 1GE to L2 switch */ -&cp0_eth1 { - status = "okay"; - phys = <&cp0_comphy3 1>; - phy-mode = "sgmii"; - nvmem-cells = <&onie_tlv_macaddr 1>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -/* SRDS #4 - mini PCIe slot near SOM */ -&cp0_pcie1 { - status = "okay"; - phys = <&cp0_comphy4 1>; - num-lanes = <1>; - reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; -}; - -/* SRDS #5 - mini PCIe slot far from SOM */ -&cp0_pcie2 { - status = "okay"; - phys = <&cp0_comphy5 2>; - num-lanes = <1>; - reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; -}; - -/* GE PHY RGMII */ -&cp0_eth2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_ge2_rgmii_pins>; - phy = <&phy0>; - phy-mode = "rgmii-id"; - nvmem-cells = <&onie_tlv_macaddr 2>; - nvmem-cell-names = "mac-address"; -}; - -/* micro SD card slot */ -&cp0_sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins &cp0_sdhci_cd_pins>; - bus-width = <4>; - cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - vqmmc-supply = <&v_3v3>; - vmmc-supply = <&v_3v3>; -}; - -&cp0_spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi1_pins>; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - #address-cells = <0x1>; - #size-cells = <0x1>; - spi-max-frequency = <10000000>; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp0_i2c0_pins: cp0-i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - - cp0_i2c1_pins: cp0-i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - - cp0_ge2_rgmii_pins: cp0-ge2-rgmii-pins { - marvell,pins = "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - - cp0_sdhci_cd_pins: cp0-sdhci-cd-pins { - marvell,pins = "mpp43"; - marvell,function = "sdio"; - }; - - cp0_sdhci_pins: cp0-sdhci-pins { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - - cp0_spi1_pins: cp0-spi1-pins { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - - cp0_dsa0_pins: cp0-dsa0-pins { - marvell,pins = "mpp27", "mpp29"; - marvell,function = "gpio"; - }; - - cp0_button_pin: cp0-button-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - cp0_expander0_pins: cp0-expander0-pins { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - }; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts deleted file mode 100644 index d214853f1b..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9131-DB board. - */ - -#include "cn9130.dtsi" -#include "puzzle-thermal.dtsi" - -#include -#include -#include - -/ { - model = "iEi Puzzle-M901"; - compatible = "iei,puzzle-m901", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - i2c0 = &cp1_i2c0; - i2c1 = &cp0_i2c0; - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - ethernet3 = &cp1_eth0; - ethernet4 = &cp1_eth1; - ethernet5 = &cp1_eth2; - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - gpio3 = &cp1_gpio1; - gpio4 = &cp1_gpio2; - led-boot = &led_power; - led-failsafe = &led_info; - led-running = &led_power; - led-upgrade = &led_info; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&cp0_uart0 { - status = "okay"; - - puzzle-mcu { - compatible = "iei,wt61p803-puzzle"; - #address-cells = <1>; - #size-cells = <1>; - current-speed = <115200>; - enable-beep; - status = "okay"; - - leds { - compatible = "iei,wt61p803-puzzle-leds"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - led@0 { - reg = <0>; - label = "white:network"; - active-low; - }; - - led@1 { - reg = <1>; - label = "green:cloud"; - active-low; - }; - - led_info: led@2 { - reg = <2>; - label = "orange:info"; - active-low; - }; - - led_power: led@3 { - reg = <3>; - function = LED_FUNCTION_POWER; - color = ; - active-low; - default-state = "on"; - }; - }; - - hwmon { - compatible = "iei,wt61p803-puzzle-hwmon"; - #address-cells = <1>; - #size-cells = <0>; - - chassis_fan_group0: fan-group@0 { - #cooling-cells = <2>; - reg = <0x00>; - cooling-levels = <0 159 195 211 223 241 255>; - }; - }; - }; -}; - -&ap_thermal_ic { - PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0); -}; - -&cp0_thermal_ic { - PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0); -}; - -/* on-board eMMC - U9 */ -&ap_sdhci0 { - pinctrl-names = "default"; - bus-width = <8>; - status = "okay"; - mmc-ddr-1_8v; - mmc-hs400-1_8v; -}; - -&cp0_crypto { - status = "okay"; -}; - -&cp0_xmdio { - status = "okay"; - cp0_nbaset_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <2>; - }; - cp0_nbaset_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - cp0_nbaset_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp0_eth0 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp0_comphy2 0>; - phy = <&cp0_nbaset_phy0>; -}; - -&cp0_eth1 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp0_comphy4 1>; - phy = <&cp0_nbaset_phy1>; -}; - -&cp0_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp0_comphy5 2>; - phy = <&cp0_nbaset_phy2>; -}; - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - wakeup-source; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp0_pcie0 { - status = "okay"; - num-lanes = <2>; - num-viewport = <8>; - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>; -}; - -/* U55 */ -&cp0_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; - reg = <0x700680 0x50>, /* control */ - <0x2000000 0x1000000>; /* CS0 */ - status = "okay"; - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <40000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "U-Boot"; - reg = <0x0 0x1f0000>; - }; - partition@1f0000 { - label = "U-Boot ENV Factory"; - reg = <0x1f0000 0x10000>; - }; - partition@200000 { - label = "Reserved"; - reg = <0x200000 0x1f0000>; - }; - partition@3f0000 { - label = "U-Boot ENV"; - reg = <0x3f0000 0x10000>; - }; - }; - }; -}; - -&cp0_rtc { - status = "disabled"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - cp0_i2c0_pins: cp0-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_i2c1_pins: cp0-i2c-pins-1 { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { - marvell,pins = "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - cp0_spi0_pins: cp0-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - }; -}; - -/* - * Instantiate the first connected CP115 - */ - -#define CP11X_NAME cp1 -#define CP11X_BASE f6000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f6600000 -#define CP11X_PCIE1_BASE f6620000 -#define CP11X_PCIE2_BASE f6640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp1_crypto { - status = "okay"; -}; - -&cp1_xmdio { - status = "okay"; - cp1_nbaset_phy0: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <2>; - }; - cp1_nbaset_phy1: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - cp1_nbaset_phy2: ethernet-phy@5 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* CON50 */ -&cp1_eth0 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy2 0>; - phy = <&cp1_nbaset_phy0>; -}; - -&cp1_eth1 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy4 1>; - phy = <&cp1_nbaset_phy1>; -}; - -&cp1_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy5 2>; - phy = <&cp1_nbaset_phy2>; -}; - -&cp1_sata0 { - status = "okay"; - sata-port@1 { - status = "okay"; - phys = <&cp1_comphy0 1>; - }; -}; - -&cp1_gpio1 { - status = "okay"; -}; - -&cp1_gpio2 { - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_i2c0_pins>; - clock-frequency = <100000>; -}; - -&cp1_rtc { - status = "disabled"; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - cp1_i2c0_pins: cp1-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp1_spi0_pins: cp1-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - cp1_sfp_pins: sfp-pins { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - }; -}; - -&cp1_thermal_ic { - PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0); -}; - -&cp1_usb3_1 { - status = "okay"; - phys = <&cp1_comphy3 1>; - phy-names = "usb"; -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts deleted file mode 100644 index 8c775e4a4f..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts +++ /dev/null @@ -1,580 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9132-DB board. - */ - -#include "cn9130.dtsi" -#include "puzzle-thermal.dtsi" - -#include -#include -#include - -/ { - model = "iEi Puzzle-M902"; - compatible = "iei,puzzle-m902", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - i2c0 = &cp1_i2c0; - i2c1 = &cp0_i2c0; - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - gpio3 = &cp1_gpio1; - gpio4 = &cp1_gpio2; - gpio5 = &cp2_gpio1; - gpio6 = &cp2_gpio2; - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - ethernet3 = &cp1_eth0; - ethernet4 = &cp1_eth1; - ethernet5 = &cp1_eth2; - ethernet6 = &cp2_eth0; - ethernet7 = &cp2_eth1; - ethernet8 = &cp2_eth2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - led-boot = &led_power; - led-failsafe = &led_info; - led-running = &led_power; - led-upgrade = &led_info; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>; - }; - }; - - cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy0: cp2_usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus0>; - }; - - cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy1: cp2_usb3_phy1 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus1>; - }; - - cp2_sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp2_sfpp0_i2c>; - los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&cp0_uart0 { - status = "okay"; - - puzzle-mcu { - compatible = "iei,wt61p803-puzzle"; - #address-cells = <1>; - #size-cells = <1>; - current-speed = <115200>; - enable-beep; - status = "okay"; - - leds { - compatible = "iei,wt61p803-puzzle-leds"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - led@0 { - reg = <0>; - label = "white:network"; - active-low; - }; - - led@1 { - reg = <1>; - label = "green:cloud"; - active-low; - }; - - led_info: led@2 { - reg = <2>; - label = "orange:info"; - active-low; - }; - - led_power: led@3 { - reg = <3>; - function = LED_FUNCTION_POWER; - color = ; - active-low; - default-state = "on"; - }; - }; - - hwmon { - compatible = "iei,wt61p803-puzzle-hwmon"; - #address-cells = <1>; - #size-cells = <0>; - - chassis_fan_group0: fan-group@0 { - #cooling-cells = <2>; - reg = <0x00>; - cooling-levels = <0 159 195 211 223 241 255>; - }; - }; - }; -}; - -&ap_thermal_ic { - PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0); -}; - -&cp0_thermal_ic { - PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0); -}; - - -/* on-board eMMC - U9 */ -&ap_sdhci0 { - pinctrl-names = "default"; - bus-width = <8>; - status = "okay"; - mmc-ddr-1_8v; - mmc-hs400-1_8v; -}; - -&cp0_crypto { - status = "okay"; -}; - -&cp0_xmdio { - status = "okay"; - cp0_nbaset_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <2>; - }; - cp0_nbaset_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - cp0_nbaset_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - phys = <&cp0_comphy2 0>; - phy = <&cp0_nbaset_phy0>; -}; - -&cp0_eth1 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp0_comphy4 1>; - phy = <&cp0_nbaset_phy1>; -}; - -&cp0_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp0_comphy1 2>; - phy = <&cp0_nbaset_phy2>; -}; - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - wakeup-source; - }; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; -}; - -/* SLM-1521-V2, CON6 */ -&cp0_sata0 { - status = "okay"; - sata-port@1 { - status = "okay"; - phys = <&cp0_comphy0 1>; - }; -}; - -&cp0_pcie2 { - status = "okay"; - num-lanes = <1>; - num-viewport = <8>; - phys = <&cp0_comphy5 2>; -}; - -/* U55 */ -&cp0_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; - reg = <0x700680 0x50>, /* control */ - <0x2000000 0x1000000>; /* CS0 */ - status = "okay"; - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <40000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "U-Boot"; - reg = <0x0 0x1f0000>; - }; - partition@1f0000 { - label = "U-Boot ENV Factory"; - reg = <0x1f0000 0x10000>; - }; - partition@200000 { - label = "Reserved"; - reg = <0x200000 0x1f0000>; - }; - partition@3f0000 { - label = "U-Boot ENV"; - reg = <0x3f0000 0x10000>; - }; - }; - }; -}; - -&cp0_rtc { - status = "disabled"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - cp0_i2c0_pins: cp0-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_i2c1_pins: cp0-i2c-pins-1 { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { - marvell,pins = "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - cp0_spi0_pins: cp0-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - }; -}; - -&cp0_usb3_1 { - status = "okay"; - phys = <&cp0_comphy3 1>; - phy-names = "usb"; -}; - -/* - * Instantiate the first connected CP115 - */ - -#define CP11X_NAME cp1 -#define CP11X_BASE f4000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f4600000 -#define CP11X_PCIE1_BASE f4620000 -#define CP11X_PCIE2_BASE f4640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp1_crypto { - status = "okay"; -}; - -&cp1_xmdio { - status = "okay"; - cp1_nbaset_phy0: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <2>; - }; - cp1_nbaset_phy1: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - cp1_nbaset_phy2: ethernet-phy@5 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* CON50 */ -&cp1_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - phys = <&cp1_comphy2 0>; - phy = <&cp1_nbaset_phy0>; -}; - -&cp1_eth1 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy4 1>; - phy = <&cp1_nbaset_phy1>; -}; - -&cp1_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy1 2>; - phy = <&cp1_nbaset_phy2>; -}; - -&cp1_gpio1 { - status = "okay"; -}; - -&cp1_gpio2 { - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_i2c0_pins>; - clock-frequency = <100000>; -}; - -&cp1_rtc { - status = "disabled"; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - cp1_i2c0_pins: cp1-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp1_spi0_pins: cp1-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - }; -}; - -&cp1_thermal_ic { - PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0); -}; - -/* - * Instantiate the second connected CP115 - */ - -#define CP11X_NAME cp2 -#define CP11X_BASE f6000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f6600000 -#define CP11X_PCIE1_BASE f6620000 -#define CP11X_PCIE2_BASE f6640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp2_crypto { - status = "okay"; -}; - -&cp2_ethernet { - status = "okay"; -}; - -&cp2_xmdio { - status = "okay"; - cp2_nbaset_phy0: ethernet-phy@6 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <2>; - }; - cp2_nbaset_phy1: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - cp2_nbaset_phy2: ethernet-phy@8 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - }; -}; - -/* SLM-1521-V2, CON9 */ -&cp2_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - phys = <&cp2_comphy2 0>; - phy = <&cp2_nbaset_phy0>; -}; - -&cp2_eth1 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp2_comphy4 1>; - phy = <&cp2_nbaset_phy1>; -}; - -&cp2_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp2_comphy1 2>; - phy = <&cp2_nbaset_phy2>; -}; - -&cp2_gpio1 { - status = "okay"; -}; - -&cp2_gpio2 { - status = "okay"; -}; - -&cp2_i2c0 { - clock-frequency = <100000>; - /* SLM-1521-V2 - U3 */ - i2c-mux@72 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - cp2_sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* U12 */ - cp2_module_expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - }; - }; -}; - -&cp2_rtc { - status = "disabled"; -}; - -&cp2_syscon0 { - cp2_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - cp2_i2c0_pins: cp2-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - }; -}; - -&cp2_thermal_ic { - PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0); -}; diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi deleted file mode 100644 index ea79ab224e..0000000000 --- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -#define PUZZLE_FAN_THERMAL(_cname, _fan) \ - polling-delay-passive = <500>; \ - polling-delay = <1000>; \ - \ - trips { \ - cpu-hot { \ - temperature = <75000>; \ - hysteresis = <5000>; \ - type = "hot"; \ - }; \ - _cname##_active_full: cpu-active-full { \ - temperature = <70000>; \ - hysteresis = <5000>; \ - type = "active"; \ - }; \ - _cname##_active_high: cpu-active-high { \ - temperature = <65000>; \ - hysteresis = <5000>; \ - type = "active"; \ - }; \ - _cname##_active_med: cpu-active-med { \ - temperature = <62500>; \ - hysteresis = <3000>; \ - type = "active"; \ - }; \ - _cname##_active_low: cpu-active-low { \ - temperature = <60000>; \ - hysteresis = <3000>; \ - type = "active"; \ - }; \ - _cname##_active_min: cpu-active-min { \ - temperature = <55000>; \ - hysteresis = <5000>; \ - type = "active"; \ - }; \ - _cname##_active_idle: cpu-active-idle { \ - temperature = <50000>; \ - hysteresis = <5000>; \ - type = "active"; \ - }; \ - }; \ - cooling-maps { \ - cpu-active-full { \ - trip = <&_cname##_active_full>; \ - cooling-device = <_fan THERMAL_NO_LIMIT \ - THERMAL_NO_LIMIT>; \ - }; \ - cpu-active-high { \ - trip = <&_cname##_active_high>; \ - cooling-device = <_fan 4 5>; \ - }; \ - cpu-active-med { \ - trip = <&_cname##_active_med>; \ - cooling-device = <_fan 3 4>; \ - }; \ - cpu-active-low { \ - trip = <&_cname##_active_low>; \ - cooling-device = <_fan 2 3>; \ - }; \ - cpu-active-min { \ - trip = <&_cname##_active_min>; \ - cooling-device = <_fan 1 2>; \ - }; \ - cpu-active-idle { \ - trip = <&_cname##_active_idle>; \ - cooling-device = <_fan 0 0>; \ - }; \ - } diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 9dfe61d590..ef8ae337a8 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -3,9 +3,7 @@ # Copyright (C) 2012-2016 OpenWrt.org # Copyright (C) 2016 LEDE-project.org -ifneq ($(KERNEL),6.1) DTS_DIR := $(DTS_DIR)/marvell -endif define Build/fortigate-header ( \ diff --git a/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch b/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch deleted file mode 100644 index 354d262015..0000000000 --- a/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 8eec6e740b564ec5e1da59ab7070b89aa23c9973 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Fri, 16 Jun 2023 12:41:30 +0100 -Subject: [PATCH] cpufreq: armada-8k: add ap807 support - -Add support for the Armada AP807 die to armada-8k. This uses a -different compatible for the CPU clock which needs to be added to -the cpufreq driver. - -This commit takes a different approach to the WindRiver patch -"cpufreq: armada: enable ap807-cpu-clk" in that rather than calling -of_find_compatible_node() for each compatible, we use a table of -IDs instead. - -Signed-off-by: Russell King (Oracle) -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/armada-8k-cpufreq.c | 16 +++++++++------- - 1 file changed, 9 insertions(+), 7 deletions(-) - ---- a/drivers/cpufreq/armada-8k-cpufreq.c -+++ b/drivers/cpufreq/armada-8k-cpufreq.c -@@ -21,6 +21,13 @@ - #include - #include - -+static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = { -+ { .compatible = "marvell,ap806-cpu-clock" }, -+ { .compatible = "marvell,ap807-cpu-clock" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match); -+ - /* - * Setup the opps list with the divider for the max frequency, that - * will be filled at runtime. -@@ -127,7 +134,8 @@ static int __init armada_8k_cpufreq_init - struct device_node *node; - struct cpumask cpus; - -- node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock"); -+ node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match, -+ NULL); - if (!node || !of_device_is_available(node)) { - of_node_put(node); - return -ENODEV; -@@ -204,12 +212,6 @@ static void __exit armada_8k_cpufreq_exi - } - module_exit(armada_8k_cpufreq_exit); - --static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = { -- { .compatible = "marvell,ap806-cpu-clock" }, -- { }, --}; --MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match); -- - MODULE_AUTHOR("Gregory Clement "); - MODULE_DESCRIPTION("Armada 8K cpufreq driver"); - MODULE_LICENSE("GPL"); diff --git a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch b/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch deleted file mode 100644 index 4936f6ad16..0000000000 --- a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch +++ /dev/null @@ -1,81 +0,0 @@ -Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout -Date: Tue, 2 Aug 2022 14:38:16 +0200 -Message-Id: <20220802123816.21817-1-pali@kernel.org> -X-Mailer: git-send-email 2.20.1 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit -Precedence: bulk -List-ID: -X-Mailing-List: linux-pci@vger.kernel.org - -Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions -document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251), -that PCIe IP does not support a strong-ordered model for inbound posted vs. -outbound completion. - -As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control -register must be set. It disables the ordering check in the core between -Completions and Posted requests received from the link. - -Marvell also suggests to do full memory barrier at the beginning of -aardvark summary interrupt handler before calling interrupt handlers of -endpoint drivers in order to minimize the risk for the race condition -documented in the Erratum between the DMA done status reading and the -completion of writing to the host memory. - -More details about this issue and suggested workarounds are in discussion: -https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u - -It was reported that enabling this workaround fixes instability issues and -"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm -QCA6335 chip under significant load which were caused by interrupt status -stuck in the outbound CMPLT queue traced back to this erratum. - -This workaround fixes also kernel panic triggered after some minutes of -usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip: - - Internal error: synchronous external abort: 96000210 [#1] SMP - Kernel panic - not syncing: Fatal exception in interrupt - -Signed-off-by: Thomas Petazzoni -Signed-off-by: Pali Rohár -Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") -Cc: stable@vger.kernel.org ---- - drivers/pci/controller/pci-aardvark.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -212,6 +212,8 @@ enum { - }; - - #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) -+#define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208) -+#define DIS_ORD_CHK BIT(30) - - /* PCIe core controller registers */ - #define CTRL_CORE_BASE_ADDR 0x18000 -@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad - PCIE_CORE_CTRL2_TD_ENABLE; - advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - -+ /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */ -+ reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG); -+ reg |= DIS_ORD_CHK; -+ advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG); -+ - /* Set lane X1 */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~LANE_CNT_MSK; -@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler - struct advk_pcie *pcie = arg; - u32 status; - -+ /* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */ -+ mb(); -+ - status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); - if (!(status & PCIE_IRQ_CORE_INT)) - return IRQ_NONE; diff --git a/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch b/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch deleted file mode 100644 index 3223861234..0000000000 --- a/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/drivers/power/reset/linkstation-poweroff.c -+++ b/drivers/power/reset/linkstation-poweroff.c -@@ -142,6 +142,12 @@ static void linkstation_poweroff(void) - } - - static const struct of_device_id ls_poweroff_of_match[] = { -+ { .compatible = "buffalo,ls220d", -+ .data = &linkstation_power_off_cfg, -+ }, -+ { .compatible = "buffalo,ls220de", -+ .data = &linkstation_power_off_cfg, -+ }, - { .compatible = "buffalo,ls421d", - .data = &linkstation_power_off_cfg, - }, diff --git a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index ec6cef800a..0000000000 --- a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,279 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella - -This patch has been modified to be mvebu specific. The original patch -did not pass the bootloader cmdline on if no append-rootblock stanza -was found, resulting in blank cmdline and failure to boot. - -Signed-off-by: Michael Gray ---- - arch/arm/Kconfig | 11 ++++ - arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++- - init/main.c | 16 +++++ - 3 files changed, 111 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const - return offset; - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop(void *fdt, const char *node_path, const char *property, - void *val_array, int size) - { -@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char - return offset; - return fdt_setprop(fdt, offset, property, val_array, size); - } -+#endif - - static int setprop_string(void *fdt, const char *node_path, - const char *property, const char *string) -@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con - return fdt_setprop_string(fdt, offset, property, string); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop_cell(void *fdt, const char *node_path, - const char *property, uint32_t val) - { -@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const - return offset; - return fdt_setprop_cell(fdt, offset, property, val); - } -+#endif - - static const void *getprop(const void *fdt, const char *node_path, - const char *property, int *len) -@@ -58,6 +64,7 @@ static const void *getprop(const void *f - return fdt_getprop(fdt, offset, property, len); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static uint32_t get_cell_size(const void *fdt) - { - int len; -@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#endif -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ const char *ptr, *end; -+ const char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if (!ptr) -+ goto no_append; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if (rootblock == NULL) -+ goto no_append; -+ -+ if (*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ -+ return dest; -+ -+no_append: -+ len = strlen(str); -+ if (len + 1 < COMMAND_LINE_SIZE) { -+ memcpy(dest, str, len); -+ dest += len; -+ } -+ -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - - setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static void hex_str(char *out, uint32_t value) - { - uint32_t digit; -@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t - } - *out = '\0'; - } -+#endif - - /* - * Convert and fold provided ATAGs into the provided FDT. -@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void * - struct tag *atag = atag_list; - /* In the case of 64 bits memory size, need to reserve 2 cells for - * address and size for each bank */ -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - __be32 mem_reg_property[2 * 2 * NR_BANKS]; -- int memcount = 0; -- int ret, memsize; -+ int memsize, memcount = 0; -+#endif -+ int ret; - - /* make sure we've got an aligned pointer */ - if ((u32)atag_list & 0x3) -@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -113,6 +113,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -996,6 +1000,18 @@ asmlinkage __visible void __init __no_sa - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", saved_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - /* parameters may set static keys */ - jump_label_init(); - parse_early_param(); diff --git a/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch b/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch deleted file mode 100644 index b75dcf596a..0000000000 --- a/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/mach-mvebu/Kconfig -+++ b/arch/arm/mach-mvebu/Kconfig -@@ -66,6 +66,7 @@ config MACH_ARMADA_38X - select HAVE_ARM_TWD if SMP - select MACH_MVEBU_V7 - select PINCTRL_ARMADA_38X -+ select ARCH_WANT_LIBATA_LEDS - help - Say 'Y' here if you want your kernel to support boards based - on the Marvell Armada 380/385 SoC with device tree. diff --git a/target/linux/mvebu/patches-6.1/302-add_powertables.patch b/target/linux/mvebu/patches-6.1/302-add_powertables.patch deleted file mode 100644 index d0c0dbeb0c..0000000000 --- a/target/linux/mvebu/patches-6.1/302-add_powertables.patch +++ /dev/null @@ -1,770 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -214,11 +214,19 @@ - &pcie1 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ }; - }; - - &pcie2 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ }; - }; - - &pinctrl { ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>; -+ CA = -+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; -+ CN = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>; -+ ETSI = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>; -+ FCC = -+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>; -+ CN = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts -@@ -157,6 +157,18 @@ - }; - }; - -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ - &sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -223,12 +223,100 @@ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; -+ -+ ETSI = -+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; -+ -+ ETSI = -+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch b/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch deleted file mode 100644 index 930c0f9494..0000000000 --- a/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp.dtsi -+++ b/arch/arm/boot/dts/armada-xp.dtsi -@@ -237,12 +237,10 @@ - }; - - &i2c0 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - &i2c1 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - diff --git a/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch deleted file mode 100644 index 31bd53b1f3..0000000000 --- a/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-rd.dts -+++ b/arch/arm/boot/dts/armada-388-rd.dts -@@ -103,6 +103,16 @@ - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0 0x400000>; -+ }; -+ -+ partition@1 { -+ label = "firmware"; -+ reg = <0x400000 0xc00000>; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch deleted file mode 100644 index aee033d21f..0000000000 --- a/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Tue, 13 Jan 2015 11:14:09 +0100 -Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions - -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/armada-385-db-ap.dts -+++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -218,19 +218,19 @@ - #size-cells = <1>; - - partition@0 { -- label = "U-Boot"; -+ label = "u-boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { -- label = "uImage"; -+ label = "kernel"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { -- label = "Root"; -+ label = "ubi"; - reg = <0x00c00000 0x3f400000>; - }; - }; diff --git a/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch deleted file mode 100644 index fc6d6239ca..0000000000 --- a/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -483,3 +483,7 @@ - }; - }; - }; -+ -+&coherencyfab { -+ broken-idle; -+}; diff --git a/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch b/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch deleted file mode 100644 index 389e03742e..0000000000 --- a/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -385,7 +385,7 @@ - - port@4 { - reg = <4>; -- label = "internet"; -+ label = "wan"; - }; - - port@5 { diff --git a/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch b/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch deleted file mode 100644 index 0ef15f2943..0000000000 --- a/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -14,6 +14,13 @@ - compatible = "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_power; -+ led-running = &led_power; -+ led-upgrade = &led_power; -+ }; -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -71,7 +78,7 @@ - pinctrl-0 = <&gpio_leds_pins>; - pinctrl-names = "default"; - -- power { -+ led_power: power { - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -26,6 +26,13 @@ - compatible = "linksys,mamba", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_power; -+ led-running = &led_power; -+ led-upgrade = &led_power; -+ }; -+ - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; -@@ -195,7 +202,7 @@ - pinctrl-0 = <&power_led_pin>; - pinctrl-names = "default"; - -- power { -+ led_power: power { - label = "mamba:white:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; diff --git a/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch b/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch deleted file mode 100644 index 84d49a004b..0000000000 --- a/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -116,7 +116,7 @@ - }; - - ð2 { -- status = "okay"; -+ status = "disabled"; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; -@@ -200,10 +200,10 @@ - label = "wan"; - }; - -- port@5 { -- reg = <5>; -+ port@6 { -+ reg = <6>; - label = "cpu"; -- ethernet = <ð2>; -+ ethernet = <ð0>; - - fixed-link { - speed = <1000>; diff --git a/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch b/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch deleted file mode 100644 index a5d3e63810..0000000000 --- a/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts -@@ -12,8 +12,8 @@ - - / { - model = "Linksys WRT3200ACM"; -- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", -- "marvell,armada380"; -+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385", -+ "marvell,armada385", "marvell,armada380"; - }; - - &expander0 { ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -22,9 +22,10 @@ - #include "armada-xp-mv78230.dtsi" - - / { -- model = "Linksys WRT1900AC"; -- compatible = "linksys,mamba", "marvell,armadaxp-mv78230", -- "marvell,armadaxp", "marvell,armada-370-xp"; -+ model = "Linksys WRT1900AC v1"; -+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba", -+ "marvell,armadaxp-mv78230", "marvell,armadaxp", -+ "marvell,armada-370-xp"; - - aliases { - led-boot = &led_power; ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -9,8 +9,9 @@ - #include "armada-385-linksys.dtsi" - - / { -- model = "Linksys WRT1900ACv2"; -- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", -+ model = "Linksys WRT1900AC v2"; -+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra", -+ "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - }; - ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -10,8 +10,8 @@ - - / { - model = "Linksys WRT1200AC"; -- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", -- "marvell,armada380"; -+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385", -+ "marvell,armada385", "marvell,armada380"; - }; - - &expander0 { ---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts -@@ -10,7 +10,8 @@ - - / { - model = "Linksys WRT1900ACS"; -- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", -+ compatible = "linksys,wrt1900acs", "linksys,shelby", -+ "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - }; - diff --git a/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch deleted file mode 100644 index f52417e83a..0000000000 --- a/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 10:15:45 +0000 -Subject: ARM: dts: armada388-clearfog: emmc on clearfog base - -Signed-off-by: Russell King ---- - .../arm/boot/dts/armada-388-clearfog-base.dts | 1 + - .../armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++++++++++++++++ - 2 files changed, 63 insertions(+) - create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi - ---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts -@@ -7,6 +7,7 @@ - - /dts-v1/; - #include "armada-388-clearfog.dtsi" -+#include "armada-38x-solidrun-microsom-emmc.dtsi" - - / { - model = "SolidRun Clearfog Base A1"; ---- /dev/null -+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi -@@ -0,0 +1,62 @@ -+/* -+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC -+ * -+ * Copyright (C) 2015 Russell King -+ * -+ * This board is in development; the contents of this file work with -+ * the A1 rev 2.0 of the board, which does not represent final -+ * production board. Things will change, don't expect this file to -+ * remain compatible info the future. -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/ { -+ soc { -+ internal-regs { -+ sdhci@d8000 { -+ bus-width = <4>; -+ no-1-8-v; -+ non-removable; -+ pinctrl-0 = <µsom_sdhci_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ wp-inverted; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch b/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch deleted file mode 100644 index 607f436297..0000000000 --- a/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-helios4.dts -+++ b/arch/arm/boot/dts/armada-388-helios4.dts -@@ -15,6 +15,13 @@ - model = "Helios4"; - compatible = "kobol,helios4", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; -+ -+ aliases { -+ led-boot = &led_status; -+ led-failsafe = &led_status; -+ led-running = &led_status; -+ led-upgrade = &led_status; -+ }; - - memory { - device_type = "memory"; -@@ -73,10 +80,9 @@ - pinctrl-names = "default"; - pinctrl-0 = <&helios_system_led_pins>; - -- status-led { -+ led_status: status-led { - label = "helios4:green:status"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; -- linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - diff --git a/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch b/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch deleted file mode 100644 index 7221e04de1..0000000000 --- a/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Tomasz Maciej Nowak -Date: Fri, 7 Jul 2023 19:06:05 +0200 -Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default - -Some boards could be placed in an enclosure, so enable LED18 by default, -since that'll be the only visible indicator that the board is operating. - -Signed-off-by: Tomasz Maciej Nowak ---- - arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts -+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts -@@ -25,6 +25,7 @@ - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; -+ default-state = "on"; - }; - }; - }; diff --git a/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch b/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch deleted file mode 100644 index c333df2784..0000000000 --- a/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001 -From: Tad -Date: Fri, 5 Feb 2021 22:32:11 -0500 -Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel - partition to 4MB - -Signed-off-by: Tad Davanzo ---- - arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -454,9 +454,9 @@ - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - -- partition@d00000 { -+ partition@e00000 { - label = "rootfs1"; -- reg = <0xd00000 0x2500000>; /* 37MB */ -+ reg = <0xe00000 0x2400000>; /* 36MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ -@@ -465,9 +465,9 @@ - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - -- partition@3500000 { -+ partition@3600000 { - label = "rootfs2"; -- reg = <0x3500000 0x2500000>; /* 37MB */ -+ reg = <0x3600000 0x2400000>; /* 36MB */ - }; - - /* diff --git a/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch deleted file mode 100644 index b5ed5ece36..0000000000 --- a/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/armada-370.dtsi -+++ b/arch/arm/boot/dts/armada-370.dtsi -@@ -254,7 +254,7 @@ - clocks = <&gateclk 23>; - clock-names = "cesa0"; - marvell,crypto-srams = <&crypto_sram>; -- marvell,crypto-sram-size = <0x7e0>; -+ marvell,crypto-sram-size = <0x800>; - }; - }; - -@@ -275,12 +275,17 @@ - * cpuidle workaround. - */ - idle-sram@0 { -+ status = "disabled"; - reg = <0x0 0x20>; - }; - }; - }; - }; - -+&coherencyfab { -+ broken-idle; -+}; -+ - /* - * Default UART pinctrl setting without RTS/CTS, can be overwritten on - * board level if a different configuration is used. diff --git a/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch b/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch deleted file mode 100644 index 280fc5957e..0000000000 --- a/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch +++ /dev/null @@ -1,134 +0,0 @@ ---- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts -+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts -@@ -31,6 +31,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ append-rootblock = "nullparameter="; /* override the bootloader args */ - }; - - memory@0 { -@@ -94,6 +95,8 @@ - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; -+ nvmem-cells = <&macaddr_vendor_0>; -+ nvmem-cell-names = "mac-address"; - }; - - sata@a0000 { -@@ -175,6 +178,24 @@ - gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - }; -+ -+ virtual_flash { -+ compatible = "mtd-concat"; -+ -+ devices = <&mtd_kernel &mtd_gap &mtd_gap2>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ compatible = "openwrt,uimage", "denx,uimage"; -+ label = "firmware"; -+ reg = <0x0 0x0>; -+ }; -+ }; -+ }; - }; - - &mdio { -@@ -265,48 +286,52 @@ - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - -- /* -- * Warning! -- * -- * Synology u-boot uses its compiled-in environment -- * and it seems Synology did not care to change u-boot -- * default configuration in order to allow saving a -- * modified environment at a sensible location. So, -- * if you do a 'saveenv' under u-boot, your modified -- * environment will be saved at 1MB after the start -- * of the flash, i.e. in the middle of the uImage. -- * For that reason, it is strongly advised not to -- * change the default environment, unless you know -- * what you are doing. -- */ -- partition@0 { /* u-boot */ -- label = "RedBoot"; -- reg = <0x00000000 0x000c0000>; /* 768KB */ -- }; -+ partitions { -+ compatible = "fixed-partitions"; - -- partition@c0000 { /* uImage */ -- label = "zImage"; -- reg = <0x000c0000 0x002d0000>; /* 2880KB */ -- }; -+ partition@0 { /* u-boot */ -+ label = "u-boot"; -+ reg = <0x00000000 0x000c0000>; /* 768KB */ -+ read-only; -+ }; - -- partition@390000 { /* uInitramfs */ -- label = "rd.gz"; -- reg = <0x00390000 0x00440000>; /* 4250KB */ -- }; -+ mtd_gap: partition@c0000 { /* gap */ -+ label = "gap"; -+ reg = <0x000c0000 0x00040000>; /* 256KB */ -+ }; - -- partition@7d0000 { /* MAC address and serial number */ -- label = "vendor"; -- reg = <0x007d0000 0x00010000>; /* 64KB */ -- }; -+ partition@100000 { /* u-boot-env */ -+ label = "u-boot-env"; -+ reg = <0x00100000 0x00010000>; /* 64KB */ -+ }; - -- partition@7e0000 { -- label = "RedBoot config"; -- reg = <0x007e0000 0x00010000>; /* 64KB */ -- }; -+ mtd_kernel: partition@110000 { -+ label = "kernel"; -+ reg = <0x00110000 0x006c0000>; /* 6912KB */ -+ }; - -- partition@7f0000 { -- label = "FIS directory"; -- reg = <0x007f0000 0x00010000>; /* 64KB */ -+ partition@7d0000 { /* MAC address and serial number */ -+ reg = <0x007d0000 0x00010000>; /* 64KB */ -+ label = "vendor"; -+ read-only; -+ -+ compatible = "nvmem-cells"; -+ -+ nvmem-layout { -+ compatible = "fixed-layout"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_vendor_0: macaddr@0 { -+ reg = <0x0 0x6>; -+ }; -+ }; -+ }; -+ -+ mtd_gap2: partition@7e0000 { -+ label = "gap2"; -+ reg = <0x007e0000 0x00020000>; /* 128KB */ -+ }; - }; - }; - }; diff --git a/target/linux/mvebu/patches-6.1/400-find_active_root.patch b/target/linux/mvebu/patches-6.1/400-find_active_root.patch deleted file mode 100644 index 90164adcd4..0000000000 --- a/target/linux/mvebu/patches-6.1/400-find_active_root.patch +++ /dev/null @@ -1,60 +0,0 @@ -The WRT1900AC among other Linksys routers uses a dual-firmware layout. -Dynamically rename the active partition to "ubi". - -Signed-off-by: Imre Kaloz - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static int mangled_rootblock; -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct - struct device_node *mtd_node; - struct device_node *ofpart_node; - const char *partname; -+ const char *owrtpart = "ubi"; - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct - parts[i].size = of_read_number(reg + a_cells, s_cells); - parts[i].of_node = pp; - -- partname = of_get_property(pp, "label", &len); -- if (!partname) -- partname = of_get_property(pp, "name", &len); -+ if (mangled_rootblock && (i == mangled_rootblock)) { -+ partname = owrtpart; -+ } else { -+ partname = of_get_property(pp, "label", &len); -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ } - parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi - return 0; - } - -+static int __init active_root(char *str) -+{ -+ get_option(&str, &mangled_rootblock); -+ -+ if (!mangled_rootblock) -+ return 1; -+ -+ return 1; -+} -+ -+__setup("mangled_rootblock=", active_root); -+ - static void __exit ofpart_parser_exit(void) - { - deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch deleted file mode 100644 index 14f93592fe..0000000000 --- a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch +++ /dev/null @@ -1,43 +0,0 @@ -From: Felix Fietkau -Subject: mvneta: tx queue workaround - -The hardware queue scheduling is apparently configured with fixed -priorities, which creates a nasty fairness issue where traffic from one -CPU can starve traffic from all other CPUs. - -Work around this issue by forcing all tx packets to go through one CPU, -until this issue is fixed properly. - -Ref: https://github.com/openwrt/openwrt/issues/5411 - -Signed-off-by: Felix Fietkau ---- ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de - } - } - -+#ifndef CONFIG_ARM64 -+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb, -+ struct net_device *sb_dev) -+{ -+ /* XXX: hardware queue scheduling is broken, -+ * use only one queue until it is fixed */ -+ return 0; -+} -+#endif -+ - static const struct net_device_ops mvneta_netdev_ops = { - .ndo_open = mvneta_open, - .ndo_stop = mvneta_stop, -@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet - .ndo_fix_features = mvneta_fix_features, - .ndo_get_stats64 = mvneta_get_stats64, - .ndo_eth_ioctl = mvneta_ioctl, -+#ifndef CONFIG_ARM64 -+ .ndo_select_queue = mvneta_select_queue, -+#endif - .ndo_bpf = mvneta_xdp, - .ndo_xdp_xmit = mvneta_xdp_xmit, - .ndo_setup_tc = mvneta_setup_tc, diff --git a/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch b/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch deleted file mode 100644 index 1c4194776a..0000000000 --- a/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Tobias Schramm -Subject: mvpp2: support fetching mac address from nvmem - -The mvpp2 driver did not query nvmem for hardware mac addresses. This -patch adds querying of mac addresses stored in nvmem cells as a further -fallback option before assigning a random address. -Purposely added separately to fwnode_get_mac_address() above to maintain -existing behaviour with builtin adapter mac address still taking -precedence. - -Signed-off-by: Tobias Schramm ---- ---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c -+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c -@@ -6134,6 +6134,12 @@ static void mvpp2_port_copy_mac_addr(str - } - } - -+ if (!of_get_mac_address(to_of_node(fwnode), hw_mac_addr)) { -+ *mac_from = "nvmem cell"; -+ eth_hw_addr_set(dev, hw_mac_addr); -+ return; -+ } -+ - *mac_from = "random"; - eth_hw_addr_random(dev); - } diff --git a/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch deleted file mode 100644 index 29f36be460..0000000000 --- a/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch +++ /dev/null @@ -1,40 +0,0 @@ -From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 3 Oct 2015 09:13:05 +0100 -Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states - -The cpuidle ->enter method expects the return value to be the sleep -state we entered. Returning negative numbers or other codes is not -permissible since coupled CPU idle was merged. - -At least some of the mvebu_v7_cpu_suspend() implementations return the -value from cpu_suspend(), which returns zero if the CPU vectors back -into the kernel via cpu_resume() (the success case), or the non-zero -return value of the suspend actor, or one (failure cases). - -We do not want to be returning the failure case value back to CPU idle -as that indicates that we successfully entered one of the deeper idle -states. Always return zero instead, indicating that we slept for the -shortest amount of time. - -Signed-off-by: Russell King ---- - drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/cpuidle/cpuidle-mvebu-v7.c -+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c -@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp - ret = mvebu_v7_cpu_suspend(deepidle); - cpu_pm_exit(); - -+ /* -+ * If we failed to enter the desired state, indicate that we -+ * slept lightly. -+ */ - if (ret) -- return ret; -+ return 0; - - return index; - } diff --git a/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch deleted file mode 100644 index d2995b375c..0000000000 --- a/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 9 Jul 2016 10:58:16 +0100 -Subject: pci: mvebu: time out reset on link up - -If the port reports that the link is up while we are resetting, there's -little point in waiting for the full duration. - -Signed-off-by: Russell King ---- - drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/pci/controller/pci-mvebu.c -+++ b/drivers/pci/controller/pci-mvebu.c -@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve - - if (port->reset_gpio) { - u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; -+ unsigned int i; - - of_property_read_u32(port->dn, "reset-delay-us", - &reset_udelay); -@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve - udelay(100); - - gpiod_set_value_cansleep(port->reset_gpio, 0); -- msleep(reset_udelay / 1000); -+ for (i = 0; i < reset_udelay; i += 1000) { -+ if (mvebu_pcie_link_up(port)) -+ break; -+ msleep(1); -+ } -+ -+ printk("%s: reset completed in %dus\n", port->name, i); - } - - return 0; -@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf - if (!child) - continue; - -- ret = mvebu_pcie_powerup(port); -- if (ret < 0) -- continue; -- - port->base = mvebu_pcie_map_registers(pdev, child, port); - if (IS_ERR(port->base)) { - dev_err(dev, "%s: cannot map registers\n", port->name); - port->base = NULL; -- mvebu_pcie_powerdown(port); -+ continue; -+ } -+ -+ ret = mvebu_pcie_powerup(port); -+ if (ret < 0) { -+ port->base = NULL; - continue; - } - diff --git a/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch deleted file mode 100644 index fc5c804582..0000000000 --- a/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch +++ /dev/null @@ -1,218 +0,0 @@ -From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:32 +0000 -Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803 - PUZZLE driver bindings - -Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED -drivers. A new vendor prefix is also added accordingly for -IEI Integration Corp. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../hwmon/iei,wt61p803-puzzle-hwmon.yaml | 53 ++++++++++++ - .../leds/iei,wt61p803-puzzle-leds.yaml | 39 +++++++++ - .../bindings/mfd/iei,wt61p803-puzzle.yaml | 82 +++++++++++++++++++ - .../devicetree/bindings/vendor-prefixes.yaml | 2 + - 4 files changed, 176 insertions(+) - create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml - create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml - create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml -@@ -0,0 +1,53 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details -+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml. -+ -+ The HWMON module is a sub-node of the MCU node in the Device Tree. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle-hwmon -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+patternProperties: -+ "^fan-group@[0-1]$": -+ type: object -+ properties: -+ reg: -+ minimum: 0 -+ maximum: 1 -+ description: -+ Fan group ID -+ -+ cooling-levels: -+ minItems: 1 -+ maxItems: 255 -+ description: -+ Cooling levels for the fans (PWM value mapping) -+ description: | -+ Properties for each fan group. -+ required: -+ - reg -+ -+required: -+ - compatible -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false ---- /dev/null -+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml -@@ -0,0 +1,39 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details -+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml. -+ -+ The LED module is a sub-node of the MCU node in the Device Tree. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle-leds -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+ led@0: -+ type: object -+ $ref: common.yaml -+ description: | -+ Properties for a single LED. -+ -+required: -+ - compatible -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml -@@ -0,0 +1,82 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards. -+ It's used for controlling system power states, fans, LEDs and temperature -+ sensors. -+ -+ For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the -+ binding documents under the respective subsystem directories. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle -+ -+ current-speed: -+ description: -+ Serial bus speed in bps -+ maxItems: 1 -+ -+ enable-beep: true -+ -+ hwmon: -+ $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml -+ -+ leds: -+ $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml -+ -+required: -+ - compatible -+ - current-speed -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ serial { -+ mcu { -+ compatible = "iei,wt61p803-puzzle"; -+ current-speed = <115200>; -+ enable-beep; -+ -+ leds { -+ compatible = "iei,wt61p803-puzzle-leds"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@0 { -+ reg = <0>; -+ function = LED_FUNCTION_POWER; -+ color = ; -+ }; -+ }; -+ -+ hwmon { -+ compatible = "iei,wt61p803-puzzle-hwmon"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ fan-group@0 { -+ #cooling-cells = <2>; -+ reg = <0x00>; -+ cooling-levels = <64 102 170 230 250>; -+ }; -+ -+ fan-group@1 { -+ #cooling-cells = <2>; -+ reg = <0x01>; -+ cooling-levels = <64 102 170 230 250>; -+ }; -+ }; -+ }; -+ }; ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -579,6 +579,8 @@ patternProperties: - description: IC Plus Corp. - "^idt,.*": - description: Integrated Device Technologies, Inc. -+ "^iei,.*": -+ description: IEI Integration Corp. - "^ifi,.*": - description: Ingenieurburo Fur Ic-Technologie (I/F/I) - "^ilitek,.*": diff --git a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch deleted file mode 100644 index 47d9e3a263..0000000000 --- a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:33 +0000 -Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU - -Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some -IEI Puzzle series devices. The microcontroller controls system power, -temperature sensors, fans and LEDs. - -This driver implements the core functionality for device communication -over the system serial (serdev bus). It handles MCU messages and the -internal MCU properties. Some properties can be managed over sysfs. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/mfd/Kconfig | 9 + - drivers/mfd/Makefile | 1 + - drivers/mfd/iei-wt61p803-puzzle.c | 908 ++++++++++++++++++++++++ - include/linux/mfd/iei-wt61p803-puzzle.h | 66 ++ - 4 files changed, 984 insertions(+) - create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c - create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -2222,6 +2222,15 @@ config SGI_MFD_IOC3 - If you have an SGI Origin, Octane, or a PCI IOC3 card, - then say Y. Otherwise say N. - -+config MFD_IEI_WT61P803_PUZZLE -+ tristate "IEI WT61P803 PUZZLE MCU driver" -+ depends on SERIAL_DEV_BUS -+ select MFD_CORE -+ help -+ IEI WT61P803 PUZZLE is a system power management microcontroller -+ used for fan control, temperature sensor reading, LED control -+ and system identification. -+ - config MFD_INTEL_M10_BMC - tristate "Intel MAX 10 Board Management Controller" - depends on SPI_MASTER ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -244,6 +244,7 @@ obj-$(CONFIG_MFD_RT4831) += rt4831.o - obj-$(CONFIG_MFD_RT5033) += rt5033.o - obj-$(CONFIG_MFD_RT5120) += rt5120.o - obj-$(CONFIG_MFD_SKY81452) += sky81452.o -+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o - - obj-$(CONFIG_INTEL_SOC_PMIC) += intel_soc_pmic_crc.o - obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o ---- /dev/null -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -0,0 +1,908 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU Driver -+ * System management microcontroller for fan control, temperature sensor reading, -+ * LED control and system identification on IEI Puzzle series ARM-based appliances. -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* start, payload and XOR checksum at end */ -+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH (1 + 20 + 1) -+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE 512 -+ -+#define IEI_WT61P803_PUZZLE_MAC_LENGTH 17 -+#define IEI_WT61P803_PUZZLE_SN_LENGTH 36 -+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH 6 -+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH 16 -+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH 8 -+#define IEI_WT61P803_PUZZLE_NB_MAC 8 -+ -+/* Use HZ as a timeout value throughout the driver */ -+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ -+ -+enum iei_wt61p803_puzzle_attribute_type { -+ IEI_WT61P803_PUZZLE_VERSION, -+ IEI_WT61P803_PUZZLE_BUILD_INFO, -+ IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, -+ IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, -+ IEI_WT61P803_PUZZLE_SERIAL_NUMBER, -+ IEI_WT61P803_PUZZLE_MAC_ADDRESS, -+ IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, -+ IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, -+ IEI_WT61P803_PUZZLE_POWER_STATUS, -+}; -+ -+struct iei_wt61p803_puzzle_device_attribute { -+ struct device_attribute dev_attr; -+ enum iei_wt61p803_puzzle_attribute_type type; -+ u8 index; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state -+ * @ac_recovery_status_flag: AC Recovery Status Flag -+ * @power_loss_recovery: System recovery after power loss -+ * @power_status: System Power-on Method -+ */ -+struct iei_wt61p803_puzzle_mcu_status { -+ u8 ac_recovery_status_flag; -+ u8 power_loss_recovery; -+ u8 power_status; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_reply - MCU reply -+ * @size: Size of the MCU reply -+ * @data: Full MCU reply buffer -+ * @state: Current state of the packet -+ * @received: Was the response fullfilled -+ */ -+struct iei_wt61p803_puzzle_reply { -+ size_t size; -+ unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE]; -+ struct completion received; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status -+ * @version: Primary firmware version -+ * @build_info: Build date and time -+ * @bootloader_mode: Status of the MCU operation -+ * @protocol_version: MCU communication protocol version -+ * @serial_number: Device factory serial number -+ * @mac_address: Device factory MAC addresses -+ * -+ * Last element of arrays is reserved for '\0'. -+ */ -+struct iei_wt61p803_puzzle_mcu_version { -+ char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1]; -+ char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1]; -+ bool bootloader_mode; -+ char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1]; -+ char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1]; -+ char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1]; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver -+ * @serdev: Pointer to underlying serdev device -+ * @dev: Pointer to underlying dev device -+ * @reply_lock: Reply mutex lock -+ * @reply: Pointer to the iei_wt61p803_puzzle_reply struct -+ * @version: MCU version related data -+ * @status: MCU status related data -+ * @response_buffer Command response buffer allocation -+ * @lock General member mutex lock -+ */ -+struct iei_wt61p803_puzzle { -+ struct serdev_device *serdev; -+ struct device *dev; -+ struct mutex reply_lock; /* lock to prevent multiple firmware calls */ -+ struct iei_wt61p803_puzzle_reply *reply; -+ struct iei_wt61p803_puzzle_mcu_version version; -+ struct iei_wt61p803_puzzle_mcu_status status; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ struct mutex lock; /* lock to protect response buffer */ -+}; -+ -+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len) -+{ -+ unsigned char checksum = 0; -+ size_t i; -+ -+ for (i = 0; i < len; i++) -+ checksum ^= buf[i]; -+ return checksum; -+} -+ -+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu, -+ const unsigned char *raw_resp_data, size_t size) -+{ -+ unsigned char checksum; -+ -+ /* Check the incoming frame header */ -+ if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START || -+ raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER || -+ (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM && -+ raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) { -+ if (mcu->reply->size + size >= sizeof(mcu->reply->data)) -+ return -EIO; -+ -+ /* Append the frame to existing data */ -+ memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size); -+ mcu->reply->size += size; -+ } else { -+ if (size >= sizeof(mcu->reply->data)) -+ return -EIO; -+ -+ /* Start processing a new frame */ -+ memcpy(mcu->reply->data, raw_resp_data, size); -+ mcu->reply->size = size; -+ } -+ -+ checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1); -+ if (checksum != mcu->reply->data[mcu->reply->size - 1]) { -+ /* The checksum isn't matched yet, wait for new frames */ -+ return size; -+ } -+ -+ /* Received all the data */ -+ complete(&mcu->reply->received); -+ -+ return size; -+} -+ -+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev, -+ const unsigned char *data, size_t size) -+{ -+ struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev); -+ int ret; -+ -+ ret = iei_wt61p803_puzzle_process_resp(mcu, data, size); -+ /* Return the number of processed bytes if function returns error, -+ * discard the remaining incoming data, since the frame this data -+ * belongs to is broken anyway -+ */ -+ if (ret < 0) -+ return size; -+ -+ return ret; -+} -+ -+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = { -+ .receive_buf = iei_wt61p803_puzzle_recv_buf, -+ .write_wakeup = serdev_device_write_wakeup, -+}; -+ -+/** -+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd -+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct -+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor)) -+ * @size: Size of the cmd char array -+ * @reply_data: Pointer to the reply/response data array (should be allocated) -+ * @reply_size: Pointer to size_t (size of reply_data) -+ * @retry_count: Number of times to retry sending the command to the MCU -+ */ -+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, -+ size_t *reply_size, int retry_count) -+{ -+ struct device *dev = &mcu->serdev->dev; -+ int ret, i; -+ -+ for (i = 0; i < retry_count; i++) { -+ ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size, -+ reply_data, reply_size); -+ if (ret != -ETIMEDOUT) -+ return ret; -+ } -+ -+ dev_err(dev, "Command response timed out. Retries: %d\n", retry_count); -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog); -+ -+/** -+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU -+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct -+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor)) -+ * @size: Size of the cmd char array -+ * @reply_data: Pointer to the reply/response data array (should be allocated) -+ * -+ * Sends a structured command to the MCU. -+ */ -+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, -+ size_t *reply_size) -+{ -+ struct device *dev = &mcu->serdev->dev; -+ int ret; -+ -+ if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH) -+ return -EINVAL; -+ -+ mutex_lock(&mcu->reply_lock); -+ -+ cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1); -+ -+ /* Initialize reply struct */ -+ reinit_completion(&mcu->reply->received); -+ mcu->reply->size = 0; -+ usleep_range(2000, 10000); -+ serdev_device_write_flush(mcu->serdev); -+ ret = serdev_device_write_buf(mcu->serdev, cmd, size); -+ if (ret < 0) -+ goto exit; -+ -+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ ret = wait_for_completion_timeout(&mcu->reply->received, -+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ if (ret == 0) { -+ dev_err(dev, "Command reply receive timeout\n"); -+ ret = -ETIMEDOUT; -+ goto exit; -+ } -+ -+ *reply_size = mcu->reply->size; -+ /* Copy the received data, as it will not be available after a new frame is received */ -+ memcpy(reply_data, mcu->reply->data, mcu->reply->size); -+ ret = 0; -+exit: -+ mutex_unlock(&mcu->reply_lock); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command); -+ -+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char buzzer_cmd[4] = {}; -+ size_t reply_size; -+ int ret; -+ -+ buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE; -+ buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */ -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto exit; -+ } -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char version_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION, -+ }; -+ unsigned char build_info_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD, -+ }; -+ unsigned char bootloader_mode_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE, -+ }; -+ unsigned char protocol_version_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION, -+ }; -+ unsigned char *rb = mcu->response_buffer; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd), -+ rb, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 7) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd, -+ sizeof(build_info_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 15) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c", -+ rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11], -+ rb[12], rb[13]); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd, -+ sizeof(bootloader_mode_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 4) { -+ ret = -EIO; -+ goto err; -+ } -+ if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS) -+ mcu->version.bootloader_mode = false; -+ else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER) -+ mcu->version.bootloader_mode = true; -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd, -+ sizeof(protocol_version_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 9) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c", -+ rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char mcu_status_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS, -+ }; -+ unsigned char *resp_buf = mcu->response_buffer; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ if (reply_size < 20) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ /* Response format: -+ * (IDX RESPONSE) -+ * 0 @ -+ * 1 O -+ * 2 S -+ * 3 S -+ * ... -+ * 5 AC Recovery Status Flag -+ * ... -+ * 10 Power Loss Recovery -+ * ... -+ * 19 Power Status (system power on method) -+ * 20 XOR checksum -+ */ -+ if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS && -+ resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) { -+ mcu->status.ac_recovery_status_flag = resp_buf[5]; -+ mcu->status.power_loss_recovery = resp_buf[10]; -+ mcu->status.power_status = resp_buf[19]; -+ } -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char serial_number_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ, -+ 0x00, /* EEPROM read address */ -+ 0x24, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd, -+ sizeof(serial_number_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ -+ if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) { -+ ret = -EIO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.serial_number, "%.*s", -+ IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu, -+ unsigned char serial_number[36]) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char serial_number_header[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE, -+ 0x00, /* EEPROM write address */ -+ 0xC, /* Data length */ -+ }; -+ unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */ -+ int ret, sn_counter; -+ size_t reply_size; -+ -+ /* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */ -+ mutex_lock(&mcu->lock); -+ for (sn_counter = 0; sn_counter < 3; sn_counter++) { -+ serial_number_header[2] = 0x0 + 0xC * sn_counter; -+ -+ memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header)); -+ memcpy(serial_number_cmd + sizeof(serial_number_header), -+ serial_number + 0xC * sn_counter, 0xC); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd, -+ sizeof(serial_number_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto err; -+ } -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto err; -+ } -+ } -+ -+ sprintf(mcu->version.serial_number, "%.*s", -+ IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char mac_address_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ, -+ 0x00, /* EEPROM read address */ -+ 0x11, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ mac_address_cmd[2] = 0x24 + 0x11 * index; -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd, -+ sizeof(mac_address_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ -+ if (reply_size < 22) { -+ ret = -EIO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.mac_address[index], "%.*s", -+ IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int -+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu, -+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH], -+ int mac_address_idx) -+{ -+ unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1]; -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char mac_address_header[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE, -+ 0x00, /* EEPROM write address */ -+ 0x11, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC) -+ return -EINVAL; -+ -+ mac_address_header[2] = 0x24 + 0x11 * mac_address_idx; -+ -+ /* Concat mac_address_header, mac_address to mac_address_cmd */ -+ memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header)); -+ memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address, -+ IEI_WT61P803_PUZZLE_MAC_LENGTH); -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd, -+ sizeof(mac_address_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto err; -+ } -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.mac_address[mac_address_idx], "%.*s", -+ IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu, -+ int power_loss_recovery_action) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char power_loss_recovery_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4) -+ return -EINVAL; -+ -+ power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER; -+ power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS; -+ power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action]; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd, -+ sizeof(power_loss_recovery_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ mcu->status.power_loss_recovery = power_loss_recovery_action; -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+#define to_puzzle_dev_attr(_attr) \ -+ container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr) -+ -+static ssize_t show_output(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr); -+ int ret; -+ -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_VERSION: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version); -+ case IEI_WT61P803_PUZZLE_BUILD_INFO: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info); -+ case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE: -+ return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode); -+ case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version); -+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER: -+ ret = iei_wt61p803_puzzle_get_serial_number(mcu); -+ if (!ret) -+ ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number); -+ else -+ ret = 0; -+ return ret; -+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS: -+ ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index); -+ if (!ret) -+ ret = scnprintf(buf, PAGE_SIZE, "%s\n", -+ mcu->version.mac_address[pattr->index]); -+ else -+ ret = 0; -+ return ret; -+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS: -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ case IEI_WT61P803_PUZZLE_POWER_STATUS: -+ ret = iei_wt61p803_puzzle_get_mcu_status(mcu); -+ if (ret) -+ return ret; -+ -+ mutex_lock(&mcu->lock); -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", -+ mcu->status.ac_recovery_status_flag); -+ break; -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery); -+ break; -+ case IEI_WT61P803_PUZZLE_POWER_STATUS: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status); -+ break; -+ default: -+ ret = 0; -+ break; -+ } -+ mutex_unlock(&mcu->lock); -+ return ret; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static ssize_t store_output(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH]; -+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH]; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr); -+ int power_loss_recovery_action = 0; -+ int ret; -+ -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER: -+ if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1)) -+ return -EINVAL; -+ memcpy(serial_number, buf, sizeof(serial_number)); -+ ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number); -+ if (ret) -+ return ret; -+ return len; -+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS: -+ if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1)) -+ return -EINVAL; -+ -+ memcpy(mac_address, buf, sizeof(mac_address)); -+ -+ if (strlen(attr->attr.name) != 13) -+ return -EIO; -+ -+ ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index); -+ if (ret) -+ return ret; -+ return len; -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ ret = kstrtoint(buf, 10, &power_loss_recovery_action); -+ if (ret) -+ return ret; -+ ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu, -+ power_loss_recovery_action); -+ if (ret) -+ return ret; -+ return len; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \ -+ struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \ -+ { .dev_attr = __ATTR(_name, _mode, _show, _store), \ -+ .type = _type, \ -+ .index = _index } -+ -+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \ -+ IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id) -+ -+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \ -+ IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id) -+ -+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7); -+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0); -+ -+static struct attribute *iei_wt61p803_puzzle_attrs[] = { -+ &dev_attr_version.dev_attr.attr, -+ &dev_attr_build_info.dev_attr.attr, -+ &dev_attr_bootloader_mode.dev_attr.attr, -+ &dev_attr_protocol_version.dev_attr.attr, -+ &dev_attr_serial_number.dev_attr.attr, -+ &dev_attr_mac_address_0.dev_attr.attr, -+ &dev_attr_mac_address_1.dev_attr.attr, -+ &dev_attr_mac_address_2.dev_attr.attr, -+ &dev_attr_mac_address_3.dev_attr.attr, -+ &dev_attr_mac_address_4.dev_attr.attr, -+ &dev_attr_mac_address_5.dev_attr.attr, -+ &dev_attr_mac_address_6.dev_attr.attr, -+ &dev_attr_mac_address_7.dev_attr.attr, -+ &dev_attr_ac_recovery_status.dev_attr.attr, -+ &dev_attr_power_loss_recovery.dev_attr.attr, -+ &dev_attr_power_status.dev_attr.attr, -+ NULL -+}; -+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle); -+ -+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev, -+ struct iei_wt61p803_puzzle *mcu) -+{ -+ int ret; -+ -+ ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups); -+ if (ret) -+ mfd_remove_devices(mcu->dev); -+ -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev, -+ struct iei_wt61p803_puzzle *mcu) -+{ -+ /* Remove sysfs groups */ -+ sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups); -+ mfd_remove_devices(mcu->dev); -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev) -+{ -+ struct device *dev = &serdev->dev; -+ struct iei_wt61p803_puzzle *mcu; -+ u32 baud; -+ int ret; -+ -+ /* Read the baud rate from 'current-speed', because the MCU supports different rates */ -+ if (device_property_read_u32(dev, "current-speed", &baud)) { -+ dev_err(dev, -+ "'current-speed' is not specified in device node\n"); -+ return -EINVAL; -+ } -+ dev_dbg(dev, "Driver baud rate: %d\n", baud); -+ -+ /* Allocate the memory */ -+ mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL); -+ if (!mcu) -+ return -ENOMEM; -+ -+ mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL); -+ if (!mcu->reply) -+ return -ENOMEM; -+ -+ /* Initialize device struct data */ -+ mcu->serdev = serdev; -+ mcu->dev = dev; -+ init_completion(&mcu->reply->received); -+ mutex_init(&mcu->reply_lock); -+ mutex_init(&mcu->lock); -+ -+ /* Setup UART interface */ -+ serdev_device_set_drvdata(serdev, mcu); -+ serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops); -+ ret = devm_serdev_device_open(dev, serdev); -+ if (ret) -+ return ret; -+ serdev_device_set_baudrate(serdev, baud); -+ serdev_device_set_flow_control(serdev, false); -+ ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE); -+ if (ret) { -+ dev_err(dev, "Failed to set parity\n"); -+ return ret; -+ } -+ -+ ret = iei_wt61p803_puzzle_get_version(mcu); -+ if (ret) -+ return ret; -+ -+ dev_dbg(dev, "MCU version: %s\n", mcu->version.version); -+ dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info); -+ dev_dbg(dev, "MCU in bootloader mode: %s\n", -+ mcu->version.bootloader_mode ? "true" : "false"); -+ dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version); -+ -+ if (device_property_read_bool(dev, "enable-beep")) { -+ ret = iei_wt61p803_puzzle_buzzer(mcu, false); -+ if (ret) -+ return ret; -+ } -+ -+ ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu); -+ if (ret) -+ return ret; -+ -+ return devm_of_platform_populate(dev); -+} -+ -+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev) -+{ -+ struct device *dev = &serdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ -+ iei_wt61p803_puzzle_sysfs_remove(dev, mcu); -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = { -+ { .compatible = "iei,wt61p803-puzzle" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids); -+ -+static struct serdev_device_driver iei_wt61p803_puzzle_drv = { -+ .probe = iei_wt61p803_puzzle_probe, -+ .remove = iei_wt61p803_puzzle_remove, -+ .driver = { -+ .name = "iei-wt61p803-puzzle", -+ .of_match_table = iei_wt61p803_puzzle_dt_ids, -+ }, -+}; -+ -+module_serdev_device_driver(iei_wt61p803_puzzle_drv); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver"); ---- /dev/null -+++ b/include/linux/mfd/iei-wt61p803-puzzle.h -@@ -0,0 +1,66 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* IEI WT61P803 PUZZLE MCU Driver -+ * System management microcontroller for fan control, temperature sensor reading, -+ * LED control and system identification on IEI Puzzle series ARM-based appliances. -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_ -+#define _MFD_IEI_WT61P803_PUZZLE_H_ -+ -+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512 -+ -+/* Command magic numbers */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START 0x40 /* @ */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER 0x25 /* % */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM 0xF7 -+ -+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK 0x30 /* 0 */ -+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK 0x70 -+ -+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ 0xA1 -+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE 0xA0 -+ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION 0x56 /* V */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD 0x42 /* B */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE 0x4D /* M */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER 0x30 -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS 0x31 -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION 0x50 /* P */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE 0x43 /* C */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER 0x4F /* O */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS 0x53 /* S */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */ -+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */ -+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FAN 0x46 /* F */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ 0x5A /* Z */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE 0x57 /* W */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE 0x30 -+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */ -+ -+struct iei_wt61p803_puzzle_mcu_version; -+struct iei_wt61p803_puzzle_reply; -+struct iei_wt61p803_puzzle; -+ -+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, size_t *reply_size, -+ int retry_count); -+ -+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, size_t *reply_size); -+ -+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */ diff --git a/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch b/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch deleted file mode 100644 index a11b387d92..0000000000 --- a/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch +++ /dev/null @@ -1,501 +0,0 @@ -From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:34 +0000 -Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver - -Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed -control via PWM, reading fan speed and reading on-board temperature -sensors. - -The driver registers a HWMON device and a simple thermal cooling device to -enable in-kernel fan management. - -This driver depends on the IEI WT61P803 PUZZLE MFD driver. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Acked-by: Guenter Roeck -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/hwmon/Kconfig | 8 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++ - 3 files changed, 454 insertions(+) - create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c - ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV - This driver can also be built as a module. If so, the module - will be called ibmpowernv. - -+config SENSORS_IEI_WT61P803_PUZZLE_HWMON -+ tristate "IEI WT61P803 PUZZLE MFD HWMON Driver" -+ depends on MFD_IEI_WT61P803_PUZZLE -+ help -+ The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed -+ and writing fan PWM values. It also supports reading on-board -+ temperature sensors. -+ - config SENSORS_IIO_HWMON - tristate "Hwmon driver that uses channels specified via iio maps" - depends on IIO ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130 - obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o - obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o - obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o -+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o - obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o - obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o - obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o ---- /dev/null -+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c -@@ -0,0 +1,445 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU HWMON Driver -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM 2 -+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL 255 -+ -+/** -+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance -+ * @mcu_hwmon: Parent driver struct pointer -+ * @tcdev: Thermal cooling device pointer -+ * @name: Thermal cooling device name -+ * @pwm_channel: Controlled PWM channel (0 or 1) -+ * @cooling_levels: Thermal cooling device cooling levels (DT) -+ * @cur_level: Current cooling level -+ * @num_levels: Number of cooling levels -+ */ -+struct iei_wt61p803_puzzle_thermal_cooling_device { -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon; -+ struct thermal_cooling_device *tcdev; -+ char name[THERMAL_NAME_LENGTH]; -+ int pwm_channel; -+ u32 *cooling_levels; -+ int cur_level; -+ u8 num_levels; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver -+ * @mcu: MCU struct pointer -+ * @response_buffer Global MCU response buffer -+ * @thermal_cooling_dev_present: Per-channel thermal cooling device control indicator -+ * @cdev: Per-channel thermal cooling device private structure -+ */ -+struct iei_wt61p803_puzzle_hwmon { -+ struct iei_wt61p803_puzzle *mcu; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM]; -+ struct iei_wt61p803_puzzle_thermal_cooling_device -+ *cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM]; -+ struct mutex lock; /* mutex to protect response_buffer array */ -+}; -+ -+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000) -+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char temp_sensor_ntc_cmd[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START, -+ IEI_WT61P803_PUZZLE_CMD_TEMP, -+ IEI_WT61P803_PUZZLE_CMD_TEMP_ALL, -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd, -+ sizeof(temp_sensor_ntc_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 7) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ /* Check the number of NTC values */ -+ if (resp_buf[3] != '2') { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ *value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]); -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60) -+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char fan_speed_cmd[4] = {}; -+ size_t reply_size; -+ int ret; -+ -+ fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel); -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd, -+ sizeof(fan_speed_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 7) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ *value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]); -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long pwm_set_val) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char pwm_set_cmd[6] = {}; -+ size_t reply_size; -+ int ret; -+ -+ pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE; -+ pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel); -+ pwm_set_cmd[4] = pwm_set_val; -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd, -+ sizeof(pwm_set_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EIO; -+ goto exit; -+ } -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char pwm_get_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ; -+ pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd, -+ sizeof(pwm_get_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ return ret; -+ -+ if (reply_size != 5) -+ return -EIO; -+ -+ if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ) -+ return -EIO; -+ -+ *value = resp_buf[3]; -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent); -+ -+ switch (type) { -+ case hwmon_pwm: -+ return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val); -+ case hwmon_fan: -+ return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val); -+ case hwmon_temp: -+ return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val); -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long val) -+{ -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent); -+ -+ return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val); -+} -+ -+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data; -+ -+ switch (type) { -+ case hwmon_pwm: -+ if (mcu_hwmon->thermal_cooling_dev_present[channel]) -+ return 0444; -+ if (attr == hwmon_pwm_input) -+ return 0644; -+ break; -+ case hwmon_fan: -+ if (attr == hwmon_fan_input) -+ return 0444; -+ break; -+ case hwmon_temp: -+ if (attr == hwmon_temp_input) -+ return 0444; -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = { -+ .is_visible = iei_wt61p803_puzzle_is_visible, -+ .read = iei_wt61p803_puzzle_read, -+ .write = iei_wt61p803_puzzle_write, -+}; -+ -+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = { -+ HWMON_CHANNEL_INFO(pwm, -+ HWMON_PWM_INPUT, -+ HWMON_PWM_INPUT), -+ HWMON_CHANNEL_INFO(fan, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT), -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT, -+ HWMON_T_INPUT), -+ NULL -+}; -+ -+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = { -+ .ops = &iei_wt61p803_puzzle_hwmon_ops, -+ .info = iei_wt61p803_puzzle_info, -+}; -+ -+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev, -+ unsigned long *state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ *state = cdev->num_levels - 1; -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev, -+ unsigned long *state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ if (cdev->cur_level < 0) -+ return -EAGAIN; -+ -+ *state = cdev->cur_level; -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev, -+ unsigned long state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ u8 pwm_level; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ if (state >= cdev->num_levels) -+ return -EINVAL; -+ -+ if (state == cdev->cur_level) -+ return 0; -+ -+ cdev->cur_level = state; -+ pwm_level = cdev->cooling_levels[state]; -+ -+ return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level); -+} -+ -+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = { -+ .get_max_state = iei_wt61p803_puzzle_get_max_state, -+ .get_cur_state = iei_wt61p803_puzzle_get_cur_state, -+ .set_cur_state = iei_wt61p803_puzzle_set_cur_state, -+}; -+ -+static int -+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev, -+ struct fwnode_handle *child, -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev; -+ u32 pwm_channel; -+ u8 num_levels; -+ int i, ret; -+ -+ ret = fwnode_property_read_u32(child, "reg", &pwm_channel); -+ if (ret) -+ return ret; -+ -+ mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true; -+ -+ num_levels = fwnode_property_count_u32(child, "cooling-levels"); -+ if (!num_levels) -+ return -EINVAL; -+ -+ cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); -+ if (!cdev) -+ return -ENOMEM; -+ -+ cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL); -+ if (!cdev->cooling_levels) -+ return -ENOMEM; -+ -+ ret = fwnode_property_read_u32_array(child, "cooling-levels", -+ cdev->cooling_levels, -+ num_levels); -+ if (ret) { -+ dev_err(dev, "Couldn't read property 'cooling-levels'\n"); -+ return ret; -+ } -+ -+ for (i = 0; i < num_levels; i++) { -+ if (cdev->cooling_levels[i] > -+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) { -+ dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i, -+ cdev->cooling_levels[i], -+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL); -+ return -EINVAL; -+ } -+ } -+ -+ cdev->mcu_hwmon = mcu_hwmon; -+ cdev->pwm_channel = pwm_channel; -+ cdev->num_levels = num_levels; -+ cdev->cur_level = -1; -+ mcu_hwmon->cdev[pwm_channel] = cdev; -+ -+ snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel); -+ cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name, -+ cdev, &iei_wt61p803_puzzle_cooling_ops); -+ if (IS_ERR(cdev->tcdev)) -+ return PTR_ERR(cdev->tcdev); -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon; -+ struct fwnode_handle *child; -+ struct device *hwmon_dev; -+ int ret; -+ -+ mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL); -+ if (!mcu_hwmon) -+ return -ENOMEM; -+ -+ mcu_hwmon->mcu = mcu; -+ platform_set_drvdata(pdev, mcu_hwmon); -+ mutex_init(&mcu_hwmon->lock); -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle", -+ mcu_hwmon, -+ &iei_wt61p803_puzzle_chip_info, -+ NULL); -+ if (IS_ERR(hwmon_dev)) -+ return PTR_ERR(hwmon_dev); -+ -+ /* Control fans via PWM lines via Linux Kernel */ -+ if (IS_ENABLED(CONFIG_THERMAL)) { -+ device_for_each_child_node(dev, child) { -+ ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon); -+ if (ret) { -+ dev_err(dev, "Enabling the PWM fan failed\n"); -+ fwnode_handle_put(child); -+ return ret; -+ } -+ } -+ } -+ return 0; -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = { -+ { .compatible = "iei,wt61p803-puzzle-hwmon" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table); -+ -+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = { -+ .driver = { -+ .name = "iei-wt61p803-puzzle-hwmon", -+ .of_match_table = iei_wt61p803_puzzle_hwmon_id_table, -+ }, -+ .probe = iei_wt61p803_puzzle_hwmon_probe, -+}; -+ -+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver); -+ -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch deleted file mode 100644 index 1abb1b9416..0000000000 --- a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch +++ /dev/null @@ -1,207 +0,0 @@ -From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:35 +0000 -Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver - -Add support for the IEI WT61P803 PUZZLE LED driver. -Currently only the front panel power LED is supported, -since it is the only LED on this board wired through the -MCU. - -The LED is wired directly to the on-board MCU controller -and is toggled using an MCU command. - -Support for more LEDs is going to be added in case more -boards implement this microcontroller, as LEDs use many -different GPIOs. - -This driver depends on the IEI WT61P803 PUZZLE MFD driver. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/leds/Kconfig | 8 ++ - drivers/leds/Makefile | 1 + - drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++ - 3 files changed, 156 insertions(+) - create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO - Choose this option if you want to use the notification LED on - Compaq/HP iPAQ h3100 and h3600. - -+config LEDS_IEI_WT61P803_PUZZLE -+ tristate "LED Support for the IEI WT61P803 PUZZLE MCU" -+ depends on LEDS_CLASS -+ depends on MFD_IEI_WT61P803_PUZZLE -+ help -+ This option enables support for LEDs controlled by the IEI WT61P803 -+ M801 MCU. -+ - config LEDS_HP6XX - tristate "LED Support for the HP Jornada 6xx" - depends on LEDS_CLASS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx. - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_IP30) += leds-ip30.o - obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o -+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE) += leds-iei-wt61p803-puzzle.o - obj-$(CONFIG_LEDS_IS31FL319X) += leds-is31fl319x.o - obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o - obj-$(CONFIG_LEDS_LM3530) += leds-lm3530.o ---- /dev/null -+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c -@@ -0,0 +1,147 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU LED Driver -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum iei_wt61p803_puzzle_led_state { -+ IEI_LED_OFF = 0x30, -+ IEI_LED_ON = 0x31, -+ IEI_LED_BLINK_5HZ = 0x32, -+ IEI_LED_BLINK_1HZ = 0x33, -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_led - MCU LED Driver -+ * @cdev: LED classdev -+ * @mcu: MCU struct pointer -+ * @response_buffer Global MCU response buffer -+ * @lock: General mutex lock to protect simultaneous R/W access to led_power_state -+ * @led_power_state: State of the front panel power LED -+ */ -+struct iei_wt61p803_puzzle_led { -+ struct led_classdev cdev; -+ struct iei_wt61p803_puzzle *mcu; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ struct mutex lock; /* mutex to protect led_power_state */ -+ int led_power_state; -+}; -+ -+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led -+ (struct led_classdev *led_cdev) -+{ -+ return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev); -+} -+ -+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ unsigned char *resp_buf = priv->response_buffer; -+ unsigned char led_power_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER; -+ led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON; -+ -+ ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd, -+ sizeof(led_power_cmd), -+ resp_buf, -+ &reply_size); -+ if (ret) -+ return ret; -+ -+ if (reply_size != 3) -+ return -EIO; -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) -+ return -EIO; -+ -+ mutex_lock(&priv->lock); -+ priv->led_power_state = brightness; -+ mutex_unlock(&priv->lock); -+ -+ return 0; -+} -+ -+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ int led_state; -+ -+ mutex_lock(&priv->lock); -+ led_state = priv->led_power_state; -+ mutex_unlock(&priv->lock); -+ -+ return led_state; -+} -+ -+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); -+ struct iei_wt61p803_puzzle_led *priv; -+ struct led_init_data init_data = {}; -+ struct fwnode_handle *child; -+ int ret; -+ -+ if (device_get_child_node_count(dev) != 1) -+ return -EINVAL; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->mcu = mcu; -+ priv->led_power_state = 1; -+ mutex_init(&priv->lock); -+ dev_set_drvdata(dev, priv); -+ -+ child = device_get_next_child_node(dev, NULL); -+ init_data.fwnode = child; -+ -+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -+ priv->cdev.max_brightness = 1; -+ -+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -+ if (ret) -+ dev_err(dev, "Could not register LED\n"); -+ -+ fwnode_handle_put(child); -+ return ret; -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = { -+ { .compatible = "iei,wt61p803-puzzle-leds" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match); -+ -+static struct platform_driver iei_wt61p803_puzzle_led_driver = { -+ .driver = { -+ .name = "iei-wt61p803-puzzle-led", -+ .of_match_table = iei_wt61p803_puzzle_led_of_match, -+ }, -+ .probe = iei_wt61p803_puzzle_led_probe, -+}; -+module_platform_driver(iei_wt61p803_puzzle_led_driver); -+ -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle"); diff --git a/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch b/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch deleted file mode 100644 index b1d420ef0a..0000000000 --- a/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:36 +0000 -Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs - interface documentation - -Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow -monitoring and control of the microcontroller from user space. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../testing/sysfs-driver-iei-wt61p803-puzzle | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle - ---- /dev/null -+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle -@@ -0,0 +1,61 @@ -+What: /sys/bus/serial/devices/.../mac_address_* -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Internal factory assigned MAC address values -+ -+What: /sys/bus/serial/devices/.../serial_number -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Internal factory assigned serial number -+ -+What: /sys/bus/serial/devices/.../version -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU firmware version -+ -+What: /sys/bus/serial/devices/.../protocol_version -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU communication protocol version -+ -+What: /sys/bus/serial/devices/.../power_loss_recovery -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Host platform power loss recovery settings -+ Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA -+ -+What: /sys/bus/serial/devices/.../bootloader_mode -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU bootloader mode status -+ Value mapping: -+ 0 - normal mode -+ 1 - bootloader mode -+ -+What: /sys/bus/serial/devices/.../power_status -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Power status indicates the host platform power on method. -+ Value mapping (bitwise list): -+ 0x80 - Null -+ 0x40 - Firmware flag -+ 0x20 - Power loss detection flag (powered off) -+ 0x10 - Power loss detection flag (AC mode) -+ 0x08 - Button power on -+ 0x04 - Wake-on-LAN power on -+ 0x02 - RTC alarm power on -+ 0x01 - AC recover power on -+ -+What: /sys/bus/serial/devices/.../build_info -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU firmware build date -+ Format: yyyy/mm/dd hh:mm -+ -+What: /sys/bus/serial/devices/.../ac_recovery_status -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Host platform AC recovery status value -+ Value mapping: -+ 0 - board has not been recovered from power down -+ 1 - board has been recovered from power down diff --git a/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch b/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch deleted file mode 100644 index 0f1a6f306b..0000000000 --- a/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:37 +0000 -Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver - documentation - -Add the iei-wt61p803-puzzle driver hwmon driver interface documentation. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../hwmon/iei-wt61p803-puzzle-hwmon.rst | 43 +++++++++++++++++++ - Documentation/hwmon/index.rst | 1 + - 2 files changed, 44 insertions(+) - create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst - ---- /dev/null -+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst -@@ -0,0 +1,43 @@ -+.. SPDX-License-Identifier: GPL-2.0-only -+ -+Kernel driver iei-wt61p803-puzzle-hwmon -+======================================= -+ -+Supported chips: -+ * IEI WT61P803 PUZZLE for IEI Puzzle M801 -+ -+ Prefix: 'iei-wt61p803-puzzle-hwmon' -+ -+Author: Luka Kovacic -+ -+ -+Description -+----------- -+ -+This driver adds fan and temperature sensor reading for some IEI Puzzle -+series boards. -+ -+Sysfs attributes -+---------------- -+ -+The following attributes are supported: -+ -+- IEI WT61P803 PUZZLE for IEI Puzzle M801 -+ -+/sys files in hwmon subsystem -+----------------------------- -+ -+================= == ===================================================== -+fan[1-5]_input RO files for fan speed (in RPM) -+pwm[1-2] RW files for fan[1-2] target duty cycle (0..255) -+temp[1-2]_input RO files for temperature sensors, in millidegree Celsius -+================= == ===================================================== -+ -+/sys files in thermal subsystem -+------------------------------- -+ -+================= == ===================================================== -+cur_state RW file for current cooling state of the cooling device -+ (0..max_state) -+max_state RO file for maximum cooling state of the cooling device -+================= == ===================================================== ---- a/Documentation/hwmon/index.rst -+++ b/Documentation/hwmon/index.rst -@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers - ibmaem - ibm-cffps - ibmpowernv -+ iei-wt61p803-puzzle-hwmon - ina209 - ina2xx - ina238 diff --git a/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch deleted file mode 100644 index e72df378ef..0000000000 --- a/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:38 +0000 -Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE - driver - -Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers). - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - MAINTAINERS | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -9900,6 +9900,22 @@ F: include/net/nl802154.h - F: net/ieee802154/ - F: net/mac802154/ - -+IEI WT61P803 M801 MFD DRIVER -+M: Luka Kovacic -+M: Luka Perkov -+M: Goran Medic -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle -+F: Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml -+F: Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml -+F: Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml -+F: Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst -+F: drivers/hwmon/iei-wt61p803-puzzle-hwmon.c -+F: drivers/leds/leds-iei-wt61p803-puzzle.c -+F: drivers/mfd/iei-wt61p803-puzzle.c -+F: include/linux/mfd/iei-wt61p803-puzzle.h -+ - IFE PROTOCOL - M: Yotam Gigi - M: Jamal Hadi Salim diff --git a/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch b/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch deleted file mode 100644 index 150a65498c..0000000000 --- a/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch +++ /dev/null @@ -1,271 +0,0 @@ ---- a/drivers/leds/leds-iei-wt61p803-puzzle.c -+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c -@@ -9,9 +9,13 @@ - #include - #include - #include -+#include - #include - #include - #include -+#include -+ -+#define IEI_LEDS_MAX 4 - - enum iei_wt61p803_puzzle_led_state { - IEI_LED_OFF = 0x30, -@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led { - struct iei_wt61p803_puzzle *mcu; - unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; - struct mutex lock; /* mutex to protect led_power_state */ -+ struct work_struct work; - int led_power_state; -+ int id; -+ u8 blinking; -+ bool active_low; - }; - - static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led -@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh - size_t reply_size; - int ret; - -+ if (priv->blinking) { -+ if (brightness == LED_OFF) -+ priv->blinking = 0; -+ else -+ return 0; -+ } -+ - led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; - led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -- led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER; -- led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON; -+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id); -+ led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ? -+ IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON; - - ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd, - sizeof(led_power_cmd), -@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_ - return led_state; - } - -+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work) -+{ -+ struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work); -+ unsigned char led_blink_cmd[5] = {}; -+ unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ size_t reply_size; -+ -+ led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -+ led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id); -+ led_blink_cmd[3] = priv->blinking; -+ -+ iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd, -+ sizeof(led_blink_cmd), -+ resp_buf, -+ &reply_size); -+ -+ return; -+} -+ -+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ u8 blink_mode = 0; -+ int ret = 0; -+ -+ /* set defaults */ -+ if (!*delay_on && !*delay_off) { -+ *delay_on = 500; -+ *delay_off = 500; -+ } -+ -+ /* minimum delay for soft-driven blinking is 100ms to keep load low */ -+ if (*delay_on < 100) -+ *delay_on = 100; -+ -+ if (*delay_off < 100) -+ *delay_off = 100; -+ -+ /* offload blinking to hardware, if possible */ -+ if (*delay_on != *delay_off) { -+ ret = -EINVAL; -+ } else if (*delay_on == 100) { -+ blink_mode = IEI_LED_BLINK_5HZ; -+ *delay_on = 100; -+ *delay_off = 100; -+ } else if (*delay_on <= 500) { -+ blink_mode = IEI_LED_BLINK_1HZ; -+ *delay_on = 500; -+ *delay_off = 500; -+ } else { -+ ret = -EINVAL; -+ } -+ -+ mutex_lock(&priv->lock); -+ priv->blinking = blink_mode; -+ mutex_unlock(&priv->lock); -+ -+ if (blink_mode) -+ schedule_work(&priv->work); -+ -+ return ret; -+} -+ -+ -+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev, -+ struct device_node *np) -+{ -+ const char *state; -+ int ret = 0; -+ -+ state = of_get_property(np, "default-state", NULL); -+ if (state) { -+ if (!strcmp(state, "on")) { -+ ret = -+ iei_wt61p803_puzzle_led_brightness_set_blocking( -+ cdev, cdev->max_brightness); -+ } else { -+ ret = iei_wt61p803_puzzle_led_brightness_set_blocking( -+ cdev, LED_OFF); -+ } -+ } -+ -+ return ret; -+} -+ - static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -+ struct device_node *np = dev_of_node(dev); -+ struct device_node *child; - struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); - struct iei_wt61p803_puzzle_led *priv; -- struct led_init_data init_data = {}; -- struct fwnode_handle *child; - int ret; -+ u32 reg; - -- if (device_get_child_node_count(dev) != 1) -+ if (device_get_child_node_count(dev) > IEI_LEDS_MAX) - return -EINVAL; - -- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; -- -- priv->mcu = mcu; -- priv->led_power_state = 1; -- mutex_init(&priv->lock); -- dev_set_drvdata(dev, priv); -- -- child = device_get_next_child_node(dev, NULL); -- init_data.fwnode = child; -- -- priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -- priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -- priv->cdev.max_brightness = 1; -+ for_each_available_child_of_node(np, child) { -+ struct led_init_data init_data = {}; - -- ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -- if (ret) -- dev_err(dev, "Could not register LED\n"); -+ ret = of_property_read_u32(child, "reg", ®); -+ if (ret) { -+ dev_err(dev, "Failed to read led 'reg' property\n"); -+ goto put_child_node; -+ } -+ -+ if (reg > IEI_LEDS_MAX) { -+ dev_err(dev, "Invalid led reg %u\n", reg); -+ ret = -EINVAL; -+ goto put_child_node; -+ } -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ ret = -ENOMEM; -+ goto put_child_node; -+ } -+ -+ mutex_init(&priv->lock); -+ -+ dev_set_drvdata(dev, priv); -+ -+ if (of_property_read_bool(child, "active-low")) -+ priv->active_low = true; -+ -+ priv->mcu = mcu; -+ priv->id = reg; -+ priv->led_power_state = 1; -+ priv->blinking = 0; -+ init_data.fwnode = of_fwnode_handle(child); -+ -+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -+ priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink; -+ -+ priv->cdev.max_brightness = 1; -+ -+ INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink); -+ -+ ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child); -+ if (ret) { -+ dev_err(dev, "Could apply default from DT\n"); -+ goto put_child_node; -+ } -+ -+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -+ if (ret) { -+ dev_err(dev, "Could not register LED\n"); -+ goto put_child_node; -+ } -+ } -+ -+ return ret; - -- fwnode_handle_put(child); -+put_child_node: -+ of_node_put(child); - return ret; - } - ---- a/include/linux/mfd/iei-wt61p803-puzzle.h -+++ b/include/linux/mfd/iei-wt61p803-puzzle.h -@@ -36,7 +36,7 @@ - #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */ - - #define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */ --#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */ -+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n) (0x30 | (n)) - - #define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */ - #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */ ---- a/drivers/mfd/iei-wt61p803-puzzle.c -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf( - struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev); - int ret; - -+ print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE, -+ 16, 1, data, size, false); -+ - ret = iei_wt61p803_puzzle_process_resp(mcu, data, size); - /* Return the number of processed bytes if function returns error, - * discard the remaining incoming data, since the frame this data -@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st - - cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1); - -+ print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE, -+ 16, 1, cmd, size, false); -+ - /* Initialize reply struct */ - reinit_completion(&mcu->reply->received); - mcu->reply->size = 0; diff --git a/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch b/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch deleted file mode 100644 index 2f0b1788ff..0000000000 --- a/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch +++ /dev/null @@ -1,63 +0,0 @@ ---- a/drivers/mfd/iei-wt61p803-puzzle.c -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st - { - struct device *dev = &mcu->serdev->dev; - int ret; -+ int retries; - - if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH) - return -EINVAL; -@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st - print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE, - 16, 1, cmd, size, false); - -+ retries = 3; - /* Initialize reply struct */ -- reinit_completion(&mcu->reply->received); -- mcu->reply->size = 0; -- usleep_range(2000, 10000); -- serdev_device_write_flush(mcu->serdev); -- ret = serdev_device_write_buf(mcu->serdev, cmd, size); -- if (ret < 0) -- goto exit; -- -- serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -- ret = wait_for_completion_timeout(&mcu->reply->received, -- IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -- if (ret == 0) { -- dev_err(dev, "Command reply receive timeout\n"); -- ret = -ETIMEDOUT; -- goto exit; -+ while (retries) { -+ reinit_completion(&mcu->reply->received); -+ mcu->reply->size = 0; -+ usleep_range(2000, 10000); -+ serdev_device_write_flush(mcu->serdev); -+ ret = serdev_device_write_buf(mcu->serdev, cmd, size); -+ if (ret < 0) -+ goto exit; -+ -+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ ret = wait_for_completion_timeout(&mcu->reply->received, -+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ retries--; -+ if (ret == 0) { -+ if (retries == 0) { -+ dev_err(dev, "Command reply receive timeout\n"); -+ ret = -ETIMEDOUT; -+ goto exit; -+ } -+ } -+ else { -+ if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) { -+ break; -+ } -+ } - } -- - *reply_size = mcu->reply->size; - /* Copy the received data, as it will not be available after a new frame is received */ - memcpy(reply_data, mcu->reply->data, mcu->reply->size); diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts new file mode 100644 index 0000000000..70f4438ab0 --- /dev/null +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "ipq8074.dtsi" +#include "ipq8074-hk-cpu.dtsi" +#include "ipq8074-ess.dtsi" +#include +#include +#include + +/ { + model = "Linksys MX8500"; + compatible = "linksys,mx8500", "qcom,ipq8074"; + + aliases { + serial0 = &blsp1_uart5; + serial1 = &blsp1_uart3; + led-boot = &led_system_blue; + led-running = &led_system_blue; + led-failsafe = &led_system_red; + led-upgrade = &led_system_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro"; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + bt_pwr { + gpio-export,name = "bt_pwr"; + gpio-export,output = <1>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset-button { + label = "reset"; + gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps-button { + label = "wps"; + gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&tlmm { + button_pins: button-state { + pins = "gpio64", "gpio67"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio_pins: mdio-state { + mdc-pins { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + /* + * Bootloader will find the NAND DT node by the compatible and + * then "fixup" it by adding the partitions from the SMEM table + * using the legacy bindings thus making it impossible for us + * to change the partition table or utilize NVMEM for calibration. + * So add a dummy partitions node that bootloader will populate + * and set it as disabled so the kernel ignores it instead of + * printing warnings due to the broken way bootloader adds the + * partitions. + */ + partitions { + status = "disabled"; + }; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:sbl1"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "0:mibib"; + reg = <0x100000 0x100000>; + read-only; + }; + + partition@200000 { + label = "0:bootconfig"; + reg = <0x200000 0x80000>; + read-only; + }; + + partition@280000 { + label = "0:bootconfig1"; + reg = <0x280000 0x80000>; + read-only; + }; + + partition@300000 { + label = "0:qsee"; + reg = <0x300000 0x300000>; + read-only; + }; + + partition@600000 { + label = "0:qsee_1"; + reg = <0x600000 0x300000>; + read-only; + }; + + partition@900000 { + label = "0:devcfg"; + reg = <0x900000 0x80000>; + read-only; + }; + + partition@980000 { + label = "0:devcfg_1"; + reg = <0x980000 0x80000>; + read-only; + }; + + partition@a00000 { + label = "0:apdp"; + reg = <0xa00000 0x80000>; + read-only; + }; + + partition@a80000 { + label = "0:apdp_1"; + reg = <0xa80000 0x80000>; + read-only; + }; + + partition@b00000 { + label = "0:rpm"; + reg = <0xb00000 0x80000>; + read-only; + }; + + partition@b80000 { + label = "0:rpm_1"; + reg = <0xb80000 0x80000>; + read-only; + }; + + partition@c00000 { + label = "0:cdt"; + reg = <0xc00000 0x80000>; + read-only; + }; + + partition@c80000 { + label = "0:cdt_1"; + reg = <0xc80000 0x80000>; + read-only; + }; + + partition@d00000 { + label = "0:appsblenv"; + reg = <0xd00000 0x80000>; + }; + + partition@d80000 { + label = "0:appsbl"; + reg = <0xd80000 0x100000>; + read-only; + }; + + partition@e80000 { + label = "0:appsbl_1"; + reg = <0xe80000 0x100000>; + read-only; + }; + + partition@f80000 { + label = "0:art"; + reg = <0xf80000 0x80000>; + read-only; + }; + + partition@1000000 { + label = "u_env"; + reg = <0x1000000 0x40000>; + }; + + partition@1040000 { + label = "s_env"; + reg = <0x1040000 0x20000>; + }; + + partition@1060000 { + label = "devinfo"; + reg = <0x1060000 0x20000>; + read-only; + }; + + partition@1080000 { + label = "kernel"; + reg = <0x1080000 0x9600000>; + }; + + partition@1680000 { + label = "rootfs"; + reg = <0x1680000 0x9000000>; + }; + + partition@a680000 { + label = "alt_kernel"; + reg = <0xa680000 0x9600000>; + }; + + partition@ac80000 { + label = "alt_rootfs"; + reg = <0xac80000 0x9000000>; + }; + + partition@13c80000 { + label = "sysdiag"; + reg = <0x13c80000 0x200000>; + read-only; + }; + + partition@13e80000 { + label = "0:ethphyfw"; + reg = <0x13e80000 0x100000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + aqr_fw: firmware@0 { + /* Skip the QCOM MBN Header of 40 bytes */ + reg = <0x28 0x60002>; + }; + }; + }; + + partition@13f80000 { + label = "syscfg"; + reg = <0x13f80000 0xb180000>; + read-only; + }; + + partition@1f100000 { + label = "app_data"; + reg = <0x1f100000 0x500000>; + read-only; + }; + + partition@1f600000 { + label = "0:wififw"; + reg = <0x1f600000 0xa00000>; + read-only; + }; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + led-controller@62 { + compatible = "nxp,pca9633"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x62>; + nxp,hw-blink; + + led_system_red: led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_system_green: led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_system_blue: led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_STATUS; + }; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + + ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qca8075-package"; + reg = <0>; + + qcom,package-mode = "qsgmii"; + + qca8075_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + qca8075_1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + qca8075_2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + qca8075_3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; + + aqr114c: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld"; + nvmem-cells = <&aqr_fw>; + nvmem-cell-names = "firmware"; + }; +}; + +&switch { + status = "okay"; + + switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */ + switch_wan_bmp = ; /* wan port bitmap */ + switch_mac_mode = ; /* mac mode for uniphy instance0*/ + switch_mac_mode2 = ; /* mac mode for uniphy instance2*/ + + qcom,port_phyinfo { + port@1 { + port_id = <1>; + phy_address = <0>; + }; + + port@2 { + port_id = <2>; + phy_address = <1>; + }; + + port@3 { + port_id = <3>; + phy_address = <2>; + }; + + port@4 { + port_id = <4>; + phy_address = <3>; + }; + + port@6 { + port_id = <6>; + phy_address = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + ethernet-phy-ieee802.3-c45; + }; + }; +}; + +&edma { + status = "okay"; +}; + +&dp1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&qca8075_0>; + label = "lan1"; +}; + +&dp2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&qca8075_1>; + label = "lan2"; +}; + +&dp3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&qca8075_2>; + label = "lan3"; +}; + +&dp4 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&qca8075_3>; + label = "lan4"; +}; + +&dp6_syn { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&aqr114c>; + label = "wan"; +}; + +&ssphy_0 { + status = "okay"; +}; + +&qusb_phy_0 { + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&pcie_qmp0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + status = "okay"; + + /* ath11k has no DT compatible for PCI cards */ + compatible = "pci17cb,1104"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath11k-calibration-variant = "Linksys-MX8500"; + }; + }; +}; + +&wifi { + status = "okay"; + + qcom,ath11k-calibration-variant = "Linksys-MX8500"; +}; diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk index f8a460d8a6..39dbf2f02b 100644 --- a/target/linux/qualcommax/image/ipq807x.mk +++ b/target/linux/qualcommax/image/ipq807x.mk @@ -103,20 +103,26 @@ define Device/edimax_cax1800 endef TARGET_DEVICES += edimax_cax1800 -define Device/linksys_mx4200v1 +define Device/linksys_mx $(call Device/FitImage) DEVICE_VENDOR := Linksys - DEVICE_MODEL := MX4200 - DEVICE_VARIANT := v1 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_SIZE := 6144k IMAGE_SIZE := 147456k NAND_SIZE := 512m - SOC := ipq8174 + SOC := ipq8072 IMAGES += factory.bin - IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX4200 - DEVICE_PACKAGES := kmod-leds-pca963x ipq-wifi-linksys_mx4200 kmod-bluetooth + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=$$$$(DEVICE_MODEL) + DEVICE_PACKAGES := kmod-leds-pca963x +endef + +define Device/linksys_mx4200v1 + $(call Device/linksys_mx) + DEVICE_MODEL := MX4200 + DEVICE_VARIANT := v1 + SOC := ipq8174 + DEVICE_PACKAGES += ipq-wifi-linksys_mx4200 kmod-bluetooth endef TARGET_DEVICES += linksys_mx4200v1 @@ -127,22 +133,21 @@ endef TARGET_DEVICES += linksys_mx4200v2 define Device/linksys_mx5300 - $(call Device/FitImage) - DEVICE_VENDOR := Linksys + $(call Device/linksys_mx) DEVICE_MODEL := MX5300 - BLOCKSIZE := 128k - PAGESIZE := 2048 - KERNEL_SIZE := 6144k - IMAGE_SIZE := 147456k - NAND_SIZE := 512m - SOC := ipq8072 - IMAGES += factory.bin - IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX5300 - DEVICE_PACKAGES := kmod-leds-pca963x kmod-rtc-ds1307 \ - ipq-wifi-linksys_mx5300 kmod-ath10k-ct ath10k-firmware-qca9984-ct + DEVICE_PACKAGES += kmod-rtc-ds1307 ipq-wifi-linksys_mx5300 \ + kmod-ath10k-ct ath10k-firmware-qca9984-ct endef TARGET_DEVICES += linksys_mx5300 +define Device/linksys_mx8500 + $(call Device/linksys_mx) + DEVICE_MODEL := MX8500 + DEVICE_PACKAGES += ipq-wifi-linksys_mx8500 kmod-ath11k-pci \ + ath11k-firmware-qcn9074 kmod-bluetooth +endef +TARGET_DEVICES += linksys_mx8500 + define Device/netgear_rax120v2 $(call Device/FitImage) $(call Device/UbiFit) diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network index 177391f0fc..0497af2378 100644 --- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network +++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network @@ -15,6 +15,7 @@ ipq807x_setup_interfaces() buffalo,wxr-5950ax12|\ dynalink,dl-wrx36|\ linksys,mx5300|\ + linksys,mx8500|\ xiaomi,ax9000|\ zbtlink,zbt-z800ax) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" @@ -79,11 +80,17 @@ ipq807x_setup_macs() done [ "$(mtd_get_mac_ascii u_env eth2addr)" != "$label_mac" ] && wan_mac=$label_mac ;; + linksys,mx8500) + label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + lan_mac=$(macaddr_add $label_mac 1) + wan_mac=$label_mac + ;; zte,mf269) wan_mac="$(mtd_get_mac_binary mac 0x0)" [ "$wan_mac" != "00:00:00:00:00:00" ] || wan_mac="$(get_mac_binary "$(find_mtd_chardev mac)" 0x20000)" lan_mac="$(macaddr_add "$wan_mac" 1)" label_mac="$wan_mac" + ;; esac diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index 5a6e9d9978..fbf353b86d 100644 --- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -31,7 +31,8 @@ case "$FIRMWARE" in zte,mf269) caldata_extract "0:art" 0x1000 0x20000 ;; - linksys,mx4200v1) + linksys,mx4200v1|\ + linksys,mx8500) caldata_extract "0:art" 0x1000 0x20000 ath11k_remove_regdomain ;; @@ -68,6 +69,10 @@ case "$FIRMWARE" in "ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\ "ath11k/QCN9074/hw1.0/cal-pci-0001:01:00.0.bin") case "$board" in + linksys,mx8500) + caldata_extract "0:art" 0x26800 0x20000 + ath11k_remove_regdomain + ;; prpl,haze) caldata_extract_mmc "0:ART" 0x26800 0x20000 ;; diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount index da2c65e2c8..3822afd709 100755 --- a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount +++ b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount @@ -12,7 +12,8 @@ boot() { ;; linksys,mx4200v1|\ linksys,mx4200v2|\ - linksys,mx5300) + linksys,mx5300|\ + linksys,mx8500) mtd resetbc s_env || true ;; redmi,ax6-stock|\ diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh index 7a0bdba7da..af0e143171 100644 --- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh @@ -77,7 +77,8 @@ platform_do_upgrade() { ;; linksys,mx4200v1|\ linksys,mx4200v2|\ - linksys,mx5300) + linksys,mx5300|\ + linksys,mx8500) boot_part="$(fw_printenv -n boot_part)" if [ "$boot_part" -eq "1" ]; then fw_setenv boot_part 2 diff --git a/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch b/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch new file mode 100644 index 0000000000..e075c590fb --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch @@ -0,0 +1,32 @@ +From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 +From: Paweł Owoc +Date: Wed, 13 Mar 2024 11:27:06 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins + +gpio16 will only be used for LCD support, as its NAND/LCDC data[8] +so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 +or 16-bit with only 8-bit one being supported in our case so that pin +is unused. + +It should be dropped from the default NAND pinctrl configuration +as its unused and only needed for LCD. + +Signed-off-by: Paweł Owoc +Reviewed-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -372,7 +372,7 @@ + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", +- "gpio15", "gpio16", "gpio17"; ++ "gpio15", "gpio17"; + function = "qpic"; + drive-strength = <8>; + bias-disable; diff --git a/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts b/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts new file mode 100644 index 0000000000..42517529af --- /dev/null +++ b/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621_elecom_wrc-gs-1pci.dtsi" + +/ { + compatible = "elecom,wmc-m1267gst2", "mediatek,mt7621-soc"; + model = "ELECOM WMC-M1267GST2"; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_fff4>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_fffa>; + nvmem-cell-names = "mac-address"; +}; + +&partitions { + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0x1800000>; + }; + + partition@1850000 { + label = "tm_pattern"; + reg = <0x1850000 0x400000>; + read-only; + }; + + partition@1c50000 { + label = "tm_key"; + reg = <0x1c50000 0x100000>; + read-only; + }; + + partition@1d50000 { + label = "nvram"; + reg = <0x1d50000 0xb0000>; + read-only; + }; + + partition@1e00000 { + label = "user_data"; + reg = <0x1e00000 0x200000>; + read-only; + }; +}; + +&wifi { + nvmem-cells = <&macaddr_factory_4 (-1)>; + nvmem-cell-names = "mac-address"; +}; + +&factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_fff4: macaddr@fff4 { + reg = <0xfff4 0x6>; + }; + + macaddr_factory_fffa: macaddr@fffa { + reg = <0xfffa 0x6>; + }; + }; +}; diff --git a/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts b/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts new file mode 100644 index 0000000000..942fa1cb46 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621_elecom_wrc-gs-1pci.dtsi" + +/ { + compatible = "elecom,wmc-s1267gs2", "mediatek,mt7621-soc"; + model = "ELECOM WMC-S1267GS2"; + + aliases { + /* + * A MAC address printed to the label is an address of + * 5 GHz band on stock firmware, but there is no + * per-band MAC address support on Linux Kernel and that + * address is not assigned to any wlan devices now. + */ + /delete-property/ label-mac-device; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_fff4>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + status = "disabled"; +}; + +&partitions { + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0x1800000>; + }; + + partition@1850000 { + label = "tm_pattern"; + reg = <0x1850000 0x400000>; + read-only; + }; + + partition@1c50000 { + label = "tm_key"; + reg = <0x1c50000 0x100000>; + read-only; + }; + + partition@1d50000 { + label = "nvram"; + reg = <0x1d50000 0xb0000>; + read-only; + }; + + partition@1e00000 { + label = "user_data"; + reg = <0x1e00000 0x200000>; + read-only; + }; +}; + +&wifi { + nvmem-cells = <&macaddr_factory_4 (-1)>; + nvmem-cell-names = "mac-address"; +}; + +&factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_fff4: macaddr@fff4 { + reg = <0xfff4 0x6>; + }; + }; +}; diff --git a/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts b/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts index 38602bc446..8512ff96b0 100644 --- a/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts +++ b/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts @@ -19,26 +19,10 @@ }; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - - button-reset { - label = "reset"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - button-wps { - label = "wps"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { + leds { compatible = "gpio-leds"; led_status_red: led-0 { @@ -59,44 +43,24 @@ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; }; }; -}; -ðphy4 { - /delete-property/ interrupts; -}; + keys { + compatible = "gpio-keys"; -&gmac0 { - nvmem-cells = <&macaddr_factory_3fff4>; - nvmem-cell-names = "mac-address"; -}; + wps { + label = "wps"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; -&gmac1 { - status = "okay"; - label = "wan"; - phy-handle = <ðphy4>; - - nvmem-cells = <&macaddr_factory_3fffa>; - nvmem-cell-names = "mac-address"; -}; - -&pcie { - status = "okay"; -}; - -&pcie1 { - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cells = <&eeprom_factory_0>; - nvmem-cell-names = "eeprom"; - mediatek,disable-radar-background; + reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; }; }; -&sdhci { - status = "okay"; -}; - &spi0 { status = "okay"; @@ -111,12 +75,13 @@ #size-cells = <1>; partition@0 { - label = "U-boot"; + label = "U-Boot"; reg = <0x0 0x40000>; read-only; }; partition@40000 { + compatible = "u-boot,env"; label = "Config"; reg = <0x40000 0x10000>; }; @@ -156,11 +121,47 @@ &state_default { gpio { - groups = "i2c"; + groups = "uart3", "jtag", "wdt"; function = "gpio"; }; }; +&sdhci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pcie1 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + mediatek,disable-radar-background; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_3fff4>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + status = "okay"; + label = "wan"; + phy-handle = <ðphy4>; + + nvmem-cells = <&macaddr_factory_3fffa>; + nvmem-cell-names = "mac-address"; +}; + +ðphy4 { + /delete-property/ interrupts; +}; + &switch0 { ports { port@1 { diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts index 21d1e48336..67cc54650f 100644 --- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts +++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts @@ -89,12 +89,14 @@ }; &wmac { - nvmem-cells = <&macaddr_factory_1f100>; - nvmem-cell-names = "mac-address"; + status = "okay"; + + nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>; + nvmem-cell-names = "eeprom", "mac-address"; }; ðernet { - nvmem-cells = <&macaddr_factory_1f100>; + nvmem-cells = <&macaddr_factory_1f100 0>; nvmem-cell-names = "mac-address"; }; @@ -105,7 +107,9 @@ #size-cells = <1>; macaddr_factory_1f100: macaddr@1f100 { + compatible = "mac-base"; reg = <0x1f100 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts index 1bd35fc334..609452dfe1 100644 --- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts +++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts @@ -89,12 +89,14 @@ }; &wmac { - nvmem-cells = <&macaddr_factory_1f100>; - nvmem-cell-names = "mac-address"; + status = "okay"; + + nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>; + nvmem-cell-names = "eeprom", "mac-address"; }; ðernet { - nvmem-cells = <&macaddr_factory_1f100>; + nvmem-cells = <&macaddr_factory_1f100 0>; nvmem-cell-names = "mac-address"; }; @@ -105,7 +107,9 @@ #size-cells = <1>; macaddr_factory_1f100: macaddr@1f100 { + compatible = "mac-base"; reg = <0x1f100 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 08d9f27f0b..be23d83ee8 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -980,6 +980,33 @@ define Device/edimax_rg21s endef TARGET_DEVICES += edimax_rg21s +define Device/elecom_wrc-gs + $(Device/dsa-migration) + $(Device/uimage-lzma-loader) + DEVICE_VENDOR := ELECOM + IMAGES += factory.bin + IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \ + elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \ + append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME) + DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools +endef + +define Device/elecom_wmc-m1267gst2 + $(Device/elecom_wrc-gs) + IMAGE_SIZE := 24576k + DEVICE_MODEL := WMC-M1267GST2 + ELECOM_HWNAME := WMC-DLGST2 +endef +TARGET_DEVICES += elecom_wmc-m1267gst2 + +define Device/elecom_wmc-s1267gs2 + $(Device/elecom_wrc-gs) + IMAGE_SIZE := 24576k + DEVICE_MODEL := WMC-S1267GS2 + ELECOM_HWNAME := WMC-DLGST2 +endef +TARGET_DEVICES += elecom_wmc-s1267gs2 + define Device/elecom_wrc-1167ghbk2-s $(Device/dsa-migration) IMAGE_SIZE := 15488k @@ -992,17 +1019,6 @@ define Device/elecom_wrc-1167ghbk2-s endef TARGET_DEVICES += elecom_wrc-1167ghbk2-s -define Device/elecom_wrc-gs - $(Device/dsa-migration) - $(Device/uimage-lzma-loader) - DEVICE_VENDOR := ELECOM - IMAGES += factory.bin - IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \ - elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \ - append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME) - DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools -endef - define Device/elecom_wrc-1167gs2-b $(Device/elecom_wrc-gs) IMAGE_SIZE := 11264k @@ -1538,7 +1554,6 @@ TARGET_DEVICES += jcg_y2 define Device/jdcloud_re-cp-02 $(Device/dsa-migration) - $(Device/uimage-lzma-loader) IMAGE_SIZE := 16000k DEVICE_VENDOR := JDCloud DEVICE_MODEL := RE-CP-02 diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index d7e0efe991..4ef57a280a 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -104,17 +104,18 @@ ramips_setup_interfaces() dlink,covr-x1860-a1) ucidef_set_interfaces_lan_wan "ethernet" "internet" ;; + elecom,wmc-s1267gs2|\ + linksys,re6500|\ + netgear,wac104|\ + zyxel,lte3301-plus) + ucidef_set_interface_lan "lan1 lan2 lan3 lan4" + ;; gnubee,gb-pc1) ucidef_set_interface_lan "ethblack ethblue" ;; gnubee,gb-pc2) ucidef_set_interface_lan "ethblack ethblue ethyellow" ;; - linksys,re6500|\ - netgear,wac104|\ - zyxel,lte3301-plus) - ucidef_set_interface_lan "lan1 lan2 lan3 lan4" - ;; mikrotik,routerboard-750gr3) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4 lan5" "wan" ;; diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index 85abbdabb7..b306040f6a 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -14,6 +14,9 @@ choice config GCC_USE_VERSION_13 bool "gcc 13.x" + + config GCC_USE_VERSION_14 + bool "gcc 14.x" endchoice config GCC_USE_GRAPHITE diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 6e71247099..47a68e400c 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -6,11 +6,16 @@ config GCC_VERSION_12 default y if GCC_USE_VERSION_12 bool +config GCC_VERSION_14 + default y if GCC_USE_VERSION_14 + bool + config GCC_VERSION string default EXTERNAL_GCC_VERSION if EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN default "11.3.0" if GCC_VERSION_11 default "12.3.0" if GCC_VERSION_12 + default "14.1.0" if GCC_VERSION_14 default "13.2.0" config GCC_USE_DEFAULT_VERSION diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index cdbf9fafa9..f5db99f869 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -42,6 +42,10 @@ ifeq ($(PKG_VERSION),13.2.0) PKG_HASH:=e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da endif +ifeq ($(PKG_VERSION),14.1.0) + PKG_HASH:=e283c654987afe3de9d8080bc0bd79534b5ca0d681a73a11ff2b5d3767426840 +endif + PATCH_DIR=../patches-$(GCC_MAJOR_VERSION).x BUGURL=http://bugs.openwrt.org/ diff --git a/toolchain/gcc/patches-14.x/002-case_insensitive.patch b/toolchain/gcc/patches-14.x/002-case_insensitive.patch new file mode 100644 index 0000000000..409497e5a3 --- /dev/null +++ b/toolchain/gcc/patches-14.x/002-case_insensitive.patch @@ -0,0 +1,24 @@ +commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e +Author: Felix Fietkau +Date: Sun Oct 19 21:45:51 2014 +0000 + + gcc: do not assume that the Mac OS X filesystem is case insensitive + + Signed-off-by: Felix Fietkau + + SVN-Revision: 42973 + +--- a/include/filenames.h ++++ b/include/filenames.h +@@ -44,11 +44,6 @@ extern "C" { + # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) + # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) + #else /* not DOSish */ +-# if defined(__APPLE__) +-# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM +-# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 +-# endif +-# endif /* __APPLE__ */ + # define HAS_DRIVE_SPEC(f) (0) + # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) + # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) diff --git a/toolchain/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch b/toolchain/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch new file mode 100644 index 0000000000..c41f35e33b --- /dev/null +++ b/toolchain/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch @@ -0,0 +1,13 @@ +--- a/gcc/real.h ++++ b/gcc/real.h +@@ -77,8 +77,10 @@ struct GTY(()) real_value { + + (REAL_VALUE_TYPE_SIZE%HOST_BITS_PER_WIDE_INT ? 1 : 0)) /* round up */ + + /* Verify the guess. */ ++#ifndef __LP64__ + extern char test_real_width + [sizeof (REAL_VALUE_TYPE) <= REAL_WIDTH * sizeof (HOST_WIDE_INT) ? 1 : -1]; ++#endif + + /* Calculate the format for CONST_DOUBLE. We need as many slots as + are necessary to overlay a REAL_VALUE_TYPE on them. This could be diff --git a/toolchain/gcc/patches-14.x/010-documentation.patch b/toolchain/gcc/patches-14.x/010-documentation.patch new file mode 100644 index 0000000000..7cf59d3a99 --- /dev/null +++ b/toolchain/gcc/patches-14.x/010-documentation.patch @@ -0,0 +1,35 @@ +commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2 +Author: Luka Perkov +Date: Tue Feb 26 16:16:33 2013 +0000 + + gcc: don't build documentation + + This closes #13039. + + Signed-off-by: Luka Perkov + + SVN-Revision: 35807 + +--- a/gcc/Makefile.in ++++ b/gcc/Makefile.in +@@ -3549,18 +3549,10 @@ doc/gcc.info: $(TEXI_GCC_FILES) + doc/gccint.info: $(TEXI_GCCINT_FILES) + doc/cppinternals.info: $(TEXI_CPPINT_FILES) + +-doc/%.info: %.texi +- if [ x$(BUILD_INFO) = xinfo ]; then \ +- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ +- -I $(gcc_docdir)/include -o $@ $<; \ +- fi ++doc/%.info: + + # Duplicate entry to handle renaming of gccinstall.info +-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) +- if [ x$(BUILD_INFO) = xinfo ]; then \ +- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ +- -I $(gcc_docdir)/include -o $@ $<; \ +- fi ++doc/gccinstall.info: + + doc/cpp.dvi: $(TEXI_CPP_FILES) + doc/gcc.dvi: $(TEXI_GCC_FILES) diff --git a/toolchain/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch new file mode 100644 index 0000000000..bd5d1f344b --- /dev/null +++ b/toolchain/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch @@ -0,0 +1,20 @@ +Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. +MIPS16 functions have a static assembler prologue which clobbers +registers v0 and v1. Add these register clobbers to function call +instructions. + +--- a/gcc/config/mips/mips.cc ++++ b/gcc/config/mips/mips.cc +@@ -3227,6 +3227,12 @@ mips_emit_call_insn (rtx pattern, rtx or + emit_insn (gen_update_got_version ()); + } + ++ if (TARGET_MIPS16 && TARGET_USE_GOT) ++ { ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); ++ } ++ + if (TARGET_MIPS16 + && TARGET_EXPLICIT_RELOCS + && TARGET_CALL_CLOBBERED_GP) diff --git a/toolchain/gcc/patches-14.x/230-musl_libssp.patch b/toolchain/gcc/patches-14.x/230-musl_libssp.patch new file mode 100644 index 0000000000..3ce5e49587 --- /dev/null +++ b/toolchain/gcc/patches-14.x/230-musl_libssp.patch @@ -0,0 +1,13 @@ +--- a/gcc/gcc.cc ++++ b/gcc/gcc.cc +@@ -985,7 +985,9 @@ proper position among the other output f + #endif + + #ifndef LINK_SSP_SPEC +-#ifdef TARGET_LIBC_PROVIDES_SSP ++#if DEFAULT_LIBC == LIBC_MUSL ++#define LINK_SSP_SPEC "-lssp_nonshared" ++#elif defined(TARGET_LIBC_PROVIDES_SSP) + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit:}" + #else diff --git a/toolchain/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch new file mode 100644 index 0000000000..2d65ba1b1f --- /dev/null +++ b/toolchain/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch @@ -0,0 +1,21 @@ +commit ecf7671b769fe96f7b5134be442089f8bdba55d2 +Author: Felix Fietkau +Date: Thu Aug 4 20:29:45 2016 +0200 + +gcc: add a patch to generate better code with Os on mips + +Also happens to reduce compressed code size a bit + +Signed-off-by: Felix Fietkau + +--- a/gcc/config/mips/mips.cc ++++ b/gcc/config/mips/mips.cc +@@ -20444,7 +20444,7 @@ mips_option_override (void) + flag_pcc_struct_return = 0; + + /* Decide which rtx_costs structure to use. */ +- if (optimize_size) ++ if (0 && optimize_size) + mips_cost = &mips_rtx_cost_optimize_size; + else + mips_cost = &mips_rtx_cost_data[mips_tune]; diff --git a/toolchain/gcc/patches-14.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-14.x/810-arm-softfloat-libgcc.patch new file mode 100644 index 0000000000..5c9d86aead --- /dev/null +++ b/toolchain/gcc/patches-14.x/810-arm-softfloat-libgcc.patch @@ -0,0 +1,33 @@ +commit 8570c4be394cff7282f332f97da2ff569a927ddb +Author: Imre Kaloz +Date: Wed Feb 2 20:06:12 2011 +0000 + + fixup arm soft-float symbols + + SVN-Revision: 25325 + +--- a/libgcc/config/arm/t-linux ++++ b/libgcc/config/arm/t-linux +@@ -1,6 +1,10 @@ + LIB1ASMSRC = arm/lib1funcs.S + LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ +- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 ++ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \ ++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ ++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ ++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ ++ _arm_fixsfsi _arm_fixunssfsi + + # Just for these, we omit the frame pointer since it makes such a big + # difference. +--- a/gcc/config/arm/linux-elf.h ++++ b/gcc/config/arm/linux-elf.h +@@ -58,8 +58,6 @@ + %{shared:-lc} \ + %{!shared:%{profile:-lc_p}%{!profile:-lc}}" + +-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" +- + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + + #define LINUX_TARGET_LINK_SPEC "%{h*} \ diff --git a/toolchain/gcc/patches-14.x/820-libgcc_pic.patch b/toolchain/gcc/patches-14.x/820-libgcc_pic.patch new file mode 100644 index 0000000000..3ab73f4857 --- /dev/null +++ b/toolchain/gcc/patches-14.x/820-libgcc_pic.patch @@ -0,0 +1,44 @@ +commit c96312958c0621e72c9b32da5bc224ffe2161384 +Author: Felix Fietkau +Date: Mon Oct 19 23:26:09 2009 +0000 + + gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow) + + SVN-Revision: 18086 + +--- a/libgcc/Makefile.in ++++ b/libgcc/Makefile.in +@@ -940,11 +940,12 @@ $(libgcov-driver-objects): %$(objext): $ + + # Static libraries. + libgcc.a: $(libgcc-objects) ++libgcc_pic.a: $(libgcc-s-objects) + libgcov.a: $(libgcov-objects) + libunwind.a: $(libunwind-objects) + libgcc_eh.a: $(libgcc-eh-objects) + +-libgcc.a libgcov.a libunwind.a libgcc_eh.a: ++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a: + -rm -f $@ + + objects="$(objects)"; \ +@@ -968,7 +969,7 @@ all: libunwind.a + endif + + ifeq ($(enable_shared),yes) +-all: libgcc_eh.a libgcc_s$(SHLIB_EXT) ++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT) + ifneq ($(LIBUNWIND),) + all: libunwind$(SHLIB_EXT) + libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT) +@@ -1174,6 +1175,10 @@ install-shared: + chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a + $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a + ++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/ ++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a ++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a ++ + $(subst @multilib_dir@,$(MULTIDIR),$(subst \ + @shlib_base_name@,libgcc_s,$(subst \ + @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL)))) diff --git a/toolchain/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch new file mode 100644 index 0000000000..82935f3d1d --- /dev/null +++ b/toolchain/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch @@ -0,0 +1,28 @@ +commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc +Author: Imre Kaloz +Date: Wed Feb 2 19:34:36 2011 +0000 + + add armv4 fixup patches + + SVN-Revision: 25322 + + +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -88,10 +88,15 @@ + #define MUSL_DYNAMIC_LINKER \ + "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" + ++/* For armv4 we pass --fix-v4bx to linker to support EABI */ ++#undef TARGET_FIX_V4BX_SPEC ++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ ++ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC +-#define LINK_SPEC EABI_LINK_SPEC \ ++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \ + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ + LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) + diff --git a/toolchain/gcc/patches-14.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-14.x/850-use_shared_libgcc.patch new file mode 100644 index 0000000000..66926ed1b3 --- /dev/null +++ b/toolchain/gcc/patches-14.x/850-use_shared_libgcc.patch @@ -0,0 +1,54 @@ +commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd +Author: Felix Fietkau +Date: Sun Feb 12 20:25:47 2012 +0000 + + gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary + + SVN-Revision: 30486 +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -129,10 +129,6 @@ + "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} " \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) + +-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we +- do not use -lfloat. */ +-#undef LIBGCC_SPEC +- + /* Clear the instruction cache from `beg' to `end'. This is + implemented in lib1funcs.S, so ensure an error if this definition + is used. */ +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -58,6 +58,10 @@ see the files COPYING3 and COPYING.RUNTI + builtin_assert ("system=posix"); \ + } while (0) + ++#ifndef LIBGCC_SPEC ++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}" ++#endif ++ + /* Determine which dynamic linker to use depending on whether GLIBC or + uClibc or Bionic or musl is the default C library and whether + -muclibc or -mglibc or -mbionic or -mmusl has been passed to change +--- a/libgcc/mkmap-symver.awk ++++ b/libgcc/mkmap-symver.awk +@@ -136,5 +136,5 @@ function output(lib) { + else if (inherit[lib]) + printf("} %s;\n", inherit[lib]); + else +- printf ("\n local:\n\t*;\n};\n"); ++ printf ("\n\t*;\n};\n"); + } +--- a/gcc/config/rs6000/linux.h ++++ b/gcc/config/rs6000/linux.h +@@ -70,6 +70,9 @@ + #undef CPP_OS_DEFAULT_SPEC + #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" + ++#undef LIBGCC_SPEC ++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc" ++ + #undef LINK_SHLIB_SPEC + #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \ + %{static-pie:-static -pie --no-dynamic-linker -z text}" diff --git a/toolchain/gcc/patches-14.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-14.x/851-libgcc_no_compat.patch new file mode 100644 index 0000000000..d710e40717 --- /dev/null +++ b/toolchain/gcc/patches-14.x/851-libgcc_no_compat.patch @@ -0,0 +1,22 @@ +commit 64661de100da1ec1061ef3e5e400285dce115e6b +Author: Felix Fietkau +Date: Sun May 10 13:16:35 2015 +0000 + + gcc: add some size optimization patches + + Signed-off-by: Felix Fietkau + + SVN-Revision: 45664 + +--- a/libgcc/config/t-libunwind ++++ b/libgcc/config/t-libunwind +@@ -2,8 +2,7 @@ + + HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER + +-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \ +- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c ++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c + LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c + + # Override the default value from t-slibgcc-elf-ver and mention -lunwind diff --git a/toolchain/gcc/patches-14.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-14.x/870-ppc_no_crtsavres.patch new file mode 100644 index 0000000000..0dca68899e --- /dev/null +++ b/toolchain/gcc/patches-14.x/870-ppc_no_crtsavres.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/rs6000/rs6000-logue.cc ++++ b/gcc/config/rs6000/rs6000-logue.cc +@@ -344,7 +344,7 @@ rs6000_savres_strategy (rs6000_stack_t * + /* Define cutoff for using out-of-line functions to save registers. */ + if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) + { +- if (!optimize_size) ++ if (1) + { + strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; + strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; diff --git a/toolchain/gcc/patches-14.x/881-no_tm_section.patch b/toolchain/gcc/patches-14.x/881-no_tm_section.patch new file mode 100644 index 0000000000..2029910fd0 --- /dev/null +++ b/toolchain/gcc/patches-14.x/881-no_tm_section.patch @@ -0,0 +1,11 @@ +--- a/libgcc/crtstuff.c ++++ b/libgcc/crtstuff.c +@@ -152,7 +152,7 @@ call_ ## FUNC (void) \ + #endif + + #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF) +-# define USE_TM_CLONE_REGISTRY 1 ++# define USE_TM_CLONE_REGISTRY 0 + #elif !defined(USE_TM_CLONE_REGISTRY) + # define USE_TM_CLONE_REGISTRY 0 + #endif diff --git a/toolchain/gcc/patches-14.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-14.x/900-bad-mips16-crt.patch new file mode 100644 index 0000000000..b355545c35 --- /dev/null +++ b/toolchain/gcc/patches-14.x/900-bad-mips16-crt.patch @@ -0,0 +1,9 @@ +--- a/libgcc/config/mips/t-mips16 ++++ b/libgcc/config/mips/t-mips16 +@@ -42,3 +42,6 @@ SYNC_CFLAGS = -mno-mips16 + + # Version these symbols if building libgcc.so. + SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver ++ ++CRTSTUFF_T_CFLAGS += -mno-mips16 ++CRTSTUFF_T_CFLAGS_S += -mno-mips16 diff --git a/toolchain/gcc/patches-14.x/910-mbsd_multi.patch b/toolchain/gcc/patches-14.x/910-mbsd_multi.patch new file mode 100644 index 0000000000..2a58df3cb6 --- /dev/null +++ b/toolchain/gcc/patches-14.x/910-mbsd_multi.patch @@ -0,0 +1,146 @@ +commit 99368862e44740ff4fd33760893f04e14f9dbdf1 +Author: Felix Fietkau +Date: Tue Jul 31 00:52:27 2007 +0000 + + Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly + + SVN-Revision: 8256 + + This patch brings over a feature from MirBSD: + * -fhonour-copts + If this option is not given, it's warned (depending + on environment variables). This is to catch errors + of misbuilt packages which override CFLAGS themselves. + + This patch was authored by Thorsten Glaser + with copyright assignment to the FSF in effect. + +--- a/gcc/c-family/c-opts.cc ++++ b/gcc/c-family/c-opts.cc +@@ -108,6 +108,9 @@ static size_t include_cursor; + /* Whether any standard preincluded header has been preincluded. */ + static bool done_preinclude; + ++/* Check if a port honours COPTS. */ ++static int honour_copts = 0; ++ + static void handle_OPT_d (const char *); + static void set_std_cxx98 (int); + static void set_std_cxx11 (int); +@@ -498,6 +501,12 @@ c_common_handle_option (size_t scode, co + flag_no_builtin = !value; + break; + ++ case OPT_fhonour_copts: ++ if (c_language == clk_c) { ++ honour_copts++; ++ } ++ break; ++ + case OPT_fconstant_string_class_: + constant_string_class_name = arg; + break; +@@ -1291,6 +1300,47 @@ c_common_init (void) + return false; + } + ++ if (c_language == clk_c) { ++ char *ev = getenv ("GCC_HONOUR_COPTS"); ++ int evv; ++ if (ev == NULL) ++ evv = -1; ++ else if ((*ev == '0') || (*ev == '\0')) ++ evv = 0; ++ else if (*ev == '1') ++ evv = 1; ++ else if (*ev == '2') ++ evv = 2; ++ else if (*ev == 's') ++ evv = -1; ++ else { ++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1"); ++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */ ++ } ++ if (evv == 1) { ++ if (honour_copts == 0) { ++ error ("someone does not honour COPTS at all in lenient mode"); ++ return false; ++ } else if (honour_copts != 1) { ++ warning (0, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ } ++ } else if (evv == 2) { ++ if (honour_copts == 0) { ++ error ("someone does not honour COPTS at all in strict mode"); ++ return false; ++ } else if (honour_copts != 1) { ++ error ("someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ return false; ++ } ++ } else if (evv == 0) { ++ if (honour_copts != 1) ++ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ } ++ } ++ + return true; + } + +--- a/gcc/c-family/c.opt ++++ b/gcc/c-family/c.opt +@@ -1910,6 +1910,9 @@ C++ ObjC++ Optimization Alias(fexception + fhonor-std + C++ ObjC++ WarnRemoved + ++fhonour-copts ++C ObjC C++ ObjC++ RejectNegative ++ + fhosted + C ObjC + Assume normal C execution environment. +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -1881,6 +1881,9 @@ Enum(hardcfr_check_noreturn_calls) Strin + EnumValue + Enum(hardcfr_check_noreturn_calls) String(always) Value(HCFRNR_ALWAYS) + ++fhonour-copts ++Common RejectNegative ++ + ; Nonzero means ignore `#ident' directives. 0 means handle them. + ; Generate position-independent code for executables if possible + ; On SVR4 targets, it also controls whether or not to emit a +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -10597,6 +10597,17 @@ This option is only supported for C and + + This warning is upgraded to an error by @option{-pedantic-errors}. + ++@item -fhonour-copts ++@opindex fhonour-copts ++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not ++given at least once, and warn if it is given more than once. ++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not ++given exactly once. ++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option ++is not given exactly once. ++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}. ++This flag and environment variable only affect the C language. ++ + @opindex Wstack-protector + @opindex Wno-stack-protector + @item -Wstack-protector +--- a/gcc/opts.cc ++++ b/gcc/opts.cc +@@ -2833,6 +2833,9 @@ common_handle_option (struct gcc_options + add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg); + break; + ++ case OPT_fhonour_copts: ++ break; ++ + case OPT_Werror: + dc->set_warning_as_error_requested (value); + break; diff --git a/toolchain/gcc/patches-14.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-14.x/920-specs_nonfatal_getenv.patch new file mode 100644 index 0000000000..121b684a2c --- /dev/null +++ b/toolchain/gcc/patches-14.x/920-specs_nonfatal_getenv.patch @@ -0,0 +1,22 @@ +Author: Jo-Philipp Wich +Date: Sat Apr 21 03:02:39 2012 +0000 + + gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset + + SVN-Revision: 31390 + +--- a/gcc/gcc.cc ++++ b/gcc/gcc.cc +@@ -10319,8 +10319,10 @@ getenv_spec_function (int argc, const ch + } + + if (!value) +- fatal_error (input_location, +- "environment variable %qs not defined", varname); ++ { ++ warning (input_location, "environment variable %qs not defined", varname); ++ value = ""; ++ } + + /* We have to escape every character of the environment variable so + they are not interpreted as active spec characters. A diff --git a/toolchain/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch b/toolchain/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch new file mode 100644 index 0000000000..b1d7576328 --- /dev/null +++ b/toolchain/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch @@ -0,0 +1,67 @@ +From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Fri, 4 May 2018 18:20:53 +0800 +Subject: [PATCH] gotools: fix compilation when making cross compiler + +libgo is "the runtime support library for the Go programming language. +This library is intended for use with the Go frontend." + +gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but +the linker will complain that it cannot find it. That's because shared libgcc +is not present in the install directory yet. libgo.so was made without problem +because gcc will emit -lgcc_s when compiled with -shared option. When gotools +were being made, it was supplied with -static-libgcc thus no link option was +provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec +for linking with libgo.so + +- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation +- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html + +When 3-pass GCC compilation is used, shared libgcc runtime libraries will be +available after gcc pass2 completed and will meet the gotools link requirement +at gcc pass3 +--- + gotools/Makefile.am | 4 +++- + gotools/Makefile.in | 4 +++- + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/gotools/Makefile.am ++++ b/gotools/Makefile.am +@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd} + STAMP = echo timestamp > + + libgodir = ../$(target_noncanonical)/libgo ++libgccdir = ../$(target_noncanonical)/libgcc + LIBGODEP = $(libgodir)/libgo.la + + LIBGOTOOL = $(libgodir)/libgotool.a +@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET) + GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) + + AM_GOCFLAGS = -I $(libgodir) +-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs ++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ ++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s + GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ + + libgosrcdir = $(srcdir)/../libgo/go +--- a/gotools/Makefile.in ++++ b/gotools/Makefile.in +@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd + PWD_COMMAND = $${PWDCMD-pwd} + STAMP = echo timestamp > + libgodir = ../$(target_noncanonical)/libgo ++libgccdir = ../$(target_noncanonical)/libgcc + LIBGODEP = $(libgodir)/libgo.la + LIBGOTOOL = $(libgodir)/libgotool.a + @NATIVE_FALSE@GOCOMPILER = $(GOC) +@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a + GOCFLAGS = $(CFLAGS_FOR_TARGET) + GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS) + AM_GOCFLAGS = -I $(libgodir) +-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs ++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \ ++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s + GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@ + libgosrcdir = $(srcdir)/../libgo/go + cmdsrcdir = $(libgosrcdir)/cmd diff --git a/toolchain/gcc/patches-14.x/970-macos_arm64-building-fix.patch b/toolchain/gcc/patches-14.x/970-macos_arm64-building-fix.patch new file mode 100644 index 0000000000..da878df21e --- /dev/null +++ b/toolchain/gcc/patches-14.x/970-macos_arm64-building-fix.patch @@ -0,0 +1,45 @@ +commit 9c6e71079b46ad5433165feaa2001450f2017b56 +Author: Przemysław Buczkowski +Date: Mon Aug 16 13:16:21 2021 +0100 + + GCC: Patch for Apple Silicon compatibility + + This patch fixes a linker error occuring when compiling + the cross-compiler on macOS and ARM64 architecture. + + Adapted from: + https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404 + + Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913 + Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329 + Reviewed-by: John Scipione + Reviewed-by: Adrien Destugues + +--- a/gcc/config/aarch64/aarch64.h ++++ b/gcc/config/aarch64/aarch64.h +@@ -1410,7 +1410,7 @@ extern enum aarch64_code_model aarch64_c + + /* Extra specs when building a native AArch64-hosted compiler. + Option rewriting rules based on host system. */ +-#if defined(__aarch64__) ++#if defined(__aarch64__) && ! defined(__APPLE__) + extern const char *host_detect_local_cpu (int argc, const char **argv); + #define HAVE_LOCAL_CPU_DETECT + # define EXTRA_SPEC_FUNCTIONS \ +--- a/gcc/config/host-darwin.cc ++++ b/gcc/config/host-darwin.cc +@@ -23,6 +23,8 @@ + #include "options.h" + #include "diagnostic-core.h" + #include "config/host-darwin.h" ++#include "hosthooks.h" ++#include "hosthooks-def.h" + #include + + /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the +@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr, + + return 1; + } ++ ++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;