From ede82f35ebede447b4203d660a6f9c643868eb73 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 25 Nov 2023 17:25:18 -0800 Subject: [PATCH 01/34] ath79: qcn: convert to nvmem-layout Allows getting rid of deprecated mac-address-increment. Signed-off-by: Rosen Penev --- .../ath79/dts/qca9563_dlink_covr-p2500-a1.dts | 2 - target/linux/ath79/dts/qcn5502_asus.dtsi | 24 ++++++----- .../ath79/dts/qcn5502_netgear_ex7300-v2.dts | 42 ++++++++++--------- .../ath79/dts/qcn5502_tplink_archer-a9-v6.dts | 40 ++++++++++-------- 4 files changed, 58 insertions(+), 50 deletions(-) diff --git a/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts b/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts index 43113ea7b5..3047c6f479 100644 --- a/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts +++ b/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts @@ -133,8 +133,6 @@ reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; diff --git a/target/linux/ath79/dts/qcn5502_asus.dtsi b/target/linux/ath79/dts/qcn5502_asus.dtsi index a2b4a76e92..ee3ef18d20 100644 --- a/target/linux/ath79/dts/qcn5502_asus.dtsi +++ b/target/linux/ath79/dts/qcn5502_asus.dtsi @@ -85,20 +85,22 @@ reg = <0x050000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_factory_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_factory_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - macaddr_factory_1002: macaddr@1002 { - reg = <0x1002 0x6>; - }; + macaddr_factory_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; - precal_factory_5000: precal@5000 { - reg = <0x5000 0x2f20>; + precal_factory_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts b/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts index 4ebbdcc105..32b97a4601 100644 --- a/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts +++ b/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts @@ -182,20 +182,22 @@ label = "artmtd"; reg = <0xfe0000 0x10000>; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_artmtd_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_artmtd_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_artmtd_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_artmtd_6: macaddr@6 { + reg = <0x6 0x6>; + }; - macaddr_artmtd_c: macaddr@c { - reg = <0xc 0x6>; + macaddr_artmtd_c: macaddr@c { + reg = <0xc 0x6>; + }; }; }; @@ -204,16 +206,18 @@ reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts b/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts index ef0ea321e0..6266f5561b 100644 --- a/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts +++ b/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts @@ -88,7 +88,7 @@ phy-mode = "sgmii"; phy-handle = <&phy0>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; @@ -118,10 +118,8 @@ compatible = "pci168c,0046"; reg = <0 0 0 0 0>; - nvmem-cells = <&macaddr_info_8>, <&precal_art_5000>; + nvmem-cells = <&macaddr_info_8 (-1)>, <&precal_art_5000>; nvmem-cell-names = "mac-address", "pre-calibration"; - - mac-address-increment = <(-1)>; }; }; @@ -162,16 +160,18 @@ reg = <0x050000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; }; @@ -180,12 +180,16 @@ reg = <0x060000 0x020000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_info_8: macaddr@8 { - reg = <0x8 0x6>; + macaddr_info_8: macaddr@8 { + compatible = "mac-base"; + reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -234,6 +238,6 @@ /* TODO: missing support in ath9k */ status = "disabled"; - nvmem-cells = <&cal_art_1000>, <&macaddr_info_8>; + nvmem-cells = <&cal_art_1000>, <&macaddr_info_8 0>; nvmem-cell-names = "calibration", "mac-address"; }; From de1d9da150a5381e8cbc363be892ebb698188db8 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 25 Nov 2023 17:36:49 -0800 Subject: [PATCH 02/34] ath79: tp9343: convert to nvmem-layout Allows getting rid of deprecated mac-address-increment. Signed-off-by: Rosen Penev --- .../ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi | 3 +- .../ath79/dts/tp9343_tplink_tl-wr940n-v4.dts | 2 +- .../ath79/dts/tp9343_tplink_tl-wr940n-v6.dts | 2 +- .../ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts | 29 ++++++++++--------- .../linux/ath79/dts/tp9343_tplink_tl-wx.dtsi | 27 ++++++++--------- 5 files changed, 32 insertions(+), 31 deletions(-) diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi index b2c009c346..b38cd41817 100644 --- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi +++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi @@ -63,7 +63,6 @@ }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts index daf7779314..f837dccff9 100644 --- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts +++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts @@ -66,6 +66,6 @@ }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts index 409f288f07..ccb3bb1670 100644 --- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts +++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts @@ -30,6 +30,6 @@ }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts index d4638f1acf..61adc08289 100644 --- a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts +++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts @@ -120,6 +120,18 @@ label = "config"; reg = <0x750000 0x0a0000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_8: macaddr@8 { + compatible = "mac-base"; + reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; art: partition@7f0000 { @@ -136,15 +148,14 @@ phy-handle = <&swphy0>; - nvmem-cells = <&macaddr_config_8>; + nvmem-cells = <&macaddr_config_8 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_config_8>; + nvmem-cells = <&macaddr_config_8 0>; nvmem-cell-names = "mac-address"; }; @@ -152,16 +163,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_config_8>; + nvmem-cells = <&macaddr_config_8 0>; nvmem-cell-names = "mac-address"; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_8: macaddr@8 { - reg = <0x8 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi b/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi index 3a38b8025a..89dff43405 100644 --- a/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi +++ b/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi @@ -28,6 +28,18 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; + reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@20000 { @@ -50,9 +62,8 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { @@ -63,16 +74,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; From 9783340af9db3be4e21d89426090c394a3074856 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 25 Nov 2023 19:31:17 -0800 Subject: [PATCH 03/34] ath79: ar: convert to nvmem-layout Will allow removing deprecated mac-address-increment. Signed-off-by: Rosen Penev --- .../linux/ath79/dts/ar7161_aruba_ap-105.dts | 1 - .../linux/ath79/dts/ar7161_aruba_ap-175.dts | 20 +++---- .../dts/ar7161_buffalo_wzr-hp-ag300h.dtsi | 28 +++++----- .../ath79/dts/ar7161_dlink_dir-825-b1.dts | 1 - .../linux/ath79/dts/ar7161_jjplus_ja76pf2.dts | 19 ++++--- target/linux/ath79/dts/ar7161_meraki_mr16.dts | 20 +++---- .../ath79/dts/ar7161_netgear_wndap360.dts | 36 +++++++------ .../ath79/dts/ar7161_netgear_wndr3700-v2.dts | 52 +++++++++---------- .../ath79/dts/ar7161_netgear_wndr3700.dts | 52 +++++++++---------- .../ath79/dts/ar7161_netgear_wndr3800.dts | 52 +++++++++---------- .../ath79/dts/ar7161_netgear_wndr3800ch.dts | 52 +++++++++---------- .../ath79/dts/ar7161_netgear_wndrmac-v1.dts | 52 +++++++++---------- .../ath79/dts/ar7161_netgear_wndrmac-v2.dts | 52 +++++++++---------- .../linux/ath79/dts/ar7161_ruckus_gd11.dtsi | 18 ------- .../linux/ath79/dts/ar7161_ruckus_zf7341.dts | 20 +++++++ .../linux/ath79/dts/ar7161_ruckus_zf7351.dts | 20 +++++++ .../linux/ath79/dts/ar7161_ruckus_zf7363.dts | 22 +++++++- .../ath79/dts/ar7240_buffalo_whr-g301n.dts | 20 +++---- .../ath79/dts/ar7240_engenius_enh202-v1.dts | 12 +++-- .../ath79/dts/ar7240_netgear_wnr1000-v2.dts | 28 +++++----- .../ath79/dts/ar7240_netgear_wnr612-v2.dtsi | 28 +++++----- .../ath79/dts/ar7240_openmesh_om2p-v1.dts | 24 +++++---- .../linux/ath79/dts/ar7240_ruckus_zf7025.dts | 36 ++++++------- target/linux/ath79/dts/ar7240_tplink.dtsi | 20 +++---- .../ath79/dts/ar7241_netgear_wnr2000-v3.dts | 28 +++++----- .../ath79/dts/ar7241_netgear_wnr2200-16m.dts | 28 +++++----- .../ath79/dts/ar7241_netgear_wnr2200-8m.dts | 28 +++++----- target/linux/ath79/dts/ar7241_tplink.dtsi | 20 +++---- .../ath79/dts/ar7241_tplink_tl-wr842n-v1.dts | 20 +++---- .../dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts | 24 +++++---- .../linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi | 18 ++++--- .../ath79/dts/ar7242_buffalo_bhr-4grv.dts | 12 +++-- .../dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts | 18 ++++--- .../ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts | 12 +++-- .../ath79/dts/ar7242_engenius_eap350-v1.dts | 12 +++-- .../ath79/dts/ar7242_engenius_ecb350-v1.dts | 12 +++-- target/linux/ath79/dts/ar7242_meraki_mr12.dts | 20 +++---- .../ath79/dts/ar7242_tplink_tl-wr2543-v1.dts | 40 +++++++------- .../ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts | 10 ---- .../ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts | 10 ---- target/linux/ath79/dts/ar7242_ubnt_sw.dtsi | 24 +++++---- target/linux/ath79/dts/ar724x_ubnt_xm.dtsi | 28 +++++----- .../dts/ar9132_buffalo_wzr-hp-g300nh.dtsi | 20 +++---- .../ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts | 20 +++---- .../dts/ar9132_tplink_tl-wr1043nd-v1.dts | 20 +++---- .../ath79/dts/ar9132_tplink_tl-wr941-v2.dts | 20 +++---- .../ath79/dts/ar9330_glinet_gl-ar150.dts | 20 +++---- .../linux/ath79/dts/ar9330_openmesh_om2p.dtsi | 28 +++++----- target/linux/ath79/dts/ar9330_pqi_air-pen.dts | 28 +++++----- .../linux/ath79/dts/ar9330_ziking_cpe46b.dts | 20 +++---- .../ath79/dts/ar9331_8dev_carambola2.dts | 28 +++++----- .../ath79/dts/ar9331_alfa-network_ap121f.dtsi | 24 +++++---- .../linux/ath79/dts/ar9331_etactica_eg200.dts | 20 +++---- target/linux/ath79/dts/ar9331_glinet_6408.dts | 20 +++---- target/linux/ath79/dts/ar9331_glinet_6416.dts | 20 +++---- .../linux/ath79/dts/ar9331_glinet_gl-mifi.dts | 20 +++---- .../ath79/dts/ar9331_glinet_gl-usb150.dts | 20 +++---- .../ath79/dts/ar9331_hak5_lan-turtle.dtsi | 20 +++---- .../dts/ar9331_hak5_wifi-pineapple-nano.dts | 20 +++---- .../linux/ath79/dts/ar9331_hiwifi_hc6361.dts | 1 - target/linux/ath79/dts/ar9331_onion_omega.dts | 20 +++---- .../linux/ath79/dts/ar9331_pisen_ts-d084.dts | 20 +++---- .../linux/ath79/dts/ar9331_pisen_wmm003n.dts | 20 +++---- .../ath79/dts/ar9331_teltonika_rut230-v1.dts | 20 +++---- .../ath79/dts/ar9331_tplink_tl-mr3020-v1.dts | 20 +++---- .../ath79/dts/ar9331_tplink_tl-mr3040-v2.dts | 20 +++---- .../dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi | 20 +++---- .../ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi | 20 +++---- .../dts/ar9331_tplink_tl-wr741nd-v4.dtsi | 20 +++---- .../ath79/dts/ar9341_engenius_eap300-v2.dts | 12 +++-- .../dts/ar9341_engenius_ens202ext-v1.dts | 12 +++-- .../ath79/dts/ar9341_openmesh_om2p-hs.dtsi | 28 +++++----- target/linux/ath79/dts/ar9341_pcs_cr3000.dts | 20 +++---- .../linux/ath79/dts/ar9341_pisen_wmb001n.dts | 20 +++---- .../ath79/dts/ar9341_tplink_tl-mr3420-v2.dts | 20 +++---- .../linux/ath79/dts/ar9341_tplink_tl-wa.dtsi | 20 +++---- .../ath79/dts/ar9341_tplink_tl-wr841-v8.dts | 20 +++---- .../ath79/dts/ar9341_tplink_tl-wr842n-v2.dts | 20 +++---- .../ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts | 20 +++---- .../linux/ath79/dts/ar9342_ruckus_zf7321.dts | 20 +++++++ .../ath79/dts/ar9342_ubnt_aircube-ac.dts | 24 +++++---- target/linux/ath79/dts/ar9342_ubnt_wa.dtsi | 20 +++---- target/linux/ath79/dts/ar9342_ubnt_xw.dtsi | 20 +++---- .../linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi | 20 +++---- .../ath79/dts/ar9344_aerohive_hiveap-121.dts | 20 +++---- .../ath79/dts/ar9344_alfa-network_n5q.dts | 30 ++++++----- .../dts/ar9344_araknis_an-300-ap-i-n.dts | 24 +++++---- .../linux/ath79/dts/ar9344_atheros_db120.dts | 30 ++++++----- .../ath79/dts/ar9344_comfast_cf-e120a-v3.dts | 28 +++++----- .../ath79/dts/ar9344_compex_wpj344-16m.dts | 20 +++---- .../ath79/dts/ar9344_devolo_dlan_wifi.dtsi | 20 +++---- .../linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi | 20 +++---- .../ath79/dts/ar9344_engenius_eap600.dts | 24 +++++---- .../ath79/dts/ar9344_engenius_ecb600.dts | 24 +++++---- .../linux/ath79/dts/ar9344_netgear_pgzng1.dts | 24 +++++---- .../linux/ath79/dts/ar9344_netgear_r6100.dts | 52 +++++++++---------- .../linux/ath79/dts/ar9344_netgear_wndr.dtsi | 44 ++++++++-------- .../linux/ath79/dts/ar9344_ocedo_raccoon.dts | 36 +++++++------ .../ath79/dts/ar9344_openmesh_mr600.dtsi | 24 +++++---- .../ath79/dts/ar9344_openmesh_om5p-an.dts | 24 +++++---- .../linux/ath79/dts/ar9344_openmesh_om5p.dts | 28 +++++----- target/linux/ath79/dts/ar9344_pcs_cap324.dts | 20 +++---- target/linux/ath79/dts/ar9344_pcs_cr5000.dts | 28 +++++----- .../ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts | 10 ---- .../ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts | 10 ---- .../ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts | 10 ---- .../ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts | 10 ---- .../linux/ath79/dts/ar9344_qxwlan_e750x.dtsi | 10 ++++ .../linux/ath79/dts/ar9344_ruckus_zf7372.dts | 28 ++++++++-- .../linux/ath79/dts/ar9344_samsung_wam250.dts | 20 +++---- .../ath79/dts/ar9344_teltonika_rut9xx.dtsi | 20 +++---- target/linux/ath79/dts/ar9344_tplink_cpe.dtsi | 20 +++---- .../ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi | 48 ++++++++--------- .../ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts | 20 +++---- .../ath79/dts/ar9344_ubnt_unifi-ap-pro.dts | 24 +++++---- .../ath79/dts/ar9344_watchguard_ap100.dts | 24 +++++---- .../ath79/dts/ar9344_watchguard_ap200.dts | 24 +++++---- .../ath79/dts/ar9344_winchannel_wb2000.dts | 30 ++++++----- .../ath79/dts/ar9344_zbtlink_zbt-wd323.dts | 28 +++++----- .../linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi | 18 ------- 120 files changed, 1419 insertions(+), 1349 deletions(-) diff --git a/target/linux/ath79/dts/ar7161_aruba_ap-105.dts b/target/linux/ath79/dts/ar7161_aruba_ap-105.dts index 32d403fe6c..c8510a8944 100644 --- a/target/linux/ath79/dts/ar7161_aruba_ap-105.dts +++ b/target/linux/ath79/dts/ar7161_aruba_ap-105.dts @@ -159,7 +159,6 @@ hwinfo: partition@fe0000 { reg = <0xfe0000 0x10000>; - compatible = "nvmem-cells"; label = "hwinfo"; read-only; diff --git a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts index dd29a687ba..14b5edb096 100644 --- a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts +++ b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts @@ -187,6 +187,16 @@ label = "hwinfo"; reg = <0xfe0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_hwinfo_1c: macaddr@1c { + reg = <0x1c 0x6>; + }; + }; }; partition@ff0000 { @@ -198,16 +208,6 @@ }; }; -&hwinfo { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_hwinfo_1c: macaddr@1c { - reg = <0x1c 0x6>; - }; -}; - &i2c0 { gpio_ext: gpio@21 { status = "okay"; diff --git a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi index 6e1ba2d47e..26147a2c80 100644 --- a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi +++ b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi @@ -148,6 +148,20 @@ label = "art"; reg = <0x0050000 0x0010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_120c: macaddr@120c { + reg = <0x120c 0x6>; + }; + + macaddr_art_520c: macaddr@520c { + reg = <0x520c 0x6>; + }; + }; }; partition@60000 { @@ -246,17 +260,3 @@ phy-handle = <&phy4>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_120c: macaddr@120c { - reg = <0x120c 0x6>; - }; - - macaddr_art_520c: macaddr@520c { - reg = <0x520c 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts index bdb678298d..b62111c110 100644 --- a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts +++ b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts @@ -186,7 +186,6 @@ }; partition@660000 { - compatible = "nvmem-cells"; label = "caldata"; reg = <0x660000 0x010000>; read-only; diff --git a/target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts b/target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts index 7f2a118b84..2d21a54fa9 100644 --- a/target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts +++ b/target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts @@ -158,16 +158,19 @@ label = "Atheros Board Data"; reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - macaddr_wan: macaddr@1000 { - reg = <0x1000 0x6>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_lan: macaddr@1006 { - reg = <0x1006 0x6>; + macaddr_wan: macaddr@1000 { + reg = <0x1000 0x6>; + }; + + macaddr_lan: macaddr@1006 { + reg = <0x1006 0x6>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar7161_meraki_mr16.dts b/target/linux/ath79/dts/ar7161_meraki_mr16.dts index 7a19da82e3..110f1ba2df 100644 --- a/target/linux/ath79/dts/ar7161_meraki_mr16.dts +++ b/target/linux/ath79/dts/ar7161_meraki_mr16.dts @@ -141,6 +141,16 @@ label = "config"; reg = <0x80000 0x20000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_66: macaddr@66 { + reg = <0x66 0x6>; + }; + }; }; partition@a0000 { @@ -157,13 +167,3 @@ }; }; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_66: macaddr@66 { - reg = <0x66 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts index 21dc423c35..7baae2450b 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts @@ -112,28 +112,30 @@ reg = <0x7f0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_120c: macaddr@120c { - reg = <0x120c 0x6>; - }; + macaddr_art_120c: macaddr@120c { + reg = <0x120c 0x6>; + }; - macaddr_art_520c: macaddr@520c { - reg = <0x520c 0x6>; - }; + macaddr_art_520c: macaddr@520c { + reg = <0x520c 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0xeb8>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0xeb8>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0xeb8>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0xeb8>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts index 351d5e0364..5b44505ce2 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts @@ -35,6 +35,32 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -57,29 +83,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts index eedd375cc9..6b89fcd0ff 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts @@ -35,6 +35,32 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -76,29 +102,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts index 487b00b0dd..cf23786ae3 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts @@ -36,6 +36,32 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -58,29 +84,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts index 0c2eadae5c..72b169fc76 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts @@ -36,6 +36,32 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -58,29 +84,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts index 88c3170c6e..2e141d07e5 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts @@ -35,6 +35,32 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -57,29 +83,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts index 0536ecb053..83b8f216cc 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts @@ -36,6 +36,32 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0xeb8>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0xeb8>; + }; + }; }; }; @@ -58,29 +84,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0xeb8>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0xeb8>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi b/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi index e97e31e58e..065068571c 100644 --- a/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi +++ b/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi @@ -223,21 +223,3 @@ &usb_phy { status = "okay"; }; - -&board_data { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_bdata_60: macaddr@60 { - reg = <0x60 0x6>; - }; - - macaddr_bdata_66: macaddr@66 { - reg = <0x66 0x6>; - }; - - macaddr_bdata_76: macaddr@76 { - reg = <0x76 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7161_ruckus_zf7341.dts b/target/linux/ath79/dts/ar7161_ruckus_zf7341.dts index 17735e596f..eacda20c61 100644 --- a/target/linux/ath79/dts/ar7161_ruckus_zf7341.dts +++ b/target/linux/ath79/dts/ar7161_ruckus_zf7341.dts @@ -6,3 +6,23 @@ model = "Ruckus ZoneFlex 7341[-U]"; compatible = "ruckus,zf7341", "qca,ar7161"; }; + +&board_data { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdata_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_bdata_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + macaddr_bdata_76: macaddr@76 { + reg = <0x76 0x6>; + }; + }; +}; diff --git a/target/linux/ath79/dts/ar7161_ruckus_zf7351.dts b/target/linux/ath79/dts/ar7161_ruckus_zf7351.dts index 37ea305790..adaeb18eda 100644 --- a/target/linux/ath79/dts/ar7161_ruckus_zf7351.dts +++ b/target/linux/ath79/dts/ar7161_ruckus_zf7351.dts @@ -113,3 +113,23 @@ gpio-hog; }; }; + +&board_data { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdata_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_bdata_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + macaddr_bdata_76: macaddr@76 { + reg = <0x76 0x6>; + }; + }; +}; diff --git a/target/linux/ath79/dts/ar7161_ruckus_zf7363.dts b/target/linux/ath79/dts/ar7161_ruckus_zf7363.dts index 4ece56dd0a..723e4d9a3b 100644 --- a/target/linux/ath79/dts/ar7161_ruckus_zf7363.dts +++ b/target/linux/ath79/dts/ar7161_ruckus_zf7363.dts @@ -33,7 +33,25 @@ }; &board_data { - macaddr_bdata_6c: macaddr@6c { - reg = <0x6c 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdata_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_bdata_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + macaddr_bdata_6c: macaddr@6c { + reg = <0x6c 0x6>; + }; + + macaddr_bdata_76: macaddr@76 { + reg = <0x76 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts index cf51078bc3..1285cdb609 100644 --- a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts +++ b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts @@ -147,6 +147,16 @@ reg = <0x3f0000 0x10000>; label = "art"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_120c: macaddr@120c { + reg = <0x120c 0x6>; + }; + }; }; }; }; @@ -184,13 +194,3 @@ pinctrl-single,bits = <0x0 0x0 0xf8>; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_120c: macaddr@120c { - reg = <0x120c 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts b/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts index 9a233c836b..ec3a371850 100644 --- a/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts +++ b/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts @@ -96,11 +96,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts index 91b72cf1db..d1cdf56d18 100644 --- a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts +++ b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts @@ -168,6 +168,20 @@ label = "art"; reg = <0x3f0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -199,17 +213,3 @@ gpio-controller; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi index 9bae95b557..d069f14235 100644 --- a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi +++ b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi @@ -101,6 +101,20 @@ reg = <0x3f0000 0x10000>; label = "art"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -132,17 +146,3 @@ gpio-controller; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts b/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts index a66d914015..17a5744661 100644 --- a/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts +++ b/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts @@ -127,20 +127,22 @@ reg = <0xfc0000 0x040000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts b/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts index 9e0671d638..f5d0a9e3b0 100644 --- a/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts +++ b/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts @@ -150,6 +150,24 @@ reg = <0xfc0000 0x40000>; label = "board-data"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_board_data_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_board_data_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + macaddr_board_data_6c: macaddr@6c { + reg = <0x6c 0x6>; + }; + }; }; }; }; @@ -176,21 +194,3 @@ nvmem-cell-names = "mac-address"; }; }; - -&board_data { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_board_data_60: macaddr@60 { - reg = <0x60 0x6>; - }; - - macaddr_board_data_66: macaddr@66 { - reg = <0x66 0x6>; - }; - - macaddr_board_data_6c: macaddr@6c { - reg = <0x6c 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7240_tplink.dtsi b/target/linux/ath79/dts/ar7240_tplink.dtsi index 60cd38c220..959032640a 100644 --- a/target/linux/ath79/dts/ar7240_tplink.dtsi +++ b/target/linux/ath79/dts/ar7240_tplink.dtsi @@ -77,6 +77,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -116,13 +126,3 @@ pinctrl-single,bits = <0x0 0x0 0xf8>; }; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts index 290871d648..61886c6589 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts @@ -171,6 +171,20 @@ label = "art"; reg = <0x3f0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -204,17 +218,3 @@ gpio-controller; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts index f5c060d780..42942834cf 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts @@ -35,6 +35,20 @@ label = "art"; reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; @@ -53,17 +67,3 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <1>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts index e47336e4d2..95217f6a7b 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts @@ -35,6 +35,20 @@ label = "art"; reg = <0x7f0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; @@ -53,17 +67,3 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <1>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_tplink.dtsi b/target/linux/ath79/dts/ar7241_tplink.dtsi index 0861cc6232..fe3f047dc1 100644 --- a/target/linux/ath79/dts/ar7241_tplink.dtsi +++ b/target/linux/ath79/dts/ar7241_tplink.dtsi @@ -64,6 +64,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -106,13 +116,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts index 6ee7d9ec4f..02b96912ba 100644 --- a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts +++ b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts @@ -102,6 +102,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -146,13 +156,3 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <1>; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts b/target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts index 3f965ec9de..e3c8f2a609 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts +++ b/target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts @@ -87,20 +87,22 @@ reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0xeb8>; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0xeb8>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi b/target/linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi index 02166a26eb..d9c7336f91 100644 --- a/target/linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi +++ b/target/linux/ath79/dts/ar7241_ubnt_unifi-ap.dtsi @@ -73,16 +73,18 @@ reg = <0x7f0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts b/target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts index dde9129505..c17a8df6fe 100644 --- a/target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts +++ b/target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts @@ -20,11 +20,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts index 4a2f749cc4..ac4c096961 100644 --- a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts +++ b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts @@ -138,16 +138,18 @@ label = "art"; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_120c: macaddr@120c { - reg = <0x120c 0x6>; - }; + macaddr_art_120c: macaddr@120c { + reg = <0x120c 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0xeb8>; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0xeb8>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts index 84d029b5dc..81290479b0 100644 --- a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts +++ b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts @@ -83,11 +83,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts index 7458685802..361d70eb39 100644 --- a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts +++ b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts @@ -88,11 +88,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts index f1f86019dd..2de6dab20d 100644 --- a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts +++ b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts @@ -88,11 +88,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar7242_meraki_mr12.dts b/target/linux/ath79/dts/ar7242_meraki_mr12.dts index 42b4966e74..070cea1217 100644 --- a/target/linux/ath79/dts/ar7242_meraki_mr12.dts +++ b/target/linux/ath79/dts/ar7242_meraki_mr12.dts @@ -140,6 +140,16 @@ label = "config"; reg = <0x80000 0x20000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_66: macaddr@66 { + reg = <0x66 0x6>; + }; + }; }; partition@a0000 { @@ -156,13 +166,3 @@ }; }; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_66: macaddr@66 { - reg = <0x66 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts index e250f2a5b4..8df1fdb4dd 100644 --- a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts +++ b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts @@ -107,6 +107,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -119,6 +129,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; + }; }; }; }; @@ -157,23 +177,3 @@ full-duplex; }; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; -}; diff --git a/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts b/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts index b353e76028..3d8f56a856 100644 --- a/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts +++ b/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts @@ -75,13 +75,3 @@ full-duplex; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts b/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts index 2ee7ab56c5..d5625fefce 100644 --- a/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts +++ b/target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts @@ -186,13 +186,3 @@ full-duplex; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi b/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi index 0268146b06..9d4ab231cc 100644 --- a/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi +++ b/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi @@ -104,6 +104,20 @@ reg = <0x7f0000 0x010000>; label = "art"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -127,13 +141,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi index 341d0bad0d..d9b01e17e3 100644 --- a/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi +++ b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi @@ -62,6 +62,20 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -89,17 +103,3 @@ nvmem-cells = <&macaddr_art_6>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi index ac3af13457..0eb38b5712 100644 --- a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi +++ b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi @@ -137,6 +137,16 @@ label = "art"; reg = <0x1fe0000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_1120c: macaddr@1120c { + reg = <0x1120c 0x6>; + }; + }; }; }; }; @@ -250,13 +260,3 @@ &usb_phy { status = "okay"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_1120c: macaddr@1120c { - reg = <0x1120c 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts index fd4a6c7a4d..476f3e18a3 100644 --- a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts +++ b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts @@ -73,6 +73,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@1 { @@ -121,13 +131,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts index 6eb2a0acb5..a4d19ce970 100644 --- a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts +++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts @@ -99,6 +99,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -136,13 +146,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts index 106ca56e7e..41e53e1fc8 100644 --- a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts +++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts @@ -122,6 +122,16 @@ label = "u-boot"; reg = <0x000000 0x20000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -158,13 +168,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts index b31d0f961b..7401cd053a 100644 --- a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts +++ b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts @@ -105,6 +105,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -138,13 +148,3 @@ nvmem-cells = <&macaddr_art_0>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi index e010e5cad0..a7fd10bd73 100644 --- a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi +++ b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi @@ -122,6 +122,20 @@ label = "ART"; reg = <0xfc0000 0x040000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -146,17 +160,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts index 5383d65884..a2665519f4 100644 --- a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts +++ b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts @@ -86,6 +86,20 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_2: macaddr@2 { + reg = <0x2 0x6>; + }; + + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; + }; }; partition@60000 { @@ -136,17 +150,3 @@ nvmem-cells = <&macaddr_art_2>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_2: macaddr@2 { - reg = <0x2 0x6>; - }; - - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts index 5801044f4e..f2bd0541c1 100644 --- a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts +++ b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts @@ -78,6 +78,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -103,13 +113,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts index d99e0a422a..f786f425f0 100644 --- a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts +++ b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts @@ -92,6 +92,20 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -124,17 +138,3 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi b/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi index 2be7cdb05d..98de255332 100644 --- a/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi +++ b/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi @@ -101,20 +101,22 @@ reg = <0x040000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9331_etactica_eg200.dts b/target/linux/ath79/dts/ar9331_etactica_eg200.dts index 402fca80a1..5a96d50940 100644 --- a/target/linux/ath79/dts/ar9331_etactica_eg200.dts +++ b/target/linux/ath79/dts/ar9331_etactica_eg200.dts @@ -109,6 +109,16 @@ art: art@ff0000 { reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -118,13 +128,3 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_glinet_6408.dts b/target/linux/ath79/dts/ar9331_glinet_6408.dts index 0d3b7d6410..eae6be3004 100644 --- a/target/linux/ath79/dts/ar9331_glinet_6408.dts +++ b/target/linux/ath79/dts/ar9331_glinet_6408.dts @@ -28,6 +28,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -61,13 +71,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_glinet_6416.dts b/target/linux/ath79/dts/ar9331_glinet_6416.dts index 91b7cc0c1c..62d0acbf5d 100644 --- a/target/linux/ath79/dts/ar9331_glinet_6416.dts +++ b/target/linux/ath79/dts/ar9331_glinet_6416.dts @@ -28,6 +28,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -61,13 +71,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts index e5460b299d..211c565c24 100644 --- a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts +++ b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts @@ -113,6 +113,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -144,13 +154,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts index 6f332dd99b..541b73850a 100644 --- a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts +++ b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts @@ -108,6 +108,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -118,13 +128,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi b/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi index 69d974eb53..32ff360e89 100644 --- a/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi +++ b/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi @@ -68,6 +68,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -92,13 +102,3 @@ &usb_phy { status = "okay"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts b/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts index 0502d5d14c..5701dff64c 100644 --- a/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts +++ b/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts @@ -102,6 +102,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -120,13 +130,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts index fa000ab90c..3751374af6 100644 --- a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts +++ b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts @@ -77,7 +77,6 @@ }; bdinfo: partition@10000 { - compatible = "nvmem-cells"; reg = <0x10000 0x10000>; label = "bdinfo"; read-only; diff --git a/target/linux/ath79/dts/ar9331_onion_omega.dts b/target/linux/ath79/dts/ar9331_onion_omega.dts index 09e4234194..f1bb5cbd74 100644 --- a/target/linux/ath79/dts/ar9331_onion_omega.dts +++ b/target/linux/ath79/dts/ar9331_onion_omega.dts @@ -100,6 +100,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -125,13 +135,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts b/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts index 58ef4ab091..4868ba2fa0 100644 --- a/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts +++ b/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts @@ -55,6 +55,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; firmware: partition@20000 { @@ -106,13 +116,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts b/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts index f438567e52..61cbb1aae2 100644 --- a/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts +++ b/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts @@ -63,6 +63,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; firmware: partition@20000 { @@ -115,13 +125,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts index 26004c1cfd..ba1daa4fb8 100644 --- a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts +++ b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts @@ -144,6 +144,16 @@ label = "config"; reg = <0x20000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; art: partition@30000 { @@ -194,13 +204,3 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <2>; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts index c23e5dac51..7a1a577ed7 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts +++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts @@ -113,6 +113,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -162,13 +172,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts index b0f24bbfa7..b07f9a7820 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts +++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts @@ -108,6 +108,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -151,13 +161,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi index 5fda458fbc..a8608a77e1 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi @@ -60,6 +60,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -114,13 +124,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi index 61ef9fb99f..cd6da59b3d 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi @@ -25,6 +25,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -59,13 +69,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi index 4d3b1dba1d..bffe358602 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi @@ -101,6 +101,16 @@ reg = <0x0 0x20000>; label = "u-boot"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; firmware: partition@20000 { @@ -147,13 +157,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts index 4a993c9301..9ba8932422 100644 --- a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts +++ b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts @@ -57,11 +57,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts index ec574ccf9f..eb304db8a3 100644 --- a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts +++ b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts @@ -88,11 +88,13 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi index 2dfdff03d8..bb6af232fd 100644 --- a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi +++ b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi @@ -132,6 +132,20 @@ label = "ART"; reg = <0xfc0000 0x040000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -156,17 +170,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts index 4e4daef1c8..722ce05014 100644 --- a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts +++ b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts @@ -118,6 +118,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -150,13 +160,3 @@ switch-phy-swap = <1>; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts b/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts index 23b5cf7450..496d6579e7 100644 --- a/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts +++ b/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts @@ -180,6 +180,16 @@ label = "art"; reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -214,13 +224,3 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts index 2ccd50d783..1f089affac 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts @@ -64,6 +64,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -106,13 +116,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi b/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi index 5d5b88c5f3..71e2c7b8d8 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi @@ -32,6 +32,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -75,13 +85,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts index d86571c531..d0f00a4a49 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts @@ -47,6 +47,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -81,13 +91,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts index 0fc3488445..3713998e24 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts @@ -65,6 +65,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -109,13 +119,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts index a61f4a381e..492e46e95c 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts @@ -57,6 +57,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -91,13 +101,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>; nvmem-cell-names = "mac-address"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts b/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts index 7bfc85d086..917dc297fe 100644 --- a/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts +++ b/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts @@ -49,6 +49,26 @@ }; }; +&board_data { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_board_data_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_board_data_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + cal_board_data_41000: cal@41000 { + reg = <0x41000 0x440>; + }; + }; +}; + ð0 { nvmem-cells = <&macaddr_board_data_66>; }; diff --git a/target/linux/ath79/dts/ar9342_ubnt_aircube-ac.dts b/target/linux/ath79/dts/ar9342_ubnt_aircube-ac.dts index 49cf39062a..c3c20985e2 100644 --- a/target/linux/ath79/dts/ar9342_ubnt_aircube-ac.dts +++ b/target/linux/ath79/dts/ar9342_ubnt_aircube-ac.dts @@ -63,20 +63,22 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x844>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi index ba0f7ad23e..d85a07a8dc 100644 --- a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi +++ b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi @@ -70,6 +70,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -81,13 +91,3 @@ ieee80211-freq-limit = <2402000 2482000>; mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi b/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi index ce49c10e5c..899f167748 100644 --- a/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi +++ b/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi @@ -98,6 +98,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -113,13 +123,3 @@ nvmem-cells = <&macaddr_art_0>; nvmem-cell-names = "mac-address"; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi index a05cc2e263..b30d545fa3 100644 --- a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi +++ b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi @@ -92,8 +92,6 @@ reg = <0xfe0000 0x010000>; read-only; - compatible = "nvmem-cells"; - nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -118,16 +116,18 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - calibration_ath9k: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_ath9k: calibration@1000 { + reg = <0x1000 0x440>; + }; - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts index a2ac53b996..1d4be4d316 100644 --- a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts +++ b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts @@ -141,6 +141,16 @@ label = "hw-info"; reg = <0x90000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_hw_info_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; partition@a0000 { @@ -230,13 +240,3 @@ rxdv-delay = <1>; }; }; - -&hw_info { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_hw_info_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts b/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts index ca762c3bca..789bd6df14 100644 --- a/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts +++ b/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts @@ -136,24 +136,26 @@ reg = <0x070000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts index ac39a62679..4838886209 100644 --- a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts +++ b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts @@ -107,19 +107,21 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_atheros_db120.dts b/target/linux/ath79/dts/ar9344_atheros_db120.dts index 8811d4f457..9d50441412 100644 --- a/target/linux/ath79/dts/ar9344_atheros_db120.dts +++ b/target/linux/ath79/dts/ar9344_atheros_db120.dts @@ -140,24 +140,26 @@ reg = <0x7f0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts index 94a82baddc..c53f03235f 100644 --- a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts +++ b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts @@ -100,6 +100,20 @@ label = "art"; reg = <0x010000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; partition@20000 { @@ -139,17 +153,3 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts index e456f1f0e5..21329db258 100644 --- a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts +++ b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts @@ -78,6 +78,16 @@ label = "u-boot"; reg = <0x000000 0x030000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_2e010: macaddr@2e010 { + reg = <0x2e010 0x6>; + }; + }; }; partition@30000 { @@ -143,13 +153,3 @@ phy-mode = "rgmii"; phy-handle = <&phy0>; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_2e010: macaddr@2e010 { - reg = <0x2e010 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi index 1cec662569..f1926cc1eb 100644 --- a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi +++ b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi @@ -116,6 +116,16 @@ label = "art"; reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; + }; }; }; }; @@ -169,13 +179,3 @@ >; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi index 8db1bf5e0c..96235dbbc4 100644 --- a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi +++ b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi @@ -116,8 +116,6 @@ reg = <0xfe0000 0x010000>; read-only; - compatible = "nvmem-cells"; - nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -142,16 +140,18 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; - cal_art_5000: cal@5000 { - reg = <0x5000 0x440>; + cal_art_5000: cal@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_engenius_eap600.dts b/target/linux/ath79/dts/ar9344_engenius_eap600.dts index 618660802c..7e906dd3e2 100644 --- a/target/linux/ath79/dts/ar9344_engenius_eap600.dts +++ b/target/linux/ath79/dts/ar9344_engenius_eap600.dts @@ -48,19 +48,21 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts index 5f6ffb130d..53456d4093 100644 --- a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts +++ b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts @@ -43,19 +43,21 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_netgear_pgzng1.dts b/target/linux/ath79/dts/ar9344_netgear_pgzng1.dts index 5b91dd1e4d..b513a36035 100644 --- a/target/linux/ath79/dts/ar9344_netgear_pgzng1.dts +++ b/target/linux/ath79/dts/ar9344_netgear_pgzng1.dts @@ -289,20 +289,22 @@ reg = <0xffe0000 0x20000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_caldata_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_caldata_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_caldata_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_caldata_6: macaddr@6 { + reg = <0x6 0x6>; + }; - cal_caldata_1000: cal@1000 { - reg = <0x1000 0x440>; + cal_caldata_1000: cal@1000 { + reg = <0x1000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_netgear_r6100.dts b/target/linux/ath79/dts/ar9344_netgear_r6100.dts index 76bd77d4c6..419fa51f61 100644 --- a/target/linux/ath79/dts/ar9344_netgear_r6100.dts +++ b/target/linux/ath79/dts/ar9344_netgear_r6100.dts @@ -130,6 +130,32 @@ label = "caldata"; reg = <0x0020000 0x0040000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_ath9k: calibration@1000 { + reg = <0x1000 0x440>; + }; + + cal_ath10k: calibration@5000 { + reg = <0x5000 0x844>; + }; + + macaddr_caldata_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_caldata_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_caldata_c: macaddr@c { + reg = <0xc 0x6>; + }; + }; }; partition@60000 { @@ -204,29 +230,3 @@ nvmem-cells = <&cal_ath9k>; nvmem-cell-names = "calibration"; }; - -&caldata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - cal_ath9k: calibration@1000 { - reg = <0x1000 0x440>; - }; - - cal_ath10k: calibration@5000 { - reg = <0x5000 0x844>; - }; - - macaddr_caldata_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_caldata_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_caldata_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi b/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi index 331a4c6fa3..d2a3000004 100644 --- a/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi +++ b/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi @@ -127,6 +127,28 @@ label = "caldata"; reg = <0x80000 0x40000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_caldata_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_caldata_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0x440>; + }; + }; }; partition@c0000 { @@ -259,25 +281,3 @@ gpio-controller; }; }; - -&caldata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_caldata_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_caldata_c: macaddr@c { - reg = <0xc 0x6>; - }; - - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0x440>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts b/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts index 11205413f4..39ba2ffc3a 100644 --- a/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts +++ b/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts @@ -114,28 +114,30 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi b/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi index b35d699bdc..b7ec8199e9 100644 --- a/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi +++ b/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi @@ -75,20 +75,22 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts index 6fab2b3219..9a7e5e16ca 100644 --- a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts +++ b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts @@ -153,20 +153,22 @@ reg = <0xff0000 0x010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts index 3e60d05ed3..e3aa19c82d 100644 --- a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts +++ b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts @@ -135,6 +135,20 @@ label = "ART"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -161,17 +175,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_pcs_cap324.dts b/target/linux/ath79/dts/ar9344_pcs_cap324.dts index ea7077d2c8..451b0ecaca 100644 --- a/target/linux/ath79/dts/ar9344_pcs_cap324.dts +++ b/target/linux/ath79/dts/ar9344_pcs_cap324.dts @@ -107,6 +107,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; }; }; @@ -160,13 +170,3 @@ phy-mode = "rgmii"; phy-handle = <&phy0>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts index b5fef91eac..a5fc1160c2 100644 --- a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts +++ b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts @@ -99,6 +99,20 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_5002: macaddr@5002 { + reg = <0x5002 0x6>; + }; + }; }; }; }; @@ -202,17 +216,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_5002: macaddr@5002 { - reg = <0x5002 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts index 7c2f90e72c..31145b3929 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts @@ -49,13 +49,3 @@ reg = <0x070000 0xf90000>; }; }; - -&pridata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_pridata_400: macaddr@400 { - reg = <0x400 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts index 042974610c..f44e7a01be 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts @@ -49,13 +49,3 @@ reg = <0x070000 0x790000>; }; }; - -&pridata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_pridata_400: macaddr@400 { - reg = <0x400 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts index ecc3d8b8cd..6b84cb0ef9 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts @@ -45,13 +45,3 @@ reg = <0x070000 0xf90000>; }; }; - -&pridata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_pridata_400: macaddr@400 { - reg = <0x400 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts index e2152ff464..13aaf322b7 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts @@ -45,13 +45,3 @@ reg = <0x070000 0x790000>; }; }; - -&pridata { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_pridata_400: macaddr@400 { - reg = <0x400 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi index a41e626ea4..0bc735c0a9 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi @@ -85,6 +85,16 @@ label = "pri-data"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_pridata_400: macaddr@400 { + reg = <0x400 0x6>; + }; + }; }; art: partition@60000 { diff --git a/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts b/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts index 2cf7240931..dbccbef023 100644 --- a/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts +++ b/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts @@ -127,11 +127,29 @@ }; &board_data { - macaddr_board_data_6c: macaddr@6c { - reg = <0x6c 0x6>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_board_data_76: macaddr@76 { - reg = <0x76 0x6>; + macaddr_board_data_60: macaddr@60 { + reg = <0x60 0x6>; + }; + + macaddr_board_data_66: macaddr@66 { + reg = <0x66 0x6>; + }; + + macaddr_board_data_6c: macaddr@6c { + reg = <0x6c 0x6>; + }; + + macaddr_board_data_76: macaddr@76 { + reg = <0x76 0x6>; + }; + + cal_board_data_41000: cal@41000 { + reg = <0x41000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_samsung_wam250.dts b/target/linux/ath79/dts/ar9344_samsung_wam250.dts index fd5bf9e81d..4b7bad7873 100644 --- a/target/linux/ath79/dts/ar9344_samsung_wam250.dts +++ b/target/linux/ath79/dts/ar9344_samsung_wam250.dts @@ -137,6 +137,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_1002: macaddr@1002 { + reg = <0x1002 0x6>; + }; + }; }; }; }; @@ -156,13 +166,3 @@ mtd-cal-data = <&art 0x1000>; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_1002: macaddr@1002 { - reg = <0x1002 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi index 937095959c..e8b6e08936 100644 --- a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi +++ b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi @@ -79,6 +79,16 @@ label = "config"; reg = <0x20000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; }; art: partition@30000 { @@ -169,13 +179,3 @@ <0x3c 0x000b0000 0x00ff0000>; }; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_0: macaddr@0 { - reg = <0x0 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi b/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi index 9d8873ddaf..f15c1c320a 100644 --- a/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi +++ b/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi @@ -55,6 +55,16 @@ label = "info"; reg = <0x030000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_info_8: macaddr@8 { + reg = <0x8 0x6>; + }; + }; }; partition@40000 { @@ -116,13 +126,3 @@ line-name = "tp-link:ext:lna1"; }; }; - -&info { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_info_8: macaddr@8 { - reg = <0x8 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi index a2649d19e9..138582166b 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi @@ -83,6 +83,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -95,6 +105,20 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_1000: cal@1000 { + reg = <0x1000 0x440>; + }; + + cal_art_5000: cal@5000 { + reg = <0x5000 0x440>; + }; + }; }; }; }; @@ -118,27 +142,3 @@ nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>; nvmem-cell-names = "mac-address", "calibration"; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - cal_art_1000: cal@1000 { - reg = <0x1000 0x440>; - }; - - cal_art_5000: cal@5000 { - reg = <0x5000 0x440>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts index 49526fb6d2..a3910d512b 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts @@ -95,6 +95,16 @@ label = "u-boot"; reg = <0x000000 0x020000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_1fc00: macaddr@1fc00 { + reg = <0x1fc00 0x6>; + }; + }; }; partition@20000 { @@ -158,13 +168,3 @@ switch-phy-swap = <1>; }; }; - -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_uboot_1fc00: macaddr@1fc00 { - reg = <0x1fc00 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar9344_ubnt_unifi-ap-pro.dts b/target/linux/ath79/dts/ar9344_ubnt_unifi-ap-pro.dts index 55626c4299..2aba2bd2c0 100644 --- a/target/linux/ath79/dts/ar9344_ubnt_unifi-ap-pro.dts +++ b/target/linux/ath79/dts/ar9344_ubnt_unifi-ap-pro.dts @@ -105,20 +105,22 @@ reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts index 0ab10c36ce..b08dce2950 100644 --- a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts +++ b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts @@ -79,19 +79,21 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts index 88c7637fc9..56f0c8e048 100644 --- a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts +++ b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts @@ -76,19 +76,21 @@ }; &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts index cbde191ac7..1ab92c698c 100644 --- a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts +++ b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts @@ -124,16 +124,18 @@ reg = <0xfe0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - calibration_art_1000: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_art_5000: calibration@5000 { - reg = <0x5000 0x440>; + calibration_art_5000: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; @@ -142,12 +144,14 @@ reg = <0xff0000 0x10000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_addr_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_addr_0: macaddr@0 { + reg = <0x0 0x6>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts index 8dc1ceb666..36802a5275 100644 --- a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts +++ b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts @@ -133,6 +133,20 @@ art: art@ff0000 { reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; }; }; @@ -160,17 +174,3 @@ pinctrl-single,bits = <0x14 0x0 0xff00>; }; }; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi b/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi index a0348e7213..d494f9b1ed 100644 --- a/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi +++ b/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi @@ -178,21 +178,3 @@ &usb_phy { status = "okay"; }; - -&board_data { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_board_data_60: macaddr@60 { - reg = <0x60 0x6>; - }; - - macaddr_board_data_66: macaddr@66 { - reg = <0x66 0x6>; - }; - - cal_board_data_41000: cal@41000 { - reg = <0x41000 0x440>; - }; -}; From b7f26c63929da908f83c767689bc25ef161db466 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 25 Nov 2023 20:36:49 -0800 Subject: [PATCH 04/34] ath79: ar: convert to mac-base Replacement for deprecated mac-address-increment Signed-off-by: Rosen Penev --- .../linux/ath79/dts/ar7161_aruba_ap-175.dts | 10 ++++---- .../dts/ar7161_buffalo_wzr-hp-ag300h.dtsi | 5 ++-- target/linux/ath79/dts/ar7161_meraki_mr16.dts | 10 ++++---- .../ath79/dts/ar7161_netgear_wndap360.dts | 5 ++-- .../ath79/dts/ar7240_buffalo_whr-g301n.dts | 9 ++++--- .../ath79/dts/ar7240_netgear_wnr1000-v2.dts | 7 +++--- .../ath79/dts/ar7240_netgear_wnr612-v2.dtsi | 7 +++--- target/linux/ath79/dts/ar7240_tplink.dtsi | 4 ++- .../linux/ath79/dts/ar7240_tplink_tl-wr.dtsi | 6 ++--- .../ath79/dts/ar7241_netgear_wnr2000-v3.dts | 7 +++--- .../ath79/dts/ar7241_netgear_wnr2200-16m.dts | 7 +++--- .../ath79/dts/ar7241_netgear_wnr2200-8m.dts | 7 +++--- target/linux/ath79/dts/ar7241_tplink.dtsi | 9 ++++--- .../ath79/dts/ar7241_tplink_tl-wr842n-v1.dts | 10 ++++---- .../ath79/dts/ar7242_engenius_eap350-v1.dts | 7 +++--- .../ath79/dts/ar7242_engenius_ecb350-v1.dts | 7 +++--- target/linux/ath79/dts/ar7242_meraki_mr12.dts | 9 ++++--- .../linux/ath79/dts/ar9330_ziking_cpe46b.dts | 7 +++--- .../ath79/dts/ar9331_hak5_lan-turtle.dtsi | 8 +++--- target/linux/ath79/dts/ar9331_onion_omega.dts | 7 +++--- .../ath79/dts/ar9331_teltonika_rut230-v1.dts | 10 ++++---- .../ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi | 9 ++++--- .../dts/ar9331_tplink_tl-wr741nd-v4.dtsi | 9 ++++--- target/linux/ath79/dts/ar9341_pcs_cr3000.dts | 7 +++--- .../ath79/dts/ar9341_tplink_tl-mr3420-v2.dts | 9 ++++--- .../ath79/dts/ar9341_tplink_tl-wr841-v8.dts | 9 ++++--- .../ath79/dts/ar9341_tplink_tl-wr842n-v2.dts | 9 ++++--- .../ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts | 9 ++++--- .../ath79/dts/ar9344_aerohive_hiveap-121.dts | 10 ++++---- .../dts/ar9344_araknis_an-300-ap-i-n.dts | 10 ++++---- .../ath79/dts/ar9344_devolo_dlan_wifi.dtsi | 5 ++-- .../ath79/dts/ar9344_engenius_eap600.dts | 10 ++++---- .../ath79/dts/ar9344_engenius_ecb600.dts | 10 ++++---- .../ath79/dts/ar9344_openmesh_mr600.dtsi | 10 ++++---- .../ath79/dts/ar9344_openmesh_om5p-an.dts | 13 +++++----- target/linux/ath79/dts/ar9344_pcs_cap324.dts | 10 ++++---- .../ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts | 5 ++-- .../ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts | 5 ++-- .../ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts | 2 +- .../ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts | 2 +- .../linux/ath79/dts/ar9344_qxwlan_e750x.dtsi | 2 ++ .../linux/ath79/dts/ar9344_samsung_wam250.dts | 7 +++--- .../dts/ar9344_teltonika_rut955-h7v3c0.dts | 5 ++-- .../ath79/dts/ar9344_teltonika_rut955.dts | 5 ++-- .../ath79/dts/ar9344_teltonika_rut9xx.dtsi | 5 ++-- .../ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts | 25 ++++++++++++++----- .../ath79/dts/ar9344_tplink_tl-wdr4300.dtsi | 19 ++++++++++++-- .../ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi | 21 ++-------------- .../ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts | 9 ++++--- .../ath79/dts/ar9344_watchguard_ap100.dts | 8 +++--- .../ath79/dts/ar9344_watchguard_ap200.dts | 11 ++++---- .../ath79/dts/ar9344_winchannel_wb2000.dts | 10 ++++---- 52 files changed, 235 insertions(+), 203 deletions(-) diff --git a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts index 14b5edb096..96a76a3cfc 100644 --- a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts +++ b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts @@ -122,9 +122,8 @@ ath9k0: wifi@0,11 { compatible = "pci168c,0029"; - nvmem-cells = <&macaddr_hwinfo_1c>; + nvmem-cells = <&macaddr_hwinfo_1c 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; reg = <0x8800 0 0 0 0>; #gpio-cells = <2>; gpio-controller; @@ -132,9 +131,8 @@ ath9k1: wifi@0,12 { compatible = "pci168c,0029"; - nvmem-cells = <&macaddr_hwinfo_1c>; + nvmem-cells = <&macaddr_hwinfo_1c 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; reg = <0x9000 0 0 0 0>; #gpio-cells = <2>; gpio-controller; @@ -151,7 +149,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_hwinfo_1c>; + nvmem-cells = <&macaddr_hwinfo_1c 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; @@ -194,7 +192,9 @@ #size-cells = <1>; macaddr_hwinfo_1c: macaddr@1c { + compatible = "mac-base"; reg = <0x1c 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi index 26147a2c80..e3f48fee85 100644 --- a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi +++ b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi @@ -159,7 +159,9 @@ }; macaddr_art_520c: macaddr@520c { + compatible = "mac-base"; reg = <0x520c 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -254,9 +256,8 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_520c>; + nvmem-cells = <&macaddr_art_520c 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; phy-handle = <&phy4>; }; diff --git a/target/linux/ath79/dts/ar7161_meraki_mr16.dts b/target/linux/ath79/dts/ar7161_meraki_mr16.dts index 110f1ba2df..6b8574e880 100644 --- a/target/linux/ath79/dts/ar7161_meraki_mr16.dts +++ b/target/linux/ath79/dts/ar7161_meraki_mr16.dts @@ -74,9 +74,8 @@ compatible = "pci168c,0029"; reg = <0x8800 0 0 0 0>; qca,no-eeprom; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; #gpio-cells = <2>; gpio-controller; }; @@ -85,9 +84,8 @@ compatible = "pci168c,0029"; reg = <0x9000 0 0 0 0>; qca,no-eeprom; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; #gpio-cells = <2>; gpio-controller; }; @@ -103,7 +101,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 0>; nvmem-cell-names = "mac-address"; pll-data = <0x00110000 0x00001099 0x00991099>; @@ -148,7 +146,9 @@ #size-cells = <1>; macaddr_config_66: macaddr@66 { + compatible = "mac-base"; reg = <0x66 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts index 7baae2450b..9761234714 100644 --- a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts +++ b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts @@ -126,7 +126,9 @@ }; macaddr_art_520c: macaddr@520c { + compatible = "mac-base"; reg = <0x520c 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { @@ -157,9 +159,8 @@ ath9k1: wifi@0,12 { compatible = "pci168c,0029"; reg = <0x9000 0 0 0 0>; - nvmem-cells = <&macaddr_art_520c>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_520c 1>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <1>; #gpio-cells = <2>; gpio-controller; }; diff --git a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts index 1285cdb609..ad42e0a05f 100644 --- a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts +++ b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts @@ -154,7 +154,9 @@ #size-cells = <1>; macaddr_art_120c: macaddr@120c { + compatible = "mac-base"; reg = <0x120c 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -163,16 +165,15 @@ }; ð0 { - nvmem-cells = <&macaddr_art_120c>; + nvmem-cells = <&macaddr_art_120c 0>; nvmem-cell-names = "mac-address"; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_120c>; + nvmem-cells = <&macaddr_art_120c 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &pcie { @@ -182,7 +183,7 @@ compatible = "pci168c,002a"; reg = <0x0000 0 0 0 0>; qca,no-eeprom; - nvmem-cells = <&macaddr_art_120c>; + nvmem-cells = <&macaddr_art_120c 0>; nvmem-cell-names = "mac-address"; #gpio-cells = <2>; gpio-controller; diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts index d1cdf56d18..32903c2e8f 100644 --- a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts +++ b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts @@ -175,7 +175,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; macaddr_art_6: macaddr@6 { @@ -188,7 +190,7 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -205,9 +207,8 @@ ath9k: wifi@0,0 { compatible = "pci168c,002b"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; qca,no-eeprom; #gpio-cells = <2>; gpio-controller; diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi index d069f14235..ac27874c68 100644 --- a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi +++ b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi @@ -108,7 +108,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; macaddr_art_6: macaddr@6 { @@ -121,7 +123,7 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -138,9 +140,8 @@ ath9k: wifi@0,0 { compatible = "pci168c,002b"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; qca,no-eeprom; #gpio-cells = <2>; gpio-controller; diff --git a/target/linux/ath79/dts/ar7240_tplink.dtsi b/target/linux/ath79/dts/ar7240_tplink.dtsi index 959032640a..5bcfb54bfc 100644 --- a/target/linux/ath79/dts/ar7240_tplink.dtsi +++ b/target/linux/ath79/dts/ar7240_tplink.dtsi @@ -84,7 +84,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -114,7 +116,7 @@ ath9k: wifi@0,0 { reg = <0x0000 0 0 0 0>; qca,no-eeprom; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; #gpio-cells = <2>; gpio-controller; diff --git a/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi b/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi index 9d896360dc..6c090fb437 100644 --- a/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi +++ b/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi @@ -30,15 +30,13 @@ }; ð0 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &ath9k { diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts index 61886c6589..0a6936c5bf 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts @@ -178,7 +178,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; macaddr_art_6: macaddr@6 { @@ -193,7 +195,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -210,9 +212,8 @@ ath9k: wifi@0,0 { compatible = "pci168c,002e"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; qca,no-eeprom; #gpio-cells = <2>; gpio-controller; diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts index 42942834cf..324207656f 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts @@ -42,7 +42,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; macaddr_art_6: macaddr@6 { @@ -53,7 +55,7 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -63,7 +65,6 @@ }; &ath9k { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts index 95217f6a7b..fbd3cb8ec8 100644 --- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts +++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts @@ -42,7 +42,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; macaddr_art_6: macaddr@6 { @@ -53,7 +55,7 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -63,7 +65,6 @@ }; &ath9k { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; diff --git a/target/linux/ath79/dts/ar7241_tplink.dtsi b/target/linux/ath79/dts/ar7241_tplink.dtsi index fe3f047dc1..01eee39f19 100644 --- a/target/linux/ath79/dts/ar7241_tplink.dtsi +++ b/target/linux/ath79/dts/ar7241_tplink.dtsi @@ -71,7 +71,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -99,7 +101,7 @@ #gpio-cells = <2>; gpio-controller; qca,no-eeprom; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; }; @@ -107,12 +109,11 @@ ð0 { /* WAN interface, initialized last as eth1 */ status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { /* LAN interface, initialized first as eth0 */ - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts index 02b96912ba..e7fe31f36d 100644 --- a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts +++ b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts @@ -109,7 +109,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -138,7 +140,7 @@ #gpio-cells = <2>; gpio-controller; qca,no-eeprom; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; }; @@ -146,13 +148,11 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; diff --git a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts index 361d70eb39..8e8deba933 100644 --- a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts +++ b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts @@ -63,7 +63,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-handle = <&phy4>; @@ -78,9 +78,8 @@ ath9k: wifi@0,0,0 { compatible = "pci168c,002a"; reg = <0x0 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; qca,no-eeprom; #gpio-cells = <2>; gpio-controller; @@ -94,7 +93,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts index 2de6dab20d..69629335b3 100644 --- a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts +++ b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts @@ -63,7 +63,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-handle = <&phy4>; @@ -78,9 +78,8 @@ ath9k: wifi@0,0,0 { compatible = "pci168c,002a"; reg = <0x0 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; qca,no-eeprom; #gpio-cells = <2>; gpio-controller; @@ -94,7 +93,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar7242_meraki_mr12.dts b/target/linux/ath79/dts/ar7242_meraki_mr12.dts index 070cea1217..adea2778ea 100644 --- a/target/linux/ath79/dts/ar7242_meraki_mr12.dts +++ b/target/linux/ath79/dts/ar7242_meraki_mr12.dts @@ -74,9 +74,8 @@ compatible = "pci168c,002a"; reg = <0x0000 0 0 0 0>; qca,no-eeprom; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; }; @@ -91,7 +90,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 0>; nvmem-cell-names = "mac-address"; pll-data = <0x02000000 0x00000101 0x00001313>; @@ -107,7 +106,7 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_config_66>; + nvmem-cells = <&macaddr_config_66 0>; nvmem-cell-names = "mac-address"; }; @@ -147,7 +146,9 @@ #size-cells = <1>; macaddr_config_66: macaddr@66 { + compatible = "mac-base"; reg = <0x66 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts index f2bd0541c1..256fe5f615 100644 --- a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts +++ b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts @@ -85,7 +85,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -96,16 +98,15 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; }; &wmac { diff --git a/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi b/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi index 32ff360e89..565f62a0ba 100644 --- a/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi +++ b/target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi @@ -24,9 +24,8 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; gmac-config { device = <&gmac>; @@ -39,9 +38,8 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &pinmux { @@ -75,7 +73,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar9331_onion_omega.dts b/target/linux/ath79/dts/ar9331_onion_omega.dts index f1bb5cbd74..81fab872b5 100644 --- a/target/linux/ath79/dts/ar9331_onion_omega.dts +++ b/target/linux/ath79/dts/ar9331_onion_omega.dts @@ -72,9 +72,8 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; gmac-config { device = <&gmac>; @@ -107,7 +106,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -132,6 +133,6 @@ mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts index ba1daa4fb8..69965f86a8 100644 --- a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts +++ b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts @@ -109,15 +109,14 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 0>; nvmem-cell-names = "mac-address"; }; @@ -151,7 +150,9 @@ #size-cells = <1>; macaddr_config_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -200,7 +201,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; }; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi index cd6da59b3d..d1336e9689 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi @@ -32,7 +32,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -53,19 +55,18 @@ }; ð0 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi index bffe358602..613b357dc8 100644 --- a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi +++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi @@ -108,7 +108,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -131,9 +133,8 @@ ð0 { /* WAN interface, initialized last as eth1 */ status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; gmac-config { device = <&gmac>; @@ -146,7 +147,7 @@ ð1 { /* LAN interface, initialized first as eth0 */ status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; @@ -154,6 +155,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts index 722ce05014..5ec17034d1 100644 --- a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts +++ b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts @@ -125,7 +125,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -143,16 +145,15 @@ status = "okay"; phy-handle = <&swphy0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { phy-handle = <&swphy4>; pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; gmac-config { diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts index 1f089affac..3971df17f8 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts @@ -71,7 +71,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -100,19 +102,18 @@ }; ð0 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts index d0f00a4a49..417461a595 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts @@ -54,7 +54,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -75,19 +77,18 @@ }; ð0 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; ð1 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts index 3713998e24..d0f4c2e1f5 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts @@ -72,7 +72,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -101,21 +103,20 @@ }; ð0 { - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; ð1 { phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts index 492e46e95c..180504523c 100644 --- a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts +++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts @@ -64,7 +64,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -85,19 +87,18 @@ }; ð0 { // WAN port, initialized last as eth1 - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { // LAN ports, initialized first as eth0 - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts index 1d4be4d316..2a2036201e 100644 --- a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts +++ b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts @@ -106,9 +106,8 @@ compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_hw_info_0>; + nvmem-cells = <&macaddr_hw_info_0 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; }; }; @@ -148,7 +147,9 @@ #size-cells = <1>; macaddr_hw_info_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -171,9 +172,8 @@ &wmac { status = "okay"; - nvmem-cells = <&macaddr_hw_info_0>; + nvmem-cells = <&macaddr_hw_info_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &nand { @@ -227,7 +227,7 @@ pll-data = <0x06000000 0x00000101 0x00001313>; - nvmem-cells = <&macaddr_hw_info_0>; + nvmem-cells = <&macaddr_hw_info_0 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii-id"; diff --git a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts index 4838886209..a45aa444de 100644 --- a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts +++ b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts @@ -72,7 +72,7 @@ ð0 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; @@ -87,9 +87,8 @@ ath9k: wifi@0,0,0 { compatible = "pci168c,0030"; reg = <0x0 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 1>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <1>; ieee80211-freq-limit = <2402000 2482000>; #gpio-cells = <2>; gpio-controller; @@ -101,9 +100,8 @@ ieee80211-freq-limit = <4900000 5990000>; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <2>; }; &art { @@ -113,7 +111,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { diff --git a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi index f1926cc1eb..df157f582c 100644 --- a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi +++ b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi @@ -123,7 +123,9 @@ #size-cells = <1>; macaddr_art_1002: macaddr@1002 { + compatible = "mac-base"; reg = <0x1002 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -140,9 +142,8 @@ pll-data = <0x02000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_art_1002>; + nvmem-cells = <&macaddr_art_1002 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; phy-mode = "rgmii"; phy-handle = <&phy0>; diff --git a/target/linux/ath79/dts/ar9344_engenius_eap600.dts b/target/linux/ath79/dts/ar9344_engenius_eap600.dts index 7e906dd3e2..888e3f82ad 100644 --- a/target/linux/ath79/dts/ar9344_engenius_eap600.dts +++ b/target/linux/ath79/dts/ar9344_engenius_eap600.dts @@ -29,22 +29,20 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-2)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-2)>; }; &pcie { wifi@0,0,0 { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 0>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; }; }; &wmac { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 (-1)>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-1)>; }; &art { @@ -54,7 +52,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { diff --git a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts index 53456d4093..ac9bbea5d4 100644 --- a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts +++ b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts @@ -24,22 +24,20 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; &pcie { wifi@0,0,0 { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 (-2)>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-2)>; }; }; &wmac { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 (-1)>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-1)>; }; &art { @@ -49,7 +47,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { diff --git a/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi b/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi index b7ec8199e9..7661789e2f 100644 --- a/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi +++ b/target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi @@ -81,7 +81,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { @@ -112,7 +114,7 @@ pll-data = <0x02000000 0x00000101 0x00001313>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii-id"; @@ -129,9 +131,8 @@ &wmac { status = "okay"; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 1>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <1>; }; &pcie { @@ -140,9 +141,8 @@ ath9k: wifi@0,0 { compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 8>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <8>; gpio-controller; #gpio-cells = <2>; diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts index 9a7e5e16ca..38153d9dc0 100644 --- a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts +++ b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts @@ -159,7 +159,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { @@ -190,7 +192,7 @@ pll-data = <0x02000000 0x00000101 0x00001313>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii-id"; @@ -208,17 +210,15 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; &wmac { status = "okay"; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <2>; }; &pcie { @@ -227,8 +227,7 @@ wifi@0,0 { compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 16>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <16>; }; }; diff --git a/target/linux/ath79/dts/ar9344_pcs_cap324.dts b/target/linux/ath79/dts/ar9344_pcs_cap324.dts index 451b0ecaca..aab04b080a 100644 --- a/target/linux/ath79/dts/ar9344_pcs_cap324.dts +++ b/target/linux/ath79/dts/ar9344_pcs_cap324.dts @@ -114,7 +114,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -128,9 +130,8 @@ ath9k: wifi@0,0 { compatible = "168c,0030"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-2)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-2)>; mtd-cal-data = <&art 0x5000>; qca,no-eeprom; ieee80211-freq-limit = <2402000 2482000>; @@ -144,9 +145,8 @@ ieee80211-freq-limit = <4900000 5990000>; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; }; &mdio0 { @@ -164,7 +164,7 @@ /* default for ar934x, except for 1000M */ pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts index 31145b3929..33e2990284 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts @@ -24,15 +24,14 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 0>; nvmem-cell-names = "mac-address"; gmac-config { diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts index f44e7a01be..b20d187941 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts @@ -24,15 +24,14 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 0>; nvmem-cell-names = "mac-address"; gmac-config { diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts index 6b84cb0ef9..ed9cd2000a 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts @@ -31,7 +31,7 @@ pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts index 13aaf322b7..5a7feba0b6 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts @@ -31,7 +31,7 @@ pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_pridata_400>; + nvmem-cells = <&macaddr_pridata_400 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi index 0bc735c0a9..238a59cbe8 100644 --- a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi +++ b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi @@ -92,7 +92,9 @@ #size-cells = <1>; macaddr_pridata_400: macaddr@400 { + compatible = "mac-base"; reg = <0x400 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_samsung_wam250.dts b/target/linux/ath79/dts/ar9344_samsung_wam250.dts index 4b7bad7873..0bbd5c92fe 100644 --- a/target/linux/ath79/dts/ar9344_samsung_wam250.dts +++ b/target/linux/ath79/dts/ar9344_samsung_wam250.dts @@ -66,9 +66,8 @@ phy-handle = <&swphy0>; - nvmem-cells = <&macaddr_art_1002>; + nvmem-cells = <&macaddr_art_1002 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; gmac-config { device = <&gmac>; @@ -79,7 +78,7 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_1002>; + nvmem-cells = <&macaddr_art_1002 0>; nvmem-cell-names = "mac-address"; }; @@ -144,7 +143,9 @@ #size-cells = <1>; macaddr_art_1002: macaddr@1002 { + compatible = "mac-base"; reg = <0x1002 0x6>; + #nvmem-cell-cells = <1>; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_teltonika_rut955-h7v3c0.dts b/target/linux/ath79/dts/ar9344_teltonika_rut955-h7v3c0.dts index 2cb8d4015c..b94b44cfc4 100644 --- a/target/linux/ath79/dts/ar9344_teltonika_rut955-h7v3c0.dts +++ b/target/linux/ath79/dts/ar9344_teltonika_rut955-h7v3c0.dts @@ -164,15 +164,14 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9344_teltonika_rut955.dts b/target/linux/ath79/dts/ar9344_teltonika_rut955.dts index 7a1f05afcc..d8ce6a1092 100644 --- a/target/linux/ath79/dts/ar9344_teltonika_rut955.dts +++ b/target/linux/ath79/dts/ar9344_teltonika_rut955.dts @@ -163,15 +163,14 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi index e8b6e08936..64959c9dc2 100644 --- a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi +++ b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi @@ -86,7 +86,9 @@ #size-cells = <1>; macaddr_config_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -154,9 +156,8 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_config_0>; + nvmem-cells = <&macaddr_config_0 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; }; &pinmux { diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts index 1600e12b64..a66e1fefa2 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts @@ -49,16 +49,30 @@ status = "okay"; }; -&ath9k { - mac-address-increment = <1>; +&wmac { + status = "okay"; + nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&pcie { + status = "okay"; + + ath9k: wifi@0,0 { + compatible = "pci168c,0033"; + reg = <0x0000 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + nvmem-cells = <&macaddr_uboot_1fc00 1>, <&cal_art_5000>; + nvmem-cell-names = "mac-address", "calibration"; + }; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; gmac-config { device = <&gmac>; @@ -72,7 +86,6 @@ phy-handle = <&swphy4>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 2>; nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; }; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdr4300.dtsi b/target/linux/ath79/dts/ar9344_tplink_tl-wdr4300.dtsi index d2791aee70..7aa1989290 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wdr4300.dtsi +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdr4300.dtsi @@ -76,7 +76,22 @@ }; &wmac { - mac-address-increment = <(-1)>; + status = "okay"; + nvmem-cells = <&macaddr_uboot_1fc00 (-1)>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&pcie { + status = "okay"; + + ath9k: wifi@0,0 { + compatible = "pci168c,0033"; + reg = <0x0000 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_5000>; + nvmem-cell-names = "mac-address", "calibration"; + }; }; &mdio0 { @@ -104,7 +119,7 @@ /* default for ar934x, except for 1000M */ pll-data = <0x06000000 0x00000101 0x00001616>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; phy-mode = "rgmii"; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi index 138582166b..7f49b9bde7 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi @@ -90,7 +90,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -123,22 +125,3 @@ }; }; }; - -&pcie { - status = "okay"; - - ath9k: wifi@0,0 { - compatible = "pci168c,0033"; - reg = <0x0000 0 0 0 0>; - #gpio-cells = <2>; - gpio-controller; - nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_5000>; - nvmem-cell-names = "mac-address", "calibration"; - }; -}; - -&wmac { - status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>; - nvmem-cell-names = "mac-address", "calibration"; -}; diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts index a3910d512b..6649e2477b 100644 --- a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts +++ b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts @@ -102,7 +102,9 @@ #size-cells = <1>; macaddr_uboot_1fc00: macaddr@1fc00 { + compatible = "mac-base"; reg = <0x1fc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -143,7 +145,7 @@ mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; }; @@ -152,15 +154,14 @@ phy-handle = <&swphy0>; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; ð1 { status = "okay"; - nvmem-cells = <&macaddr_uboot_1fc00>; + nvmem-cells = <&macaddr_uboot_1fc00 0>; nvmem-cell-names = "mac-address"; gmac-config { diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts index b08dce2950..2fd9a6e51b 100644 --- a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts +++ b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts @@ -56,9 +56,8 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-2)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-2)>; }; &pcie { @@ -73,9 +72,8 @@ &wmac { /delete-property/ ieee80211-freq-limit; - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 (-2)>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-2)>; }; &art { @@ -85,7 +83,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts index 56f0c8e048..9cf6819958 100644 --- a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts +++ b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts @@ -56,23 +56,20 @@ }; ð0 { - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 (-2)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-2)>; }; &pcie { wifi@0,0,0 { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_art_0 (-1)>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-1)>; }; }; &wmac { - nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_art_0 (-2)>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <(-2)>; }; &art { @@ -82,7 +79,9 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; calibration_art_1000: calibration@1000 { diff --git a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts index 1ab92c698c..4b692b6d9b 100644 --- a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts +++ b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts @@ -150,7 +150,9 @@ #size-cells = <1>; macaddr_addr_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -164,9 +166,8 @@ ath9k: wifi@0,0 { compatible = "pci168c,0030"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&macaddr_addr_0>, <&calibration_art_5000>; + nvmem-cells = <&macaddr_addr_0 0x10>, <&calibration_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <0x10>; #gpio-cells = <2>; gpio-controller; }; @@ -183,7 +184,7 @@ &wmac { status = "okay"; - nvmem-cells = <&macaddr_addr_0>, <&calibration_art_1000>; + nvmem-cells = <&macaddr_addr_0 0>, <&calibration_art_1000>; nvmem-cell-names = "mac-address", "calibration"; }; @@ -200,9 +201,8 @@ pll-data = <0xe000000 0x04000101 0x04001313>; - nvmem-cells = <&macaddr_addr_0>; + nvmem-cells = <&macaddr_addr_0 0x21>; nvmem-cell-names = "mac-address"; - mac-address-increment = <0x21>; phy-mode = "rgmii-rxid"; phy-handle = <&phy4>; From e29f4a3f70d278cf7e360519d97d94f54baae278 Mon Sep 17 00:00:00 2001 From: Rani Hod Date: Mon, 13 Nov 2023 01:15:31 +0200 Subject: [PATCH 05/34] ath79: add support for D-link DAP-1720 A1 D-Link DAP-1720 rev A1 is a mains-powered AC1750 Wi-Fi range extender, manufactured by Alpha Networks [8WAPAC28.1A1G]. (in square brackets: PCB silkscreen markings) Specifications: * CPU (Qualcomm Atheros QCA9563-AL3A [U5]): 775 MHz single core MIPS 74Kc; * RAM (Winbond W9751G6KB-25J [U3]): 64 MiB DDR2; * ROM (Winbond W25Q128FV [U16]): 16 MiB SPI NOR flash; * Ethernet (AR8033-AL1A PHY [U1], no switch): 1 GbE RJ45 port (no PHY LEDs); * Wi-Fi * 2.4 GHz (Qualcomm Atheros QCA9563-AL3A [U5]): 3x3 802.11n; * 5 GHz (Qualcomm Atheros QCA9880-BR4A [U9]): 3x3 802.11ac Wave 1; * 3 foldable dual-band antennas (U.fl) [P1],[P2],[P3]; * GPIO LEDs: * RSSI low (red/green) [D2]; * RSSI medium (green) [D3]; * RSSI high (green) [D4]; * status (red/green) [D5]; * GPIO buttons: * WPS [SW1], co-located with status LED; * reset [SW4], accessible via hole in the side; * Serial/UART: Tx-Gnd-3v3-Rx [JP1], Tx is the square pin, 1.25mm pitch; 125000-8-n-1 in U-boot, 115200-8-n-1 in kernel; * Misc: * 12V VCC [JP2], fed from internal 12V/1A AC to DC converter; * on/off slide switch [SW2] (disconnects VCC mechanically); * unpopulated footprints for a Wi-Fi LED [D1]; * unpopulated footprints for a 4-pin 3-position slide switch (SW3); MAC addresses: * Label = LAN; * 2.4 GHz WiFi = LAN; * 5 GHz WiFi = LAN+2; Installation: * `factory.bin` can be used to install OpenWrt from OEM firmware via the standard upgrade webpage at http://192.168.0.50/UpdateFirmware.html * `recovery.bin` can be used to install OpenWrt (or revert to OEM firmware) from D-Link Web Recovery. To enter web recovery, keep reset button pressed and then power on the device. Reset button can be released when the red status LED is bright; it will then blink slowly. Set static IP to 192.168.0.10, navigate to http://192.168.0.50 and upload 'recovery.bin'. Note that in web recovery mode the device ignores ping and DHCP requests. Note: 802.11s is not supported by the default `ath10k` driver and firmware, but is supported by the non-CT driver and firmware variants. The `-smallbuffers` driver variant is recommended due to RAM size. Co-developed-by: Anthony Sepa Signed-off-by: Rani Hod --- package/boot/uboot-envtools/files/ath79 | 1 + .../ath79/dts/qca9563_dlink_dap-1720-a1.dts | 214 ++++++++++++++++++ .../generic/base-files/etc/board.d/01_leds | 7 + .../generic/base-files/etc/board.d/02_network | 1 + .../etc/uci-defaults/09_fix-checksum | 1 + target/linux/ath79/image/generic.mk | 16 ++ 6 files changed, 240 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_dlink_dap-1720-a1.dts diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 2ad79700d7..7c0cdf9013 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -31,6 +31,7 @@ asus,zenwifi-cd6n|\ asus,zenwifi-cd6r|\ buffalo,bhr-4grv2|\ devolo,magic-2-wifi|\ +dlink,dap-1720-a1|\ dlink,dir-859-a1|\ dlink,dir-859-a3|\ dlink,dir-869-a1|\ diff --git a/target/linux/ath79/dts/qca9563_dlink_dap-1720-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dap-1720-a1.dts new file mode 100644 index 0000000000..35f3913d9b --- /dev/null +++ b/target/linux/ath79/dts/qca9563_dlink_dap-1720-a1.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca956x.dtsi" + +#include +#include +#include + +/ { + model = "D-Link DAP-1720 A1"; + compatible = "dlink,dap-1720-a1", "qca,qca9563"; + + aliases { + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_red; + + label-mac-device = ð0; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + + button-wps { + label = "wps"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: led-status-red { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + + led_status_green: led-status-green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-rssi-middle { + color = ; + function = "signal"; //LED_FUNCTION_SIGNAL; + function-enumerator = <2>; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + led-rssi-top { + color = ; + function = "signal"; //LED_FUNCTION_SIGNAL; + function-enumerator = <3>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + led-rssi-bottom-green { + color = ; + function = "signal"; //LED_FUNCTION_SIGNAL; + function-enumerator = <1>; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + + led-rssi-bottom-red { + color = ; + function = "signal"; //LED_FUNCTION_SIGNAL; + function-enumerator = <1>; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; // vendor calls it `bootloader` + reg = <0x000000 0x40000>; + read-only; + }; + + partition@40000 { + compatible = "u-boot,env"; + label = "u-boot-env"; // vendor calls it `bdcfg` + reg = <0x040000 0x10000>; + read-only; + }; + + partition@50000 { + label = "devdata"; + reg = <0x050000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ath10k: macaddr@94 { + compatible = "mac-base"; + reg = <0x94 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_ath9k: macaddr@b0 { + compatible = "mac-base"; + reg = <0xb0 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_lan: macaddr@c9 { + compatible = "mac-base"; + reg = <0xc9 0x11>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@60000 { + label = "devconf"; + reg = <0x060000 0x10000>; + read-only; + }; + + partition@70000 { + compatible = "seama"; + label = "firmware"; + reg = <0x070000 0xf80000>; + }; + + partition@ff0000 { + label = "art"; // vendor calls it `radiocfg` + reg = <0xff0000 0x010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_ath9k: cal@1000 { + reg = <0x1000 0x440>; + }; + + cal_ath10k: cal@5000 { + reg = <0x5000 0x844>; + }; + }; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&phy0>; + phy-mode = "sgmii"; + + nvmem-cells = <&macaddr_lan 0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + + nvmem-cells = <&cal_ath10k>, <&macaddr_ath10k 0>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&cal_ath9k>, <&macaddr_ath9k 0>; + nvmem-cell-names = "calibration", "mac-address"; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds index c1d411b9a9..615abe4b3b 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds +++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds @@ -241,6 +241,13 @@ dlink,dap-1365-a1) ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "green:rssimediumhigh" "wlan0" "51" "100" ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "green:rssihigh" "wlan0" "76" "100" ;; +dlink,dap-1720-a1) + ucidef_set_rssimon "wlan0" "200000" "1" + ucidef_set_led_rssi "rssilow" "RSSI LOW" "red:signal-1" "wlan0" "1" "40" + ucidef_set_led_rssi "rssimediumlow" "RSSI MEDIUM-LOW" "green:signal-1" "wlan0" "21" "100" + ucidef_set_led_rssi "rssimediumhigh" "RSSI MEDIUM-HIGH" "green:signal-2" "wlan0" "61" "100" + ucidef_set_led_rssi "rssihigh" "RSSI HIGH" "green:signal-3" "wlan0" "81" "100" + ;; dlink,dir-859-a1) ucidef_set_led_switch "internet" "WAN" "green:internet" "switch0" "0x20" ;; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index a9b78e4350..cdea3b5f67 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -34,6 +34,7 @@ ath79_setup_interfaces() devolo,dvl1750x|\ dlink,dap-1330-a1|\ dlink,dap-1365-a1|\ + dlink,dap-1720-a1|\ dlink,dap-2230-a1|\ dlink,dap-2660-a1|\ dlink,dap-2680-a1|\ diff --git a/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum b/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum index 0ea81a8dc3..4ec8c13eb7 100644 --- a/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum +++ b/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum @@ -21,6 +21,7 @@ dlink,dap-3320-a1|\ dlink,dap-3662-a1) fixwrgg ;; +dlink,dap-1720-a1|\ dlink,dir-629-a1|\ dlink,dir-859-a1|\ dlink,dir-859-a3|\ diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index e6e78b9287..e435806c7b 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1053,6 +1053,22 @@ define Device/dlink_dap-1365-a1 endef TARGET_DEVICES += dlink_dap-1365-a1 +define Device/dlink_dap-1720-a1 + $(Device/seama) + SOC := qca9563 + DEVICE_VENDOR := D-Link + DEVICE_MODEL := DAP-1720 + DEVICE_VARIANT := A1 + DEVICE_PACKAGES := rssileds -swconfig \ + kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct + SEAMA_SIGNATURE := wapac28_dlink.2015_dap1720 + IMAGE_SIZE := 15872k + IMAGES += recovery.bin + IMAGE/recovery.bin := $$(IMAGE/default) | pad-rootfs -x 64 | seama | \ + seama-seal | check-size +endef +TARGET_DEVICES += dlink_dap-1720-a1 + define Device/dlink_dap-2xxx IMAGES += factory.img IMAGE/factory.img := append-kernel | pad-offset 6144k 160 | \ From c66511bc488c3665d47dd60baf981ca1c385c221 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Sun, 1 Oct 2023 21:51:32 -0700 Subject: [PATCH 06/34] ipq40xx: fix typo in Linksys WHW01 image definition Use lower-case "k" in IMAGE_SIZE for Linksys WHW01, permitting proper unit conversions in build recipes (e.g. 75776k -> 75776*1024). Fixes: 2a9f3b7717 ("ipq40xx: fix up Linksys WHW01 board name, device definition") Signed-off-by: Tony Ambardar --- target/linux/ipq40xx/image/generic.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index d79fda3156..1757684a7c 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -742,7 +742,7 @@ define Device/linksys_whw01 DEVICE_VENDOR := Linksys DEVICE_MODEL := WHW01 KERNEL_SIZE := 6144k - IMAGE_SIZE := 75776K + IMAGE_SIZE := 75776k SOC := qcom-ipq4018 BLOCKSIZE := 128k PAGESIZE := 2048 From b16e14a220fcab19e3145328057e7188f00b6a17 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Sat, 11 Nov 2023 04:29:26 -0800 Subject: [PATCH 07/34] image: use helper function for size units Add the make function 'exp_units' for helping evaluate k/m/g size units in expressions, and use this to consistently replace many ad hoc substitutions like '$(subst k,* 1024,$(subst m, * 1024k,$(IMAGE_SIZE)))' in makefiles. Signed-off-by: Tony Ambardar --- include/image-commands.mk | 8 ++++---- include/image.mk | 2 ++ target/linux/ath79/image/generic.mk | 2 +- target/linux/ath79/image/nand.mk | 2 +- target/linux/ipq40xx/image/generic.mk | 2 +- target/linux/mediatek/image/mt7622.mk | 2 +- target/linux/ramips/image/Makefile | 4 ++-- 7 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/image-commands.mk b/include/image-commands.mk index d07c882761..0f292d15ee 100644 --- a/include/image-commands.mk +++ b/include/image-commands.mk @@ -215,7 +215,7 @@ endef define Build/check-size @imagesize="$$(stat -c%s $@)"; \ - limitsize="$$(($(subst k,* 1024,$(subst m, * 1024k,$(if $(1),$(1),$(IMAGE_SIZE))))))"; \ + limitsize="$$(($(call exp_units,$(if $(1),$(1),$(IMAGE_SIZE)))))"; \ [ $$limitsize -ge $$imagesize ] || { \ $(call ERROR_MESSAGE, WARNING: Image file $@ is too big: $$imagesize > $$limitsize); \ rm -f $@; \ @@ -466,8 +466,8 @@ endef define Build/pad-offset let \ size="$$(stat -c%s $@)" \ - pad="$(subst k,* 1024,$(word 1, $(1)))" \ - offset="$(subst k,* 1024,$(word 2, $(1)))" \ + pad="$(call exp_units,$(word 1, $(1)))" \ + offset="$(call exp_units,$(word 2, $(1)))" \ pad="(pad - ((size + offset) % pad)) % pad" \ newsize='size + pad'; \ dd if=$@ of=$@.new bs=$$newsize count=1 conv=sync @@ -629,7 +629,7 @@ endef define Build/zyxel-ras-image let \ - newsize="$(subst k,* 1024,$(RAS_ROOTFS_SIZE))"; \ + newsize="$(call exp_units,$(RAS_ROOTFS_SIZE))"; \ $(STAGING_DIR_HOST)/bin/mkrasimage \ -b $(RAS_BOARD) \ -v $(RAS_VERSION) \ diff --git a/include/image.mk b/include/image.mk index 4ebff2e9ae..ef52337dee 100644 --- a/include/image.mk +++ b/include/image.mk @@ -20,6 +20,8 @@ include $(INCLUDE_DIR)/rootfs.mk override MAKE:=$(_SINGLE)$(SUBMAKE) override NO_TRACE_MAKE:=$(_SINGLE)$(NO_TRACE_MAKE) +exp_units = $(subst k, * 1024,$(subst m, * 1024k,$(subst g, * 1024m,$(1)))) + target_params = $(subst +,$(space),$*) param_get = $(patsubst $(1)=%,%,$(filter $(1)=%,$(2))) param_get_default = $(firstword $(call param_get,$(1),$(2)) $(3)) diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index e435806c7b..68c4105561 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -85,7 +85,7 @@ define Build/mkmylofw_16m let \ size="$$(stat -c%s $@)" \ - pad="$(subst k,* 1024,$(BLOCKSIZE))" \ + pad="$(call exp_units,$(BLOCKSIZE))" \ pad="(pad - (size % pad)) % pad" \ newsize='size + pad' ; \ [ $$newsize -lt $$((0x660000)) ] && newsize=0x660000 ; \ diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk index 5c9e190e19..bf2b1a1f8a 100644 --- a/target/linux/ath79/image/nand.mk +++ b/target/linux/ath79/image/nand.mk @@ -32,7 +32,7 @@ endef define Build/zyxel-factory let \ - maxsize="$(subst k,* 1024,$(RAS_ROOTFS_SIZE))"; \ + maxsize="$(call exp_units,$(RAS_ROOTFS_SIZE))"; \ let size="$$(stat -c%s $@)"; \ if [ $$size -lt $$maxsize ]; then \ $(STAGING_DIR_HOST)/bin/mkrasimage \ diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 1757684a7c..b4719033c0 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -68,7 +68,7 @@ define Build/mkmylofw_32m let \ size="$$(stat -c%s $@)" \ - pad="$(subst k,* 1024,$(BLOCKSIZE))" \ + pad="$(call exp_units,$(BLOCKSIZE))" \ pad="(pad - (size % pad)) % pad" \ newsize='size + pad'; \ $(STAGING_DIR_HOST)/bin/mkmylofw \ diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index e362e7428b..d0f5280dcf 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -21,7 +21,7 @@ define Build/buffalo-trx -f $(kern_bin) \ $(if $(rtfs_bin),\ -a 0x20000 \ - -b $$(( $(subst k, * 1024,$(kern_size)) )) \ + -b $$(( $(call exp_units,$(kern_size)) )) \ -f $(rtfs_bin),) \ $(if $(apnd_bin),\ -A $(apnd_bin) \ diff --git a/target/linux/ramips/image/Makefile b/target/linux/ramips/image/Makefile index 265e9fb5e0..fdc15aa1ef 100644 --- a/target/linux/ramips/image/Makefile +++ b/target/linux/ramips/image/Makefile @@ -31,7 +31,7 @@ KERNEL_DTB = kernel-bin | append-dtb | lzma define Build/jcg-header $(STAGING_DIR_HOST)/bin/jcgimage -v $(1) \ - $(if $(JCG_MAXSIZE), -m $$(($(subst k, * 1024,$(JCG_MAXSIZE)))),) \ + $(if $(JCG_MAXSIZE), -m $$(($(call exp_units,$(JCG_MAXSIZE)))),) \ -u $@ -o $@.new mv $@.new $@ endef @@ -142,7 +142,7 @@ endef define Build/trx $(STAGING_DIR_HOST)/bin/trx $(1) \ -o $@ \ - -m $$(($(subst k, * 1024,$(IMAGE_SIZE)))) \ + -m $$(($(call exp_units,$(IMAGE_SIZE)))) \ -f $(IMAGE_KERNEL) \ -a 4 -f $(IMAGE_ROOTFS) endef From cd5e0134b6bd2e34ad237d985da99c5307816c93 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Mon, 13 Nov 2023 17:14:07 -0800 Subject: [PATCH 08/34] image: fix Linksys image alignment and simplify footer creation Current factory image sizes for Linksys devices are 256-byte aligned. This is not an issue writing factory images from the OpenWrt or Linksys GUIs, but can lead to failures using a TFTP client from the Linksys bootloader: NAND write: device 1 offset 0x2800000, size 0xc00100 Attempt to write to non page aligned data NAND write to offset 2800000 failed -22 0 bytes written: ERROR Simplify Linksys footer creation by migrating to a makefile build recipe, and pre-pad the footer (with 0xFF) to ensure the final image is $(PAGESIZE) aligned. Finally, remove the old linksys-image.sh script no longer needed. Linksys footer details are given below for future reference. The 256-byte footer is appended to factory images and tested by both the Linksys Upgrader (observed in EA6350v3) and OpenWrt sysupgrade. Footer format: .LINKSYS. Checked by Linksys upgrader before continuing. (9 bytes) Upgrade version number, unchecked so arbitrary. (8 bytes) Model of device, space padded (0x20). (15 bytes) CRC checksum of factory image to flash. (8 bytes) Padding ('0' + 0x20 * 7) (8 bytes) Signature of signer, unchecked so arbitrary. (16 bytes) Padding with nulls (0x00) (192 bytes) Link: https://github.com/openwrt/openwrt/pull/11405#issuecomment-1358510123 Link: https://github.com/openwrt/openwrt/pull/11405#issuecomment-1587517739 Reported-by: Stijn Segers Reported-by: Wyatt Martin Signed-off-by: Tony Ambardar --- include/image-commands.mk | 13 ++++++-- scripts/linksys-image.sh | 64 --------------------------------------- 2 files changed, 10 insertions(+), 67 deletions(-) delete mode 100755 scripts/linksys-image.sh diff --git a/include/image-commands.mk b/include/image-commands.mk index 0f292d15ee..7d9f93fed7 100644 --- a/include/image-commands.mk +++ b/include/image-commands.mk @@ -389,10 +389,17 @@ define Build/kernel-bin endef define Build/linksys-image - $(TOPDIR)/scripts/linksys-image.sh \ + let \ + size="$$(stat -c%s $@)" \ + pad="$(call exp_units,$(PAGESIZE))" \ + offset="256" \ + pad="(pad - ((size + offset) % pad)) % pad"; \ + dd if=/dev/zero bs=$$pad count=1 | tr '\000' '\377' >> $@ + printf ".LINKSYS.01000409%-15s%08X%-8s%-16s" \ "$(call param_get_default,type,$(1),$(DEVICE_NAME))" \ - $@ $@.new - mv $@.new $@ + "$$(cksum $@ | cut -d ' ' -f1)" \ + "0" "K0000000F0246434" >> $@ + dd if=/dev/zero bs=192 count=1 >> $@ endef define Build/lzma diff --git a/scripts/linksys-image.sh b/scripts/linksys-image.sh deleted file mode 100755 index d251b5da8e..0000000000 --- a/scripts/linksys-image.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2018 Oceanic Systems (UK) Ltd -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# Maintained by: Ryan Pannell -# -# Write Linksys signature for factory image -# This is appended to the factory image and is tested by the Linksys Upgrader - as observed in civic. -# The footer is 256 bytes. The format is: -# .LINKSYS. This is detected by the Linksys upgrader before continuing with upgrade. (9 bytes) -# The version number of upgrade. Not checked so use arbitrary value (8 bytes) -# Model of target device, padded (0x20) to (15 bytes) -# CRC checksum of the image to flash (8 byte) -# Padding ('0' + 0x20 *7) (8 bytes) -# Signature of signer. Not checked so use arbitrary value (16 bytes) -# Padding (0x00) (192 bytes) - -## version history -# * version 1: initial commit - -set -e - -ME="${0##*/}" - -usage() { - echo "Usage: $ME " - [ "$IMG_OUT" ] && rm -f "$IMG_OUT" - exit 1 -} - -[ "$#" -lt 3 ] && usage - -TYPE=$1 - -tmpdir="$( mktemp -d 2> /dev/null )" -if [ -z "$tmpdir" ]; then - # try OSX signature - tmpdir="$( mktemp -t 'ubitmp' -d )" -fi - -if [ -z "$tmpdir" ]; then - exit 1 -fi - -trap "rm -rf $tmpdir" EXIT - -IMG_TMP_OUT="${tmpdir}/out" - -IMG_IN=$2 -IMG_OUT="${IMG_IN}.new" - -[ ! -f "$IMG_IN" ] && echo "$ME: Not a valid image: $IMG_IN" && usage - -dd if="${IMG_IN}" of="${IMG_TMP_OUT}" -CRC=$(printf "%08X" $(dd if="${IMG_IN}" bs=$(stat -c%s "${IMG_IN}") count=1|cksum| cut -d ' ' -f1)) - -printf ".LINKSYS.01000409%-15s%-8s%-8s%-16s" "${TYPE}" "${CRC}" "0" "K0000000F0246434" >> "${IMG_TMP_OUT}" - -dd if=/dev/zero bs=1 count=192 conv=notrunc >> "${IMG_TMP_OUT}" - -cp "${IMG_TMP_OUT}" "${IMG_OUT}" From fc16df9fdd596d1a3f5c3be897dc0cf69c84c469 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Sat, 11 Nov 2023 04:46:14 -0800 Subject: [PATCH 09/34] image: improve UBI image sizing on NAND devices Many NAND devices use a build recipe with "append-ubi | check-size" to ensure factory images don't exceed the target flash partition size. However, UBI reserves space for bad block handling and other operational overhead, and thus 'check-size' can overestimate the space available by several MB. In practice, this means a failed check is definitely a failure, while a passing check is only probably a pass. Improve the situation by teaching 'Build/append-ubi' to check image sizes while accounting for UBI reserved blocks. Add new device variable NAND_SIZE and use with existing IMAGE_SIZE to derate the available space. Each UBI device reserves 20 PEBs per 1024 PEBs of the entire NAND device for bad blocks, plus an additional 4 PEBs overhead. Many devices can transparently enable this check by setting NAND_SIZE based on their flash storage, and may then remove any unneeded 'check-size'. Link: http://www.linux-mtd.infradead.org/doc/ubi.html#L_overhead Suggested-by: Shiji Yang Suggested-by: Robert Marko Signed-off-by: Tony Ambardar --- include/image-commands.mk | 4 ++++ include/image.mk | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/image-commands.mk b/include/image-commands.mk index 7d9f93fed7..41a5e1198a 100644 --- a/include/image-commands.mk +++ b/include/image-commands.mk @@ -133,6 +133,8 @@ define Build/append-md5sum-ascii-salted rm $@.salted endef +UBI_NAND_SIZE_LIMIT = $(IMAGE_SIZE) - ($(NAND_SIZE)*20/1024 + 4*$(BLOCKSIZE)) + define Build/append-ubi sh $(TOPDIR)/scripts/ubinize-image.sh \ $(if $(UBOOTENV_IN_UBI),--uboot-env) \ @@ -146,6 +148,8 @@ define Build/append-ubi $(UBINIZE_OPTS) cat $@.tmp >> $@ rm $@.tmp + $(if $(and $(IMAGE_SIZE),$(NAND_SIZE)),\ + $(call Build/check-size,$(UBI_NAND_SIZE_LIMIT))) endef define Build/ubinize-kernel diff --git a/include/image.mk b/include/image.mk index ef52337dee..096ccb5f18 100644 --- a/include/image.mk +++ b/include/image.mk @@ -397,6 +397,7 @@ define Device/Init DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1)-$$(2) FACTORY_IMG_NAME := IMAGE_SIZE := + NAND_SIZE := KERNEL_PREFIX = $$(DEVICE_IMG_PREFIX) KERNEL_SUFFIX := -kernel.bin KERNEL_INITRAMFS_SUFFIX = $$(KERNEL_SUFFIX) @@ -457,7 +458,7 @@ DEFAULT_DEVICE_VARS := \ DEVICE_DTS_DIR DEVICE_DTS_OVERLAY DEVICE_DTS_LOADADDR \ DEVICE_FDT_NUM DEVICE_IMG_PREFIX SOC BOARD_NAME UIMAGE_MAGIC UIMAGE_NAME \ UIMAGE_TIME SUPPORTED_DEVICES IMAGE_METADATA KERNEL_ENTRY KERNEL_LOADADDR \ - UBOOT_PATH IMAGE_SIZE \ + UBOOT_PATH IMAGE_SIZE NAND_SIZE \ FACTORY_IMG_NAME FACTORY_SIZE \ DEVICE_PACKAGES DEVICE_COMPAT_VERSION DEVICE_COMPAT_MESSAGE \ DEVICE_VENDOR DEVICE_MODEL DEVICE_VARIANT \ From a7818e0550a2594d50d2874c1321784be093d8d2 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Sat, 11 Nov 2023 04:53:26 -0800 Subject: [PATCH 10/34] ipq40xx: enable UBI size checks for some Linksys NAND devices Add correct NAND_SIZE in device definitions for EA6350v3, EA8300, MR8300, WHW01 and WHW03v2, to enable improved image size checks wrt UBI reserved blocks on NAND devices. Signed-off-by: Tony Ambardar --- target/linux/ipq40xx/image/generic.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index b4719033c0..f5132cb91f 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -680,6 +680,7 @@ define Device/linksys_ea6350v3 PAGESIZE := 2048 KERNEL_SIZE := 5120k IMAGE_SIZE := 35840k + NAND_SIZE := 128m UBINIZE_OPTS := -E 5 IMAGES += factory.bin IMAGE/factory.bin := append-kernel | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=EA6350v3 @@ -694,6 +695,7 @@ define Device/linksys_ea8300 SOC := qcom-ipq4019 KERNEL_SIZE := 5120k IMAGE_SIZE := 84992k + NAND_SIZE := 256m BLOCKSIZE := 128k PAGESIZE := 2048 UBINIZE_OPTS := -E 5 # EOD marks to "hide" factory sig at EOF @@ -711,6 +713,7 @@ define Device/linksys_mr8300 SOC := qcom-ipq4019 KERNEL_SIZE := 5120k IMAGE_SIZE := 84992k + NAND_SIZE := 256m BLOCKSIZE := 128k PAGESIZE := 2048 UBINIZE_OPTS := -E 5 # EOD marks to "hide" factory sig at EOF @@ -728,6 +731,7 @@ define Device/linksys_whw03v2 SOC := qcom-ipq4019 KERNEL_SIZE := 6144k IMAGE_SIZE := 158720k + NAND_SIZE := 512m BLOCKSIZE := 128k PAGESIZE := 2048 UBINIZE_OPTS := -E 5 # EOD marks to "hide" factory sig at EOF @@ -743,6 +747,7 @@ define Device/linksys_whw01 DEVICE_MODEL := WHW01 KERNEL_SIZE := 6144k IMAGE_SIZE := 75776k + NAND_SIZE := 256m SOC := qcom-ipq4018 BLOCKSIZE := 128k PAGESIZE := 2048 From a3ec85507370efd7802837aabebe691c1f6b34db Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:27 +0800 Subject: [PATCH 11/34] u-boot: introduce dependencies check for swig and pyelftools They are required by modern u-boot builds, e.g. uboot-rockchip and uboot-sunxi. Signed-off-by: Tianling Shen --- include/u-boot.mk | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/include/u-boot.mk b/include/u-boot.mk index 280c6e35a1..06867a70e4 100644 --- a/include/u-boot.mk +++ b/include/u-boot.mk @@ -1,3 +1,5 @@ +include $(INCLUDE_DIR)/prereq.mk + PKG_NAME ?= u-boot ifndef PKG_SOURCE_PROTO @@ -18,6 +20,31 @@ PKG_LICENSE_FILES:=Licenses/README PKG_BUILD_PARALLEL ?= 1 +ifdef UBOOT_USE_BINMAN + $(eval $(call TestHostCommand,python3-pyelftools, \ + Please install the Python3 elftools module, \ + $(STAGING_DIR_HOST)/bin/python3 -c 'import elftools')) +endif + +ifdef UBOOT_USE_INTREE_DTC + $(eval $(call TestHostCommand,python3-dev, \ + Please install the python3-dev package, \ + python3.11-config --includes 2>&1 | grep 'python3', \ + python3.10-config --includes 2>&1 | grep 'python3', \ + python3.9-config --includes 2>&1 | grep 'python3', \ + python3.8-config --includes 2>&1 | grep 'python3', \ + python3.7-config --includes 2>&1 | grep 'python3', \ + python3-config --includes 2>&1 | grep -E 'python3\.([7-9]|[0-9][0-9])\.?')) + + $(eval $(call TestHostCommand,python3-setuptools, \ + Please install the Python3 setuptools module, \ + $(STAGING_DIR_HOST)/bin/python3 -c 'import setuptools')) + + $(eval $(call TestHostCommand,swig, \ + Please install the swig package, \ + swig -version)) +endif + export GCC_HONOUR_COPTS=s define Package/u-boot/install/default @@ -88,7 +115,9 @@ define Build/Configure/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) oldconfig) endef -DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) +ifndef UBOOT_USE_INTREE_DTC + DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) +endif define Build/Compile/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \ From 20f81f49eacdca75046e3f3e0d26ee456aa28eac Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Nov 2023 23:21:22 +0800 Subject: [PATCH 12/34] uboot-mediatek: use intree dtc explicitly This replaces pylibfdt hack. Signed-off-by: Tianling Shen --- package/boot/uboot-mediatek/Makefile | 2 ++ .../patches/300-force-pylibfdt-build.patch | 30 ------------------- 2 files changed, 2 insertions(+), 30 deletions(-) delete mode 100644 package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index d0e59d1017..a9e6d35f00 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -5,6 +5,8 @@ PKG_VERSION:=2023.07.02 PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host +UBOOT_USE_INTREE_DTC:=1 + include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/host-build.mk diff --git a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch deleted file mode 100644 index 89cdf60f95..0000000000 --- a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -2006,26 +2006,7 @@ endif - # Check dtc and pylibfdt, if DTC is provided, else build them - PHONY += scripts_dtc - scripts_dtc: scripts_basic -- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ -- $(MAKE) $(build)=scripts/dtc; \ -- else \ -- if ! $(DTC) -v >/dev/null; then \ -- echo '*** Failed to check dtc version: $(DTC)'; \ -- false; \ -- else \ -- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ -- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ -- false; \ -- else \ -- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ -- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ -- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ -- false; \ -- fi; \ -- fi; \ -- fi; \ -- fi; \ -- fi -+ $(MAKE) $(build)=scripts/dtc - - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds = LDS $@ From fb3af8611942feb24f9b51934d8d1901050bf0d9 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Nov 2023 23:22:59 +0800 Subject: [PATCH 13/34] uboot-sifiveu: use intree dtc explicitly This replaces pylibfdt hack. Signed-off-by: Tianling Shen --- package/boot/uboot-sifiveu/Makefile | 2 ++ .../patches/300-force-pylibfdt-build.patch | 30 ------------------- 2 files changed, 2 insertions(+), 30 deletions(-) delete mode 100644 package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch diff --git a/package/boot/uboot-sifiveu/Makefile b/package/boot/uboot-sifiveu/Makefile index 5def1c1fcb..4cbfe344af 100644 --- a/package/boot/uboot-sifiveu/Makefile +++ b/package/boot/uboot-sifiveu/Makefile @@ -10,6 +10,8 @@ PKG_RELEASE:=1 PKG_VERSION:=2022.10 PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 +UBOOT_USE_INTREE_DTC:=1 + include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch deleted file mode 100644 index 4abf13eda8..0000000000 --- a/package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -2028,26 +2028,7 @@ endif - # Check dtc and pylibfdt, if DTC is provided, else build them - PHONY += scripts_dtc - scripts_dtc: scripts_basic -- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ -- $(MAKE) $(build)=scripts/dtc; \ -- else \ -- if ! $(DTC) -v >/dev/null; then \ -- echo '*** Failed to check dtc version: $(DTC)'; \ -- false; \ -- else \ -- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ -- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ -- false; \ -- else \ -- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ -- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ -- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ -- false; \ -- fi; \ -- fi; \ -- fi; \ -- fi; \ -- fi -+ $(MAKE) $(build)=scripts/dtc - - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds = LDS $@ From 8fc4fe7b488e41f79b70b049bf669b0d2088e61f Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Nov 2023 23:17:15 +0800 Subject: [PATCH 14/34] uboot-sunxi: use intree dtc explicitly This replaces pylibfdt hack. Signed-off-by: Tianling Shen --- package/boot/uboot-sunxi/Makefile | 2 ++ .../patches/300-force-pylibfdt-build.patch | 30 ------------------- 2 files changed, 2 insertions(+), 30 deletions(-) delete mode 100644 package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 17905802c3..7f50992e69 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -15,6 +15,8 @@ PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341 PKG_MAINTAINER:=Zoltan HERPAI +UBOOT_USE_INTREE_DTC:=1 + include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch deleted file mode 100644 index d34ed6f2ae..0000000000 --- a/package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -2000,26 +2000,7 @@ endif - # Check dtc and pylibfdt, if DTC is provided, else build them - PHONY += scripts_dtc - scripts_dtc: scripts_basic -- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ -- $(MAKE) $(build)=scripts/dtc; \ -- else \ -- if ! $(DTC) -v >/dev/null; then \ -- echo '*** Failed to check dtc version: $(DTC)'; \ -- false; \ -- else \ -- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ -- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ -- false; \ -- else \ -- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ -- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ -- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ -- false; \ -- fi; \ -- fi; \ -- fi; \ -- fi; \ -- fi -+ $(MAKE) $(build)=scripts/dtc - - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds = LDS $@ From 548ab9d7ada9812000d5fe8c4ee0aca637b45edf Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:27 +0800 Subject: [PATCH 15/34] uboot-rockchip: Update to 2023.07.02 * Removed swig hacks and prebuilt of-platdata * Removed upstreamed patches - 101-rock64pro-disable-CONFIG_USE_PREBOOT.patch - 102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch * Reordered patches * Introduced new dependencies check * Overrided default PATH to avoid race condition (host python3 vs hostpkg python3) * Switched to use UBOOT_CUSTOMIZE_CONFIG for config update Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 32 +-- ...01-scripts-remove-dependency-on-swig.patch | 24 -- ...-spl-remove-dtoc-of-pdata-generation.patch | 28 --- ...8-Add-support-for-Orange-Pi-R1-Plus.patch} | 80 +++++-- ...rock64pro-disable-CONFIG_USE_PREBOOT.patch | 27 --- ...dd-support-for-Orange-Pi-R1-Plus-LT.patch} | 63 +++-- ...d-support-for-FriendlyARM-NanoPi-R2C.patch | 199 ---------------- .../of-platdata/nanopi-r2c-rk3328/dt-decl.h | 23 -- .../of-platdata/nanopi-r2c-rk3328/dt-plat.c | 155 ------------- .../nanopi-r2c-rk3328/dt-structs-gen.h | 51 ---- .../of-platdata/nanopi-r2s-rk3328/dt-decl.h | 23 -- .../of-platdata/nanopi-r2s-rk3328/dt-plat.c | 155 ------------- .../nanopi-r2s-rk3328/dt-structs-gen.h | 51 ---- .../orangepi-r1-plus-lts-rk3328/dt-decl.h | 24 -- .../orangepi-r1-plus-lts-rk3328/dt-plat.c | 170 -------------- .../dt-structs-gen.h | 55 ----- .../orangepi-r1-plus-rk3328/dt-decl.h | 24 -- .../orangepi-r1-plus-rk3328/dt-plat.c | 170 -------------- .../orangepi-r1-plus-rk3328/dt-structs-gen.h | 55 ----- .../src/of-platdata/roc-cc-rk3328/dt-decl.h | 24 -- .../src/of-platdata/roc-cc-rk3328/dt-plat.c | 189 --------------- .../roc-cc-rk3328/dt-structs-gen.h | 55 ----- .../of-platdata/rock-pi-e-rk3328/dt-decl.h | 24 -- .../of-platdata/rock-pi-e-rk3328/dt-plat.c | 189 --------------- .../rock-pi-e-rk3328/dt-structs-gen.h | 54 ----- .../src/of-platdata/rock64-rk3328/dt-decl.h | 27 --- .../src/of-platdata/rock64-rk3328/dt-plat.c | 219 ------------------ .../rock64-rk3328/dt-structs-gen.h | 63 ----- 28 files changed, 106 insertions(+), 2147 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch delete mode 100644 package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch rename package/boot/uboot-rockchip/patches/{103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch => 100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch} (91%) delete mode 100644 package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch rename package/boot/uboot-rockchip/patches/{104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch => 101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch} (86%) delete mode 100644 package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c delete mode 100644 package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cdaad7ce46..35eaf198be 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,13 +5,15 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2021.07 -PKG_RELEASE:=5 - -PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e +PKG_VERSION:=2023.07.02 +PKG_RELEASE:=1 +PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 PKG_MAINTAINER:=Tobias Maedel +UBOOT_USE_BINMAN:=1 +UBOOT_USE_INTREE_DTC:=1 + include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -28,7 +30,6 @@ define U-Boot/rk3328/Default BUILD_SUBTARGET:=armv8 DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328 ATF:=rk3328_bl31.elf - OF_PLATDATA:=$(1) endef define U-Boot/nanopi-r2c-rk3328 @@ -131,24 +132,15 @@ UBOOT_TARGETS := \ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes +UBOOT_CUSTOMIZE_CONFIG := \ + --disable SPL_FIT_SIGNATURE \ + --disable TOOLS_MKEFICAPSULE \ + --set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc + UBOOT_MAKE_FLAGS += \ + PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ BL31=$(STAGING_DIR_IMAGE)/$(ATF) -define Build/Configure - $(call Build/Configure/U-Boot) - -ifneq ($(OF_PLATDATA),) - mkdir -p $(PKG_BUILD_DIR)/tpl/dts - mkdir -p $(PKG_BUILD_DIR)/include/generated - - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h -endif - - $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config -endef - define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img diff --git a/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch b/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch deleted file mode 100644 index 0505589385..0000000000 --- a/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 13 Jul 2020 23:37:37 +0200 -Subject: [PATCH] scripts: remove dependency on swig - -Don't build the libfdt tool, as it has a dependency on swig (which -OpenWrt does not ship). - -This requires more hacks, as of-platdata generation does not work -without it. - -Signed-off-by: David Bauer ---- - scripts/dtc/Makefile | 2 -- - 1 file changed, 2 deletions(-) - ---- a/scripts/dtc/Makefile -+++ b/scripts/dtc/Makefile -@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src) - # dependencies on generated files need to be listed explicitly - $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h - --# Added for U-Boot --subdir-$(CONFIG_PYLIBFDT) += pylibfdt diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch deleted file mode 100644 index 14bcbfb630..0000000000 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Tue, 14 Jul 2020 22:44:22 +0200 -Subject: [PATCH] spl: remove dtoc of-pdata generation - -Remove the dtoc of-pdata generation. This generation is dependant on -libpython-dev. As OpenWrt does not ship with this dependency, use -pre-generated pdata files and remove the generation from the -build-process. - -This only affects RK3328 boards. - -Signed-off-by: David Bauer ---- - scripts/Makefile.spl | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/scripts/Makefile.spl -+++ b/scripts/Makefile.spl -@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) - @# of OF_PLATDATA_INST and this might change between builds. Leaving old - @# ones around is confusing and it is possible that switching the - @# setting again will use the old one instead of regenerating it. -- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) -- $(call if_changed,dtoc) - - ifdef CONFIG_SAMSUNG - ifdef CONFIG_VAR_SIZE_SPL diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch similarity index 91% rename from package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch rename to package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch index ff17559c2f..487e6afda8 100644 --- a/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch @@ -1,4 +1,4 @@ -From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001 +From 89afb631d965292aaf433806d8224b53d9e74036 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 18:50:38 +0800 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus @@ -27,7 +27,7 @@ Signed-off-by: Tianling Shen --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ +@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ @@ -53,24 +53,24 @@ Signed-off-by: Tianling Shen +}; + +&gpio0 { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&pinctrl { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + -+&sdmmc0m1_gpio { -+ u-boot,dm-spl; ++&sdmmc0m1_pin { ++ bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&gmac2io { @@ -81,12 +81,12 @@ Signed-off-by: Tianling Shen + +&spi0 { + spi_flash: spiflash@0 { -+ u-boot,dm-pre-reloc; ++ bootph-all; + }; +}; --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,359 @@ +@@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Based on rk3328-nanopi-r2s.dts, which is: @@ -104,6 +104,7 @@ Signed-off-by: Tianling Shen + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; + + aliases { ++ ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + @@ -146,7 +147,7 @@ Signed-off-by: Tianling Shen + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; @@ -439,6 +440,19 @@ Signed-off-by: Tianling Shen + status = "okay"; +}; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Second port is for USB 3.0 */ ++ rtl8153: device@2 { ++ compatible = "usbbda,8153"; ++ reg = <2>; ++ }; ++}; ++ +&usb_host0_ehci { + status = "okay"; +}; @@ -463,39 +477,52 @@ Signed-off-by: Tianling Shen M: Chen-Yu Tsai --- /dev/null +++ b/configs/orangepi-r1-plus-rk3328_defconfig -@@ -0,0 +1,98 @@ +@@ -0,0 +1,114 @@ +CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SPL_STACK=0x400000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y ++CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" -+CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y @@ -504,11 +531,11 @@ Signed-off-by: Tianling Shen +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y @@ -526,13 +553,14 @@ Signed-off-by: Tianling Shen +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y ++CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y @@ -542,9 +570,11 @@ Signed-off-by: Tianling Shen +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y diff --git a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch deleted file mode 100644 index 174c9ea29c..0000000000 --- a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sun, 17 Jan 2021 15:26:09 -0500 -Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT - -On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3 -CONFIG_USE_PREBOOT was enabled on the RockPro64. - -When the board is booting, U-Boot hangs as soon as it disables the USB -controller. This is a workaround until a final solution is deployed -upstream. - -Signed-off-by: Marty Jones ---- - configs/rockpro64-rk3399_defconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -12,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI_SUPPORT=y - CONFIG_DEBUG_UART=y --CONFIG_USE_PREBOOT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" - CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_MISC_INIT_R=y diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch b/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch similarity index 86% rename from package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch rename to package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch index 05d569e720..56d36c74dc 100644 --- a/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch +++ b/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch @@ -1,4 +1,4 @@ -From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001 +From 408fd4570c0f1e6b1fe3722998394651144f2a29 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 20 May 2023 18:52:14 +0800 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS @@ -10,7 +10,6 @@ changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen - --- arch/arm/dts/Makefile | 1 + .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++ @@ -24,7 +23,7 @@ Signed-off-by: Tianling Shen --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ +@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ rk3328-orangepi-r1-plus.dtb \ @@ -50,24 +49,24 @@ Signed-off-by: Tianling Shen +}; + +&gpio0 { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&pinctrl { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + -+&sdmmc0m1_gpio { -+ u-boot,dm-spl; ++&sdmmc0m1_pin { ++ bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { -+ u-boot,dm-spl; ++ bootph-pre-ram; +}; + +&gmac2io { @@ -78,7 +77,7 @@ Signed-off-by: Tianling Shen + +&spi0 { + spi_flash: spiflash@0 { -+ u-boot,dm-pre-reloc; ++ bootph-all; + }; +}; --- /dev/null @@ -141,39 +140,52 @@ Signed-off-by: Tianling Shen M: Chen-Yu Tsai --- /dev/null +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig -@@ -0,0 +1,98 @@ +@@ -0,0 +1,114 @@ +CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SPL_STACK=0x400000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y ++CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" -+CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y @@ -182,11 +194,11 @@ Signed-off-by: Tianling Shen +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y @@ -204,13 +216,14 @@ Signed-off-by: Tianling Shen +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y ++CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y @@ -220,9 +233,11 @@ Signed-off-by: Tianling Shen +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y diff --git a/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch b/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch deleted file mode 100644 index bc450b0dd4..0000000000 --- a/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Tue, 11 Apr 2023 18:14:49 +0800 -Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C - -The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC -chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. - -The device tree is taken from the kernel linux-next branch: -https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 - -Signed-off-by: Tianling Shen -Reviewed-by: Kever Yang ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 3 + - arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ++++++++ - board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ - configs/nanopi-r2c-rk3328_defconfig | 112 +++++++++++++++++++++ - 5 files changed, 162 insertions(+) - create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts - create mode 100644 configs/nanopi-r2c-rk3328_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ -+ rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -@@ -0,0 +1,3 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ tx_delay = <0x22>; -+ rx_delay = <0x12>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; ---- a/board/rockchip/evb_rk3328/MAINTAINERS -+++ b/board/rockchip/evb_rk3328/MAINTAINERS -@@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328 - F: include/configs/evb_rk3328.h - F: configs/evb-rk3328_defconfig - -+NANOPI-R2C-RK3328 -+M: Tianling Shen -+S: Maintained -+F: configs/nanopi-r2c-rk3328_defconfig -+F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -+ - NANOPI-R2S-RK3328 - M: David Bauer - S: Maintained ---- /dev/null -+++ b/configs/nanopi-r2c-rk3328_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed53..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d9..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a927..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h deleted file mode 100644 index 0919e4ed53..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c deleted file mode 100644 index e5b330c9d9..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 4 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h deleted file mode 100644 index b1ff08a927..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h deleted file mode 100644 index 75795aa6cc..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c deleted file mode 100644 index 12081b19e0..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: spi_at_ff190000 rockchip_rk3328_spi - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15, - 0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0, - 0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8, - 0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4, - 0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c, - 0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120, - 0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190, - 0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244, - 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c, - 0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 4 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h deleted file mode 100644 index d095831531..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h deleted file mode 100644 index 75795aa6cc..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c deleted file mode 100644 index 90656fc306..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: serial_at_ff130000 ns16550_serial - * 4: spi_at_ff190000 rockchip_rk3328_spi - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 3 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 4 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h deleted file mode 100644 index d095831531..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h deleted file mode 100644 index 72675609cd..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c deleted file mode 100644 index aa03298e58..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, - 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, - 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, - 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, - 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, - 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, - 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, - 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, - 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, - 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, - 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_ddr_1_8v = true, - .mmc_hs200_1_8v = true, - .non_removable = true, - .pinctrl_0 = {0x4c, 0x4d, 0x4e, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1c, - .vqmmc_supply = 0x1d, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h deleted file mode 100644 index 5b729fc57f..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_ddr_1_8v; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool sd_uhs_sdr104; - bool sd_uhs_sdr12; - bool sd_uhs_sdr25; - bool sd_uhs_sdr50; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h deleted file mode 100644 index 72675609cd..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c deleted file mode 100644 index f86414d5d3..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x38, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15, - 0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0, - 0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8, - 0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4, - 0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c, - 0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180, - 0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0, - 0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, - 0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c, - 0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .card_detect_delay = 0xc8, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .num_slots = 0x1, - .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .supports_sd = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x49, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_hs200_1_8v = true, - .non_removable = true, - .num_slots = 0x1, - .pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .supports_emmc = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1c, - .vqmmc_supply = 0x1d, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x24, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* - * Node /syscon@ff100000 index 5 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h deleted file mode 100644 index fae089030b..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - fdt32_t card_detect_delay; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t num_slots; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool supports_emmc; - bool supports_sd; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h deleted file mode 100644 index a13aaea1fb..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares externs for all device/uclass instances. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include - -/* driver declarations - these allow DM_DRIVER_GET() to be used */ -extern U_BOOT_DRIVER(rockchip_rk3328_cru); -extern U_BOOT_DRIVER(rockchip_rk3328_dmc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); -extern U_BOOT_DRIVER(ns16550_serial); -extern U_BOOT_DRIVER(rockchip_rk3328_spi); -extern U_BOOT_DRIVER(jedec_spi_nor); -extern U_BOOT_DRIVER(rockchip_rk3328_grf); - -/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ -extern UCLASS_DRIVER(clk); -extern UCLASS_DRIVER(mmc); -extern UCLASS_DRIVER(ram); -extern UCLASS_DRIVER(serial); -extern UCLASS_DRIVER(spi_flash); -extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c deleted file mode 100644 index 70a8c001a3..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * DO NOT MODIFY - * - * Declares the U_BOOT_DRIVER() records and platform data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -/* Allow use of U_BOOT_DRVINFO() in this file */ -#define DT_PLAT_C - -#include -#include -#include - -/* - * driver_info declarations, ordered by 'struct driver_info' linker_list idx: - * - * idx driver_info driver - * --- -------------------- -------------------- - * 0: clock_controller_at_ff440000 rockchip_rk3328_cru - * 1: dmc rockchip_rk3328_dmc - * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc - * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc - * 4: serial_at_ff130000 ns16550_serial - * 5: spi_at_ff190000 rockchip_rk3328_spi - * 6: spiflash_at_0 jedec_spi_nor - * 7: syscon_at_ff100000 rockchip_rk3328_grf - * --- -------------------- -------------------- - */ - -/* - * Node /clock-controller@ff440000 index 0 - * driver rockchip_rk3328_cru parent None - */ -static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { - .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3b, -}; -U_BOOT_DRVINFO(clock_controller_at_ff440000) = { - .name = "rockchip_rk3328_cru", - .plat = &dtv_clock_controller_at_ff440000, - .plat_size = sizeof(dtv_clock_controller_at_ff440000), - .parent_idx = -1, -}; - -/* - * Node /dmc index 1 - * driver rockchip_rk3328_dmc parent None - */ -static struct dtd_rockchip_rk3328_dmc dtv_dmc = { - .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, - 0xff720000, 0x1000, 0xff798000, 0x1000}, - .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, - 0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15, - 0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0, - 0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8, - 0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4, - 0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c, - 0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120, - 0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190, - 0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244, - 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c, - 0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, - 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, - 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, - 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, - 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, - 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, - 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x79, 0x9}, -}; -U_BOOT_DRVINFO(dmc) = { - .name = "rockchip_rk3328_dmc", - .plat = &dtv_dmc, - .plat_size = sizeof(dtv_dmc), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff500000 index 2 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {0, {317}}, - {0, {33}}, - {0, {74}}, - {0, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4e, -}; -U_BOOT_DRVINFO(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff500000, - .plat_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* - * Node /mmc@ff520000 index 3 - * driver rockchip_rk3288_dw_mshc parent None - */ -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = { - .bus_width = 0x8, - .cap_mmc_highspeed = true, - .clocks = { - {0, {319}}, - {0, {35}}, - {0, {76}}, - {0, {80}},}, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xe, 0x4}, - .max_frequency = 0x8f0d180, - .mmc_hs200_1_8v = true, - .non_removable = true, - .pinctrl_0 = {0x4f, 0x50, 0x51, 0x0}, - .pinctrl_names = "default", - .reg = {0xff520000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x1e, - .vqmmc_supply = 0x1f, -}; -U_BOOT_DRVINFO(mmc_at_ff520000) = { - .name = "rockchip_rk3288_dw_mshc", - .plat = &dtv_mmc_at_ff520000, - .plat_size = sizeof(dtv_mmc_at_ff520000), - .parent_idx = -1, -}; - -/* - * Node /serial@ff130000 index 4 - * driver ns16550_serial parent None - */ -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {0, {40}}, - {0, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x27, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DRVINFO(serial_at_ff130000) = { - .name = "ns16550_serial", - .plat = &dtv_serial_at_ff130000, - .plat_size = sizeof(dtv_serial_at_ff130000), - .parent_idx = -1, -}; - -/* Node /spi@ff190000 index 5 */ -static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { - .clocks = { - {0, {32}}, - {0, {209}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x8, 0x10, 0x9}, - .interrupts = {0x0, 0x31, 0x4}, - .pinctrl_0 = {0x2f, 0x30, 0x31, 0x32}, - .pinctrl_names = "default", - .reg = {0xff190000, 0x1000}, -}; -U_BOOT_DRVINFO(spi_at_ff190000) = { - .name = "rockchip_rk3328_spi", - .plat = &dtv_spi_at_ff190000, - .plat_size = sizeof(dtv_spi_at_ff190000), - .parent_idx = -1, -}; - -/* - * Node /spi@ff190000/spiflash@0 index 6 - * driver jedec_spi_nor parent None - */ -static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = { - .reg = {0x0}, - .spi_max_frequency = 0x2faf080, -}; -U_BOOT_DRVINFO(spiflash_at_0) = { - .name = "jedec_spi_nor", - .plat = &dtv_spiflash_at_0, - .plat_size = sizeof(dtv_spiflash_at_0), - .parent_idx = 5, -}; - -/* - * Node /syscon@ff100000 index 7 - * driver rockchip_rk3328_grf parent None - */ -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DRVINFO(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .plat = &dtv_syscon_at_ff100000, - .plat_size = sizeof(dtv_syscon_at_ff100000), - .parent_idx = -1, -}; - diff --git a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h deleted file mode 100644 index e15d848729..0000000000 --- a/package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * DO NOT MODIFY - * - * Defines the structs used to hold devicetree data. - * This was generated by dtoc from a .dtb (device tree binary) file. - */ - -#include -#include -struct dtd_jedec_spi_nor { - fdt32_t reg[1]; - fdt32_t spi_max_frequency; -}; -struct dtd_ns16550_serial { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -struct dtd_rockchip_rk3288_dw_mshc { - fdt32_t bus_width; - bool cap_mmc_highspeed; - bool cap_sd_highspeed; - struct phandle_1_arg clocks[4]; - bool disable_wp; - fdt32_t fifo_depth; - fdt32_t interrupts[3]; - fdt32_t max_frequency; - bool mmc_hs200_1_8v; - bool non_removable; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; - bool u_boot_spl_fifo_mode; - fdt32_t vmmc_supply; - fdt32_t vqmmc_supply; -}; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_grf { - fdt64_t reg[2]; -}; -struct dtd_rockchip_rk3328_spi { - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0[4]; - const char * pinctrl_names; - fdt64_t reg[2]; -}; From b061e2d890bc47fe9ae352a4700f094cf2aea7b1 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:28 +0800 Subject: [PATCH 16/34] rkbin: add new TF-A package for rk35xx Currently there's no usable mainline (open source) TF-A implementation for rk35xx SoCs, so pack the prebuilt firmware from the vendor. Signed-off-by: Tianling Shen --- package/boot/rkbin/Makefile | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 package/boot/rkbin/Makefile diff --git a/package/boot/rkbin/Makefile b/package/boot/rkbin/Makefile new file mode 100644 index 0000000000..affdd7b4e1 --- /dev/null +++ b/package/boot/rkbin/Makefile @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2021-2023 ImmortalWrt.org + +include $(TOPDIR)/rules.mk + +PKG_NAME:=rkbin +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git +PKG_SOURCE_DATE:=2023-07-26 +PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23 +PKG_MIRROR_HASH:=5842fbcb7e217c336235573e431e427f2f745390d989f6765a6c258a5bdf1b6e + +PKG_LICENSE_FILES:=LICENSE +PKG_MAINTAINER:=Tianling Shen + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/trusted-firmware-a.mk +include $(INCLUDE_DIR)/package.mk + +define Trusted-Firmware-A/Default + NAME:=Rockchip $(1) SoCs + BUILD_TARGET:=rockchip +endef + +define Trusted-Firmware-A/rk3568 + BUILD_SUBTARGET:=armv8 + ATF:=rk35/rk3568_bl31_v1.43.elf + TPL:=rk35/rk3568_ddr_1560MHz_v1.18.bin +endef + +TFA_TARGETS:= \ + rk3568 + +define Build/Compile +endef + +define Package/trusted-firmware-a/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + + $(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/ + $(CP) $(PKG_BUILD_DIR)/bin/$(TPL) $(STAGING_DIR_IMAGE)/ +endef + +$(eval $(call BuildPackage/Trusted-Firmware-A)) From dd8972fde37cacfce073ed70da92ee4a6ff51eea Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:28 +0800 Subject: [PATCH 17/34] rockchip: move image generation command to default It's applicable for all devices so move it to default to reduce redudant code. Addtionally introduce a new variable `BOOT_SCRIPT` to allow custom boot script (if necessary). Signed-off-by: Tianling Shen --- target/linux/rockchip/image/Makefile | 2 ++ target/linux/rockchip/image/armv8.mk | 13 ------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/target/linux/rockchip/image/Makefile b/target/linux/rockchip/image/Makefile index 3b118201b6..d34948f6ae 100644 --- a/target/linux/rockchip/image/Makefile +++ b/target/linux/rockchip/image/Makefile @@ -48,7 +48,9 @@ endef define Device/Default PROFILES := Default KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb + BOOT_SCRIPT := IMAGES := sysupgrade.img.gz + IMAGE/sysupgrade.img.gz = boot-common | boot-script $$(BOOT_SCRIPT) | pine64-img | gzip | append-metadata DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1))) UBOOT_DEVICE_NAME = $(lastword $(subst _, ,$(1)))-$$(SOC) endef diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index dd6a2d5bfe..608ad79ca4 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -11,7 +11,6 @@ define Device/firefly_roc-rk3328-cc SOC := rk3328 DEVICE_DTS := rockchip/rk3328-roc-cc UBOOT_DEVICE_NAME := roc-cc-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += firefly_roc-rk3328-cc @@ -19,7 +18,6 @@ define Device/friendlyarm_nanopc-t4 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPC T4 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio endef TARGET_DEVICES += friendlyarm_nanopc-t4 @@ -28,7 +26,6 @@ define Device/friendlyarm_nanopi-r2c DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2C SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2c @@ -37,7 +34,6 @@ define Device/friendlyarm_nanopi-r2s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2S SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2s @@ -47,7 +43,6 @@ define Device/friendlyarm_nanopi-r4s DEVICE_MODEL := NanoPi R4S DEVICE_VARIANT := 4GB LPDDR4 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-r8169 endef TARGET_DEVICES += friendlyarm_nanopi-r4s @@ -56,8 +51,6 @@ define Device/pine64_rock64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := Rock64 SOC := rk3328 - UBOOT_DEVICE_NAME := rock64-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += pine64_rock64 @@ -65,7 +58,6 @@ define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 SOC := rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += pine64_rockpro64 @@ -75,7 +67,6 @@ define Device/radxa_rock-pi-4a SOC := rk3399 SUPPORTED_DEVICES := radxa,rockpi4a radxa,rockpi4 UBOOT_DEVICE_NAME := rock-pi-4-rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-pi-4a @@ -83,8 +74,6 @@ define Device/radxa_rock-pi-e DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK Pi E SOC := rk3328 - UBOOT_DEVICE_NAME := rock-pi-e-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-pi-e @@ -92,7 +81,6 @@ define Device/xunlong_orangepi-r1-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += xunlong_orangepi-r1-plus @@ -101,7 +89,6 @@ define Device/xunlong_orangepi-r1-plus-lts DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus LTS SOC := rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += xunlong_orangepi-r1-plus-lts From 48c9a4b47c8bccd8d25de3bcc72544fd16e3c39d Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:28 +0800 Subject: [PATCH 18/34] rockchip: switch to kernel 6.1 Required by the following rk3568 support. Signed-off-by: Tianling Shen --- target/linux/rockchip/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index f17f0bdf49..42d75e3b4f 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -7,8 +7,7 @@ BOARDNAME:=Rockchip FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs SUBTARGETS:=armv8 -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 define Target/Description Build firmware image for Rockchip SoC devices. From 22a9c4b67d521527d19b34f63c263346194b769f Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:29 +0800 Subject: [PATCH 19/34] rockchip: remove kernel 5.15 patches and config As we switched to kernel 6.1, these files can go. Signed-off-by: Tianling Shen --- target/linux/rockchip/armv8/config-5.15 | 635 ------------------ ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 31 - ...-rockchip-Add-FriendlyARM-NanoPi-R2C.patch | 70 -- ...ockchip-rk3328-Add-Orange-Pi-R1-Plus.patch | 407 ----------- ...hip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch | 71 -- ...-rockchip-use-system-LED-for-OpenWrt.patch | 65 -- ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 24 - .../105-nanopi-r4s-sd-signalling.patch | 36 - .../patches-5.15/106-r4s-openwrt-leds.patch | 16 - ...ip-Update-LED-properties-for-Orange-.patch | 56 -- ...ip-add-LED-configuration-to-Orange-P.patch | 24 - .../109-nanopc-t4-add-led-aliases.patch | 16 - 12 files changed, 1451 deletions(-) delete mode 100644 target/linux/rockchip/armv8/config-5.15 delete mode 100644 target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch delete mode 100644 target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch delete mode 100644 target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch delete mode 100644 target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch delete mode 100644 target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch delete mode 100644 target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch delete mode 100644 target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch delete mode 100644 target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch delete mode 100644 target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch delete mode 100644 target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 deleted file mode 100644 index 54fad098dd..0000000000 --- a/target/linux/rockchip/armv8/config-5.15 +++ /dev/null @@ -1,635 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_EPAN=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CHARGER_GPIO=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FORTIFY_SOURCE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SYSCON=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_PCIE is not set -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_IIO=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -# CONFIG_INPUT_RK805_PWRKEY is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -CONFIG_KSM=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK808=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 -CONFIG_NVMEM=y -CONFIG_NVMEM_ROCKCHIP_EFUSE=y -# CONFIG_NVMEM_ROCKCHIP_OTP is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_STUB=y -CONFIG_PCS_XPCS=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_RK805=y -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ROCKCHIP_MBOX=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -# CONFIG_SPI_ROCKCHIP_SFC is not set -CONFIG_SPI_SPIDEV=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_DP_ALTMODE is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch deleted file mode 100644 index 792028b292..0000000000 --- a/target/linux/rockchip/patches-5.15/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ /dev/null @@ -1,31 +0,0 @@ -From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 7 Jun 2021 15:45:37 +0800 -Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S - -NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which -stores the MAC address. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,15 @@ - status = "disabled"; - }; - -+&i2c2 { -+ eeprom@51 { -+ compatible = "microchip,24c02", "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ read-only; /* This holds our MAC */ -+ }; -+}; -+ - &i2c4 { - status = "disabled"; - }; diff --git a/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch deleted file mode 100644 index f58463b3d1..0000000000 --- a/target/linux/rockchip/patches-5.15/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 25 Mar 2023 15:40:20 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C - -The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC -chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ tx_delay = <0x22>; -+ rx_delay = <0x12>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch deleted file mode 100644 index 053a4d0d8e..0000000000 --- a/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 3 Dec 2022 15:41:49 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus - -Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. - -This device is similar to the NanoPi R2S, and has a 16MB -SPI NOR (mx25l12805d). The reset button is changed to -directly reset the power supply, another detail is that -both network ports have independent MAC addresses. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ - 2 files changed, 374 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,373 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Based on rk3328-nanopi-r2s.dts, which is: -+ * Copyright (c) 2020 David Bauer -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328.dtsi" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus"; -+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -+ -+ aliases { -+ ethernet1 = &rtl8153; -+ mmc0 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ led-0 { -+ function = LED_FUNCTION_LAN; -+ color = ; -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-2 { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vdd_5v_lan: vdd-5v-lan-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&lan_vdd_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vdd_5v_lan"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&display_subsystem { -+ status = "disabled"; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ snps,aal; -+ rx_delay = <0x18>; -+ tx_delay = <0x24>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io>; -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_io>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac2io { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ lan { -+ lan_vdd_pin: lan-vdd-pin { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ vmmc-supply = <&vcc_sd>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Second port is for USB 3.0 */ -+ rtl8153: device@2 { -+ compatible = "usbbda,8153"; -+ reg = <2>; -+ }; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch deleted file mode 100644 index cedf28dc79..0000000000 --- a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 25 Mar 2023 15:40:22 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS - -The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with -the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise -identical to OrangePi R1 Plus. - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2016 Xunlong Software. Co., Ltd. -+ * (http://www.orangepi.org) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8531c>; -+ tx_delay = <0x19>; -+ rx_delay = <0x05>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8531c: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <15000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 01009c5eb8..0000000000 --- a/target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -16,6 +16,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - chosen { -@@ -49,18 +54,18 @@ - - lan_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; -+ label = "green:lan"; - }; - - sys_led: led-1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; -+ label = "red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; -+ label = "green:wan"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { diff --git a/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch deleted file mode 100644 index 2221077c97..0000000000 --- a/target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R2S. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 1 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -402,6 +402,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch deleted file mode 100644 index 856970738a..0000000000 --- a/target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: David Bauer -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S - -The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting -while U-Boot requires the card to be in 3.3V mode. - -Remove UHS support from the SD controller so the card remains in 3.3V -mode. This reduces transfer speeds but ensures a reboot whether from -userspace or following a kernel panic is always working. - -Signed-off-by: David Bauer - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -335,7 +335,6 @@ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; -- sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -121,6 +121,11 @@ - status = "disabled"; - }; - -+&sdmmc { -+ /delete-property/ sd-uhs-sdr104; -+ cap-sd-highspeed; -+}; -+ - &u2phy0_host { - phy-supply = <&vdd_5v>; - }; diff --git a/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch deleted file mode 100644 index d7579d61e9..0000000000 --- a/target/linux/rockchip/patches-5.15/106-r4s-openwrt-leds.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { diff --git a/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch deleted file mode 100644 index b1e26d4e3e..0000000000 --- a/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch +++ /dev/null @@ -1,56 +0,0 @@ -From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:10:52 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 - Plus - -Add OpenWrt's LED aliases for showing system status. -Also replace function/color with legacy label as OpenWrt relys on it -to update LED settings. - -Signed-off-by: Tianling Shen ---- - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -17,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -36,22 +41,18 @@ - pinctrl-names = "default"; - - led-0 { -- function = LED_FUNCTION_LAN; -- color = ; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; - }; - -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -+ status_led: led-1 { - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -+ label = "red:status"; - }; - - led-2 { -- function = LED_FUNCTION_WAN; -- color = ; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch deleted file mode 100644 index 37b59925fc..0000000000 --- a/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:38:04 +0800 -Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 - Plus - -Add the correct value for the RTL8153 LED configuration register to -match the blink behavior of the other port on the device. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -362,6 +362,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch deleted file mode 100644 index 1a80dadd48..0000000000 --- a/target/linux/rockchip/patches-5.15/109-nanopc-t4-add-led-aliases.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -15,6 +15,13 @@ - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; From 4be1e39c4e54fd2c7174e9e8c196265112103e1e Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:29 +0800 Subject: [PATCH 20/34] rockchip: enable drivers for rk356x Enable all necessary drivers for the rk356x SoCs, including PHY, SCMI, SPI etc. Also backport 2 upstream patches for sdhci fixes. Signed-off-by: Tianling Shen --- target/linux/rockchip/armv8/config-6.1 | 24 ++++++-- ...-Update-DLL-and-pre-change-delay-for.patch | 60 +++++++++++++++++++ ...mshc-properly-determine-max-clock-on.patch | 52 ++++++++++++++++ 3 files changed, 131 insertions(+), 5 deletions(-) create mode 100644 target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch create mode 100644 target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index 0f9a89f596..1830a89c93 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -66,6 +66,15 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=y +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_ARM_SCPI_PROTOCOL=y @@ -112,7 +121,7 @@ CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7 # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_CMA_SIZE_MBYTES=16 # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set @@ -121,6 +130,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y @@ -292,6 +302,7 @@ CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_RK3X=y CONFIG_IIO=y +# CONFIG_IIO_SCMI is not set CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INDIRECT_PIO=y CONFIG_INPUT=y @@ -300,7 +311,7 @@ CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_MATRIXKMAP=y -# CONFIG_INPUT_RK805_PWRKEY is not set +CONFIG_INPUT_RK805_PWRKEY=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set @@ -457,9 +468,9 @@ CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y -# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_PCIE=y -# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PINCTRL=y @@ -514,6 +525,7 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_ARM_SCMI=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y @@ -521,6 +533,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SCMI=y CONFIG_RFS_ACCEL=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -549,6 +562,7 @@ CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SAS_LIBSAS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_DW=y @@ -584,7 +598,7 @@ CONFIG_SPI_DYNAMIC=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_ROCKCHIP=y -# CONFIG_SPI_ROCKCHIP_SFC is not set +CONFIG_SPI_ROCKCHIP_SFC=y CONFIG_SPI_SPIDEV=y # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y diff --git a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch new file mode 100644 index 0000000000..2bb542be36 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch @@ -0,0 +1,60 @@ +From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001 +From: Shawn Lin +Date: Thu, 2 Feb 2023 08:35:16 +0800 +Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for + rockchip platform + +For Rockchip platform, DLL bypass bit and start bit need to be set if +DLL is not locked. And adjust pre-change delay to 0x3 for better signal +test result. + +Signed-off-by: Shawn Lin +Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -48,6 +48,7 @@ + #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 + #define DWCMSHC_EMMC_DLL_START_POINT 16 + #define DWCMSHC_EMMC_DLL_INC 8 ++#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) + #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) + #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 + #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA +@@ -60,6 +61,7 @@ + #define DLL_RXCLK_NO_INVERTER 1 + #define DLL_RXCLK_INVERTER 0 + #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 ++#define DLL_RXCLK_ORI_GATE BIT(31) + #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) + #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) + #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) +@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str + sdhci_writel(host, extra, reg); + + if (clock <= 52000000) { +- /* Disable DLL and reset both of sample and drive clock */ +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); ++ /* ++ * Disable DLL and reset both of sample and drive clock. ++ * The bypass bit and start bit need to be set if DLL is not locked. ++ */ ++ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); ++ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); + /* +@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str + } + + extra = 0x1 << 16 | /* tune clock stop en */ +- 0x2 << 17 | /* pre-change delay */ ++ 0x3 << 17 | /* pre-change delay */ + 0x3 << 19; /* post-change delay */ + sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + diff --git a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch new file mode 100644 index 0000000000..9d9c1b5c1c --- /dev/null +++ b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch @@ -0,0 +1,52 @@ +From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Thu, 9 Mar 2023 17:03:49 -0800 +Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on + Rockchip + +Currently .get_max_clock returns the current clock rate for cclk_emmc +on rk35xx, thus max clock gets set to whatever bootloader set it to. + +In case of u-boot, it is intentionally reset to 50 MHz if it boots +from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and +HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit +clears appropriate caps if host->mmc->f_max is < 52MHz + +cclk_emmc is not a fixed clock on rk35xx, so using +sdhci_pltfm_clk_get_max_clock is not appropriate here. + +Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc. + +Signed-off-by: Vasily Khoruzhick +Acked-by: Adrian Hunter +Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc + return pltfm_host->clock; + } + ++static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ ++ return clk_round_rate(pltfm_host->clk, ULONG_MAX); ++} ++ + static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, + struct mmc_request *mrq) + { +@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm + .set_clock = dwcmshc_rk3568_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, +- .get_max_clock = sdhci_pltfm_clk_get_max_clock, ++ .get_max_clock = rk35xx_get_max_clock, + .reset = rk35xx_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + }; From 4d9059aed9c03595962af95f4735225461119f3e Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:29 +0800 Subject: [PATCH 21/34] rockchip: armv8: broaden boardname Now we have rk356x support :-) Signed-off-by: Tianling Shen --- target/linux/rockchip/armv8/target.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/rockchip/armv8/target.mk b/target/linux/rockchip/armv8/target.mk index a5e60a613e..085b475c4b 100644 --- a/target/linux/rockchip/armv8/target.mk +++ b/target/linux/rockchip/armv8/target.mk @@ -1,6 +1,6 @@ ARCH:=aarch64 SUBTARGET:=armv8 -BOARDNAME:=RK33xx boards (64 bit) +BOARDNAME:=RK33xx/RK356x boards (64 bit) define Target/Description Build firmware image for Rockchip RK33xx devices. From 2670bb4a832b432cafeff255ddfffb90d7f86a07 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:30 +0800 Subject: [PATCH 22/34] uboot-rockchip: add NanoPi R5S support Add support for the FriendlyARM NanoPi R5S support. Tested-by: Packet Please Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 23 +- ...Add-support-for-FriendlyARM-NanoPi-R.patch | 917 ++++++++++++++++++ 2 files changed, 938 insertions(+), 2 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 35eaf198be..5e55077484 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -117,6 +117,23 @@ define U-Boot/rockpro64-rk3399 pine64_rockpro64 endef + +# RK3568 boards + +define U-Boot/rk3568/Default + BUILD_SUBTARGET:=armv8 + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568 + ATF:=rk3568_bl31_v1.43.elf + TPL:=rk3568_ddr_1560MHz_v1.18.bin +endef + +define U-Boot/nanopi-r5s-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5s +endef + UBOOT_TARGETS := \ nanopc-t4-rk3399 \ nanopi-r4s-rk3399 \ @@ -128,7 +145,8 @@ UBOOT_TARGETS := \ orangepi-r1-plus-lts-rk3328 \ roc-cc-rk3328 \ rock64-rk3328 \ - rock-pi-e-rk3328 + rock-pi-e-rk3328 \ + nanopi-r5s-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes @@ -139,7 +157,8 @@ UBOOT_CUSTOMIZE_CONFIG := \ UBOOT_MAKE_FLAGS += \ PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ - BL31=$(STAGING_DIR_IMAGE)/$(ATF) + BL31=$(STAGING_DIR_IMAGE)/$(ATF) \ + $(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL)) define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..09cafb3227 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,917 @@ +From c84214aab0e4c5b2f619dd89655f27b3ae40e82b Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue, 30 May 2023 15:00:33 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S + +FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device. + +Board Specifications +- Rockchip RK3568 +- 2 or 4GB LPDDR4X +- 8GB or 16GB eMMC, SD card slot +- GbE LAN (Native) +- 2x 2.5G LAN (PCIe) +- M.2 Connector +- HDMI 2.0, MIPI DSI/CSI +- 2xUSB 3.0 Host +- USB Type C PD, 5V/9V/12V +- GPIO: 12-pin 0.5mm FPC connector + +The device tree is taken from kernel v6.4-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 31 ++ + arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ + arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ + board/rockchip/evb_rk3568/MAINTAINERS | 8 + + configs/nanopi-r5s-rk3568_defconfig | 85 +++ + 6 files changed, 851 insertions(+) + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts + create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi + create mode 100644 configs/nanopi-r5s-rk3568_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ ++ rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3588) += \ +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++}; ++ ++&uart2 { ++ clock-frequency = <24000000>; ++ bootph-all; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s.dts +@@ -0,0 +1,136 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5S"; ++ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; ++ ++ led-lan1 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <1>; ++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-lan2 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <2>; ++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 15ms, 50ms for rtl8211f */ ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy0_reset_pin>; ++ pinctrl-names = "default"; ++ }; ++}; ++ ++&pcie2x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ num-ib-windows = <8>; ++ num-ob-windows = <8>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac0 { ++ eth_phy0_reset_pin: eth-phy0-reset-pin { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi +@@ -0,0 +1,590 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig + F: arch/arm/dts/rk3568-evb-boot.dtsi + F: arch/arm/dts/rk3568-evb.dts + ++NANOPI-R5S ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r5s-rk3568_defconfig ++F: arch/arm/dts/rk3568-nanopi-r5s.dts ++F: arch/arm/dts/rk3568-nanopi-r5s.dtsi ++F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi ++ + RADXA-CM3 + M: Jagan Teki + S: Maintained +--- /dev/null ++++ b/configs/nanopi-r5s-rk3568_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y From c06a71f0b3fae00dbd402840ea6e3b532c35b0da Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:30 +0800 Subject: [PATCH 23/34] rockchip: add NanoPi R5S support Hardware -------- RockChip RK3568 ARM64 (4 cores) 2GB or 4GB LPDDR4X RAM 1x 1000 Base-T 2x 2500 Base-T 4 LEDs (LAN1 / LAN2 / WAN / POWER) 8GB eMMC on-board Micro-SD Slot M.2 Slot 2x USB 3.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Tested-by: Packet Please Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 5 + .../armv8/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/net/40-net-smp-affinity | 5 + target/linux/rockchip/image/armv8.mk | 8 + ...rockchip-Add-FriendlyElec-Nanopi-R5S.patch | 754 ++++++++++ ...eate-common-dtsi-for-NanoPi-R5-serie.patch | 1226 +++++++++++++++++ ...chip-fix-gmac-support-for-NanoPi-R5S.patch | 49 + ...move-I2S1-TDM-node-for-the-NanoPi-R5.patch | 39 + ...ip-Update-LED-properties-for-NanoPi-.patch | 63 + 9 files changed, 2156 insertions(+) create mode 100644 target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch create mode 100644 target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch create mode 100644 target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch create mode 100644 target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch create mode 100644 target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index d82e47cf53..cfab545849 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -16,6 +16,11 @@ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; +friendlyarm,nanopi-r5s) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" + ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" + ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2" + ;; esac board_config_flush diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 7ac5148275..838a107193 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -14,6 +14,9 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; + friendlyarm,nanopi-r5s) + ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' + ;; *) ucidef_set_interface_lan 'eth0' ;; @@ -58,6 +61,10 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; + friendlyarm,nanopi-r5s) + wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; xunlong,orangepi-r1-plus|\ xunlong,orangepi-r1-plus-lts) wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index bb119b9185..161059a87b 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -40,5 +40,10 @@ friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; +friendlyarm,nanopi-r5s) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + set_interface_core 8 "eth2" + ;; esac diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 608ad79ca4..e836e3c91d 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -47,6 +47,14 @@ define Device/friendlyarm_nanopi-r4s endef TARGET_DEVICES += friendlyarm_nanopi-r4s +define Device/friendlyarm_nanopi-r5s + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R5S + SOC := rk3568 + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += friendlyarm_nanopi-r5s + define Device/pine64_rock64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := Rock64 diff --git a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch new file mode 100644 index 0000000000..3d502a65b6 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch @@ -0,0 +1,754 @@ +From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Tue, 7 Mar 2023 22:32:40 -0800 +Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S + +FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. + +Board Specifications +- Rockchip RK3568 +- 2 or 4GB LPDDR4X +- 8GB or 16GB eMMC, SD card slot +- GbE LAN (Native) +- 2x 2.5G LAN (PCIe) +- M.2 Connector +- HDMI 2.0, MIPI DSI/CSI +- 2xUSB 3.0 Host +- USB Type C PD, 5V/9V/12V +- GPIO: 12-pin 0.5mm FPC connector + +Based on Tianling Shen's work. + +Signed-off-by: Vasily Khoruzhick +Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++ + 2 files changed, 714 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -0,0 +1,713 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5S"; ++ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; ++ ++ led-lan1 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <1>; ++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-lan2 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ function-enumerator = <2>; ++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 15ms, 50ms for rtl8211f */ ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy0_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ num-ib-windows = <8>; ++ num-ob-windows = <8>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac0 { ++ eth_phy0_reset_pin: eth-phy0-reset-pin { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ gpio-leds { ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch new file mode 100644 index 0000000000..cf9fe06ad0 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch @@ -0,0 +1,1226 @@ +From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:41 +0800 +Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series + +Create common dtsi for the FriendlyElec NanoPi R5 series. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +---------------- + .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++ + 2 files changed, 597 insertions(+), 574 deletions(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -7,12 +7,7 @@ + */ + + /dts-v1/; +-#include +-#include +-#include +-#include +-#include +-#include "rk3568.dtsi" ++#include "rk3568-nanopi-r5s.dtsi" + + / { + model = "FriendlyElec NanoPi R5S"; +@@ -20,23 +15,6 @@ + + aliases { + ethernet0 = &gmac0; +- mmc0 = &sdmmc0; +- mmc1 = &sdhci; +- }; +- +- chosen: chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- hdmi-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; + }; + + gpio-leds { +@@ -71,130 +49,6 @@ + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +- +- vdd_usbc: vdd-usbc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_usbc"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc3v3_sys: vcc3v3-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc5v0_sys: vcc5v0-sys-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc3v3_pcie: vcc3v3-pcie-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- enable-active-high; +- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; +- startup-delay-us = <200000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_usb: vcc5v0-usb-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vdd_usbc>; +- }; +- +- vcc5v0_usb_host: vcc5v0-usb-host-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_host_en>; +- regulator-name = "vcc5v0_usb_host"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_otg_en>; +- regulator-name = "vcc5v0_usb_otg"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_usb>; +- }; +- +- pcie30_avdd0v9: pcie30-avdd0v9-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pcie30_avdd0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc3v3_sys>; +- }; +- +- pcie30_avdd1v8: pcie30-avdd1v8-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "pcie30_avdd1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc3v3_sys>; +- }; +-}; +- +-&combphy0 { +- status = "okay"; +-}; +- +-&combphy1 { +- status = "okay"; +-}; +- +-&combphy2 { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu1 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu2 { +- cpu-supply = <&vdd_cpu>; +-}; +- +-&cpu3 { +- cpu-supply = <&vdd_cpu>; + }; + + &gmac0 { +@@ -219,292 +73,6 @@ + status = "okay"; + }; + +-&gpu { +- mali-supply = <&vdd_gpu>; +- status = "okay"; +-}; +- +-&hdmi { +- avdd-0v9-supply = <&vdda0v9_image>; +- avdd-1v8-supply = <&vcca1v8_image>; +- status = "okay"; +-}; +- +-&hdmi_in { +- hdmi_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi>; +- }; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- +-&hdmi_sound { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +- +- vdd_cpu: regulator@1c { +- compatible = "tcs,tcs4525"; +- reg = <0x1c>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1150000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk809: pmic@20 { +- compatible = "rockchip,rk809"; +- reg = <0x20>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- #clock-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; +- rockchip,system-power-controller; +- vcc1-supply = <&vcc3v3_sys>; +- vcc2-supply = <&vcc3v3_sys>; +- vcc3-supply = <&vcc3v3_sys>; +- vcc4-supply = <&vcc3v3_sys>; +- vcc5-supply = <&vcc3v3_sys>; +- vcc6-supply = <&vcc3v3_sys>; +- vcc7-supply = <&vcc3v3_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc3v3_sys>; +- wakeup-source; +- +- regulators { +- vdd_logic: DCDC_REG1 { +- regulator-name = "vdd_logic"; +- regulator-always-on; +- regulator-boot-on; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: DCDC_REG2 { +- regulator-name = "vdd_gpu"; +- regulator-always-on; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-initial-mode = <0x2>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vdd_npu: DCDC_REG4 { +- regulator-name = "vdd_npu"; +- regulator-init-microvolt = <900000>; +- regulator-initial-mode = <0x2>; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <1350000>; +- regulator-ramp-delay = <6001>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG5 { +- regulator-name = "vcc_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda0v9_image: LDO_REG1 { +- regulator-name = "vdda0v9_image"; +- regulator-min-microvolt = <950000>; +- regulator-max-microvolt = <950000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda_0v9: LDO_REG2 { +- regulator-name = "vdda_0v9"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdda0v9_pmu: LDO_REG3 { +- regulator-name = "vdda0v9_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vccio_acodec: LDO_REG4 { +- regulator-name = "vccio_acodec"; +- regulator-always-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd: LDO_REG5 { +- regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_pmu: LDO_REG6 { +- regulator-name = "vcc3v3_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcca_1v8: LDO_REG7 { +- regulator-name = "vcca_1v8"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcca1v8_pmu: LDO_REG8 { +- regulator-name = "vcca1v8_pmu"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_image: LDO_REG9 { +- regulator-name = "vcca1v8_image"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3: SWITCH_REG1 { +- regulator-name = "vcc_3v3"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc3v3_sd: SWITCH_REG2 { +- regulator-name = "vcc3v3_sd"; +- regulator-always-on; +- regulator-boot-on; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- +- }; +-}; +- +-&i2c5 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- #clock-cells = <0>; +- clock-output-names = "rtcic_32kout"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- wakeup-source; +- }; +-}; +- +-&i2s0_8ch { +- status = "okay"; +-}; +- +-&i2s1_8ch { +- rockchip,trcm-sync-tx-only; +- status = "okay"; +-}; +- + &mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -568,146 +136,5 @@ + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +- +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- pmic { +- pmic_int: pmic-int { +- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; +- +- usb { +- vcc5v0_usb_host_en: vcc5v0-usb-host-en { +- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { +- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pmu_io_domains { +- pmuio1-supply = <&vcc3v3_pmu>; +- pmuio2-supply = <&vcc3v3_pmu>; +- vccio1-supply = <&vccio_acodec>; +- vccio3-supply = <&vccio_sd>; +- vccio4-supply = <&vcc_1v8>; +- vccio5-supply = <&vcc_3v3>; +- vccio6-supply = <&vcc_1v8>; +- vccio7-supply = <&vcc_3v3>; +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&vcca_1v8>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- max-frequency = <200000000>; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; +- status = "okay"; +-}; +- +-&sdmmc0 { +- max-frequency = <150000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- disable-wp; +- vmmc-supply = <&vcc3v3_sd>; +- vqmmc-supply = <&vccio_sd>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; +- status = "okay"; +-}; +- +-&tsadc { +- rockchip,hw-tshut-mode = <1>; +- rockchip,hw-tshut-polarity = <0>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host0_xhci { +- extcon = <&usb2phy0>; +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; + }; + +-&usb_host1_xhci { +- status = "okay"; +-}; +- +-&usb2phy0 { +- status = "okay"; +-}; +- +-&usb2phy0_host { +- phy-supply = <&vcc5v0_usb_host>; +- status = "okay"; +-}; +- +-&usb2phy0_otg { +- status = "okay"; +-}; +- +-&usb2phy1 { +- status = "okay"; +-}; +- +-&usb2phy1_host { +- phy-supply = <&vcc5v0_usb_otg>; +- status = "okay"; +-}; +- +-&usb2phy1_otg { +- status = "okay"; +-}; +- +-&vop { +- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; +- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&vp0 { +- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi_in_vp0>; +- }; +-}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -0,0 +1,596 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vdd_usbc: vdd-usbc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch new file mode 100644 index 0000000000..47f76d54e7 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch @@ -0,0 +1,49 @@ +From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:44 +0800 +Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S + +- Changed phy-mode to rgmii. + +- Fixed pull type in pinctrl for gmac0. + +- Removed duplicate properties in mdio node. + These properties are defined in the gmac0 node already. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -57,7 +57,7 @@ + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; +- phy-mode = "rgmii-id"; ++ phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 +@@ -79,9 +79,6 @@ + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; +- reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + }; + +@@ -115,7 +112,7 @@ + &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { +- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch new file mode 100644 index 0000000000..48021b226a --- /dev/null +++ b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch @@ -0,0 +1,39 @@ +From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:45 +0800 +Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5 + series + +This is for the audio output which does not exist on the boards. +Also disable regulator-always-on for vccio_acodec since it's only +used by the audio output. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -330,7 +330,6 @@ + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; +- regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + +@@ -441,11 +440,6 @@ + status = "okay"; + }; + +-&i2s1_8ch { +- rockchip,trcm-sync-tx-only; +- status = "okay"; +-}; +- + &pcie30phy { + data-lanes = <1 2>; + status = "okay"; diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch new file mode 100644 index 0000000000..8339ef5dbc --- /dev/null +++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch @@ -0,0 +1,63 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue Jun 20 16:45:27 2023 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5 + series + +Add OpenWrt's LED aliases for showing system status. +Also replace function/color with legacy label as OpenWrt relys on it +to update LED settings. + +Signed-off-by: Tianling Shen +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -23,29 +23,22 @@ + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <1>; ++ label = "green:lan1"; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <2>; ++ label = "green:lan2"; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; ++ label = "red:power"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { +- color = ; +- function = LED_FUNCTION_WAN; ++ label = "green:wan"; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -18,6 +18,11 @@ + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen: chosen { From e2cea0506a5beb9c6c988783d87bf2dd441c464e Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:30 +0800 Subject: [PATCH 24/34] uboot-rockchip: add NanoPi R5C support Add support for the FriendlyARM NanoPi R5C. Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 8 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 269 ++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 5e55077484..1dad3c1e1c 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -127,6 +127,13 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.18.bin endef +define U-Boot/nanopi-r5c-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5c +endef + define U-Boot/nanopi-r5s-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5S @@ -146,6 +153,7 @@ UBOOT_TARGETS := \ roc-cc-rk3328 \ rock64-rk3328 \ rock-pi-e-rk3328 \ + nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000000..d1a5197e7d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/104-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,269 @@ +From 41538742491c46100f570680c02fbdd0d2b6b880 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue, 30 May 2023 15:00:33 +0800 +Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C + +FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. + +Specification: +- Rockchip RK3568 +- 1/4GB LPDDR4X RAM +- 8/32GB eMMC +- SD card slot +- M.2 Connector +- 2x USB 3.0 Port +- 2x 2500 Base-T (PCIe, r8125) +- HDMI 2.0 +- MIPI DSI/CSI +- USB Type C 5V + +The device tree is taken from kernel v6.4-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 + + arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++ + board/rockchip/evb_rk3568/MAINTAINERS | 7 ++ + configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++ + 5 files changed, 208 insertions(+) + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts + create mode 100644 configs/nanopi-r5c-rk3568_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ ++ rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +@@ -0,0 +1,3 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++#include "rk3568-nanopi-r5s-u-boot.dtsi" +--- /dev/null ++++ b/arch/arm/dts/rk3568-nanopi-r5c.dts +@@ -0,0 +1,112 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5C"; ++ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; ++ ++ led-lan { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_reset_pin>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_led_pin: wlan-led-pin { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_reset_pin: pcie20-reset-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig + F: arch/arm/dts/rk3568-evb-boot.dtsi + F: arch/arm/dts/rk3568-evb.dts + ++NANOPI-R5C ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r5c-rk3568_defconfig ++F: arch/arm/dts/rk3568-nanopi-r5c.dts ++F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi ++ + NANOPI-R5S + M: Tianling Shen + S: Maintained +--- /dev/null ++++ b/configs/nanopi-r5c-rk3568_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_EVB_RK3568=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_WARN=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y From 4e09722a68825274048806c37a405eb3ee25500c Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Jun 2023 00:37:31 +0800 Subject: [PATCH 25/34] rockchip: add NanoPi R5C support Hardware -------- RockChip RK3568 ARM64 (4 cores) 1GB or 4GB LPDDR4X RAM 2x 2500 Base-T 4 LEDs (LAN / WAN / WIFI / POWER) 1 Button (Reset) 8GB or 32GB eMMC on-board Micro-SD Slot M.2 Slot 2x USB 3.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 5 + .../armv8/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/net/40-net-smp-affinity | 4 + target/linux/rockchip/image/armv8.mk | 8 + ...-rockchip-Add-FriendlyARM-NanoPi-R5C.patch | 152 ++++++++++++++++++ ...-fix-button-reset-pin-for-nanopi-r5c.patch | 37 +++++ ...ip-Update-LED-properties-for-NanoPi-.patch | 34 ++++ 7 files changed, 247 insertions(+) create mode 100644 target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch create mode 100644 target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index cfab545849..fbbe2735e9 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -16,6 +16,11 @@ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; +friendlyarm,nanopi-r5c) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" + ucidef_set_led_netdev "wlan" "WLAN" "green:wlan" "phy0-ap0" + ;; friendlyarm,nanopi-r5s) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 838a107193..01e32c7740 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -14,6 +14,9 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; + friendlyarm,nanopi-r5c) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; @@ -61,6 +64,10 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; + friendlyarm,nanopi-r5c) + wan_mac=$(macaddr_generate_from_mmc_cid mmcblk*) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; friendlyarm,nanopi-r5s) wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) lan_mac=$(macaddr_add "$wan_mac" 1) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 161059a87b..84064d4f8b 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -40,6 +40,10 @@ friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; +friendlyarm,nanopi-r5c) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + ;; friendlyarm,nanopi-r5s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index e836e3c91d..0bf91d15ca 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -47,6 +47,14 @@ define Device/friendlyarm_nanopi-r4s endef TARGET_DEVICES += friendlyarm_nanopi-r4s +define Device/friendlyarm_nanopi-r5c + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R5C + SOC := rk3568 + DEVICE_PACKAGES := kmod-r8169 kmod-rtw88-8822ce rtl8822ce-firmware wpad-basic-mbedtls +endef +TARGET_DEVICES += friendlyarm_nanopi-r5c + define Device/friendlyarm_nanopi-r5s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R5S diff --git a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch new file mode 100644 index 0000000000..0465d80cba --- /dev/null +++ b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch @@ -0,0 +1,152 @@ +From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 18 Mar 2023 16:37:43 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C + +FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. + +Specification: +- Rockchip RK3568 +- 1/4GB LPDDR4X RAM +- 8/32GB eMMC +- SD card slot +- M.2 Connector +- 2x USB 3.0 Port +- 2x 2500 Base-T (PCIe, r8125) +- HDMI 2.0 +- MIPI DSI/CSI +- USB Type C 5V + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++ + 2 files changed, 113 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -0,0 +1,112 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3568-nanopi-r5s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R5C"; ++ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; ++ ++ led-lan { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power_led: led-power { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wan { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-wlan { ++ color = ; ++ function = LED_FUNCTION_WLAN; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_reset_pin>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <1>; ++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_led_pin: wlan-led-pin { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_reset_pin: pcie20-reset-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch new file mode 100644 index 0000000000..0e59f0275b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch @@ -0,0 +1,37 @@ +From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 11 May 2023 00:18:50 +0800 +Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c + +The reset pin was wrongly assigned due to a copy/paste error, +fix it to match actual gpio pin. + +While at it, remove a blank line from nanopi r5s dts. + +Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C") +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -106,7 +106,7 @@ + + rockchip-key { + reset_button_pin: reset-button-pin { +- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -134,4 +134,3 @@ + }; + }; + }; +- diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch index 8339ef5dbc..64dc433a30 100644 --- a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch +++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch @@ -11,6 +11,40 @@ to update LED settings. Signed-off-by: Tianling Shen --- +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -32,27 +32,22 @@ + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; + + led-lan { +- color = ; +- function = LED_FUNCTION_LAN; ++ label = "green:lan"; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; ++ label = "red:power"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { +- color = ; +- function = LED_FUNCTION_WAN; ++ label = "green:wan"; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-wlan { +- color = ; +- function = LED_FUNCTION_WLAN; ++ label = "green:wlan"; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -23,29 +23,22 @@ From 711dcb77630e96e75413b5cdbe3ddb5432f394f6 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Sat, 18 Nov 2023 16:29:09 +0100 Subject: [PATCH 26/34] dnsmasq: mark global ubus context as closed after fork If the dnsmasq process forks to handle TCP connections, it closes the ubus context. But instead of changing the daemon wide pointer to NULL, only the local variable was adjusted - and this portion of the code was even dropped (dead store) by some optimizing compilers. It makes more sense to change the daemon->ubus pointer because various functions are already checking it for NULL. It is also the behavior which ubus_destroy() implements. Fixes: d8b33dad0bb7 ("dnsmasq: add support for monitoring and modifying dns lookup results via ubus") Signed-off-by: Sven Eckelmann --- package/network/services/dnsmasq/patches/200-ubus_dns.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/network/services/dnsmasq/patches/200-ubus_dns.patch b/package/network/services/dnsmasq/patches/200-ubus_dns.patch index 8a70bb8bdf..ccbe70ab9c 100644 --- a/package/network/services/dnsmasq/patches/200-ubus_dns.patch +++ b/package/network/services/dnsmasq/patches/200-ubus_dns.patch @@ -210,7 +210,7 @@ + return; + + ubus_free(ubus); -+ ubus = NULL; ++ daemon->ubus = NULL; +} + static int ubus_handle_metrics(struct ubus_context *ctx, struct ubus_object *obj, From 5899689159e2a608b74a20b103e052128d443672 Mon Sep 17 00:00:00 2001 From: Xiaojun Liu Date: Mon, 13 Nov 2023 03:59:45 +0000 Subject: [PATCH 27/34] x86 64: Add new device Cordoba Edge Platform Add new device Cordoba Edge Platform hardware specifications: CPU - Intel Atom C3000 Ethernet - 2 10Gbps ixgbe SPF+ 2 1Gbps ixgbe RJ45/SPF 4 2.5Gbps igc RJ45 WiFi - mt7915e LED - 3 multicolor(red|blue|green) LEDs Signed-off-by: Xiaojun Liu --- target/linux/x86/base-files/etc/board.d/01_leds | 4 ++++ target/linux/x86/base-files/etc/board.d/02_network | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/linux/x86/base-files/etc/board.d/01_leds b/target/linux/x86/base-files/etc/board.d/01_leds index efc5460df3..47ea0929e6 100644 --- a/target/linux/x86/base-files/etc/board.d/01_leds +++ b/target/linux/x86/base-files/etc/board.d/01_leds @@ -28,6 +28,10 @@ traverse-technologies-geos) ucidef_set_led_netdev "wlan" "WiFi" "geos:2" "phy0tpt" ucidef_set_led_default "diag" "DIAG" "geos:3" "1" ;; +silicom-80500-0214-*) + ucidef_set_led_netdev "wan" "WAN" "multicolor:fp_center" "wan0" + ucidef_set_led_netdev "lan" "LAN" "multicolor:fp_right" "br-lan" + ;; esac board_config_flush diff --git a/target/linux/x86/base-files/etc/board.d/02_network b/target/linux/x86/base-files/etc/board.d/02_network index 0a0f32eb80..b18ab60120 100644 --- a/target/linux/x86/base-files/etc/board.d/02_network +++ b/target/linux/x86/base-files/etc/board.d/02_network @@ -78,6 +78,17 @@ traverse-technologies-geos) macaddr="$(cat /sys/class/net/eth0/address)" 2>/dev/null [ -n "$macaddr" ] && ucidef_set_interface_macaddr "wan" "$macaddr" ;; +silicom-80500-0214-*) + ucidef_set_network_device_path "wan0" "pci0000:00/0000:00:16.0/0000:03:00.0" + ucidef_set_network_device_path "wan1" "pci0000:00/0000:00:16.0/0000:03:00.1" + ucidef_set_network_device_path "media0" "pci0000:00/0000:00:17.0/0000:02:00.1" + ucidef_set_network_device_path "media1" "pci0000:00/0000:00:17.0/0000:02:00.0" + ucidef_set_network_device_path "eth0" "pci0000:00/0000:00:0c.0/0000:04:00.0" + ucidef_set_network_device_path "eth1" "pci0000:00/0000:00:0e.0/0000:05:00.0" + ucidef_set_network_device_path "eth2" "pci0000:00/0000:00:0f.0/0000:06:00.0" + ucidef_set_network_device_path "eth3" "pci0000:00/0000:00:10.0/0000:07:00.0" + ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3" "wan0" + ;; esac board_config_flush From fa55f595fbd66ad38e09dbf139dad35b9b6e5804 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 26 Nov 2023 20:37:01 +0100 Subject: [PATCH 28/34] ustream-ssl: update to Git HEAD (2023-11-26) 91666a3 ustream-mbedtls: Add compatibility with Mbed TLS 3.0.0 263b9a9 cmake: Fail if undefined symbols are used Signed-off-by: Hauke Mehrtens --- package/libs/ustream-ssl/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/ustream-ssl/Makefile b/package/libs/ustream-ssl/Makefile index ae5c8026c2..076053abf6 100644 --- a/package/libs/ustream-ssl/Makefile +++ b/package/libs/ustream-ssl/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git -PKG_SOURCE_DATE:=2023-02-25 -PKG_SOURCE_VERSION:=498f6e268d4d2b0ad33b430f4ba1abe397d31496 -PKG_MIRROR_HASH:=a201d065dd613e30886c9f13a0851cec79538192cfe591b6f8ecd88724d55fb1 +PKG_SOURCE_DATE:=2023-11-26 +PKG_SOURCE_VERSION:=263b9a97cf7e1e2467319c23832b705fc01190b5 +PKG_MIRROR_HASH:=1c01d633f21c6cb578a785826d1983284b28f49b20d608d82179842dcdbeed6e CMAKE_INSTALL:=1 PKG_LICENSE:=ISC From cee7622ab0cd0d7154f93793a8fc8508c016aa7e Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Sat, 25 Nov 2023 03:09:30 +0100 Subject: [PATCH 29/34] ath79: fortinet-fap-220-b: fix WLAN MAC addresses Addresses were swapped compared to the factory firmware. In addition to that, one of them was shifted by -1. Fix that by setting wlan0 MAC offset to 9, and wlan1 MAC offset to 2. Signed-off-by: Lech Perczak --- target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts index 331bc31714..63fe9ade53 100644 --- a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts +++ b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts @@ -101,7 +101,7 @@ ieee80211-freq-limit = <2402000 2482000>; nvmem-cells = <&macaddr_art_120c>, <&cal_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <1>; + mac-address-increment = <9>; #gpio-cells = <2>; gpio-controller; }; @@ -112,7 +112,7 @@ ieee80211-freq-limit = <2402000 2482000 4900000 5990000>; nvmem-cells = <&macaddr_art_520c>, <&cal_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <9>; + mac-address-increment = <2>; #gpio-cells = <2>; gpio-controller; }; From 7e5e0100358d59e6652ddbe2869f804c19854922 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Thu, 16 Nov 2023 17:17:32 +0100 Subject: [PATCH 30/34] ath79: fortinet-fap-220-b: convert to nvmem-layout Now that MAC address parser supports the hex format (without delimiters), use the canonical MAC address stored in U-boot partition. Get rid of the "mac-address-increment" binding. While at that, convert ART partition too. Signed-off-by: Lech Perczak --- .../ath79/dts/ar7161_fortinet_fap-220-b.dts | 45 ++++++------------- .../ath79/dts/arxxxx_fortinet_loader.dtsi | 12 +++++ 2 files changed, 25 insertions(+), 32 deletions(-) diff --git a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts index 63fe9ade53..ddcf68970d 100644 --- a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts +++ b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts @@ -99,9 +99,8 @@ compatible = "pci168c,0029"; reg = <0x8800 0 0 0 0>; ieee80211-freq-limit = <2402000 2482000>; - nvmem-cells = <&macaddr_art_120c>, <&cal_art_1000>; + nvmem-cells = <&macaddr_uboot_3ff80 9>, <&cal_art_1000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <9>; #gpio-cells = <2>; gpio-controller; }; @@ -110,9 +109,8 @@ compatible = "pci168c,0029"; reg = <0x9000 0 0 0 0>; ieee80211-freq-limit = <2402000 2482000 4900000 5990000>; - nvmem-cells = <&macaddr_art_520c>, <&cal_art_5000>; + nvmem-cells = <&macaddr_uboot_3ff80 2>, <&cal_art_5000>; nvmem-cell-names = "mac-address", "calibration"; - mac-address-increment = <2>; #gpio-cells = <2>; gpio-controller; }; @@ -133,7 +131,7 @@ ð1 { status = "okay"; - nvmem-cells = <&macaddr_art_120c>; + nvmem-cells = <&macaddr_uboot_3ff80 0>; nvmem-cell-names = "mac-address"; pll-data = <0x00110000 0x00001099 0x00991099>; @@ -149,35 +147,18 @@ status = "okay"; }; -&uboot { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - /* Currently doesn't work, because this one lacks colons as delimiters */ - macaddr_uboot_3ff80: mac-address-ascii@3ff80 { - reg = <0x3ff80 0xc>; - }; -}; - &art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - cal_art_1000: calibration@1000 { - reg = <0x1000 0xeb8>; - }; + cal_art_1000: calibration@1000 { + reg = <0x1000 0xeb8>; + }; - macaddr_art_120c: mac-address@120c { - reg = <0x120c 0x6>; - }; - - cal_art_5000: calibration@5000 { - reg = <0x5000 0xeb8>; - }; - - macaddr_art_520c: mac-address@520c { - reg = <0x520c 0x6>; + cal_art_5000: calibration@5000 { + reg = <0x5000 0xeb8>; + }; }; }; diff --git a/target/linux/ath79/dts/arxxxx_fortinet_loader.dtsi b/target/linux/ath79/dts/arxxxx_fortinet_loader.dtsi index 3bc734313f..786626828f 100644 --- a/target/linux/ath79/dts/arxxxx_fortinet_loader.dtsi +++ b/target/linux/ath79/dts/arxxxx_fortinet_loader.dtsi @@ -40,6 +40,18 @@ label = "u-boot"; reg = <0x000000 0x040000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_uboot_3ff80: mac-address@3ff80 { + compatible = "mac-base"; + reg = <0x3ff80 0xc>; + #nvmem-cell-cells = <1>; + }; + }; }; fwconcat0: partition@40000 { From 32098554d911f092b9779e4768bf6d819d850bb5 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Thu, 16 Nov 2023 17:30:11 +0100 Subject: [PATCH 31/34] ath79: fortinet-fap-221-b: convert to nvmem-layout Now that MAC address parser supports the hex format (without delimiters), use the canonical MAC address stored in U-boot partition. Get rid of the userspace adjustments which are no longer necessary. While at that, move the mac-base to the common part, as it is again exactly the same in both models. And convert ART partition too - keep that one separate, as calibration data length differs between the models. Signed-off-by: Lech Perczak --- .../ath79/dts/ar9344_fortinet_fap-221-b.dts | 33 +++++++++++++------ .../generic/base-files/etc/board.d/02_network | 4 --- .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 3 -- .../base-files/lib/preinit/10_fix_eth_mac.sh | 3 -- 4 files changed, 23 insertions(+), 20 deletions(-) diff --git a/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts b/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts index b78a588f5c..0cad9b76d1 100644 --- a/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts +++ b/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts @@ -6,6 +6,10 @@ compatible = "fortinet,fap-221-b", "qca,ar9344"; model = "Fortinet FAP-221-B"; + aliases { + label-mac-device = <ð0>; + }; + leds { compatible = "gpio-leds"; @@ -51,25 +55,34 @@ &ath9k { ieee80211-freq-limit = <2402000 2482000>; - nvmem-cells = <&calibration_pcie>; - nvmem-cell-names = "calibration"; + nvmem-cells = <&calibration_pcie>, <&macaddr_uboot_3ff80 8>; + nvmem-cell-names = "calibration", "mac-address"; +}; + +ð0 { + nvmem-cells = <&macaddr_uboot_3ff80 0>; + nvmem-cell-names = "mac-address"; }; &wmac { ieee80211-freq-limit = <2402000 2482000 4900000 5990000>; - nvmem-cells = <&calibration_wmac>; - nvmem-cell-names = "calibration"; + nvmem-cells = <&calibration_wmac>, <&macaddr_uboot_3ff80 1>; + nvmem-cell-names = "calibration", "mac-address"; }; &art { - compatible = "nvmem-cells"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - calibration_wmac: calibration@1000 { - reg = <0x1000 0x440>; - }; + calibration_wmac: calibration@1000 { + reg = <0x1000 0x440>; + }; - calibration_pcie: calibration@5000 { - reg = <0x5000 0x440>; + calibration_pcie: calibration@5000 { + reg = <0x5000 0x440>; + }; }; }; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index cdea3b5f67..b74a7ff6b4 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -726,10 +726,6 @@ ath79_setup_macs() enterasys,ws-ap3705i) label_mac=$(mtd_get_mac_ascii u-boot-env0 ethaddr) ;; - fortinet,fap-221-b) - lan_mac=$(mtd_get_mac_text u-boot 0x3ff80 12) - label_mac=$lan_mac - ;; hak5,lan-turtle|\ hak5,packet-squirrel) label_mac=$(mtd_get_mac_binary u-boot 0x1fc00) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index ccff35e5c6..42b69d2ca0 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -47,9 +47,6 @@ case "$board" in engenius,esr900) macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" "$PHYNBR" > /sys${DEVPATH}/macaddress ;; - fortinet,fap-221-b) - macaddr_add "$(mtd_get_mac_text u-boot 0x3ff80 12)" $((PHYNBR*7+1)) > /sys${DEVPATH}/macaddress - ;; iodata,wn-ac1600dgr) # There is no eeprom data for 5 GHz wlan in "art" partition # which would allow to patch the macaddress diff --git a/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh index 8b39a17eb0..76f4b93a35 100644 --- a/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -25,9 +25,6 @@ preinit_set_mac_address() { siemens,ws-ap3610) ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr) ;; - fortinet,fap-221-b) - ip link set dev eth0 address $(mtd_get_mac_text u-boot 0x3ff80 12) - ;; moxa,awk-1137c) ip link set dev eth0 address $(mtd_get_mac_ascii u-boot-env mac_addr) ;; From 54e52fdacbbff30ec16fea60c2c7a13d4d3c31d3 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Tue, 21 Nov 2023 14:10:09 +0100 Subject: [PATCH 32/34] rockchip: require image metadata All devices in the rockchip target have appended image-metadata. Enforce the presence of this metadata to avoid flashing incomplete images. This is the de-facto standard for almost all OpenWrt targets. Signed-off-by: David Bauer --- target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh b/target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh index faed0667f1..49a969f410 100644 --- a/target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh +++ b/target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh @@ -1,3 +1,5 @@ +REQUIRE_IMAGE_METADATA=1 + platform_check_image() { local diskdev partdev diff From 12396686484a488dff1c4a1ee8b5197c552572fe Mon Sep 17 00:00:00 2001 From: David Bauer Date: Thu, 20 Apr 2023 19:49:55 +0200 Subject: [PATCH 33/34] mediatek: add support for GL.iNet GL-MT2500 Hardware -------- SoC: MediaTek MT7981BA RAM: 1GB DDR4 (NANYA NT5AD512M16C4-JR) MMC: 8GB eMMC (Samsung 8GTF4R) ETH: 1000Base-T LAN (ePHY) 2500Base-T WAN (MaxLinear GPY211C) BTN: 1x Reset Button LED: System (blue/white) VPN (white) USB: 1x USB-A (USB 3.0) UART: 115200 8N1 - Pinout on board next to LAN port Don't connect 3.3V! Known Issues ------------ U-Boot vendor recovery does not seem to accept any images, neither GL.iNet images nor OpenWrt images. Recovery requires serial access! Installation ------------ Upload the OpenWrt sysupgrade image to the Gl.iNet Web-UI. Make sure to not retain existing settings. Signed-off-by: David Bauer --- .../uboot-envtools/files/mediatek_filogic | 4 + .../mediatek/dts/mt7981b-glinet-gl-mt2500.dts | 151 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 6 + .../base-files/lib/upgrade/platform.sh | 2 + target/linux/mediatek/image/filogic.mk | 17 ++ 5 files changed, 180 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index ae8e1589a0..4d37828f1d 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -74,6 +74,10 @@ xiaomi,redmi-router-ax6000-ubootmod) ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1" ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1" ;; +glinet,gl-mt2500) + local envdev=$(find_mmc_part "u-boot-env") + ubootenv_add_uci_config "$envdev" "0x400000" "0x80000" + ;; glinet,gl-mt3000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000" ;; diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts new file mode 100644 index 0000000000..068dd0f236 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "GL.iNet GL-MT2500"; + compatible = "glinet,gl-mt2500", "mediatek,mt7981"; + + aliases { + label-mac-device = &gmac0; + led-boot = &led_sys_white; + led-failsafe = &led_sys_blue; + led-running = &led_sys_white; + led-upgrade = &led_sys_blue; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=PARTLABEL=rootfs rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-vpn { + label = "white:vpn"; + gpios = <&pio 31 GPIO_ACTIVE_LOW>; + }; + + led_sys_white: led-system-white { + label = "white:system"; + gpios = <&pio 30 GPIO_ACTIVE_LOW>; + }; + + led_sys_blue: led-system-blue { + label = "blue:system"; + gpios = <&pio 29 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulstor-usb { + compatible = "regulator-fixed"; + + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&mmc0 { + status = "okay"; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <52000000>; + vmmc-supply = <®_3p3v>; + cap-mmc-highspeed; + non-removable; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 5153c156f6..0675e87853 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -32,6 +32,7 @@ mediatek_setup_interfaces() h3c,magic-nx30-pro) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 ;; + glinet,gl-mt2500|\ glinet,gl-mt3000) ucidef_set_interfaces_lan_wan eth1 eth0 ;; @@ -109,6 +110,11 @@ mediatek_setup_macs() ;; esac ;; + glinet,gl-mt2500) + label_mac="$(get_mac_binary "/dev/mmcblk0boot1" 0xA)" + wan_mac="$label_mac" + lan_mac="$(macaddr_add $label_mac 1)" + ;; glinet,gl-mt6000) label_mac=$(mmc_get_mac_binary factory 0x0a) wan_mac=$label_mac diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 3c278d5faf..6130768cb4 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -97,6 +97,7 @@ platform_do_upgrade() { cudy,wr3000-v1) default_do_upgrade "$1" ;; + glinet,gl-mt2500|\ glinet,gl-mt6000) CI_KERNPART="kernel" CI_ROOTPART="rootfs" @@ -176,6 +177,7 @@ platform_copy_config() { ;; esac ;; + glinet,gl-mt2500|\ glinet,gl-mt6000|\ ubnt,unifi-6-plus) emmc_copy_config diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 4886db1141..a0a5f944a8 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -274,6 +274,23 @@ define Device/cudy_wr3000-v1 endef TARGET_DEVICES += cudy_wr3000-v1 +define Device/glinet_gl-mt2500 + DEVICE_VENDOR := GL.iNet + DEVICE_MODEL := GL-MT2500 + DEVICE_DTS := mt7981b-glinet-gl-mt2500 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + DEVICE_PACKAGES := kmod-usb3 + SUPPORTED_DEVICES += glinet,mt2500-emmc + IMAGES := sysupgrade.bin + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += glinet_gl-mt2500 + define Device/glinet_gl-mt3000 DEVICE_VENDOR := GL.iNet DEVICE_MODEL := GL-MT3000 From 6b73d9bf499a6add7393283ebb6212b59535b863 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 20 Nov 2023 16:36:43 +0100 Subject: [PATCH 34/34] mediatek: copy config for Acer Predator W6 Config was previously not copied on sysupgrade. Signed-off-by: David Bauer --- target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 6130768cb4..c9599cdc9b 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -177,6 +177,7 @@ platform_copy_config() { ;; esac ;; + acer,predator-w6|\ glinet,gl-mt2500|\ glinet,gl-mt6000|\ ubnt,unifi-6-plus)