From 57f5d4ef5957ca42beb26c2e8c7b6a47329f1e93 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 10 Jun 2023 13:31:26 +0800 Subject: [PATCH] uboot-rockchip: bump to 2023.07-rc3 Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 5 +- ...vert-rockchip-rk3399-Drop-altbootcmd.patch | 26 --- ...Disable-DISTRO_DEFAULTS-for-rk3399-b.patch | 24 --- ...Convert-rockpro64-rk3399-to-use-stan.patch | 50 ----- ...dwc3-config-to-chip-specific-handler.patch | 2 +- ...k35xx-Fix-boot-with-a-large-fdt-blob.patch | 43 ---- ...le-fdtoverlay-and-kernel-compression.patch | 74 ------- ...-clk-scmi-Add-Kconfig-option-for-SPL.patch | 72 ------- ...kchip-Fix-IO-mux-selection-on-RK3568.patch | 126 ----------- ...-support-for-RK3568-and-RK3588-banks.patch | 202 ------------------ ...3568-Add-dummy-I2S1_MCLKOUT_TX-clock.patch | 30 --- .../patches/900-arm-add-dts-files.patch | 17 +- .../arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 7 - .../src/arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ---- .../arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi | 8 +- .../arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi | 7 +- .../arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi | 9 +- .../arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 15 +- .../configs/fastrhino-r66s-rk3568_defconfig | 38 +--- .../configs/fastrhino-r68s-rk3568_defconfig | 22 +- .../configs/guangmiao-g4c-rk3399_defconfig | 12 +- .../src/configs/mrkaio-m68s-rk3568_defconfig | 38 +--- .../configs/nanopi-r2c-plus-rk3328_defconfig | 2 +- .../src/configs/nanopi-r2c-rk3328_defconfig | 112 ---------- .../nanopi-r4s-enterprise-rk3399_defconfig | 12 +- .../src/configs/nanopi-r4se-rk3399_defconfig | 12 +- .../src/configs/nanopi-r5c-rk3568_defconfig | 38 +--- .../src/configs/nanopi-r5s-rk3568_defconfig | 38 +--- .../orangepi-r1-plus-lts-rk3328_defconfig | 2 +- .../configs/orangepi-r1-plus-rk3328_defconfig | 2 +- 30 files changed, 74 insertions(+), 1011 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch delete mode 100644 package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch delete mode 100644 package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch delete mode 100644 package/boot/uboot-rockchip/patches/105-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch delete mode 100644 package/boot/uboot-rockchip/patches/106-rockchip-rk35xx-Enable-fdtoverlay-and-kernel-compression.patch delete mode 100644 package/boot/uboot-rockchip/patches/107-clk-scmi-Add-Kconfig-option-for-SPL.patch delete mode 100644 package/boot/uboot-rockchip/patches/108-pinctrl-rockchip-Fix-IO-mux-selection-on-RK3568.patch delete mode 100644 package/boot/uboot-rockchip/patches/109-gpio-rockchip-Add-support-for-RK3568-and-RK3588-banks.patch delete mode 100644 package/boot/uboot-rockchip/patches/110-clk-rockchip-rk3568-Add-dummy-I2S1_MCLKOUT_TX-clock.patch delete mode 100644 package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi delete mode 100644 package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c.dts delete mode 100644 package/boot/uboot-rockchip/src/configs/nanopi-r2c-rk3328_defconfig diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cac31f8546..2ea144a5f1 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,9 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.04 +PKG_VERSION:=2023.07-rc3 PKG_RELEASE:=1 - -PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341 +PKG_HASH:=42ec083674bd30fa4c16e78c3f5f453c08d9f737595a77b5dda595ac3a09d82f PKG_MAINTAINER:=Tobias Maedel diff --git a/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch b/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch deleted file mode 100644 index 09df37fb00..0000000000 --- a/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1ab5d2b9cf1b9c1c7ccb58243992fb163c64a14d Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:06:19 +0800 -Subject: [PATCH 1/3] Revert "rockchip: rk3399: Drop altbootcmd" - -This reverts commit d00fb6421c8fad639f608f55f9291305061ffb17. - -Signed-off-by: Tianling Shen ---- - include/configs/rk3399_common.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/configs/rk3399_common.h -+++ b/include/configs/rk3399_common.h -@@ -52,7 +52,10 @@ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ -- "boot_targets=" BOOT_TARGETS "\0" -+ "boot_targets=" BOOT_TARGETS "\0" \ -+ "altbootcmd=" \ -+ "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ -+ "run distro_bootcmd\0" - - #endif - diff --git a/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch b/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch deleted file mode 100644 index a9dc5556a9..0000000000 --- a/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 535b09f84be0660ef5e85431328746e74cc8e6b7 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:08:21 +0800 -Subject: [PATCH 2/3] Revert "rockchip: Disable DISTRO_DEFAULTS for rk3399 - boards" - -This reverts commit 2b9cc7845cf96955db363519faab9a78e166c453. - -Signed-off-by: Tianling Shen ---- - arch/arm/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1955,7 +1955,7 @@ config ARCH_ROCKCHIP - imply ADC - imply CMD_DM - imply DEBUG_UART_BOARD_INIT -- imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399 -+ imply DISTRO_DEFAULTS - imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS - imply FAT_WRITE - imply SARADC_ROCKCHIP diff --git a/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch b/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch deleted file mode 100644 index 2b7fb8dd66..0000000000 --- a/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 93ac12531f7c672ef1fe7689cf8b67ec2372efef Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:08:27 +0800 -Subject: [PATCH 3/3] Revert "rockchip: Convert rockpro64-rk3399 to use - standard boot" - -This reverts commit 3891c68ef50eda38d78c95ecd03aed030aa6bb53. - -Signed-off-by: Tianling Shen ---- - include/configs/rk3399_common.h | 5 ++++- - include/configs/rockchip-common.h | 2 -- - 2 files changed, 4 insertions(+), 3 deletions(-) - ---- a/include/configs/rk3399_common.h -+++ b/include/configs/rk3399_common.h -@@ -47,12 +47,15 @@ - #define ROCKCHIP_DEVICE_SETTINGS - #endif - -+#include -+#include - #define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ -- "boot_targets=" BOOT_TARGETS "\0" \ -+ BOOTENV \ -+ BOOTENV_SF \ - "altbootcmd=" \ - "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ - "run distro_bootcmd\0" ---- a/include/configs/rockchip-common.h -+++ b/include/configs/rockchip-common.h -@@ -67,14 +67,12 @@ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) \ - BOOT_TARGET_SF(func) --#define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi" - #else - #define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_MMC(func) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) --#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp" - #endif - - #ifdef CONFIG_ARM64 diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-move-dwc3-config-to-chip-specific-handler.patch b/package/boot/uboot-rockchip/patches/103-rockchip-move-dwc3-config-to-chip-specific-handler.patch index 732930426f..97218f7286 100644 --- a/package/boot/uboot-rockchip/patches/103-rockchip-move-dwc3-config-to-chip-specific-handler.patch +++ b/package/boot/uboot-rockchip/patches/103-rockchip-move-dwc3-config-to-chip-specific-handler.patch @@ -19,7 +19,7 @@ Signed-off-by: Peter Geis --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c -@@ -280,30 +280,6 @@ int board_usb_cleanup(int index, enum us +@@ -287,30 +287,6 @@ int board_usb_cleanup(int index, enum us } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ diff --git a/package/boot/uboot-rockchip/patches/105-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch b/package/boot/uboot-rockchip/patches/105-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch deleted file mode 100644 index d4115f4e03..0000000000 --- a/package/boot/uboot-rockchip/patches/105-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch +++ /dev/null @@ -1,43 +0,0 @@ -From bc902a9e239c427bd2b4ab38ebde827094849a47 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 Mar 2023 21:43:07 +0000 -Subject: [PATCH] rockchip: rk35xx: Fix boot with a large fdt blob - -The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf -v2.3. Mainline atf v2.3 contains an issue that could lead to a crash -when it fails to parse the fdt blob being passed as the platform param. -An issue that was fixed in atf v2.4. - -The vendor TF-A seem to suffer from a similar issue, and this prevents -booting when fdt blob is large enough to trigger this condition. - -Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a -NULL pointer instead of the fdt blob as the platform param. - -This fixes booting Radxa ROCK 3A after recent sync of device tree. - -Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") -Signed-off-by: Jonas Karlman -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230321214301.2590326-4-jonas@kwiboo.se/ ---- - arch/arm/mach-rockchip/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/mach-rockchip/Kconfig -+++ b/arch/arm/mach-rockchip/Kconfig -@@ -288,6 +288,7 @@ config ROCKCHIP_RK3568 - select BOARD_LATE_INIT - select DM_REGULATOR_FIXED - select DM_RESET -+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply ROCKCHIP_OTP - imply MISC_INIT_R -@@ -309,6 +310,7 @@ config ROCKCHIP_RK3588 - select REGMAP - select SYSCON - select BOARD_LATE_INIT -+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply ROCKCHIP_OTP - imply MISC_INIT_R diff --git a/package/boot/uboot-rockchip/patches/106-rockchip-rk35xx-Enable-fdtoverlay-and-kernel-compression.patch b/package/boot/uboot-rockchip/patches/106-rockchip-rk35xx-Enable-fdtoverlay-and-kernel-compression.patch deleted file mode 100644 index 167a11ee14..0000000000 --- a/package/boot/uboot-rockchip/patches/106-rockchip-rk35xx-Enable-fdtoverlay-and-kernel-compression.patch +++ /dev/null @@ -1,74 +0,0 @@ -From af7274e5d84deb2c2ec4526f755b01907b3f1d76 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 Mar 2023 21:43:08 +0000 -Subject: [PATCH] rockchip: rk35xx: Enable fdtoverlay and kernel compression - -Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of -OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay -and kernel compression. - -Signed-off-by: Jonas Karlman -Reviewed-by: Simon Glass -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230321214301.2590326-5-jonas@kwiboo.se/ ---- - arch/arm/mach-rockchip/Kconfig | 2 ++ - include/configs/rk3568_common.h | 7 ++++++- - include/configs/rk3588_common.h | 7 ++++++- - 3 files changed, 14 insertions(+), 2 deletions(-) - ---- a/arch/arm/mach-rockchip/Kconfig -+++ b/arch/arm/mach-rockchip/Kconfig -@@ -290,6 +290,7 @@ config ROCKCHIP_RK3568 - select DM_RESET - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD -+ imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP - imply MISC_INIT_R - help -@@ -312,6 +313,7 @@ config ROCKCHIP_RK3588 - select BOARD_LATE_INIT - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD -+ imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP - imply MISC_INIT_R - help ---- a/include/configs/rk3568_common.h -+++ b/include/configs/rk3568_common.h -@@ -17,10 +17,15 @@ - - #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00c00000\0" \ -+ "script_offset_f=0xffe000\0" \ -+ "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ -+ "fdtoverlay_addr_r=0x02000000\0" \ - "kernel_addr_r=0x02080000\0" \ -- "ramdisk_addr_r=0x0a200000\0" -+ "ramdisk_addr_r=0x0a200000\0" \ -+ "kernel_comp_addr_r=0x08000000\0" \ -+ "kernel_comp_size=0x2000000\0" - - #include - #define CFG_EXTRA_ENV_SETTINGS \ ---- a/include/configs/rk3588_common.h -+++ b/include/configs/rk3588_common.h -@@ -16,10 +16,15 @@ - - #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00c00000\0" \ -+ "script_offset_f=0xffe000\0" \ -+ "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ -+ "fdtoverlay_addr_r=0x02000000\0" \ - "kernel_addr_r=0x02080000\0" \ -- "ramdisk_addr_r=0x0a200000\0" -+ "ramdisk_addr_r=0x0a200000\0" \ -+ "kernel_comp_addr_r=0x08000000\0" \ -+ "kernel_comp_size=0x2000000\0" - - #include - #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/package/boot/uboot-rockchip/patches/107-clk-scmi-Add-Kconfig-option-for-SPL.patch b/package/boot/uboot-rockchip/patches/107-clk-scmi-Add-Kconfig-option-for-SPL.patch deleted file mode 100644 index cc36d6b5d6..0000000000 --- a/package/boot/uboot-rockchip/patches/107-clk-scmi-Add-Kconfig-option-for-SPL.patch +++ /dev/null @@ -1,72 +0,0 @@ -From e50cb82db61266f8d62596567c18adcb28b158d9 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 17 Mar 2023 19:16:45 +0000 -Subject: [PATCH] clk: scmi: Add Kconfig option for SPL - -Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options -enabled and SPL_FIRMWARE disabled result in the following error. - - drivers/clk/clk_scmi.o: in function `scmi_clk_gate': - drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': - drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': - drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_probe': - drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' - make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 - make: *** [Makefile:2043: spl/u-boot-spl] Error 2 - -Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. - -Signed-off-by: Jonas Karlman -Reviewed-by: Kever Yang -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230317191638.2558279-2-jonas@kwiboo.se/ ---- - drivers/clk/Kconfig | 8 ++++++++ - drivers/clk/Makefile | 2 +- - drivers/firmware/scmi/scmi_agent-uclass.c | 2 +- - 3 files changed, 10 insertions(+), 2 deletions(-) - ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -166,6 +166,14 @@ config CLK_SCMI - by a SCMI agent based on SCMI clock protocol communication - with a SCMI server. - -+config SPL_CLK_SCMI -+ bool "Enable SCMI clock driver in SPL" -+ depends on SCMI_FIRMWARE && SPL_FIRMWARE -+ help -+ Enable this option if you want to support clock devices exposed -+ by a SCMI agent based on SCMI clock protocol communication -+ with a SCMI server in SPL. -+ - config CLK_HSDK - bool "Enable cgu clock driver for HSDK boards" - depends on CLK && TARGET_HSDK ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/ - obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o - obj-$(CONFIG_CLK_OWL) += owl/ - obj-$(CONFIG_CLK_RENESAS) += renesas/ --obj-$(CONFIG_CLK_SCMI) += clk_scmi.o -+obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o - obj-$(CONFIG_CLK_SIFIVE) += sifive/ - obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ - obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o ---- a/drivers/firmware/scmi/scmi_agent-uclass.c -+++ b/drivers/firmware/scmi/scmi_agent-uclass.c -@@ -75,7 +75,7 @@ static int scmi_bind_protocols(struct ud - name = ofnode_get_name(node); - switch (protocol_id) { - case SCMI_PROTOCOL_ID_CLOCK: -- if (IS_ENABLED(CONFIG_CLK_SCMI)) -+ if (CONFIG_IS_ENABLED(CLK_SCMI)) - drv = DM_DRIVER_GET(scmi_clock); - break; - case SCMI_PROTOCOL_ID_RESET_DOMAIN: diff --git a/package/boot/uboot-rockchip/patches/108-pinctrl-rockchip-Fix-IO-mux-selection-on-RK3568.patch b/package/boot/uboot-rockchip/patches/108-pinctrl-rockchip-Fix-IO-mux-selection-on-RK3568.patch deleted file mode 100644 index 5df911c48f..0000000000 --- a/package/boot/uboot-rockchip/patches/108-pinctrl-rockchip-Fix-IO-mux-selection-on-RK3568.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 6b203686878837c9be2fbb5b97a154f7a1074cfa Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 18 Mar 2023 23:30:42 +0000 -Subject: [PATCH] pinctrl: rockchip: Fix IO mux selection on RK3568 - -IO mux selection is not working correctly for all pins. Sync mux route -data from linux to add any missing and update wrong trigger pins to fix -this. Also apply the pull-up fix needed for GPIO0 D3-D6. - -Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") -Signed-off-by: Jonas Karlman -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jonas@kwiboo.se/ ---- - drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++---------- - 1 file changed, 38 insertions(+), 28 deletions(-) - ---- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c -+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c -@@ -13,6 +13,12 @@ - #include "pinctrl-rockchip.h" - - static struct rockchip_mux_route_data rk3568_mux_route_data[] = { -+ MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ -@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk - MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ -@@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk - MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ -@@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ -@@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk - MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ -@@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockch - return ret; - } - -+ /* -+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, -+ * where that pull up value becomes 3. -+ */ -+ if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { -+ if (ret == 1) -+ ret = 3; -+ } -+ - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - diff --git a/package/boot/uboot-rockchip/patches/109-gpio-rockchip-Add-support-for-RK3568-and-RK3588-banks.patch b/package/boot/uboot-rockchip/patches/109-gpio-rockchip-Add-support-for-RK3568-and-RK3588-banks.patch deleted file mode 100644 index 87a8782e36..0000000000 --- a/package/boot/uboot-rockchip/patches/109-gpio-rockchip-Add-support-for-RK3568-and-RK3588-banks.patch +++ /dev/null @@ -1,202 +0,0 @@ -From fa3d7e841365da1bc26a3ac42b6eeb963b286cec Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 19 Mar 2023 18:39:51 +0000 -Subject: [PATCH] gpio: rockchip: Add support for RK3568 and RK3588 banks - -The GPIO V2 controller on RK3568 and RK3588 works very similar to -prior generation, main difference is the use of a write mask in the -upper 16 bits and register address offset have changed. - -GPIO_VER_ID is a new register at 0x0078 that is used to determine when -the driver should use new or old register offsets and values. Earlier -generation return 0x0 from this offset. - -Refactor code and add support for the GPIO V2 controller used in RK3568 -and RK3588. - -Signed-off-by: Jonas Karlman -Reviewed-by: Kever Yang -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230319183949.1375997-1-jonas@kwiboo.se/ ---- - drivers/gpio/rk_gpio.c | 112 ++++++++++++++++++++++++++++------------- - 1 file changed, 76 insertions(+), 36 deletions(-) - ---- a/drivers/gpio/rk_gpio.c -+++ b/drivers/gpio/rk_gpio.c -@@ -13,83 +13,118 @@ - #include - #include - #include -+#include - #include - #include --#include -+#include -+#include -+ -+#define SWPORT_DR 0x0000 -+#define SWPORT_DDR 0x0004 -+#define EXT_PORT 0x0050 -+#define SWPORT_DR_L 0x0000 -+#define SWPORT_DR_H 0x0004 -+#define SWPORT_DDR_L 0x0008 -+#define SWPORT_DDR_H 0x000C -+#define EXT_PORT_V2 0x0070 -+#define VER_ID_V2 0x0078 - - enum { - ROCKCHIP_GPIOS_PER_BANK = 32, - }; - --#define OFFSET_TO_BIT(bit) (1UL << (bit)) -- - struct rockchip_gpio_priv { -- struct rockchip_gpio_regs *regs; -+ void __iomem *regs; - struct udevice *pinctrl; - int bank; - char name[2]; -+ u32 version; - }; - --static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) -+static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) - { - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- struct rockchip_gpio_regs *regs = priv->regs; -+ u32 mask = BIT(offset), data; - -- clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset)); -+ if (priv->version) -+ data = readl(priv->regs + EXT_PORT_V2); -+ else -+ data = readl(priv->regs + EXT_PORT); - -- return 0; -+ return (data & mask) ? 1 : 0; - } - --static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, -- int value) -+static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, -+ int value) - { - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- struct rockchip_gpio_regs *regs = priv->regs; -- int mask = OFFSET_TO_BIT(offset); -+ u32 mask = BIT(offset), data = value ? mask : 0; - -- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); -- setbits_le32(®s->swport_ddr, mask); -+ if (priv->version && offset >= 16) -+ rk_clrsetreg(priv->regs + SWPORT_DR_H, mask >> 16, data >> 16); -+ else if (priv->version) -+ rk_clrsetreg(priv->regs + SWPORT_DR_L, mask, data); -+ else -+ clrsetbits_le32(priv->regs + SWPORT_DR, mask, data); - - return 0; - } - --static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) -+static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) - { - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- struct rockchip_gpio_regs *regs = priv->regs; -+ u32 mask = BIT(offset); -+ -+ if (priv->version && offset >= 16) -+ rk_clrreg(priv->regs + SWPORT_DDR_H, mask >> 16); -+ else if (priv->version) -+ rk_clrreg(priv->regs + SWPORT_DDR_L, mask); -+ else -+ clrbits_le32(priv->regs + SWPORT_DDR, mask); - -- return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0; -+ return 0; - } - --static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, -- int value) -+static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, -+ int value) - { - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- struct rockchip_gpio_regs *regs = priv->regs; -- int mask = OFFSET_TO_BIT(offset); -+ u32 mask = BIT(offset); -+ -+ rockchip_gpio_set_value(dev, offset, value); - -- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); -+ if (priv->version && offset >= 16) -+ rk_setreg(priv->regs + SWPORT_DDR_H, mask >> 16); -+ else if (priv->version) -+ rk_setreg(priv->regs + SWPORT_DDR_L, mask); -+ else -+ setbits_le32(priv->regs + SWPORT_DDR, mask); - - return 0; - } - - static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) - { --#ifdef CONFIG_SPL_BUILD -- return -ENODATA; --#else - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- struct rockchip_gpio_regs *regs = priv->regs; -- bool is_output; -+ u32 mask = BIT(offset), data; - int ret; - -- ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); -- if (ret) -- return ret; -- is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset); -+ if (CONFIG_IS_ENABLED(PINCTRL)) { -+ ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); -+ if (ret < 0) -+ return ret; -+ else if (ret != RK_FUNC_GPIO) -+ return GPIOF_FUNC; -+ } -+ -+ if (priv->version && offset >= 16) -+ data = readl(priv->regs + SWPORT_DDR_H) << 16; -+ else if (priv->version) -+ data = readl(priv->regs + SWPORT_DDR_L); -+ else -+ data = readl(priv->regs + SWPORT_DDR); - -- return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; --#endif -+ return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; - } - - /* Simple SPL interface to GPIOs */ -@@ -147,9 +182,12 @@ static int rockchip_gpio_probe(struct ud - int ret; - - priv->regs = dev_read_addr_ptr(dev); -- ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); -- if (ret) -- return ret; -+ -+ if (CONFIG_IS_ENABLED(PINCTRL)) { -+ ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); -+ if (ret) -+ return ret; -+ } - - /* - * If "gpio-ranges" is present in the devicetree use it to parse -@@ -170,6 +208,8 @@ static int rockchip_gpio_probe(struct ud - priv->name[0] = 'A' + priv->bank; - uc_priv->bank_name = priv->name; - -+ priv->version = readl(priv->regs + VER_ID_V2); -+ - return 0; - } - diff --git a/package/boot/uboot-rockchip/patches/110-clk-rockchip-rk3568-Add-dummy-I2S1_MCLKOUT_TX-clock.patch b/package/boot/uboot-rockchip/patches/110-clk-rockchip-rk3568-Add-dummy-I2S1_MCLKOUT_TX-clock.patch deleted file mode 100644 index 50976f0c87..0000000000 --- a/package/boot/uboot-rockchip/patches/110-clk-rockchip-rk3568-Add-dummy-I2S1_MCLKOUT_TX-clock.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8a894773cb87645f5bfe3315f79935f50bd011f4 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 2 Apr 2023 15:58:18 +0000 -Subject: [PATCH] clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock - support - -A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock -in assigned-clocks, add dummy support to set parent of this clock to the -rk3568 cru driver. - -Fixes probe of pmic driver and missing regulators on affected boards, -rk3568-evb and rk3568-rock-3a. - -Signed-off-by: Jonas Karlman -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230402155816.1312383-1-jonas@kwiboo.se/ ---- - drivers/clk/rockchip/clk_rk3568.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/rockchip/clk_rk3568.c -+++ b/drivers/clk/rockchip/clk_rk3568.c -@@ -2838,6 +2838,8 @@ static int rk3568_clk_set_parent(struct - case ACLK_RKVDEC_PRE: - case CLK_RKVDEC_CORE: - return rk3568_rkvdec_set_parent(clk, parent); -+ case I2S1_MCLKOUT_TX: -+ break; - default: - return -ENOENT; - } diff --git a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch index 2c835fe389..41e566aac0 100644 --- a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch +++ b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch @@ -1,10 +1,9 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -123,7 +123,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - +@@ -124,7 +124,10 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ -+ rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2c-plus.dtb \ rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ @@ -12,7 +11,7 @@ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb -@@ -141,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -142,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ rk3399-gru-kevin.dtb \ @@ -20,7 +19,7 @@ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ -@@ -151,6 +156,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -152,6 +156,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-m4b.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-nanopi-r4s.dtb \ @@ -29,15 +28,15 @@ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ rk3399-pinephone-pro.dtb \ -@@ -166,6 +173,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ +@@ -169,6 +175,11 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-fastrhino-r66s.dtb \ + rk3568-fastrhino-r68s.dtb \ + rk3568-mrkaio-m68s.dtb \ + rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ - rk3566-radxa-cm3-io.dtb \ rk3568-rock-3a.dtb + dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi deleted file mode 100644 index c2e86d0f0e..0000000000 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd - * (C) Copyright 2021 Tianling Shen - */ - -#include "rk3328-nanopi-r2s-u-boot.dtsi" diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c.dts deleted file mode 100644 index a07a26b944..0000000000 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021-2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - tx_delay = <0x22>; - rx_delay = <0x12>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi index d37ca9fdfc..fd1a92576d 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi @@ -9,14 +9,8 @@ }; }; -&sdmmc0 { - bus-width = <4>; - u-boot,spl-fifo-mode; - status = "okay"; -}; - &uart2 { clock-frequency = <24000000>; - u-boot,dm-spl; + bootph-all; status = "okay"; }; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi index fad2a26324..f4769d12bd 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi @@ -9,8 +9,13 @@ }; }; +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + &uart2 { clock-frequency = <24000000>; - u-boot,dm-spl; + bootph-all; status = "okay"; }; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi index 45fa817065..816274db9b 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi @@ -9,14 +9,13 @@ }; }; -&sdmmc0 { - bus-width = <4>; - u-boot,dm-spl; - u-boot,spl-fifo-mode; +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; }; &uart2 { clock-frequency = <24000000>; - u-boot,dm-spl; + bootph-all; status = "okay"; }; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 4840957767..0ecca85b20 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -2,6 +2,8 @@ /* * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen */ #include "rk356x-u-boot.dtsi" @@ -13,14 +15,17 @@ }; }; -&sdmmc0 { - bus-width = <4>; - u-boot,dm-spl; - u-boot,spl-fifo-mode; +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; &uart2 { clock-frequency = <24000000>; - u-boot,dm-spl; + bootph-all; status = "okay"; }; diff --git a/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig index 3bbcda2f95..905ef77211 100644 --- a/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig +++ b/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig @@ -9,11 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-fastrhino-r66s" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -27,9 +24,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -37,27 +33,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_WARN=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -66,24 +53,19 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y @@ -100,16 +82,4 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_LAN75XX=y -CONFIG_USB_ETHER_LAN78XX=y -CONFIG_USB_ETHER_SMSC95XX=y CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/fastrhino-r68s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/fastrhino-r68s-rk3568_defconfig index 2ed8e8d751..90c2a7d48d 100644 --- a/package/boot/uboot-rockchip/src/configs/fastrhino-r68s-rk3568_defconfig +++ b/package/boot/uboot-rockchip/src/configs/fastrhino-r68s-rk3568_defconfig @@ -9,11 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-fastrhino-r68s" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -27,9 +24,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r68s.dtb" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -37,16 +33,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ADC=y CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -59,17 +47,16 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_WARN=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -79,9 +66,10 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_POWER_DOMAIN=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y diff --git a/package/boot/uboot-rockchip/src/configs/guangmiao-g4c-rk3399_defconfig b/package/boot/uboot-rockchip/src/configs/guangmiao-g4c-rk3399_defconfig index 17e1f20fc1..cd57cd44ff 100644 --- a/package/boot/uboot-rockchip/src/configs/guangmiao-g4c-rk3399_defconfig +++ b/package/boot/uboot-rockchip/src/configs/guangmiao-g4c-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -39,6 +40,9 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -53,6 +57,8 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -72,9 +78,3 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -CONFIG_MISC=y -CONFIG_MISC_INIT_R=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_ROCKCHIP_OTP=y -CONFIG_SYSINFO=y -CONFIG_SYSINFO_SMBIOS=y diff --git a/package/boot/uboot-rockchip/src/configs/mrkaio-m68s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/mrkaio-m68s-rk3568_defconfig index 09add3639c..c833d5a650 100644 --- a/package/boot/uboot-rockchip/src/configs/mrkaio-m68s-rk3568_defconfig +++ b/package/boot/uboot-rockchip/src/configs/mrkaio-m68s-rk3568_defconfig @@ -9,11 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -27,9 +24,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -37,27 +33,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_WARN=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -66,24 +53,19 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y @@ -100,16 +82,4 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_LAN75XX=y -CONFIG_USB_ETHER_LAN78XX=y -CONFIG_USB_ETHER_SMSC95XX=y CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig index 26cee82bc3..6adb75b602 100644 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r2c-plus-rk3328_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" CONFIG_DM_RESET=y @@ -72,7 +73,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r2c-rk3328_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r2c-rk3328_defconfig deleted file mode 100644 index 1460ab32f5..0000000000 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r2c-rk3328_defconfig +++ /dev/null @@ -1,112 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=24000000 -CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" -CONFIG_DM_RESET=y -CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -CONFIG_DEBUG_UART_BASE=0xFF130000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_TPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL_OF_PLATDATA=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_TPL_DM=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_TPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_TPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_TPL_RAM=y -CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550_MEM32=y -CONFIG_SYSINFO=y -CONFIG_SYSRESET=y -# CONFIG_TPL_SYSRESET is not set -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y -CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r4s-enterprise-rk3399_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r4s-enterprise-rk3399_defconfig index 15a61cb431..1c5cf675e9 100644 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r4s-enterprise-rk3399_defconfig +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r4s-enterprise-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-enterprise.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -39,6 +40,9 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -53,6 +57,8 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -72,9 +78,3 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -CONFIG_MISC=y -CONFIG_MISC_INIT_R=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_ROCKCHIP_OTP=y -CONFIG_SYSINFO=y -CONFIG_SYSINFO_SMBIOS=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig index 2e895d68ba..68cddd21d1 100644 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -39,6 +40,9 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -53,6 +57,8 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -72,9 +78,3 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -CONFIG_MISC=y -CONFIG_MISC_INIT_R=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_ROCKCHIP_OTP=y -CONFIG_SYSINFO=y -CONFIG_SYSINFO_SMBIOS=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r5c-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r5c-rk3568_defconfig index be9d00dd47..b913ad4494 100644 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r5c-rk3568_defconfig +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r5c-rk3568_defconfig @@ -9,11 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -27,9 +24,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -37,27 +33,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_WARN=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -66,24 +53,19 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y @@ -100,16 +82,4 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_LAN75XX=y -CONFIG_USB_ETHER_LAN78XX=y -CONFIG_USB_ETHER_SMSC95XX=y CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r5s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r5s-rk3568_defconfig index ce968d69f4..0a298c65a7 100644 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r5s-rk3568_defconfig +++ b/package/boot/uboot-rockchip/src/configs/nanopi-r5s-rk3568_defconfig @@ -9,11 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -27,9 +24,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -37,27 +33,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_WARN=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -66,24 +53,19 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y @@ -100,16 +82,4 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_LAN75XX=y -CONFIG_USB_ETHER_LAN78XX=y -CONFIG_USB_ETHER_SMSC95XX=y CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-lts-rk3328_defconfig b/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-lts-rk3328_defconfig index 523b8e1b0c..935c8ce348 100644 --- a/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" CONFIG_DM_RESET=y @@ -72,7 +73,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y diff --git a/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-rk3328_defconfig b/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-rk3328_defconfig index 40631d5c4d..9ffe6d6f0f 100644 --- a/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-rk3328_defconfig +++ b/package/boot/uboot-rockchip/src/configs/orangepi-r1-plus-rk3328_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" CONFIG_DM_RESET=y @@ -72,7 +73,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y