From 720c4e2102b3adfd798a590f4ad91912d16e7aa3 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 May 2024 14:04:36 +0800 Subject: [PATCH] rockchip: configure ETH LED for NanoPi R5C/R5S Signed-off-by: Tianling Shen (cherry picked from commit e7fbc901f1901a3c294f83ff5b1879859bd02f25) --- ...0-arm64-rockchip-add-OF-node-for-eth.patch | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch index bb940f073c..7785f0a67c 100644 --- a/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch +++ b/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch @@ -193,6 +193,48 @@ Signed-off-by: David Bauer &sdhci { bus-width = <8>; max-frequency = <200000000>; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -65,6 +65,19 @@ + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x00100000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ rtl8125_1: pcie-eth@10,0 { ++ compatible = "pci10ec,8125"; ++ reg = <0x000000 0 0 0 0>; ++ ++ realtek,led-data = <0x0 0x0 0x2b 0x200>; ++ }; ++ }; + }; + + &pcie3x2 { +@@ -72,6 +85,19 @@ + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x00200000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ rtl8125_2: pcie-eth@20,0 { ++ compatible = "pci10ec,8125"; ++ reg = <0x000000 0 0 0 0>; ++ ++ realtek,led-data = <0x0 0x0 0x2b 0x200>; ++ }; ++ }; + }; + + &pinctrl { --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -72,6 +72,7 @@ @@ -203,3 +245,43 @@ Signed-off-by: David Bauer }; }; +@@ -79,6 +80,19 @@ + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x00000000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ rtl8125_1: pcie@1,0 { ++ compatible = "pci10ec,8125"; ++ reg = <0x000000 0 0 0 0>; ++ ++ realtek,led-data = <0x0 0x0 0x2b 0x200>; ++ }; ++ }; + }; + + &pcie30phy { +@@ -91,6 +105,19 @@ + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x00100000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ rtl8125_2: pcie@10,0 { ++ compatible = "pci10ec,8125"; ++ reg = <0x000000 0 0 0 0>; ++ ++ realtek,led-data = <0x0 0x0 0x2b 0x200>; ++ }; ++ }; + }; + + &pcie3x2 {