From 7564d4123a08ed3b87cfcfbe71a22ef891470c37 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Wed, 23 Aug 2023 12:45:07 +0800 Subject: [PATCH] rockchip: add LED configuration for FastRhino R68S Signed-off-by: Tianling Shen --- ...0-arm64-rockchip-add-OF-node-for-eth.patch | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch index 242fca42ad..17a1d3e374 100644 --- a/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch +++ b/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch @@ -104,10 +104,22 @@ Signed-off-by: David Bauer phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; -@@ -88,6 +90,34 @@ +@@ -76,6 +78,7 @@ + reg = <0>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; ++ realtek,led-data = <0x6d60>; }; }; +@@ -85,6 +88,35 @@ + reg = <0>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; ++ realtek,led-data = <0x6d60>; ++ }; ++}; ++ +&pcie3x1 { + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; @@ -133,9 +145,6 @@ Signed-off-by: David Bauer + reg = <0x000000 0 0 0 0>; + label = "eth2"; + }; -+ }; -+}; -+ - &pinctrl { - gmac0 { - eth_phy0_reset_pin: eth-phy0-reset-pin { + }; + }; +