diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index ad36042730..f3b7a5c709 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -268,7 +268,7 @@ define U-Boot/mt7981_jcg_q30-pro endef define U-Boot/mt7981_nokia_ea0326gmp - NAME:=Qihoo 360T7 + NAME:=Nokia EA0326GMP BUILD_SUBTARGET:=filogic BUILD_DEVICES:=nokia_ea0326gmp UBOOT_CONFIG:=mt7981_nokia_ea0326gmp diff --git a/target/linux/airoha/Makefile b/target/linux/airoha/Makefile index 5906a1307e..0a66ef839c 100644 --- a/target/linux/airoha/Makefile +++ b/target/linux/airoha/Makefile @@ -6,8 +6,7 @@ BOARDNAME:=Airoha ARM CPU_TYPE:=cortex-a7 FEATURES:=dt squashfs nand ramdisk gpio source-only -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/airoha/files-5.15/arch/arm/mach-airoha/Makefile b/target/linux/airoha/files-5.15/arch/arm/mach-airoha/Makefile deleted file mode 100644 index a5857d0d02..0000000000 --- a/target/linux/airoha/files-5.15/arch/arm/mach-airoha/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += airoha.o diff --git a/target/linux/airoha/files-5.15/arch/arm/mach-airoha/airoha.c b/target/linux/airoha/files-5.15/arch/arm/mach-airoha/airoha.c deleted file mode 100644 index ea23b5abb4..0000000000 --- a/target/linux/airoha/files-5.15/arch/arm/mach-airoha/airoha.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree support for Airoha SoCs - * - * Copyright (c) 2022 Felix Fietkau - */ -#include - -static const char * const airoha_board_dt_compat[] = { - "airoha,en7523", - NULL, -}; - -DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)") - .dt_compat = airoha_board_dt_compat, -MACHINE_END diff --git a/target/linux/airoha/files-5.15/drivers/clk/clk-en7523.c b/target/linux/airoha/files-5.15/drivers/clk/clk-en7523.c deleted file mode 100644 index 29f0126cbd..0000000000 --- a/target/linux/airoha/files-5.15/drivers/clk/clk-en7523.c +++ /dev/null @@ -1,351 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include -#include -#include - -#define REG_PCI_CONTROL 0x88 -#define REG_PCI_CONTROL_PERSTOUT BIT(29) -#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) -#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) -#define REG_GSW_CLK_DIV_SEL 0x1b4 -#define REG_EMI_CLK_DIV_SEL 0x1b8 -#define REG_BUS_CLK_DIV_SEL 0x1bc -#define REG_SPI_CLK_DIV_SEL 0x1c4 -#define REG_SPI_CLK_FREQ_SEL 0x1c8 -#define REG_NPU_CLK_DIV_SEL 0x1fc -#define REG_CRYPTO_CLKSRC 0x200 -#define REG_RESET_CONTROL 0x834 -#define REG_RESET_CONTROL_PCIEHB BIT(29) -#define REG_RESET_CONTROL_PCIE1 BIT(27) -#define REG_RESET_CONTROL_PCIE2 BIT(26) - -struct en_clk_desc { - int id; - const char *name; - u32 base_reg; - u8 base_bits; - u8 base_shift; - union { - const unsigned int *base_values; - unsigned int base_value; - }; - size_t n_base_values; - - u16 div_reg; - u8 div_bits; - u8 div_shift; - u16 div_val0; - u8 div_step; -}; - -struct en_clk_gate { - void __iomem *base; - struct clk_hw hw; -}; - -static const u32 gsw_base[] = { 400000000, 500000000 }; -static const u32 emi_base[] = { 333000000, 400000000 }; -static const u32 bus_base[] = { 500000000, 540000000 }; -static const u32 slic_base[] = { 100000000, 3125000 }; -static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; - -static const struct en_clk_desc en7523_base_clks[] = { - { - .id = EN7523_CLK_GSW, - .name = "gsw", - - .base_reg = REG_GSW_CLK_DIV_SEL, - .base_bits = 1, - .base_shift = 8, - .base_values = gsw_base, - .n_base_values = ARRAY_SIZE(gsw_base), - - .div_bits = 3, - .div_shift = 0, - .div_step = 1, - }, { - .id = EN7523_CLK_EMI, - .name = "emi", - - .base_reg = REG_EMI_CLK_DIV_SEL, - .base_bits = 1, - .base_shift = 8, - .base_values = emi_base, - .n_base_values = ARRAY_SIZE(emi_base), - - .div_bits = 3, - .div_shift = 0, - .div_step = 1, - }, { - .id = EN7523_CLK_BUS, - .name = "bus", - - .base_reg = REG_BUS_CLK_DIV_SEL, - .base_bits = 1, - .base_shift = 8, - .base_values = bus_base, - .n_base_values = ARRAY_SIZE(bus_base), - - .div_bits = 3, - .div_shift = 0, - .div_step = 1, - }, { - .id = EN7523_CLK_SLIC, - .name = "slic", - - .base_reg = REG_SPI_CLK_FREQ_SEL, - .base_bits = 1, - .base_shift = 0, - .base_values = slic_base, - .n_base_values = ARRAY_SIZE(slic_base), - - .div_reg = REG_SPI_CLK_DIV_SEL, - .div_bits = 5, - .div_shift = 24, - .div_val0 = 20, - .div_step = 2, - }, { - .id = EN7523_CLK_SPI, - .name = "spi", - - .base_reg = REG_SPI_CLK_DIV_SEL, - - .base_value = 400000000, - - .div_bits = 5, - .div_shift = 8, - .div_val0 = 40, - .div_step = 2, - }, { - .id = EN7523_CLK_NPU, - .name = "npu", - - .base_reg = REG_NPU_CLK_DIV_SEL, - .base_bits = 2, - .base_shift = 8, - .base_values = npu_base, - .n_base_values = ARRAY_SIZE(npu_base), - - .div_bits = 3, - .div_shift = 0, - .div_step = 1, - }, { - .id = EN7523_CLK_CRYPTO, - .name = "crypto", - - .base_reg = REG_CRYPTO_CLKSRC, - .base_bits = 1, - .base_shift = 8, - .base_values = emi_base, - .n_base_values = ARRAY_SIZE(emi_base), - } -}; - -static const struct of_device_id of_match_clk_en7523[] = { - { .compatible = "airoha,en7523-scu", }, - { /* sentinel */ } -}; - -static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) -{ - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 val; - - if (!desc->base_bits) - return desc->base_value; - - val = readl(base + desc->base_reg); - val >>= desc->base_shift; - val &= (1 << desc->base_bits) - 1; - - if (val >= desc->n_base_values) - return 0; - - return desc->base_values[val]; -} - -static u32 en7523_get_div(void __iomem *base, int i) -{ - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 reg, val; - - if (!desc->div_bits) - return 1; - - reg = desc->div_reg ? desc->div_reg : desc->base_reg; - val = readl(base + reg); - val >>= desc->div_shift; - val &= (1 << desc->div_bits) - 1; - - if (!val && desc->div_val0) - return desc->div_val0; - - return (val + 1) * desc->div_step; -} - -static int en7523_pci_is_enabled(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); -} - -static int en7523_pci_prepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - /* Need to pull device low before reset */ - val = readl(np_base + REG_PCI_CONTROL); - val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); - writel(val, np_base + REG_PCI_CONTROL); - usleep_range(1000, 2000); - - /* Enable PCIe port 1 */ - val |= REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); - usleep_range(1000, 2000); - - /* Reset to default */ - val = readl(np_base + REG_RESET_CONTROL); - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - writel(val & ~mask, np_base + REG_RESET_CONTROL); - usleep_range(1000, 2000); - writel(val | mask, np_base + REG_RESET_CONTROL); - msleep(100); - writel(val & ~mask, np_base + REG_RESET_CONTROL); - usleep_range(5000, 10000); - - /* Release device */ - mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); - usleep_range(1000, 2000); - writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); - - return 0; -} - -static void en7523_pci_unprepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val; - - val = readl(np_base + REG_PCI_CONTROL); - val &= ~REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); -} - -static struct clk_hw *en7523_register_pcie_clk(struct device *dev, - void __iomem *np_base) -{ - static const struct clk_ops pcie_gate_ops = { - .is_enabled = en7523_pci_is_enabled, - .prepare = en7523_pci_prepare, - .unprepare = en7523_pci_unprepare, - }; - struct clk_init_data init = { - .name = "pcie", - .ops = &pcie_gate_ops, - }; - struct en_clk_gate *cg; - - cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); - if (!cg) - return NULL; - - cg->base = np_base; - cg->hw.init = &init; - en7523_pci_unprepare(&cg->hw); - - if (clk_hw_register(dev, &cg->hw)) - return NULL; - - return &cg->hw; -} - -static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - void __iomem *base, void __iomem *np_base) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - - rate = en7523_get_base_rate(base, i); - rate /= en7523_get_div(base, i); - - hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] = hw; - } - - hw = en7523_register_pcie_clk(dev, np_base); - clk_data->hws[EN7523_CLK_PCIE] = hw; - - clk_data->num = EN7523_NUM_CLOCKS; -} - -static int en7523_clk_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - void __iomem *base, *np_base; - int r; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - np_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); - - clk_data = devm_kzalloc(&pdev->dev, - struct_size(clk_data, hws, EN7523_NUM_CLOCKS), - GFP_KERNEL); - if (!clk_data) - return -ENOMEM; - - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - -static struct platform_driver clk_en7523_drv = { - .probe = en7523_clk_probe, - .driver = { - .name = "clk-en7523", - .of_match_table = of_match_clk_en7523, - .suppress_bind_attrs = true, - }, -}; - -static int __init clk_en7523_init(void) -{ - return platform_driver_register(&clk_en7523_drv); -} - -arch_initcall(clk_en7523_init); diff --git a/target/linux/airoha/files-5.15/drivers/gpio/gpio-en7523.c b/target/linux/airoha/files-5.15/drivers/gpio/gpio-en7523.c deleted file mode 100644 index f836a8db4c..0000000000 --- a/target/linux/airoha/files-5.15/drivers/gpio/gpio-en7523.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include -#include -#include -#include - -#define AIROHA_GPIO_MAX 32 - -/** - * airoha_gpio_ctrl - Airoha GPIO driver data - * @gc: Associated gpio_chip instance. - * @data: The data register. - * @dir0: The direction register for the lower 16 pins. - * @dir1: The direction register for the higher 16 pins. - * @output: The output enable register. - */ -struct airoha_gpio_ctrl { - struct gpio_chip gc; - void __iomem *data; - void __iomem *dir[2]; - void __iomem *output; -}; - -static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc) -{ - return container_of(gc, struct airoha_gpio_ctrl, gc); -} - -static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, - int val, int out) -{ - struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); - u32 dir = ioread32(ctrl->dir[gpio / 16]); - u32 output = ioread32(ctrl->output); - u32 mask = BIT((gpio % 16) * 2); - - if (out) { - dir |= mask; - output |= BIT(gpio); - } else { - dir &= ~mask; - output &= ~BIT(gpio); - } - - iowrite32(dir, ctrl->dir[gpio / 16]); - - if (out) - gc->set(gc, gpio, val); - - iowrite32(output, ctrl->output); - - return 0; -} - -static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio, - int val) -{ - return airoha_dir_set(gc, gpio, val, 1); -} - -static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio) -{ - return airoha_dir_set(gc, gpio, 0, 0); -} - -static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio) -{ - struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); - u32 dir = ioread32(ctrl->dir[gpio / 16]); - u32 mask = BIT((gpio % 16) * 2); - - return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; -} - -static int airoha_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct airoha_gpio_ctrl *ctrl; - int err; - - ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) - return -ENOMEM; - - ctrl->data = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ctrl->data)) - return PTR_ERR(ctrl->data); - - ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(ctrl->dir[0])) - return PTR_ERR(ctrl->dir[0]); - - ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2); - if (IS_ERR(ctrl->dir[1])) - return PTR_ERR(ctrl->dir[1]); - - ctrl->output = devm_platform_ioremap_resource(pdev, 3); - if (IS_ERR(ctrl->output)) - return PTR_ERR(ctrl->output); - - err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL, - NULL, NULL, NULL, 0); - if (err) - return dev_err_probe(dev, err, "unable to init generic GPIO"); - - ctrl->gc.ngpio = AIROHA_GPIO_MAX; - ctrl->gc.owner = THIS_MODULE; - ctrl->gc.direction_output = airoha_dir_out; - ctrl->gc.direction_input = airoha_dir_in; - ctrl->gc.get_direction = airoha_get_dir; - - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); -} - -static const struct of_device_id airoha_gpio_of_match[] = { - { .compatible = "airoha,en7523-gpio" }, - { } -}; -MODULE_DEVICE_TABLE(of, airoha_gpio_of_match); - -static struct platform_driver airoha_gpio_driver = { - .driver = { - .name = "airoha-gpio", - .of_match_table = airoha_gpio_of_match, - }, - .probe = airoha_gpio_probe, -}; -module_platform_driver(airoha_gpio_driver); - -MODULE_DESCRIPTION("Airoha GPIO support"); -MODULE_AUTHOR("John Crispin "); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/airoha/files-5.15/include/dt-bindings/clock/en7523-clk.h b/target/linux/airoha/files-5.15/include/dt-bindings/clock/en7523-clk.h deleted file mode 100644 index 717d23a5e5..0000000000 --- a/target/linux/airoha/files-5.15/include/dt-bindings/clock/en7523-clk.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ -#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ - -#define EN7523_CLK_GSW 0 -#define EN7523_CLK_EMI 1 -#define EN7523_CLK_BUS 2 -#define EN7523_CLK_SLIC 3 -#define EN7523_CLK_SPI 4 -#define EN7523_CLK_NPU 5 -#define EN7523_CLK_CRYPTO 6 -#define EN7523_CLK_PCIE 7 - -#define EN7523_NUM_CLOCKS 8 - -#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch b/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch deleted file mode 100644 index 5b356ea23e..0000000000 --- a/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -572,6 +572,18 @@ config ARCH_VIRT - select HAVE_ARM_ARCH_TIMER - select ARCH_SUPPORTS_BIG_ENDIAN - -+config ARCH_AIROHA -+ bool "Airoha SoC Support" -+ depends on ARCH_MULTI_V7 -+ select ARM_AMBA -+ select ARM_GIC -+ select ARM_GIC_V3 -+ select ARM_PSCI -+ select HAVE_ARM_ARCH_TIMER -+ select COMMON_CLK -+ help -+ Support for Airoha EN7523 SoCs -+ - # - # This is sorted alphabetically by mach-* pathname. However, plat-* - # Kconfigs may be included either alphabetically (according to the ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080 - # Machine directory name. This list is sorted alphanumerically - # by CONFIG_* macro name. - machine-$(CONFIG_ARCH_ACTIONS) += actions -+machine-$(CONFIG_ARCH_AIROHA) += airoha - machine-$(CONFIG_ARCH_ALPINE) += alpine - machine-$(CONFIG_ARCH_ARTPEC) += artpec - machine-$(CONFIG_ARCH_ASPEED) += aspeed diff --git a/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch b/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch deleted file mode 100644 index bae5cacc5e..0000000000 --- a/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP - help - If you say yes here you get support for the CS2000 clock multiplier. - -+config COMMON_CLK_EN7523 -+ bool "Clock driver for Airoha EN7523 SoC system clocks" -+ depends on OF -+ depends on ARCH_AIROHA || COMPILE_TEST -+ default ARCH_AIROHA -+ help -+ This driver provides the fixed clocks and gates present on Airoha -+ ARM silicon. -+ - config COMMON_CLK_FSL_FLEXSPI - tristate "Clock driver for FlexSPI on Layerscape SoCs" - depends on ARCH_LAYERSCAPE || COMPILE_TEST ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk- - obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o - obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o - obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o -+obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o - obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o - obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o - obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch b/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch deleted file mode 100644 index 319336257b..0000000000 --- a/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -247,6 +247,16 @@ config GPIO_EM - help - Say yes here to support GPIO on Renesas Emma Mobile SoCs. - -+config GPIO_EN7523 -+ tristate "Airoha GPIO support" -+ depends on ARCH_AIROHA -+ default ARCH_AIROHA -+ select GPIO_GENERIC -+ select GPIOLIB_IRQCHIP -+ help -+ Say Y or M here to support the GPIO controller block on the -+ Airoha EN7523 SoC. It supports two banks of 32 GPIOs. -+ - config GPIO_EP93XX - def_bool y - depends on ARCH_EP93XX ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o - obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o - obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o - obj-$(CONFIG_GPIO_EM) += gpio-em.o -+obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o - obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o - obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o - obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o diff --git a/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch b/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch deleted file mode 100644 index 0f0cbaa10f..0000000000 --- a/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 48342ae751c797ac73ac9c894b3f312df18ffd21 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Wed, 15 Sep 2021 13:46:20 +0100 -Subject: [PATCH] ARM: 9124/1: uncompress: Parse "linux,usable-memory-range" DT - property - -Add support for parsing the "linux,usable-memory-range" DT property. -This property is used to describe the usable memory reserved for the -crash dump kernel, and thus makes the memory reservation explicit. -If present, Linux no longer needs to mask the program counter, and rely -on the "mem=" kernel parameter to obtain the start and size of usable -memory. - -For backwards compatibility, the traditional method to derive the start -of memory is still used if "linux,usable-memory-range" is absent. - -Signed-off-by: Geert Uytterhoeven -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Danzberger ---- - .../arm/boot/compressed/fdt_check_mem_start.c | 48 ++++++++++++++++--- - 1 file changed, 42 insertions(+), 6 deletions(-) - ---- a/arch/arm/boot/compressed/fdt_check_mem_start.c -+++ b/arch/arm/boot/compressed/fdt_check_mem_start.c -@@ -55,16 +55,17 @@ static uint64_t get_val(const fdt32_t *c - * DTB, and, if out-of-range, replace it by the real start address. - * To preserve backwards compatibility (systems reserving a block of memory - * at the start of physical memory, kdump, ...), the traditional method is -- * always used if it yields a valid address. -+ * used if it yields a valid address, unless the "linux,usable-memory-range" -+ * property is present. - * - * Return value: start address of physical memory to use - */ - uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) - { -- uint32_t addr_cells, size_cells, base; -+ uint32_t addr_cells, size_cells, usable_base, base; - uint32_t fdt_mem_start = 0xffffffff; -- const fdt32_t *reg, *endp; -- uint64_t size, end; -+ const fdt32_t *usable, *reg, *endp; -+ uint64_t size, usable_end, end; - const char *type; - int offset, len; - -@@ -80,6 +81,27 @@ uint32_t fdt_check_mem_start(uint32_t me - if (addr_cells > 2 || size_cells > 2) - return mem_start; - -+ /* -+ * Usable memory in case of a crash dump kernel -+ * This property describes a limitation: memory within this range is -+ * only valid when also described through another mechanism -+ */ -+ usable = get_prop(fdt, "/chosen", "linux,usable-memory-range", -+ (addr_cells + size_cells) * sizeof(fdt32_t)); -+ if (usable) { -+ size = get_val(usable + addr_cells, size_cells); -+ if (!size) -+ return mem_start; -+ -+ if (addr_cells > 1 && fdt32_ld(usable)) { -+ /* Outside 32-bit address space */ -+ return mem_start; -+ } -+ -+ usable_base = fdt32_ld(usable + addr_cells - 1); -+ usable_end = usable_base + size; -+ } -+ - /* Walk all memory nodes and regions */ - for (offset = fdt_next_node(fdt, -1, NULL); offset >= 0; - offset = fdt_next_node(fdt, offset, NULL)) { -@@ -107,7 +129,20 @@ uint32_t fdt_check_mem_start(uint32_t me - - base = fdt32_ld(reg + addr_cells - 1); - end = base + size; -- if (mem_start >= base && mem_start < end) { -+ if (usable) { -+ /* -+ * Clip to usable range, which takes precedence -+ * over mem_start -+ */ -+ if (base < usable_base) -+ base = usable_base; -+ -+ if (end > usable_end) -+ end = usable_end; -+ -+ if (end <= base) -+ continue; -+ } else if (mem_start >= base && mem_start < end) { - /* Calculated address is valid, use it */ - return mem_start; - } -@@ -123,7 +158,8 @@ uint32_t fdt_check_mem_start(uint32_t me - } - - /* -- * The calculated address is not usable. -+ * The calculated address is not usable, or was overridden by the -+ * "linux,usable-memory-range" property. - * Use the lowest usable physical memory address from the DTB instead, - * and make sure this is a multiple of 2 MiB for phys/virt patching. - */ diff --git a/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch deleted file mode 100644 index 6c21666ed1..0000000000 --- a/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch +++ /dev/null @@ -1,341 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -307,6 +307,12 @@ config SPI_DLN2 - This driver can also be built as a module. If so, the module - will be called spi-dln2. - -+config SPI_AIROHA_EN7523 -+ bool "Airoha EN7523 SPI controller support" -+ depends on ARCH_AIROHA -+ help -+ This enables SPI controller support for the Airoha EN7523 SoC. -+ - config SPI_EP93XX - tristate "Cirrus Logic EP93xx SPI controller" - depends on ARCH_EP93XX || COMPILE_TEST ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1. - obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o - obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o - obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o -+obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o - obj-$(CONFIG_SPI_FALCON) += spi-falcon.o - obj-$(CONFIG_SPI_FSI) += spi-fsi.o - obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o ---- /dev/null -+++ b/drivers/spi/spi-en7523.c -@@ -0,0 +1,313 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+ -+ -+#define ENSPI_READ_IDLE_EN 0x0004 -+#define ENSPI_MTX_MODE_TOG 0x0014 -+#define ENSPI_RDCTL_FSM 0x0018 -+#define ENSPI_MANUAL_EN 0x0020 -+#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024 -+#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028 -+#define ENSPI_MANUAL_OPFIFO_FULL 0x002C -+#define ENSPI_MANUAL_OPFIFO_WR 0x0030 -+#define ENSPI_MANUAL_DFIFO_FULL 0x0034 -+#define ENSPI_MANUAL_DFIFO_WDATA 0x0038 -+#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C -+#define ENSPI_MANUAL_DFIFO_RD 0x0040 -+#define ENSPI_MANUAL_DFIFO_RDATA 0x0044 -+#define ENSPI_IER 0x0090 -+#define ENSPI_NFI2SPI_EN 0x0130 -+ -+// TODO not in spi block -+#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4) -+ -+#define OP_CSH 0x00 -+#define OP_CSL 0x01 -+#define OP_CK 0x02 -+#define OP_OUTS 0x08 -+#define OP_OUTD 0x09 -+#define OP_OUTQ 0x0A -+#define OP_INS 0x0C -+#define OP_INS0 0x0D -+#define OP_IND 0x0E -+#define OP_INQ 0x0F -+#define OP_OS2IS 0x10 -+#define OP_OS2ID 0x11 -+#define OP_OS2IQ 0x12 -+#define OP_OD2IS 0x13 -+#define OP_OD2ID 0x14 -+#define OP_OD2IQ 0x15 -+#define OP_OQ2IS 0x16 -+#define OP_OQ2ID 0x17 -+#define OP_OQ2IQ 0x18 -+#define OP_OSNIS 0x19 -+#define OP_ODNID 0x1A -+ -+#define MATRIX_MODE_AUTO 1 -+#define CONF_MTX_MODE_AUTO 0 -+#define MANUALEN_AUTO 0 -+#define MATRIX_MODE_MANUAL 0 -+#define CONF_MTX_MODE_MANUAL 9 -+#define MANUALEN_MANUAL 1 -+ -+#define _ENSPI_MAX_XFER 0x1ff -+ -+#define REG(x) (iobase + x) -+ -+ -+static void __iomem *iobase; -+ -+ -+static void opfifo_write(u32 cmd, u32 len) -+{ -+ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff); -+ -+ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA)); -+ -+ /* Wait for room in OPFIFO */ -+ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL))) -+ ; -+ -+ /* Shift command into OPFIFO */ -+ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR)); -+ -+ /* Wait for command to finish */ -+ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY))) -+ ; -+} -+ -+static void set_cs(int state) -+{ -+ if (state) -+ opfifo_write(OP_CSH, 1); -+ else -+ opfifo_write(OP_CSL, 1); -+} -+ -+static void manual_begin_cmd(void) -+{ -+ /* Disable read idle state */ -+ writel(0, REG(ENSPI_READ_IDLE_EN)); -+ -+ /* Wait for FSM to reach idle state */ -+ while (readl(REG(ENSPI_RDCTL_FSM))) -+ ; -+ -+ /* Set SPI core to manual mode */ -+ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG)); -+ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN)); -+} -+ -+static void manual_end_cmd(void) -+{ -+ /* Set SPI core to auto mode */ -+ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG)); -+ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN)); -+ -+ /* Enable read idle state */ -+ writel(1, REG(ENSPI_READ_IDLE_EN)); -+} -+ -+static void dfifo_read(u8 *buf, int len) -+{ -+ int i; -+ -+ for (i = 0; i < len; i++) { -+ /* Wait for requested data to show up in DFIFO */ -+ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY))) -+ ; -+ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA)); -+ /* Queue up next byte */ -+ writel(1, REG(ENSPI_MANUAL_DFIFO_RD)); -+ } -+} -+ -+static void dfifo_write(const u8 *buf, int len) -+{ -+ int i; -+ -+ for (i = 0; i < len; i++) { -+ /* Wait for room in DFIFO */ -+ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL))) -+ ; -+ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA)); -+ } -+} -+ -+#if 0 -+static void set_spi_clock_speed(int freq_mhz) -+{ -+ u32 tmp, val; -+ -+ tmp = readl(ENSPI_CLOCK_DIVIDER); -+ tmp &= 0xffff0000; -+ writel(tmp, ENSPI_CLOCK_DIVIDER); -+ -+ val = (400 / (freq_mhz * 2)); -+ tmp |= (val << 8) | 1; -+ writel(tmp, ENSPI_CLOCK_DIVIDER); -+} -+#endif -+ -+static void init_hw(void) -+{ -+ /* Disable manual/auto mode clash interrupt */ -+ writel(0, REG(ENSPI_IER)); -+ -+ // TODO via clk framework -+ // set_spi_clock_speed(50); -+ -+ /* Disable DMA */ -+ writel(0, REG(ENSPI_NFI2SPI_EN)); -+} -+ -+static int xfer_read(struct spi_transfer *xfer) -+{ -+ int opcode; -+ uint8_t *buf = xfer->rx_buf; -+ -+ switch (xfer->rx_nbits) { -+ case SPI_NBITS_SINGLE: -+ opcode = OP_INS; -+ break; -+ case SPI_NBITS_DUAL: -+ opcode = OP_IND; -+ break; -+ case SPI_NBITS_QUAD: -+ opcode = OP_INQ; -+ break; -+ } -+ -+ opfifo_write(opcode, xfer->len); -+ dfifo_read(buf, xfer->len); -+ -+ return xfer->len; -+} -+ -+static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx) -+{ -+ int opcode; -+ const uint8_t *buf = xfer->tx_buf; -+ -+ if (next_xfer_is_rx) { -+ /* need to use Ox2Ix opcode to set the core to input afterwards */ -+ switch (xfer->tx_nbits) { -+ case SPI_NBITS_SINGLE: -+ opcode = OP_OS2IS; -+ break; -+ case SPI_NBITS_DUAL: -+ opcode = OP_OS2ID; -+ break; -+ case SPI_NBITS_QUAD: -+ opcode = OP_OS2IQ; -+ break; -+ } -+ } else { -+ switch (xfer->tx_nbits) { -+ case SPI_NBITS_SINGLE: -+ opcode = OP_OUTS; -+ break; -+ case SPI_NBITS_DUAL: -+ opcode = OP_OUTD; -+ break; -+ case SPI_NBITS_QUAD: -+ opcode = OP_OUTQ; -+ break; -+ } -+ } -+ -+ opfifo_write(opcode, xfer->len); -+ dfifo_write(buf, xfer->len); -+ -+ return xfer->len; -+} -+ -+size_t max_transfer_size(struct spi_device *spi) -+{ -+ return _ENSPI_MAX_XFER; -+} -+ -+int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg) -+{ -+ struct spi_transfer *xfer; -+ int next_xfer_is_rx = 0; -+ -+ manual_begin_cmd(); -+ set_cs(0); -+ list_for_each_entry(xfer, &msg->transfers, transfer_list) { -+ if (xfer->tx_buf) { -+ if (!list_is_last(&xfer->transfer_list, &msg->transfers) -+ && list_next_entry(xfer, transfer_list)->rx_buf != NULL) -+ next_xfer_is_rx = 1; -+ else -+ next_xfer_is_rx = 0; -+ msg->actual_length += xfer_write(xfer, next_xfer_is_rx); -+ } else if (xfer->rx_buf) { -+ msg->actual_length += xfer_read(xfer); -+ } -+ } -+ set_cs(1); -+ manual_end_cmd(); -+ -+ msg->status = 0; -+ spi_finalize_current_message(ctrl); -+ -+ return 0; -+} -+ -+static int spi_probe(struct platform_device *pdev) -+{ -+ struct spi_controller *ctrl; -+ int err; -+ -+ ctrl = devm_spi_alloc_master(&pdev->dev, 0); -+ if (!ctrl) { -+ dev_err(&pdev->dev, "Error allocating SPI controller\n"); -+ return -ENOMEM; -+ } -+ -+ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); -+ if (IS_ERR(iobase)) { -+ dev_err(&pdev->dev, "Could not map SPI register address"); -+ return -ENOMEM; -+ } -+ -+ init_hw(); -+ -+ ctrl->dev.of_node = pdev->dev.of_node; -+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; -+ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL; -+ ctrl->max_transfer_size = max_transfer_size; -+ ctrl->transfer_one_message = transfer_one_message; -+ err = devm_spi_register_controller(&pdev->dev, ctrl); -+ if (err) { -+ dev_err(&pdev->dev, "Could not register SPI controller\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id spi_of_ids[] = { -+ { .compatible = "airoha,en7523-spi" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, spi_of_ids); -+ -+static struct platform_driver spi_driver = { -+ .probe = spi_probe, -+ .driver = { -+ .name = "airoha-en7523-spi", -+ .of_match_table = spi_of_ids, -+ }, -+}; -+ -+module_platform_driver(spi_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Bert Vermeulen "); -+MODULE_DESCRIPTION("Airoha EN7523 SPI driver"); diff --git a/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch b/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch deleted file mode 100644 index 4659809074..0000000000 --- a/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch +++ /dev/null @@ -1,31 +0,0 @@ -From b3b76fc86f0fb4d98918f48c784138bfa950dff6 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Wed, 15 Jun 2022 14:53:34 +0200 -Subject: [PATCH] PCI: mediatek: Allow building for ARCH_AIROHA - -Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the -Airoha EN7523 SoC uses the same controller as MT7622. - -The driver itself is not modified. The PCIe controller DT node should use -mediatek,mt7622-pcie after airoha,en7523-pcie. - -Link: https://lore.kernel.org/r/20220615125335.96089-2-nbd@nbd.name -Signed-off-by: Felix Fietkau -Signed-off-by: Bjorn Helgaas -Acked-by: Lorenzo Pieralisi -Signed-off-by: Daniel Danzberger ---- - drivers/pci/controller/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP - - config PCIE_MEDIATEK - tristate "MediaTek PCIe controller" -- depends on ARCH_MEDIATEK || COMPILE_TEST -+ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST - depends on OF - depends on PCI_MSI_IRQ_DOMAIN - help diff --git a/target/linux/bcm47xx/Makefile b/target/linux/bcm47xx/Makefile index a56c53ca6d..22fc36e9b1 100644 --- a/target/linux/bcm47xx/Makefile +++ b/target/linux/bcm47xx/Makefile @@ -11,6 +11,7 @@ FEATURES:=squashfs usb SUBTARGETS:=generic mips74k legacy KERNEL_PATCHVER:=5.15 +KERNEL_TESTING_PATCHVER:=6.1 define Target/Description Build firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM. diff --git a/target/linux/bcm47xx/config-6.1 b/target/linux/bcm47xx/config-6.1 new file mode 100644 index 0000000000..d86e79d98b --- /dev/null +++ b/target/linux/bcm47xx/config-6.1 @@ -0,0 +1,190 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BCM47XX=y +CONFIG_BCM47XX_BCMA=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_BCM47XX_SSB=y +CONFIG_BCM47XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_DEBUG=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_MIPS=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y +CONFIG_BCMA_FALLBACK_SPROM=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_NFLASH=y +CONFIG_BCMA_PFLASH=y +CONFIG_BCMA_SFLASH=y +# CONFIG_BGMAC_BCMA is not set +CONFIG_BLK_MQ_PCI=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_COMMON_CLK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_CPU_BMIPS is not set +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_WDT=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO_REGISTER=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_BCM47XXSFLASH=y +CONFIG_MTD_BCM47XX_PARTS=y +CONFIG_MTD_NAND_BCM47XXNFLASH=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_BRCMNAND_BCMA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_SELFTESTS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_OF is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SRCU=y +CONFIG_SSB=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_DRIVER_EXTIF=y +CONFIG_SSB_DRIVER_GIGE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_MIPS=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_EMBEDDED=y +CONFIG_SSB_FALLBACK_SPROM=y +CONFIG_SSB_HOST_SOC=y +CONFIG_SSB_PCICORE_HOSTMODE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_SERIAL=y +CONFIG_SSB_SFLASH=y +CONFIG_SSB_SPROM=y +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_B53=y +CONFIG_SWCONFIG_B53_PHY_DRIVER=y +CONFIG_SWCONFIG_B53_PHY_FIXUP=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_BMIPS=y +CONFIG_SYS_HAS_CPU_BMIPS32_3300=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZBOOT_LOAD_ADDRESS=0xffffffff80400000 diff --git a/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch b/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch index 30b6d97a85..f6f90a8165 100644 --- a/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch +++ b/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch @@ -22,7 +22,7 @@ Signed-off-by: Florian Fainelli /* Enable the static key if the soc provides I/O operations indicating * that a non-memory mapped IO access path must be used -@@ -3205,8 +3206,6 @@ int brcmnand_probe(struct platform_devic +@@ -3209,8 +3210,6 @@ int brcmnand_probe(struct platform_devic * interesting ways */ if (soc) { diff --git a/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch index 6a17ea7182..fdfd35a44f 100644 --- a/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch +++ b/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch @@ -43,7 +43,7 @@ Signed-off-by: Florian Fainelli nand_set_controller_data(chip, host); mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", host->cs); -@@ -3236,7 +3229,16 @@ int brcmnand_probe(struct platform_devic +@@ -3240,7 +3233,16 @@ int brcmnand_probe(struct platform_devic host->pdev = pdev; host->ctrl = ctrl; diff --git a/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch b/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch index ecc3e954ce..08cecf3d4a 100644 --- a/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch +++ b/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch @@ -32,7 +32,7 @@ Signed-off-by: Florian Fainelli /* switch to interrupt polling and PIO mode */ disable_ctrl_irqs(ctrl); sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, -@@ -3187,33 +3187,29 @@ int brcmnand_probe(struct platform_devic +@@ -3191,33 +3191,29 @@ int brcmnand_probe(struct platform_devic } /* IRQ */ diff --git a/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch b/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch index b9ad82ecf9..4942389b5a 100644 --- a/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch +++ b/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch @@ -72,7 +72,7 @@ Signed-off-by: Florian Fainelli return PTR_ERR(ctrl->nand_base); /* Enable clock before using NAND registers */ -@@ -3214,7 +3214,6 @@ int brcmnand_probe(struct platform_devic +@@ -3218,7 +3218,6 @@ int brcmnand_probe(struct platform_devic for_each_available_child_of_node(dn, child) { if (of_device_is_compatible(child, "brcm,nandcs")) { @@ -80,7 +80,7 @@ Signed-off-by: Florian Fainelli host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { -@@ -3234,7 +3233,7 @@ int brcmnand_probe(struct platform_devic +@@ -3238,7 +3237,7 @@ int brcmnand_probe(struct platform_devic nand_set_flash_node(&host->chip, child); @@ -89,7 +89,7 @@ Signed-off-by: Florian Fainelli if (ret) { devm_kfree(dev, host); continue; /* Try all chip-selects */ -@@ -3244,6 +3243,32 @@ int brcmnand_probe(struct platform_devic +@@ -3248,6 +3247,32 @@ int brcmnand_probe(struct platform_devic } } diff --git a/target/linux/bcm47xx/patches-6.1/030-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch b/target/linux/bcm47xx/patches-6.1/030-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch new file mode 100644 index 0000000000..4faecdc7d5 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/030-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch @@ -0,0 +1,65 @@ +From fc605b914167de75432c3b5aae239fb191e84a31 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 8 Feb 2023 08:03:01 +0100 +Subject: [PATCH] MIPS: BCM47XX: Add support for Linksys E2500 V3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It's a BCM5358 based home WiFi router. 16 MiB flash, 64 MiB RAM, BCM5325 +switch, on-SoC 802.11n radio. + +Signed-off-by: Rafał Miłecki +Reviewed-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/board.c | 1 + + arch/mips/bcm47xx/buttons.c | 9 +++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + + 3 files changed, 11 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -130,6 +130,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ + {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"}, + {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"}, + {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"}, ++ {{BCM47XX_BOARD_LINKSYS_E2500V3, "Linksys E2500 V3"}, "E2500", "1.0"}, + /* like WRT610N v2.0 */ + {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -223,6 +223,12 @@ bcm47xx_buttons_linksys_e2000v1[] __init + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_linksys_e2500v3[] __initconst = { ++ BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(10, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_linksys_e3000v1[] __initconst = { + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), + BCM47XX_GPIO_KEY(6, KEY_RESTART), +@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_LINKSYS_E2000V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1); + break; ++ case BCM47XX_BOARD_LINKSYS_E2500V3: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2500v3); ++ break; + case BCM47XX_BOARD_LINKSYS_E3000V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -61,6 +61,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_LINKSYS_E1000V21, + BCM47XX_BOARD_LINKSYS_E1200V2, + BCM47XX_BOARD_LINKSYS_E2000V1, ++ BCM47XX_BOARD_LINKSYS_E2500V3, + BCM47XX_BOARD_LINKSYS_E3000V1, + BCM47XX_BOARD_LINKSYS_E3200V1, + BCM47XX_BOARD_LINKSYS_E4200V1, diff --git a/target/linux/bcm47xx/patches-6.1/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch b/target/linux/bcm47xx/patches-6.1/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch new file mode 100644 index 0000000000..333c3d7b87 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch @@ -0,0 +1,61 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 27 Feb 2023 07:44:38 +0100 +Subject: [PATCH] MIPS: BCM47XX: Add support for Huawei B593u-12 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It's a BCM5358 based home router. One of very few bcm47xx devices with +cellular modems (here: LTE). + +Signed-off-by: Rafał Miłecki +--- + arch/mips/bcm47xx/board.c | 1 + + arch/mips/bcm47xx/leds.c | 8 ++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ + /* boardtype, boardnum, boardrev */ + static const + struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { ++ {{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"}, + {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, + {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, + {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -223,6 +223,11 @@ bcm47xx_leds_dlink_dir330[] __initconst + /* Huawei */ + + static const struct gpio_led ++bcm47xx_leds_huawei_b593u_12[] __initconst = { ++ BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_huawei_e970[] __initconst = { + BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), + }; +@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void) + bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330); + break; + ++ case BCM47XX_BOARD_HUAWEI_B593U_12: ++ bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12); ++ break; + case BCM47XX_BOARD_HUAWEI_E970: + bcm47xx_set_pdata(bcm47xx_leds_huawei_e970); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -53,6 +53,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_DLINK_DIR130, + BCM47XX_BOARD_DLINK_DIR330, + ++ BCM47XX_BOARD_HUAWEI_B593U_12, + BCM47XX_BOARD_HUAWEI_E970, + + BCM47XX_BOARD_LINKSYS_E900V1, diff --git a/target/linux/bcm47xx/patches-6.1/159-cpu_fixes.patch b/target/linux/bcm47xx/patches-6.1/159-cpu_fixes.patch new file mode 100644 index 0000000000..f51ed83d93 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/159-cpu_fixes.patch @@ -0,0 +1,484 @@ +--- a/arch/mips/include/asm/r4kcache.h ++++ b/arch/mips/include/asm/r4kcache.h +@@ -27,6 +27,38 @@ + extern void (*r4k_blast_dcache)(void); + extern void (*r4k_blast_icache)(void); + ++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2) ++#include ++#include ++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg() ++ ++static inline unsigned long bcm4710_dummy_rreg(void) ++{ ++ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE)); ++} ++ ++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr)) ++ ++static inline unsigned long bcm4710_fill_tlb(void *addr) ++{ ++ return *(unsigned long *)addr; ++} ++ ++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr)) ++ ++static inline void bcm4710_protected_fill_tlb(void *addr) ++{ ++ unsigned long x; ++ get_dbe(x, (unsigned long *)addr);; ++} ++ ++#else ++#define BCM4710_DUMMY_RREG() ++ ++#define BCM4710_FILL_TLB(addr) ++#define BCM4710_PROTECTED_FILL_TLB(addr) ++#endif ++ + /* + * This macro return a properly sign-extended address suitable as base address + * for indexed cache operations. Two issues here: +@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind + + static inline void flush_dcache_line_indexed(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + cache_op(Index_Writeback_Inv_D, addr); + } + +@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns + + static inline void flush_dcache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Writeback_Inv_D, addr); + } + + static inline void invalidate_dcache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Invalidate_D, addr); + } + +@@ -160,6 +195,7 @@ static inline int protected_flush_icache + return protected_cache_op(Hit_Invalidate_I_Loongson2, addr); + + default: ++ BCM4710_DUMMY_RREG(); + return protected_cache_op(Hit_Invalidate_I, addr); + } + } +@@ -172,6 +208,7 @@ static inline int protected_flush_icache + */ + static inline int protected_writeback_dcache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + return protected_cache_op(Hit_Writeback_Inv_D, addr); + } + +@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag + unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \ + } while (0) + ++static inline void blast_dcache(void) ++{ ++ unsigned long start = KSEG0; ++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways; ++ unsigned long end = (start + dcache_size); ++ ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ ++ BCM4710_FILL_TLB(start); ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Hit_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page_indexed(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; ++ unsigned long ws_end = current_cpu_data.dcache.ways << ++ current_cpu_data.dcache.waybit; ++ unsigned long ws, addr; ++ for (ws = 0; ws < ws_end; ws += ws_inc) { ++ start = page + ws; ++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, addr); ++ } ++ } ++} ++ + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ ++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \ + static inline void extra##blast_##pfx##cache##lsize(void) \ + { \ + unsigned long start = INDEX_BASE; \ +@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ ++ war \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache_unroll(32, kernel_cache, indexop, \ +@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ ++ war \ + do { \ + cache_unroll(32, kernel_cache, hitop, start, lsize); \ + start += lsize * 32; \ +@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ ++ war \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache_unroll(32, kernel_cache, indexop, \ + addr | ws, lsize); \ + } + +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) +- +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , ) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , ) ++ ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , ) ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , ) + + #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ + static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ +@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde + __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) + + /* build blast_xxx_range, protected_blast_xxx_range */ +-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ ++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \ + static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ + { \ + unsigned long lsize = cpu_##desc##_line_size(); \ +- unsigned long lsize_2 = lsize * 2; \ +- unsigned long lsize_3 = lsize * 3; \ +- unsigned long lsize_4 = lsize * 4; \ +- unsigned long lsize_5 = lsize * 5; \ +- unsigned long lsize_6 = lsize * 6; \ +- unsigned long lsize_7 = lsize * 7; \ +- unsigned long lsize_8 = lsize * 8; \ + unsigned long addr = start & ~(lsize - 1); \ +- unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \ +- int lines = (aend - addr) / lsize; \ +- \ +- while (lines >= 8) { \ +- prot##cache_op(hitop, addr); \ +- prot##cache_op(hitop, addr + lsize); \ +- prot##cache_op(hitop, addr + lsize_2); \ +- prot##cache_op(hitop, addr + lsize_3); \ +- prot##cache_op(hitop, addr + lsize_4); \ +- prot##cache_op(hitop, addr + lsize_5); \ +- prot##cache_op(hitop, addr + lsize_6); \ +- prot##cache_op(hitop, addr + lsize_7); \ +- addr += lsize_8; \ +- lines -= 8; \ +- } \ ++ unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ +- if (lines & 0x4) { \ +- prot##cache_op(hitop, addr); \ +- prot##cache_op(hitop, addr + lsize); \ +- prot##cache_op(hitop, addr + lsize_2); \ +- prot##cache_op(hitop, addr + lsize_3); \ +- addr += lsize_4; \ +- } \ +- \ +- if (lines & 0x2) { \ +- prot##cache_op(hitop, addr); \ +- prot##cache_op(hitop, addr + lsize); \ +- addr += lsize_2; \ +- } \ ++ war \ + \ +- if (lines & 0x1) { \ ++ while (1) { \ ++ war2 \ + prot##cache_op(hitop, addr); \ ++ if (addr == aend) \ ++ break; \ ++ addr += lsize; \ + } \ + } + +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , ) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , ) + __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ +- protected_, loongson2_) +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) ++ protected_, loongson2_, , ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , ) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , ) + /* blast_inv_dcache_range */ +-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) +-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) ++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , ) + + /* Currently, this is very specific to Loongson-3 */ + #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \ +--- a/arch/mips/include/asm/stackframe.h ++++ b/arch/mips/include/asm/stackframe.h +@@ -429,6 +429,10 @@ + #else + .set push + .set arch=r4000 ++#ifdef CONFIG_BCM47XX ++ nop ++ nop ++#endif + eret + .set pop + #endif +--- a/arch/mips/kernel/genex.S ++++ b/arch/mips/kernel/genex.S +@@ -21,6 +21,19 @@ + #include + #include + ++#ifdef CONFIG_BCM47XX ++# ifdef eret ++# undef eret ++# endif ++# define eret \ ++ .set push; \ ++ .set noreorder; \ ++ nop; \ ++ nop; \ ++ eret; \ ++ .set pop; ++#endif ++ + __INIT + + /* +@@ -32,6 +45,9 @@ + NESTED(except_vec3_generic, 0, sp) + .set push + .set noat ++#ifdef CONFIG_BCM47XX ++ nop ++#endif + mfc0 k1, CP0_CAUSE + andi k1, k1, 0x7c + #ifdef CONFIG_64BIT +@@ -52,6 +68,9 @@ NESTED(except_vec3_r4000, 0, sp) + .set push + .set arch=r4000 + .set noat ++#ifdef CONFIG_BCM47XX ++ nop ++#endif + mfc0 k1, CP0_CAUSE + li k0, 31<<2 + andi k1, k1, 0x7c +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -37,6 +37,9 @@ + #include + #include + ++/* For enabling BCM4710 cache workarounds */ ++static int bcm4710 = 0; ++ + /* + * Bits describing what cache ops an SMP callback function may perform. + * +@@ -189,6 +192,9 @@ static void r4k_blast_dcache_user_page_s + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page = blast_dcache_page; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_user_page = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -207,6 +213,9 @@ static void r4k_blast_dcache_page_indexe + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -226,6 +235,9 @@ static void r4k_blast_dcache_setup(void) + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache = blast_dcache; ++ else + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -1779,6 +1791,17 @@ static void coherency_setup(void) + * silly idea of putting something else there ... + */ + switch (current_cpu_type()) { ++ case CPU_BMIPS3300: ++ { ++ u32 cm; ++ cm = read_c0_diag(); ++ /* Enable icache */ ++ cm |= (1 << 31); ++ /* Enable dcache */ ++ cm |= (1 << 30); ++ write_c0_diag(cm); ++ } ++ break; + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: +@@ -1825,6 +1848,15 @@ void r4k_cache_init(void) + extern void build_copy_page(void); + struct cpuinfo_mips *c = ¤t_cpu_data; + ++ /* Check if special workarounds are required */ ++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2) ++ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) { ++ printk("Enabling BCM4710A0 cache workarounds.\n"); ++ bcm4710 = 1; ++ } else ++#endif ++ bcm4710 = 0; ++ + probe_pcache(); + probe_vcache(); + setup_scache(); +@@ -1897,7 +1929,15 @@ void r4k_cache_init(void) + */ + local_r4k___flush_cache_all(NULL); + ++#ifdef CONFIG_BCM47XX ++ { ++ static void (*_coherency_setup)(void); ++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup); ++ _coherency_setup(); ++ } ++#else + coherency_setup(); ++#endif + board_cache_error_setup = r4k_cache_error_setup; + + /* +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -958,6 +958,9 @@ void build_get_pgde32(u32 **p, unsigned + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + uasm_i_addu(p, ptr, tmp, ptr); + #else ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + UASM_i_LA_mostly(p, ptr, pgdc); + #endif + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ +@@ -1304,6 +1307,9 @@ static void build_r4000_tlb_refill_handl + #ifdef CONFIG_64BIT + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ + #else ++# ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++# endif + build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ + #endif + +@@ -1315,6 +1321,9 @@ static void build_r4000_tlb_refill_handl + build_update_entries(&p, K0, K1); + build_tlb_write_entry(&p, &l, &r, tlb_random); + uasm_l_leave(&l, p); ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++#endif + uasm_i_eret(&p); /* return from trap */ + } + #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT +@@ -2016,6 +2025,9 @@ build_r4000_tlbchange_handler_head(u32 * + #ifdef CONFIG_64BIT + build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ + #else ++# ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++# endif + build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ + #endif + +@@ -2062,6 +2074,9 @@ build_r4000_tlbchange_handler_tail(u32 * + build_tlb_write_entry(p, l, r, tlb_indexed); + uasm_l_leave(l, *p); + build_restore_work_registers(p); ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + uasm_i_eret(p); /* return from trap */ + + #ifdef CONFIG_64BIT diff --git a/target/linux/bcm47xx/patches-6.1/160-kmap_coherent.patch b/target/linux/bcm47xx/patches-6.1/160-kmap_coherent.patch new file mode 100644 index 0000000000..2af9d42fe5 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/160-kmap_coherent.patch @@ -0,0 +1,78 @@ +From: Jeff Hansen +Subject: [PATCH] kmap_coherent + +On ASUS WL-500gP there are some "Data bus error"s when executing simple +commands liks "ps" or "cat /proc/1/cmdline". + +This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485 +--- +--- a/arch/mips/include/asm/cpu-features.h ++++ b/arch/mips/include/asm/cpu-features.h +@@ -257,6 +257,9 @@ + #ifndef cpu_has_pindexed_dcache + #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) + #endif ++#ifndef cpu_use_kmap_coherent ++#define cpu_use_kmap_coherent 1 ++#endif + + /* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors +--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h +@@ -79,4 +79,6 @@ + #define cpu_scache_line_size() 0 + #define cpu_has_vz 0 + ++#define cpu_use_kmap_coherent 0 ++ + #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */ +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -701,7 +701,7 @@ static inline void local_r4k_flush_cache + map_coherent = (cpu_has_dc_aliases && + page_mapcount(page) && + !Page_dcache_dirty(page)); +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + vaddr = kmap_coherent(page, addr); + else + vaddr = kmap_atomic(page); +@@ -728,7 +728,7 @@ static inline void local_r4k_flush_cache + } + + if (vaddr) { +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + kunmap_coherent(); + else + kunmap_atomic(vaddr); +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -172,7 +172,7 @@ void copy_user_highpage(struct page *to, + void *vfrom, *vto; + + vto = kmap_atomic(to); +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapcount(from) && !Page_dcache_dirty(from)) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); +@@ -194,7 +194,7 @@ void copy_to_user_page(struct vm_area_st + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapcount(page) && !Page_dcache_dirty(page)) { + void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(vto, src, len); +@@ -212,7 +212,7 @@ void copy_from_user_page(struct vm_area_ + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapcount(page) && !Page_dcache_dirty(page)) { + void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(dst, vfrom, len); diff --git a/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch new file mode 100644 index 0000000000..af4e218f9e --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch @@ -0,0 +1,121 @@ +From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 9 Nov 2013 17:03:59 +0100 +Subject: [PATCH 210/210] b44: register adm switch + +--- + drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++ + drivers/net/ethernet/broadcom/b44.h | 3 ++ + 2 files changed, 60 insertions(+) + +--- a/drivers/net/ethernet/broadcom/b44.c ++++ b/drivers/net/ethernet/broadcom/b44.c +@@ -31,6 +31,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -2249,6 +2251,69 @@ static void b44_adjust_link(struct net_d + } + } + ++#ifdef CONFIG_BCM47XX ++static int b44_register_adm_switch(struct b44 *bp) ++{ ++ int gpio; ++ struct platform_device *pdev; ++ struct adm6996_gpio_platform_data adm_data = {0}; ++ struct platform_device_info info = {0}; ++ ++ adm_data.model = ADM6996L; ++ gpio = bcm47xx_nvram_gpio_pin("adm_eecs"); ++ if (gpio >= 0) ++ adm_data.eecs = gpio; ++ else ++ adm_data.eecs = 2; ++ ++ gpio = bcm47xx_nvram_gpio_pin("adm_eesk"); ++ if (gpio >= 0) ++ adm_data.eesk = gpio; ++ else ++ adm_data.eesk = 3; ++ ++ gpio = bcm47xx_nvram_gpio_pin("adm_eedi"); ++ if (gpio >= 0) ++ adm_data.eedi = gpio; ++ else ++ adm_data.eedi = 4; ++ ++ /* ++ * We ignore the "adm_rc" GPIO here. The driver does not use it, ++ * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1. ++ */ ++ ++ info.parent = bp->sdev->dev; ++ info.name = "adm6996_gpio"; ++ info.id = -1; ++ info.data = &adm_data; ++ info.size_data = sizeof(adm_data); ++ ++ if (!bp->adm_switch) { ++ pdev = platform_device_register_full(&info); ++ if (IS_ERR(pdev)) ++ return PTR_ERR(pdev); ++ ++ bp->adm_switch = pdev; ++ } ++ return 0; ++} ++static void b44_unregister_adm_switch(struct b44 *bp) ++{ ++ if (bp->adm_switch) ++ platform_device_unregister(bp->adm_switch); ++} ++#else ++static int b44_register_adm_switch(struct b44 *bp) ++{ ++ return 0; ++} ++static void b44_unregister_adm_switch(struct b44 *bp) ++{ ++ ++} ++#endif /* CONFIG_BCM47XX */ ++ + static int b44_register_phy_one(struct b44 *bp) + { + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +@@ -2285,6 +2350,9 @@ static int b44_register_phy_one(struct b + if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) && + (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) { + ++ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM) ++ b44_register_adm_switch(bp); ++ + dev_info(sdev->dev, + "could not find PHY at %i, use fixed one\n", + bp->phy_addr); +@@ -2479,6 +2547,7 @@ static void b44_remove_one(struct ssb_de + unregister_netdev(dev); + if (bp->flags & B44_FLAG_EXTERNAL_PHY) + b44_unregister_phy_one(bp); ++ b44_unregister_adm_switch(bp); + ssb_device_disable(sdev, 0); + ssb_bus_may_powerdown(sdev->bus); + netif_napi_del(&bp->napi); +--- a/drivers/net/ethernet/broadcom/b44.h ++++ b/drivers/net/ethernet/broadcom/b44.h +@@ -408,6 +408,9 @@ struct b44 { + struct mii_bus *mii_bus; + int old_link; + struct mii_if_info mii_if; ++ ++ /* platform device for associated switch */ ++ struct platform_device *adm_switch; + }; + + #endif /* _B44_H */ diff --git a/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch new file mode 100644 index 0000000000..ffe029b9fe --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch @@ -0,0 +1,54 @@ +--- a/drivers/net/ethernet/broadcom/b44.c ++++ b/drivers/net/ethernet/broadcom/b44.c +@@ -430,10 +430,34 @@ static void b44_wap54g10_workaround(stru + error: + pr_warn("PHY: cannot reset MII transceiver isolate bit\n"); + } ++ ++static void b44_bcm47xx_workarounds(struct b44 *bp) ++{ ++ char buf[20]; ++ struct ssb_device *sdev = bp->sdev; ++ ++ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */ ++ if (sdev->bus->sprom.board_num == 100) { ++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; ++ } else { ++ /* WL-HDD */ ++ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 && ++ !strncmp(buf, "WL300-", strlen("WL300-"))) { ++ if (sdev->bus->sprom.et0phyaddr == 0 && ++ sdev->bus->sprom.et1phyaddr == 1) ++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; ++ } ++ } ++ return; ++} + #else + static inline void b44_wap54g10_workaround(struct b44 *bp) + { + } ++ ++static inline void b44_bcm47xx_workarounds(struct b44 *bp) ++{ ++} + #endif + + static int b44_setup_phy(struct b44 *bp) +@@ -442,6 +466,7 @@ static int b44_setup_phy(struct b44 *bp) + int err; + + b44_wap54g10_workaround(bp); ++ b44_bcm47xx_workarounds(bp); + + if (bp->flags & B44_FLAG_EXTERNAL_PHY) + return 0; +@@ -2179,6 +2204,8 @@ static int b44_get_invariants(struct b44 + * valid PHY address. */ + bp->phy_addr &= 0x1F; + ++ b44_bcm47xx_workarounds(bp); ++ + eth_hw_addr_set(bp->dev, addr); + + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ diff --git a/target/linux/bcm47xx/patches-6.1/280-activate_ssb_support_in_usb.patch b/target/linux/bcm47xx/patches-6.1/280-activate_ssb_support_in_usb.patch new file mode 100644 index 0000000000..f6e9e6d30a --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/280-activate_ssb_support_in_usb.patch @@ -0,0 +1,25 @@ +This prevents the options from being delete with make kernel_oldconfig. +--- + drivers/ssb/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -36,6 +36,7 @@ config BCMA_HOST_PCI + config BCMA_HOST_SOC + bool "Support for BCMA in a SoC" + depends on HAS_IOMEM ++ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD + help + Host interface for a Broadcom AIX bus directly mapped into + the memory. This only works with the Broadcom SoCs from the +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -141,6 +141,7 @@ config SSB_SFLASH + config SSB_EMBEDDED + bool + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE ++ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD + default y + + config SSB_DRIVER_EXTIF diff --git a/target/linux/bcm47xx/patches-6.1/300-fork_cacheflush.patch b/target/linux/bcm47xx/patches-6.1/300-fork_cacheflush.patch new file mode 100644 index 0000000000..daa2c1adf0 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/300-fork_cacheflush.patch @@ -0,0 +1,21 @@ +From: Wolfram Joost +Subject: [PATCH] fork_cacheflush + +On ASUS WL-500gP there are many unexpected "Segmentation fault"s that +seem to be caused by a kernel. They can be avoided by: +1) Disabling highpage +2) Using flush_cache_mm in flush_cache_dup_mm + +For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 +--- +--- a/arch/mips/include/asm/cacheflush.h ++++ b/arch/mips/include/asm/cacheflush.h +@@ -46,7 +46,7 @@ + extern void (*flush_cache_all)(void); + extern void (*__flush_cache_all)(void); + extern void (*flush_cache_mm)(struct mm_struct *mm); +-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0) ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + extern void (*flush_cache_range)(struct vm_area_struct *vma, + unsigned long start, unsigned long end); + extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); diff --git a/target/linux/bcm47xx/patches-6.1/310-no_highpage.patch b/target/linux/bcm47xx/patches-6.1/310-no_highpage.patch new file mode 100644 index 0000000000..8f368e3e9e --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/310-no_highpage.patch @@ -0,0 +1,74 @@ +From: Jeff Hansen +Subject: [PATCH] no highpage + +On ASUS WL-500gP there are many unexpected "Segmentation fault"s that +seem to be caused by a kernel. They can be avoided by: +1) Disabling highpage +2) Using flush_cache_mm in flush_cache_dup_mm + +For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 +--- +--- a/arch/mips/include/asm/page.h ++++ b/arch/mips/include/asm/page.h +@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl + #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ + + #include ++#include + + extern void build_clear_page(void); + extern void build_copy_page(void); +@@ -110,11 +111,16 @@ static inline void clear_user_page(void + flush_data_cache_page((unsigned long)addr); + } + +-struct vm_area_struct; +-extern void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma); ++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, ++ struct page *to) ++{ ++ extern void (*flush_data_cache_page)(unsigned long addr); + +-#define __HAVE_ARCH_COPY_USER_HIGHPAGE ++ copy_page(vto, vfrom); ++ if (!cpu_has_ic_fills_f_dc || ++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) ++ flush_data_cache_page((unsigned long)vto); ++} + + /* + * These are used to make use of C type-checking.. +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -166,30 +166,6 @@ void kunmap_coherent(void) + preempt_enable(); + } + +-void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma) +-{ +- void *vfrom, *vto; +- +- vto = kmap_atomic(to); +- if (cpu_has_dc_aliases && cpu_use_kmap_coherent && +- page_mapcount(from) && !Page_dcache_dirty(from)) { +- vfrom = kmap_coherent(from, vaddr); +- copy_page(vto, vfrom); +- kunmap_coherent(); +- } else { +- vfrom = kmap_atomic(from); +- copy_page(vto, vfrom); +- kunmap_atomic(vfrom); +- } +- if ((!cpu_has_ic_fills_f_dc) || +- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) +- flush_data_cache_page((unsigned long)vto); +- kunmap_atomic(vto); +- /* Make sure this page is cleared on other CPU's too before using it */ +- smp_wmb(); +-} +- + void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) diff --git a/target/linux/bcm47xx/patches-6.1/400-mtd-bcm47xxpart-get-nvram.patch b/target/linux/bcm47xx/patches-6.1/400-mtd-bcm47xxpart-get-nvram.patch new file mode 100644 index 0000000000..17abe89d1d --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/400-mtd-bcm47xxpart-get-nvram.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/parsers/bcm47xxpart.c ++++ b/drivers/mtd/parsers/bcm47xxpart.c +@@ -98,6 +98,7 @@ static int bcm47xxpart_parse(struct mtd_ + int trx_num = 0; /* Number of found TRX partitions */ + int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, }; + int err; ++ bool found_nvram = false; + + /* + * Some really old flashes (like AT45DB*) had smaller erasesize-s, but +@@ -279,12 +280,23 @@ static int bcm47xxpart_parse(struct mtd_ + if (buf[0] == NVRAM_HEADER) { + bcm47xxpart_add_part(&parts[curr_part++], "nvram", + master->size - blocksize, 0); ++ found_nvram = true; + break; + } + } + + kfree(buf); + ++ if (!found_nvram) { ++ pr_err("can not find a nvram partition reserve last block\n"); ++ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess", ++ master->size - blocksize * 2, MTD_WRITEABLE); ++ for (i = 0; i < curr_part; i++) { ++ if (parts[i].size + parts[i].offset == master->size) ++ parts[i].offset -= blocksize * 2; ++ } ++ } ++ + /* + * Assume that partitions end at the beginning of the one they are + * followed by. diff --git a/target/linux/bcm47xx/patches-6.1/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-6.1/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch new file mode 100644 index 0000000000..2fcfbb7438 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch @@ -0,0 +1,42 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 7 Nov 2021 14:20:40 +0100 +Subject: [PATCH] net: bgmac: connect to PHY even if it is BGMAC_PHY_NOREGS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Recent bgmac change was meant to just fix a race between "Generic PHY" +and "bcm53xx" drivers after -EPROBE_DEFER. It modified bgmac to use +phy_connect() only if there is a real PHY device connected. + +That change broke bgmac on bcm47xx. bcma_phy_connect() now registers a +fixed PHY with the bgmac_phy_connect_direct(). That fails as another +fixed PHY (also using address 0) is already registered - by bcm47xx arch +code bcm47xx_register_bus_complete(). + +This change brings origial behaviour. It connects Ethernet interface +with pseudo-PHY (switch device) and adjusts Ethernet interface link to +match connected switch. + +This fixes: +[ 2.548098] bgmac_bcma bcma0:1: Failed to register fixed PHY device +[ 2.554584] bgmac_bcma bcma0:1: Cannot connect to phy + +Fixes: b5375509184d ("net: bgmac: improve handling PHY") +Link: https://lore.kernel.org/netdev/3639116e-9292-03ca-b9d9-d741118a4541@gmail.com/T/#u +Signed-off-by: Rafał Miłecki +--- + drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c ++++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c +@@ -94,7 +94,7 @@ static int bcma_phy_connect(struct bgmac + return 0; + + /* Connect to the PHY */ +- if (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) { ++ if (bgmac->mii_bus) { + snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id, + bgmac->phyaddr); + phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link, diff --git a/target/linux/bcm47xx/patches-6.1/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch b/target/linux/bcm47xx/patches-6.1/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch new file mode 100644 index 0000000000..3a2f4b06ed --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch @@ -0,0 +1,33 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 10 Jun 2022 13:10:47 +0200 +Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +bgmac allocates new replacement buffer before handling each received +frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU +time. Ideally bgmac should just respect currently set MTU but it isn't +the case right now. For now just revert back to the old limited frame +size. + +This change bumps NAT masquarade speed by ~95%. + +Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size") +Signed-off-by: Rafał Miłecki +--- + drivers/net/ethernet/broadcom/bgmac.h | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -328,8 +328,7 @@ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ + #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ + BGMAC_RX_FRAME_OFFSET) +-/* Jumbo frame size with FCS */ +-#define BGMAC_RX_MAX_FRAME_SIZE 9724 ++#define BGMAC_RX_MAX_FRAME_SIZE 1536 + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) + #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) diff --git a/target/linux/bcm47xx/patches-6.1/791-tg3-no-pci-sleep.patch b/target/linux/bcm47xx/patches-6.1/791-tg3-no-pci-sleep.patch new file mode 100644 index 0000000000..76e979ad58 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/791-tg3-no-pci-sleep.patch @@ -0,0 +1,17 @@ +When the Ethernet controller is powered down and someone wants to +access the mdio bus like the witch driver (b53) the system crashed if +PCI_D3hot was set before. This patch deactivates this power sawing mode +when a switch driver is in use. + +--- a/drivers/net/ethernet/broadcom/tg3.c ++++ b/drivers/net/ethernet/broadcom/tg3.c +@@ -4269,7 +4269,8 @@ static int tg3_power_down_prepare(struct + static void tg3_power_down(struct tg3 *tp) + { + pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); +- pci_set_power_state(tp->pdev, PCI_D3hot); ++ if (!tg3_flag(tp, ROBOSWITCH)) ++ pci_set_power_state(tp->pdev, PCI_D3hot); + } + + static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) diff --git a/target/linux/bcm47xx/patches-6.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch b/target/linux/bcm47xx/patches-6.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch new file mode 100644 index 0000000000..318dc55810 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch @@ -0,0 +1,73 @@ +From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 20 Nov 2014 21:32:42 +0100 +Subject: [PATCH] bcma: add table of serial flashes with smaller blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/drivers/bcma/driver_chipcommon_sflash.c ++++ b/drivers/bcma/driver_chipcommon_sflash.c +@@ -9,6 +9,7 @@ + + #include + #include ++#include + + static struct resource bcma_sflash_resource = { + .name = "bcma_sflash", +@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc + { NULL }, + }; + ++/* Some devices use smaller blocks (and have more of them) */ ++static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = { ++ { "M25P16", 0x14, 0x1000, 512, }, ++ { "M25P32", 0x15, 0x1000, 1024, }, ++ { NULL }, ++}; ++ + static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { + { "SST25WF512", 1, 0x1000, 16, }, + { "SST25VF512", 0x48, 0x1000, 16, }, +@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_ + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n"); + } + ++const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ const struct bcma_sflash_tbl_e *e; ++ ++ switch (board) { ++ case BCM47XX_BOARD_NETGEAR_WGR614_V10: ++ case BCM47XX_BOARD_NETGEAR_WNR1000_V3: ++ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) { ++ if (e->id == id) ++ return e; ++ } ++ return NULL; ++ default: ++ return NULL; ++ } ++} ++ + /* Initialize serial flash access */ + int bcma_sflash_init(struct bcma_drv_cc *cc) + { +@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc + case 0x13: + return -ENOTSUPP; + default: ++ e = bcma_sflash_shrink_flash(id); ++ if (e) ++ break; ++ + for (e = bcma_sflash_st_tbl; e->name; e++) { + if (e->id == id) + break; diff --git a/target/linux/bcm47xx/patches-6.1/820-wgt634u-nvram-fix.patch b/target/linux/bcm47xx/patches-6.1/820-wgt634u-nvram-fix.patch new file mode 100644 index 0000000000..82997ca65a --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/820-wgt634u-nvram-fix.patch @@ -0,0 +1,296 @@ +The Netgear wgt634u uses a different format for storing the +configuration. This patch is needed to read out the correct +configuration. The cfe_env.c file uses a different method way to read +out the configuration than the in kernel cfe config reader. + +--- a/drivers/firmware/broadcom/Makefile ++++ b/drivers/firmware/broadcom/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o ++obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o cfe_env.o + obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx_sprom.o + obj-$(CONFIG_TEE_BNXT_FW) += tee_bnxt_fw.o +--- /dev/null ++++ b/drivers/firmware/broadcom/cfe_env.c +@@ -0,0 +1,228 @@ ++/* ++ * CFE environment variable access ++ * ++ * Copyright 2001-2003, Broadcom Corporation ++ * Copyright 2006, Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define NVRAM_SIZE (0x1ff0) ++static char _nvdata[NVRAM_SIZE]; ++static char _valuestr[256]; ++ ++/* ++ * TLV types. These codes are used in the "type-length-value" ++ * encoding of the items stored in the NVRAM device (flash or EEPROM) ++ * ++ * The layout of the flash/nvram is as follows: ++ * ++ * ++ * ++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list. ++ * The "length" field marks the length of the data section, not ++ * including the type and length fields. ++ * ++ * Environment variables are stored as follows: ++ * ++ * = ++ * ++ * If bit 0 (low bit) is set, the length is an 8-bit value. ++ * If bit 0 (low bit) is clear, the length is a 16-bit value ++ * ++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still ++ * indicates the size of the length field. ++ * ++ * Flags are from the constants below: ++ * ++ */ ++#define ENV_LENGTH_16BITS 0x00 /* for low bit */ ++#define ENV_LENGTH_8BITS 0x01 ++ ++#define ENV_TYPE_USER 0x80 ++ ++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l)) ++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER) ++ ++/* ++ * The actual TLV types we support ++ */ ++ ++#define ENV_TLV_TYPE_END 0x00 ++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS) ++ ++/* ++ * Environment variable flags ++ */ ++ ++#define ENV_FLG_NORMAL 0x00 /* normal read/write */ ++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */ ++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */ ++ ++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */ ++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */ ++ ++ ++/* ********************************************************************* ++ * _nvram_read(buffer,offset,length) ++ * ++ * Read data from the NVRAM device ++ * ++ * Input parameters: ++ * buffer - destination buffer ++ * offset - offset of data to read ++ * length - number of bytes to read ++ * ++ * Return value: ++ * number of bytes read, or <0 if error occured ++ ********************************************************************* */ ++static int ++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length) ++{ ++ int i; ++ if (offset > NVRAM_SIZE) ++ return -1; ++ ++ for ( i = 0; i < length; i++) { ++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i]; ++ } ++ return length; ++} ++ ++ ++static char* ++_strnchr(const char *dest,int c,size_t cnt) ++{ ++ while (*dest && (cnt > 0)) { ++ if (*dest == c) return (char *) dest; ++ dest++; ++ cnt--; ++ } ++ return NULL; ++} ++ ++ ++ ++/* ++ * Core support API: Externally visible. ++ */ ++ ++/* ++ * Get the value of an NVRAM variable ++ * @param name name of variable to get ++ * @return value of variable or NULL if undefined ++ */ ++ ++char *cfe_env_get(unsigned char *nv_buf, const char *name) ++{ ++ int size; ++ unsigned char *buffer; ++ unsigned char *ptr; ++ unsigned char *envval; ++ unsigned int reclen; ++ unsigned int rectype; ++ int offset; ++ int flg; ++ ++ if (!strcmp(name, "nvram_type")) ++ return "cfe"; ++ ++ size = NVRAM_SIZE; ++ buffer = &_nvdata[0]; ++ ++ ptr = buffer; ++ offset = 0; ++ ++ /* Read the record type and length */ ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { ++ goto error; ++ } ++ ++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) { ++ ++ /* Adjust pointer for TLV type */ ++ rectype = *(ptr); ++ offset++; ++ size--; ++ ++ /* ++ * Read the length. It can be either 1 or 2 bytes ++ * depending on the code ++ */ ++ if (rectype & ENV_LENGTH_8BITS) { ++ /* Read the record type and length - 8 bits */ ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { ++ goto error; ++ } ++ reclen = *(ptr); ++ size--; ++ offset++; ++ } ++ else { ++ /* Read the record type and length - 16 bits, MSB first */ ++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) { ++ goto error; ++ } ++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1); ++ size -= 2; ++ offset += 2; ++ } ++ ++ if (reclen > size) ++ break; /* should not happen, bad NVRAM */ ++ ++ switch (rectype) { ++ case ENV_TLV_TYPE_ENV: ++ /* Read the TLV data */ ++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen) ++ goto error; ++ flg = *ptr++; ++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1)); ++ if (envval) { ++ *envval++ = '\0'; ++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr)); ++ _valuestr[(reclen-1)-(envval-ptr)] = '\0'; ++#if 0 ++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr); ++#endif ++ if(!strcmp(ptr, name)){ ++ return _valuestr; ++ } ++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name)) ++ return _valuestr; ++ } ++ break; ++ ++ default: ++ /* Unknown TLV type, skip it. */ ++ break; ++ } ++ ++ /* ++ * Advance to next TLV ++ */ ++ ++ size -= (int)reclen; ++ offset += reclen; ++ ++ /* Read the next record type */ ++ ptr = buffer; ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) ++ goto error; ++ } ++ ++error: ++ return NULL; ++ ++} ++ +--- a/drivers/firmware/broadcom/bcm47xx_nvram.c ++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c +@@ -33,6 +33,8 @@ struct nvram_header { + static char nvram_buf[NVRAM_SPACE]; + static size_t nvram_len; + static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000}; ++static int cfe_env; ++extern char *cfe_env_get(char *nv_buf, const char *name); + + /** + * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory +@@ -80,6 +82,26 @@ static int bcm47xx_nvram_find_and_copy(v + return -EEXIST; + } + ++ cfe_env = 0; ++ ++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */ ++ if (res_size >= 8 * 1024 * 1024) { ++ u32 *src = (u32 *)(flash_start + 8 * 1024 * 1024 - 0x2000); ++ u32 *dst = (u32 *)nvram_buf; ++ ++ if ((*src & 0xff00ff) == 0x000001) { ++ printk("early_nvram_init: WGT634U NVRAM found.\n"); ++ ++ for (i = 0; i < 0x1ff0; i++) { ++ if (*src == 0xFFFFFFFF) ++ break; ++ *dst++ = *src++; ++ } ++ cfe_env = 1; ++ return 0; ++ } ++ } ++ + /* TODO: when nvram is on nand flash check for bad blocks first. */ + + /* Try every possible flash size and check for NVRAM at its end */ +@@ -190,6 +212,13 @@ int bcm47xx_nvram_getenv(const char *nam + if (!name) + return -EINVAL; + ++ if (cfe_env) { ++ value = cfe_env_get(nvram_buf, name); ++ if (!value) ++ return -ENOENT; ++ return snprintf(val, val_len, "%s", value); ++ } ++ + if (!nvram_len) { + err = nvram_init(); + if (err) diff --git a/target/linux/bcm47xx/patches-6.1/830-huawei_e970_support.patch b/target/linux/bcm47xx/patches-6.1/830-huawei_e970_support.patch new file mode 100644 index 0000000000..1746fee592 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/830-huawei_e970_support.patch @@ -0,0 +1,101 @@ +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f + .duplex = DUPLEX_FULL, + }; + ++static struct gpio_wdt_platform_data gpio_wdt_data; ++ ++static struct platform_device gpio_wdt_device = { ++ .name = "gpio-wdt", ++ .id = 0, ++ .dev = { ++ .platform_data = &gpio_wdt_data, ++ }, ++}; ++ ++static int __init bcm47xx_register_gpio_watchdog(void) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ ++ switch (board) { ++ case BCM47XX_BOARD_HUAWEI_E970: ++ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n"); ++ gpio_wdt_data.gpio = 7; ++ gpio_wdt_data.interval = HZ; ++ gpio_wdt_data.first_interval = HZ / 5; ++ return platform_device_register(&gpio_wdt_device); ++ default: ++ /* Nothing to do */ ++ return 0; ++ } ++} ++ + static int __init bcm47xx_register_bus_complete(void) + { + switch (bcm47xx_bus_type) { +@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c + bcm47xx_workarounds(); + + fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); ++ bcm47xx_register_gpio_watchdog(); + return 0; + } + device_initcall(bcm47xx_register_bus_complete); +--- a/arch/mips/configs/bcm47xx_defconfig ++++ b/arch/mips/configs/bcm47xx_defconfig +@@ -63,6 +63,7 @@ CONFIG_HW_RANDOM=y + CONFIG_GPIO_SYSFS=y + CONFIG_WATCHDOG=y + CONFIG_BCM47XX_WDT=y ++CONFIG_GPIO_WDT=y + CONFIG_SSB_DRIVER_GIGE=y + CONFIG_BCMA_DRIVER_GMAC_CMN=y + CONFIG_USB=y +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu + } + EXPORT_SYMBOL(ssb_watchdog_timer_set); + ++#ifdef CONFIG_BCM47XX ++#include ++ ++static bool ssb_watchdog_supported(void) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ ++ /* The Huawei E970 has a hardware watchdog using a GPIO */ ++ switch (board) { ++ case BCM47XX_BOARD_HUAWEI_E970: ++ return false; ++ default: ++ return true; ++ } ++} ++#else ++static bool ssb_watchdog_supported(void) ++{ ++ return true; ++} ++#endif ++ + int ssb_watchdog_register(struct ssb_bus *bus) + { + struct bcm47xx_wdt wdt = {}; + struct platform_device *pdev; + ++ if (!ssb_watchdog_supported()) ++ return 0; ++ + if (ssb_chipco_available(&bus->chipco)) { + wdt.driver_data = &bus->chipco; + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt; diff --git a/target/linux/bcm47xx/patches-6.1/831-old_gpio_wdt.patch b/target/linux/bcm47xx/patches-6.1/831-old_gpio_wdt.patch new file mode 100644 index 0000000000..55639c6d2e --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/831-old_gpio_wdt.patch @@ -0,0 +1,360 @@ +This generic GPIO watchdog is used on Huawei E970 (bcm47xx) + +Signed-off-by: Mathias Adam + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1728,6 +1728,15 @@ config WDT_MTX1 + Hardware driver for the MTX-1 boards. This is a watchdog timer that + will reboot the machine after a 100 seconds timer expired. + ++config GPIO_WDT ++ tristate "GPIO Hardware Watchdog" ++ help ++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and ++ toggle interval settings are platform-specific. The driver ++ will stop toggling the GPIO (i.e. machine reboots) after a ++ 100 second timer expired and no process has written to ++ /dev/watchdog during that time. ++ + config SIBYTE_WDOG + tristate "Sibyte SoC hardware watchdog" + depends on CPU_SB1 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -164,6 +164,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o ++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o +--- /dev/null ++++ b/drivers/watchdog/old_gpio_wdt.c +@@ -0,0 +1,301 @@ ++/* ++ * Driver for GPIO-controlled Hardware Watchdogs. ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): ++ * ++ * (C) Copyright 2005 4G Systems , ++ * All Rights Reserved. ++ * http://www.4g-systems.biz ++ * ++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Neither Michael Stickel nor 4G Systems admit liability nor provide ++ * warranty for any of this software. This material is provided ++ * "AS-IS" and at no charge. ++ * ++ * (c) Copyright 2005 4G Systems ++ * ++ * Release 0.01. ++ * Author: Michael Stickel michael.stickel@4g-systems.biz ++ * ++ * Release 0.02. ++ * Author: Florian Fainelli florian@openwrt.org ++ * use the Linux watchdog/timer APIs ++ * ++ * Release 0.03. ++ * Author: Mathias Adam ++ * make it a generic gpio watchdog driver ++ * ++ * The Watchdog is configured to reset the MTX-1 ++ * if it is not triggered for 100 seconds. ++ * It should not be triggered more often than 1.6 seconds. ++ * ++ * A timer triggers the watchdog every 5 seconds, until ++ * it is opened for the first time. After the first open ++ * it MUST be triggered every 2..95 seconds. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ticks = 100 * HZ; ++ ++static struct { ++ struct completion stop; ++ spinlock_t lock; ++ int running; ++ struct timer_list timer; ++ int queue; ++ int default_ticks; ++ unsigned long inuse; ++ unsigned gpio; ++ unsigned int gstate; ++ int interval; ++ int first_interval; ++} gpio_wdt_device; ++ ++static void gpio_wdt_trigger(struct timer_list *unused) ++{ ++ spin_lock(&gpio_wdt_device.lock); ++ if (gpio_wdt_device.running && ticks > 0) ++ ticks -= gpio_wdt_device.interval; ++ ++ /* toggle wdt gpio */ ++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; ++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); ++ ++ if (gpio_wdt_device.queue && ticks > 0) ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); ++ else ++ complete(&gpio_wdt_device.stop); ++ spin_unlock(&gpio_wdt_device.lock); ++} ++ ++static void gpio_wdt_reset(void) ++{ ++ ticks = gpio_wdt_device.default_ticks; ++} ++ ++ ++static void gpio_wdt_start(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (!gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 1; ++ gpio_wdt_device.gstate = 1; ++ gpio_set_value(gpio_wdt_device.gpio, 1); ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); ++ } ++ gpio_wdt_device.running++; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++} ++ ++static int gpio_wdt_stop(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ gpio_wdt_device.gstate = 0; ++ gpio_set_value(gpio_wdt_device.gpio, 0); ++ } ++ ticks = gpio_wdt_device.default_ticks; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++ return 0; ++} ++ ++/* Filesystem functions */ ++ ++static int gpio_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) ++ return -EBUSY; ++ return nonseekable_open(inode, file); ++} ++ ++ ++static int gpio_wdt_release(struct inode *inode, struct file *file) ++{ ++ clear_bit(0, &gpio_wdt_device.inuse); ++ return 0; ++} ++ ++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = (int __user *)argp; ++ unsigned int value; ++ static const struct watchdog_info ident = { ++ .options = WDIOF_CARDRESET, ++ .identity = "GPIO WDT", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ if (copy_to_user(argp, &ident, sizeof(ident))) ++ return -EFAULT; ++ break; ++ case WDIOC_GETSTATUS: ++ case WDIOC_GETBOOTSTATUS: ++ put_user(0, p); ++ break; ++ case WDIOC_SETOPTIONS: ++ if (get_user(value, p)) ++ return -EFAULT; ++ if (value & WDIOS_ENABLECARD) ++ gpio_wdt_start(); ++ else if (value & WDIOS_DISABLECARD) ++ gpio_wdt_stop(); ++ else ++ return -EINVAL; ++ return 0; ++ case WDIOC_KEEPALIVE: ++ gpio_wdt_reset(); ++ break; ++ default: ++ return -ENOTTY; ++ } ++ return 0; ++} ++ ++ ++static ssize_t gpio_wdt_write(struct file *file, const char *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (!count) ++ return -EIO; ++ gpio_wdt_reset(); ++ return count; ++} ++ ++static const struct file_operations gpio_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gpio_wdt_ioctl, ++ .open = gpio_wdt_open, ++ .write = gpio_wdt_write, ++ .release = gpio_wdt_release, ++}; ++ ++ ++static struct miscdevice gpio_wdt_misc = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gpio_wdt_fops, ++}; ++ ++ ++static int gpio_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; ++ ++ gpio_wdt_device.gpio = gpio_wdt_data->gpio; ++ gpio_wdt_device.interval = gpio_wdt_data->interval; ++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; ++ if (gpio_wdt_device.first_interval <= 0) { ++ gpio_wdt_device.first_interval = gpio_wdt_device.interval; ++ } ++ ++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request gpio"); ++ return ret; ++ } ++ ++ spin_lock_init(&gpio_wdt_device.lock); ++ init_completion(&gpio_wdt_device.stop); ++ gpio_wdt_device.queue = 0; ++ clear_bit(0, &gpio_wdt_device.inuse); ++ timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); ++ gpio_wdt_device.default_ticks = ticks; ++ ++ gpio_wdt_start(); ++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", ++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); ++ return 0; ++} ++ ++static int gpio_wdt_remove(struct platform_device *pdev) ++{ ++ /* FIXME: do we need to lock this test ? */ ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ wait_for_completion(&gpio_wdt_device.stop); ++ } ++ ++ gpio_free(gpio_wdt_device.gpio); ++ misc_deregister(&gpio_wdt_misc); ++ return 0; ++} ++ ++static struct platform_driver gpio_wdt_driver = { ++ .probe = gpio_wdt_probe, ++ .remove = gpio_wdt_remove, ++ .driver.name = "gpio-wdt", ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gpio_wdt_init(void) ++{ ++ return platform_driver_register(&gpio_wdt_driver); ++} ++arch_initcall(gpio_wdt_init); ++ ++/* ++ * We do wdt initialization in two steps: arch_initcall probes the wdt ++ * very early to start pinging the watchdog (misc devices are not yet ++ * available), and later module_init() just registers the misc device. ++ */ ++static int gpio_wdt_init_late(void) ++{ ++ int ret; ++ ++ ret = misc_register(&gpio_wdt_misc); ++ if (ret < 0) { ++ pr_err("GPIO_WDT: failed to register misc device\n"); ++ return ret; ++ } ++ return 0; ++} ++#ifndef MODULE ++module_init(gpio_wdt_init_late); ++#endif ++ ++static void __exit gpio_wdt_exit(void) ++{ ++ platform_driver_unregister(&gpio_wdt_driver); ++} ++module_exit(gpio_wdt_exit); ++ ++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); ++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gpio-wdt"); +--- /dev/null ++++ b/include/linux/old_gpio_wdt.h +@@ -0,0 +1,21 @@ ++/* ++ * Definitions for the GPIO watchdog driver ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _GPIO_WDT_H_ ++#define _GPIO_WDT_H_ ++ ++struct gpio_wdt_platform_data { ++ int gpio; /* GPIO line number */ ++ int interval; /* watchdog reset interval in system ticks */ ++ int first_interval; /* first wd reset interval in system ticks */ ++}; ++ ++#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/bcm47xx/patches-6.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch b/target/linux/bcm47xx/patches-6.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch new file mode 100644 index 0000000000..970e36eb68 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch @@ -0,0 +1,30 @@ +From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 8 Apr 2015 06:58:11 +0200 +Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If SoC has a CardBus we can set resources of device at slot 1 only. It's +impossigle to set bridge resources as it simply overwrites device 1 +configuration and usually results in Data bus error-s. + +Signed-off-by: Rafał Miłecki +--- + drivers/ssb/driver_pcicore.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -165,6 +165,10 @@ static int ssb_extpci_write_config(struc + WARN_ON(!pc->hostmode); + if (unlikely(len != 1 && len != 2 && len != 4)) + goto out; ++ /* CardBus SoCs allow configuring dev 1 resources only */ ++ if (extpci_core->cardbusmode && dev != 1 && ++ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5) ++ goto out; + addr = get_cfgspace_addr(pc, bus, dev, func, off); + if (unlikely(!addr)) + goto out; diff --git a/target/linux/bcm47xx/patches-6.1/940-bcm47xx-yenta.patch b/target/linux/bcm47xx/patches-6.1/940-bcm47xx-yenta.patch new file mode 100644 index 0000000000..f1b46c2ce4 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/940-bcm47xx-yenta.patch @@ -0,0 +1,48 @@ +--- a/drivers/pcmcia/yenta_socket.c ++++ b/drivers/pcmcia/yenta_socket.c +@@ -925,6 +925,8 @@ static struct cardbus_type cardbus_type[ + + static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask) + { ++/* WRT54G3G does not like this */ ++#ifndef CONFIG_BCM47XX + int i; + unsigned long val; + u32 mask; +@@ -953,6 +955,9 @@ static unsigned int yenta_probe_irq(stru + mask = probe_irq_mask(val) & 0xffff; + + return mask; ++#else ++ return 0; ++#endif + } + + +@@ -1033,6 +1038,10 @@ static void yenta_get_socket_capabilitie + else + socket->socket.irq_mask = 0; + ++ /* irq mask probing is broken for the WRT54G3G */ ++ if (socket->socket.irq_mask == 0) ++ socket->socket.irq_mask = 0x6f8; ++ + dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n", + socket->socket.irq_mask, socket->cb_irq); + } +@@ -1264,6 +1273,15 @@ static int yenta_probe(struct pci_dev *d + dev_info(&dev->dev, "Socket status: %08x\n", + cb_readl(socket, CB_SOCKET_STATE)); + ++ /* Generate an interrupt on card insert/remove */ ++ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK); ++ ++ /* Set up Multifunction Routing Status Register */ ++ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */); ++ ++ /* Switch interrupts to parallelized */ ++ config_writeb(socket, 0x92, 0x64); ++ + yenta_fixup_parent_bridge(dev->subordinate); + + /* Register it with the pcmcia layer.. */ diff --git a/target/linux/bcm47xx/patches-6.1/976-ssb_increase_pci_delay.patch b/target/linux/bcm47xx/patches-6.1/976-ssb_increase_pci_delay.patch new file mode 100644 index 0000000000..201be1b187 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/976-ssb_increase_pci_delay.patch @@ -0,0 +1,11 @@ +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -394,7 +394,7 @@ static void ssb_pcicore_init_hostmode(st + /* Give some time to the PCI controller to configure itself with the new + * values. Not waiting at this point causes crashes of the machine. + */ +- mdelay(10); ++ mdelay(300); + register_pci_controller(&ssb_pcicore_controller); + } + diff --git a/target/linux/bcm47xx/patches-6.1/999-wl_exports.patch b/target/linux/bcm47xx/patches-6.1/999-wl_exports.patch new file mode 100644 index 0000000000..b47913af70 --- /dev/null +++ b/target/linux/bcm47xx/patches-6.1/999-wl_exports.patch @@ -0,0 +1,24 @@ +--- a/drivers/firmware/broadcom/bcm47xx_nvram.c ++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c +@@ -30,7 +30,8 @@ struct nvram_header { + u32 config_ncdl; /* ncdl values for memc */ + }; + +-static char nvram_buf[NVRAM_SPACE]; ++char nvram_buf[NVRAM_SPACE]; ++EXPORT_SYMBOL(nvram_buf); + static size_t nvram_len; + static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000}; + static int cfe_env; +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -63,6 +63,9 @@ void (*_dma_cache_wback_inv)(unsigned lo + void (*_dma_cache_wback)(unsigned long start, unsigned long size); + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + ++EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_inv); ++ + #endif /* CONFIG_DMA_NONCOHERENT */ + + /* diff --git a/target/linux/bcm4908/Makefile b/target/linux/bcm4908/Makefile index 45b4a62f2f..d515912829 100644 --- a/target/linux/bcm4908/Makefile +++ b/target/linux/bcm4908/Makefile @@ -9,8 +9,7 @@ FEATURES:=squashfs nand usb gpio CPU_TYPE:=cortex-a53 SUBTARGETS:=generic -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 define Target/Description Build firmware images for Broadcom BCM4908 SoC family routers. diff --git a/target/linux/bcm4908/config-6.6 b/target/linux/bcm4908/config-6.6 new file mode 100644 index 0000000000..0c604a1860 --- /dev/null +++ b/target/linux/bcm4908/config-6.6 @@ -0,0 +1,281 @@ +CONFIG_64BIT=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCMBCA=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_PSCI_FW=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_B53=y +CONFIG_BCM4908_ENET=y +CONFIG_BCM7038_WDT=y +CONFIG_BCM7XXX_PHY=y +CONFIG_BCM_NET_PHYLIB=y +CONFIG_BCM_PMB=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_PM=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLK_BCM_63XX=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_IPROC=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_BRCMSTB=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_BCM63138=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BCM_UNIMAC=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_BRCM_U_BOOT=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_BRCMNAND_BCMBCA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_OF_PARTS_BCM4908=y +# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPLIT_CFE_BOOTFS=y +# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_BCM_SF2=y +CONFIG_NET_DSA_TAG_BRCM=y +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM_LEGACY=y +CONFIG_NET_DSA_TAG_BRCM_PREPEND=y +CONFIG_NET_DSA_TAG_NONE=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_BRCM_SATA is not set +CONFIG_PHY_BRCM_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_BCM4908=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RELOCATABLE=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB_SUPPORT=y +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch b/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch new file mode 100644 index 0000000000..d43d6d84f0 --- /dev/null +++ b/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch @@ -0,0 +1,31 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 28 Mar 2024 10:24:34 +0100 +Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set + brcm,wp-not-connected +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Every described BCM4908 board has WP pin not connected. This caused +problems for drivers since day 0 but there was no property to describe +that properly. Projects like OpenWrt were modifying Linux driver to deal +with it. + +It's not clear if that is hardware limitation or just reference design +being copied over and over but this applies to all known / supported +BCM4908 boards. Handle it by marking WP as not connected by default. + +Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +@@ -596,6 +596,7 @@ + reg-names = "nand", "nand-int-base"; + interrupts = ; + interrupt-names = "nand_ctlrdy"; ++ brcm,wp-not-connected; + status = "okay"; + + nandcs: nand@0 { diff --git a/target/linux/bcm4908/patches-5.15/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch b/target/linux/bcm4908/patches-5.15/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch deleted file mode 100644 index 65066236db..0000000000 --- a/target/linux/bcm4908/patches-5.15/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 21 Jan 2021 10:44:53 +0100 -Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 contains NAND controller version 0x0701 (v7.1). It means that -NAND_WP should be available. - -For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP -status bit: -[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0) -[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on - -For now try working without touching #WP. - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -38,7 +38,11 @@ - * 1: NAND_WP is set by default, cleared for erase/write operations - * 2: NAND_WP is always cleared - */ -+#if IS_ENABLED(CONFIG_ARCH_BCM4908) -+static int wp_on = 0; -+#else - static int wp_on = 1; -+#endif - module_param(wp_on, int, 0444); - - /*********************************************************************** diff --git a/target/linux/bcm4908/patches-6.1/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch b/target/linux/bcm4908/patches-6.1/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch new file mode 100644 index 0000000000..d43d6d84f0 --- /dev/null +++ b/target/linux/bcm4908/patches-6.1/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch @@ -0,0 +1,31 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 28 Mar 2024 10:24:34 +0100 +Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set + brcm,wp-not-connected +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Every described BCM4908 board has WP pin not connected. This caused +problems for drivers since day 0 but there was no property to describe +that properly. Projects like OpenWrt were modifying Linux driver to deal +with it. + +It's not clear if that is hardware limitation or just reference design +being copied over and over but this applies to all known / supported +BCM4908 boards. Handle it by marking WP as not connected by default. + +Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +@@ -596,6 +596,7 @@ + reg-names = "nand", "nand-int-base"; + interrupts = ; + interrupt-names = "nand_ctlrdy"; ++ brcm,wp-not-connected; + status = "okay"; + + nandcs: nand@0 { diff --git a/target/linux/bcm4908/patches-6.1/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch b/target/linux/bcm4908/patches-6.1/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch deleted file mode 100644 index ce20a5526b..0000000000 --- a/target/linux/bcm4908/patches-6.1/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 21 Jan 2021 10:44:53 +0100 -Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 contains NAND controller version 0x0701 (v7.1). It means that -NAND_WP should be available. - -For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP -status bit: -[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0) -[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on - -For now try working without touching #WP. - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -39,7 +39,11 @@ - * 1: NAND_WP is set by default, cleared for erase/write operations - * 2: NAND_WP is always cleared - */ -+#if IS_ENABLED(CONFIG_ARCH_BCMBCA) -+static int wp_on = 0; -+#else - static int wp_on = 1; -+#endif - module_param(wp_on, int, 0444); - - /*********************************************************************** diff --git a/target/linux/bcm4908/patches-6.6/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch b/target/linux/bcm4908/patches-6.6/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch new file mode 100644 index 0000000000..442a71fc8f --- /dev/null +++ b/target/linux/bcm4908/patches-6.6/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch @@ -0,0 +1,31 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 28 Mar 2024 10:24:34 +0100 +Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set + brcm,wp-not-connected +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Every described BCM4908 board has WP pin not connected. This caused +problems for drivers since day 0 but there was no property to describe +that properly. Projects like OpenWrt were modifying Linux driver to deal +with it. + +It's not clear if that is hardware limitation or just reference design +being copied over and over but this applies to all known / supported +BCM4908 boards. Handle it by marking WP as not connected by default. + +Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +@@ -597,6 +597,7 @@ + reg-names = "nand", "nand-int-base"; + interrupts = ; + interrupt-names = "nand_ctlrdy"; ++ brcm,wp-not-connected; + status = "okay"; + + nandcs: nand@0 { diff --git a/target/linux/bcm4908/patches-6.6/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch b/target/linux/bcm4908/patches-6.6/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch new file mode 100644 index 0000000000..6fd7d92233 --- /dev/null +++ b/target/linux/bcm4908/patches-6.6/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch @@ -0,0 +1,23 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 Feb 2021 22:01:03 +0100 +Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Linux driver can't handle more than 64 GPIOs + +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +@@ -344,7 +344,7 @@ + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; +- reg = <0x500 0x28>, <0x528 0x28>; ++ reg = <0x500 0x8>, <0x528 0x8>; + + #gpio-cells = <2>; + gpio-controller; diff --git a/target/linux/bcm4908/patches-6.6/301-arm64-don-t-issue-HVC-on-boot.patch b/target/linux/bcm4908/patches-6.6/301-arm64-don-t-issue-HVC-on-boot.patch new file mode 100644 index 0000000000..be1b4a0e4d --- /dev/null +++ b/target/linux/bcm4908/patches-6.6/301-arm64-don-t-issue-HVC-on-boot.patch @@ -0,0 +1,30 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 12 Aug 2021 11:52:42 +0200 +Subject: [PATCH] arm64: don't issue HVC on boot +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Broadcom's CFE loader seems to miss setting SCR_EL3.HCE which results in +generating an UNDEF and kernel panic on the first HVC. + +HVC gets issued by kernels 5.12+ while booting, by kexec and KVM. Until +someone finds a workaround we have to avoid all above. + +Workarounds: 0c93df9622d4 ("arm64: Initialise as nVHE before switching to VHE") +Signed-off-by: Rafał Miłecki +--- + arch/arm64/kernel/hyp-stub.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/kernel/hyp-stub.S ++++ b/arch/arm64/kernel/hyp-stub.S +@@ -252,7 +252,7 @@ SYM_FUNC_START(finalise_el2) + b.ne 1f + + mov x0, #HVC_FINALISE_EL2 +- hvc #0 ++// hvc #0 + 1: + ret + SYM_FUNC_END(finalise_el2) diff --git a/target/linux/bcm4908/patches-6.6/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch b/target/linux/bcm4908/patches-6.6/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch new file mode 100644 index 0000000000..cf089fec61 --- /dev/null +++ b/target/linux/bcm4908/patches-6.6/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch @@ -0,0 +1,46 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 Feb 2021 23:59:26 +0100 +Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +GPHY needs to be enabled to succesfully probe & setup switch port +connected to it. Otherwise hardcoding PHY OUI would be required. + +Before: +brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7 + +After: +brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL) +brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL) + +Signed-off-by: Rafał Miłecki +--- + drivers/net/dsa/bcm_sf2.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/dsa/bcm_sf2.c ++++ b/drivers/net/dsa/bcm_sf2.c +@@ -1522,10 +1522,14 @@ static int bcm_sf2_sw_probe(struct platf + rev = reg_readl(priv, REG_PHY_REVISION); + priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; + ++ bcm_sf2_gphy_enable_set(priv->dev->ds, true); ++ + ret = b53_switch_register(dev); + if (ret) + goto out_mdio; + ++ bcm_sf2_gphy_enable_set(priv->dev->ds, false); ++ + dev_info(&pdev->dev, + "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", + priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, diff --git a/target/linux/bcm4908/patches-6.6/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch b/target/linux/bcm4908/patches-6.6/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch new file mode 100644 index 0000000000..865eac729a --- /dev/null +++ b/target/linux/bcm4908/patches-6.6/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch @@ -0,0 +1,30 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Feb 2021 00:06:35 +0100 +Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908 + +Trying to access disabled PHY results in MDIO_READ_FAIL and: +[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode +[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan +[ 11.980205] ------------[ cut here ]------------ +[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58 + +Signed-off-by: Rafał Miłecki +--- + drivers/net/dsa/bcm_sf2.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/dsa/bcm_sf2.c ++++ b/drivers/net/dsa/bcm_sf2.c +@@ -1536,6 +1536,12 @@ static int bcm_sf2_sw_probe(struct platf + priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, + priv->irq0, priv->irq1); + ++ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable ++ * GPHY when needed. Leave it enabled here. ++ */ ++ if (priv->type == BCM4908_DEVICE_ID) ++ bcm_sf2_gphy_enable_set(priv->dev->ds, true); ++ + return 0; + + out_mdio: diff --git a/target/linux/bcm53xx/Makefile b/target/linux/bcm53xx/Makefile index 84f08f1f80..5b778454fa 100644 --- a/target/linux/bcm53xx/Makefile +++ b/target/linux/bcm53xx/Makefile @@ -11,8 +11,8 @@ FEATURES:=squashfs nand usb pci pcie gpio pwm CPU_TYPE:=cortex-a9 SUBTARGETS:=generic -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 define Target/Description Build firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS. diff --git a/target/linux/bcm53xx/config-6.1 b/target/linux/bcm53xx/config-6.1 index fba523175a..259c6559a6 100644 --- a/target/linux/bcm53xx/config-6.1 +++ b/target/linux/bcm53xx/config-6.1 @@ -134,6 +134,7 @@ CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -236,6 +237,7 @@ CONFIG_NET_SWITCHDEV=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y CONFIG_NVMEM_BRCM_NVRAM=y +CONFIG_NVMEM_LAYOUTS=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y @@ -263,6 +265,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y # CONFIG_PHY_BCM_NS_USB2 is not set # CONFIG_PHY_BCM_NS_USB3 is not set diff --git a/target/linux/airoha/config-5.15 b/target/linux/bcm53xx/config-6.6 similarity index 53% rename from target/linux/airoha/config-5.15 rename to target/linux/bcm53xx/config-6.6 index 259ab03521..37088eb101 100644 --- a/target/linux/airoha/config-5.15 +++ b/target/linux/bcm53xx/config-6.6 @@ -1,56 +1,88 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_AIROHA=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM_5301X=y +CONFIG_ARCH_BCM_53573=y +CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MULTIPLATFORM=y CONFIG_ARCH_MULTI_V6_V7=y CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1 +CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_ARM_HEAVY_MB=y -# CONFIG_ARM_HIGHBANK_CPUIDLE is not set CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_ARM_PATCH_IDIV=y CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SMMU is not set CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y CONFIG_ATAGS=y CONFIG_AUTO_ZRELADDR=y +CONFIG_B53=y +CONFIG_B53_MDIO_DRIVER=y +CONFIG_B53_SRAB_DRIVER=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_BCM47XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_DEBUG=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_FALLBACK_SPROM=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_SFLASH=y +# CONFIG_BCM_CYGNUS_PHY is not set +CONFIG_BCM_NET_PHYLIB=y +CONFIG_BCM_NS_THERMAL=y +CONFIG_BCM_SR_THERMAL=y +CONFIG_BGMAC=y +CONFIG_BGMAC_BCMA=y +# CONFIG_BGMAC_PLATFORM is not set CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BOUNCE=y +CONFIG_BROADCOM_PHY=y CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y +CONFIG_CLKSRC_MMIO=y +# CONFIG_CLK_BCM_NS2 is not set +CONFIG_CLK_BCM_NSP=y +# CONFIG_CLK_BCM_SR is not set CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_EN7523=y +CONFIG_COMMON_CLK_IPROC=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y @@ -60,10 +92,8 @@ CONFIG_CPU_COPY_V6=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_SPECTRE=y CONFIG_CPU_THUMB_CAPABLE=y @@ -73,21 +103,40 @@ CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_BCM_5301X=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" CONFIG_DEBUG_MISC=y +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=0 +CONFIG_DEBUG_UART_PHYS=0x18000300 +CONFIG_DEBUG_UART_VIRT=0xf1000300 +CONFIG_DEBUG_USER=y CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXTCON=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -99,13 +148,10 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y @@ -118,65 +164,88 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_BCM_XGS_IPROC=y CONFIG_GPIO_CDEV=y -CONFIG_GPIO_EN7523=y CONFIG_GPIO_GENERIC=y -CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_GRO_CELLS=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_BCM2835=y CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_LEDS_BCM63138 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BCM_IPROC=y CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set +CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y CONFIG_MIGRATION=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_BCM47XXSFLASH=y +CONFIG_MTD_BCM47XX_PARTS=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_BRCMNAND_IPROC=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_OF_PARTS_LINKSYS_NS=y +CONFIG_MTD_PARSER_TPLINK_SAFELOADER=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SPLIT_SEAMA_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_BRCM=y +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM_LEGACY=y +CONFIG_NET_DSA_TAG_BRCM_PREPEND=y +CONFIG_NET_DSA_TAG_NONE=y +CONFIG_NET_EGRESS=y CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y +CONFIG_NVMEM_BRCM_NVRAM=y +CONFIG_NVMEM_LAYOUTS=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y @@ -192,56 +261,67 @@ CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_PADATA=y CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PARTITION_PERCPU=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y +CONFIG_PCIE_IPROC=y +CONFIG_PCIE_IPROC_BCMA=y +# CONFIG_PCIE_IPROC_PLATFORM is not set CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_BCM_NS_USB2 is not set +# CONFIG_PHY_BCM_NS_USB3 is not set +# CONFIG_PHY_BCM_SR_PCIE is not set +CONFIG_PHY_BCM_SR_USB=y +# CONFIG_PHY_BRCM_SATA is not set +# CONFIG_PHY_NS2_USB_DRD is not set CONFIG_PINCTRL=y -CONFIG_PM=y -CONFIG_PM_CLK=y +# CONFIG_PINCTRL_IPROC_GPIO is not set +CONFIG_PINCTRL_NS=y +# CONFIG_PINCTRL_NS2_MUX is not set +CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y +CONFIG_PWM_BCM_IPROC=y CONFIG_PWM_SYSFS=y -CONFIG_RAS=y +CONFIG_RANDSTRUCT_NONE=y CONFIG_RATIONAL=y CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y CONFIG_RFS_ACCEL=y CONFIG_RPS=y CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_FSL=y -# CONFIG_SERIAL_8250_SHARE_IRQ is not set CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y -CONFIG_SPI_AIROHA_EN7523=y +CONFIG_SPI_BCM_QSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y CONFIG_SWPHY=y CONFIG_SWP_EMULATE=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y @@ -250,22 +330,18 @@ CONFIG_TREE_SRCU=y CONFIG_UBIFS_FS=y CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USE_OF=y # CONFIG_VFP is not set CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_XPS=y CONFIG_XXHASH=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/bcm53xx/image/Makefile b/target/linux/bcm53xx/image/Makefile index f336ce01ec..42cbc7a2c1 100644 --- a/target/linux/bcm53xx/image/Makefile +++ b/target/linux/bcm53xx/image/Makefile @@ -127,6 +127,12 @@ define Build/dwl8610ap-image mv $@.new $@ endef +ifneq ($(KERNEL),5.15) +ifneq ($(KERNEL),6.1) +DTS_DIR := $(DTS_DIR)/broadcom +endif +endif + DEVICE_VARS += ASUS_PRODUCTID DEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR DEVICE_VARS += SIGNATURE diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0001-ARM-dts-BCM5301X-Set-MACs-for-D-Link-DIR-885L.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0001-ARM-dts-BCM5301X-Set-MACs-for-D-Link-DIR-885L.patch new file mode 100644 index 0000000000..707e4a31e9 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0001-ARM-dts-BCM5301X-Set-MACs-for-D-Link-DIR-885L.patch @@ -0,0 +1,56 @@ +From 5cbee5828219c4f7b33e96b5d8ce5e467b2857c8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 1 Sep 2023 12:55:49 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Set MACs for D-Link DIR-885L +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Specify NVRAM access and use its "et2macaddr" NVMEM cell. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230901105549.7076-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../dts/broadcom/bcm47094-dlink-dir-885l.dts | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts +@@ -25,6 +25,15 @@ + <0x88000000 0x08000000>; + }; + ++ nvram@1e3f0000 { ++ compatible = "brcm,nvram"; ++ reg = <0x1e3f0000 0x10000>; ++ ++ et2macaddr: et2macaddr { ++ #nvmem-cell-cells = <1>; ++ }; ++ }; ++ + nand_controller: nand-controller@18028000 { + nand@0 { + partitions { +@@ -112,6 +121,11 @@ + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + ++&gmac0 { ++ nvmem-cells = <&et2macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &spi_nor { + status = "okay"; + }; +@@ -142,6 +156,8 @@ + + port@4 { + label = "wan"; ++ nvmem-cells = <&et2macaddr 3>; ++ nvmem-cell-names = "mac-address"; + }; + + port@5 { diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0002-ARM-dts-BCM5301X-Set-MAC-address-for-Asus-RT-AC87U.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0002-ARM-dts-BCM5301X-Set-MAC-address-for-Asus-RT-AC87U.patch new file mode 100644 index 0000000000..8a8066ba63 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0002-ARM-dts-BCM5301X-Set-MAC-address-for-Asus-RT-AC87U.patch @@ -0,0 +1,44 @@ +From a9e79863b62aaaefcdf469fc331bf482ae00db0d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 1 Sep 2023 14:43:11 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Specify NVRAM access and use its "et1macaddr" NVMEM cell. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20230901124311.31156-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts +@@ -25,6 +25,12 @@ + <0x88000000 0x08000000>; + }; + ++ nvram@1c080000 { ++ et1macaddr: et1macaddr { ++ #nvmem-cell-cells = <1>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -62,6 +68,11 @@ + }; + }; + ++&gmac0 { ++ nvmem-cells = <&et1macaddr 0>; ++ nvmem-cell-names = "mac-address"; ++}; ++ + &usb3_phy { + status = "okay"; + }; diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0003-ARM-dts-BCM5301X-Relicense-Felix-s-code-to-the-GPL-2.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0003-ARM-dts-BCM5301X-Relicense-Felix-s-code-to-the-GPL-2.patch new file mode 100644 index 0000000000..842f47af42 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0003-ARM-dts-BCM5301X-Relicense-Felix-s-code-to-the-GPL-2.patch @@ -0,0 +1,57 @@ +From 81ea360a16978a4df61df9db56b171909bd659c0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 16 Sep 2023 10:30:57 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / + MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move code added by Felix to the bcm-ns.dtsi which uses dual licensing. +That syncs more Northstar code to be based on the same licensing schema. + +This code was added in the commit 1ff80363524c ("ARM: BCM5301X: Add +profiling support"). + +Cc: Felix Fietkau +Signed-off-by: Rafał Miłecki +Acked-by: Felix Fietkau +Link: https://lore.kernel.org/r/20230916083057.10458-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 7 +++++++ + arch/arm/boot/dts/broadcom/bcm5301x.dtsi | 7 ------- + 2 files changed, 7 insertions(+), 7 deletions(-) + +--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +@@ -14,6 +14,13 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = ++ , ++ ; ++ }; ++ + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; +--- a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi +@@ -26,13 +26,6 @@ + }; + }; + +- pmu { +- compatible = "arm,cortex-a9-pmu"; +- interrupts = +- , +- ; +- }; +- + clocks { + #address-cells = <1>; + #size-cells = <1>; diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0004-ARM-dts-BCM5301X-Relicense-Vivek-s-code-to-the-GPL-2.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0004-ARM-dts-BCM5301X-Relicense-Vivek-s-code-to-the-GPL-2.patch new file mode 100644 index 0000000000..960908100e --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0004-ARM-dts-BCM5301X-Relicense-Vivek-s-code-to-the-GPL-2.patch @@ -0,0 +1,104 @@ +From b8d4f7c1be04d66c37c119c501c87bccc4197694 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 16 Sep 2023 10:58:55 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / + MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move code added by Vivek to the bcm-ns.dtsi which uses dual licensing. +That syncs more Northstar code to be based on the same licensing schema. + +This code was added in the commit 37f6130ec39f ("ARM: dts: BCM5301X: +Make USB 3.0 PHY use MDIO PHY driver"). + +Cc: Vivek Unune +Signed-off-by: Rafał Miłecki +Acked-by: Vivek Unune +Link: https://lore.kernel.org/r/20230916085855.28375-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 27 ++++++++++++++++++++++++ + arch/arm/boot/dts/broadcom/bcm5301x.dtsi | 27 ------------------------ + 2 files changed, 27 insertions(+), 27 deletions(-) + +--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +@@ -327,6 +327,29 @@ + #address-cells = <1>; + }; + ++ mdio-mux@18003000 { ++ compatible = "mdio-mux-mmioreg", "mdio-mux"; ++ mdio-parent-bus = <&mdio>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x18003000 0x4>; ++ mux-mask = <0x200>; ++ ++ mdio@0 { ++ reg = <0x0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb3_phy: usb3-phy@10 { ++ compatible = "brcm,ns-ax-usb3-phy"; ++ reg = <0x10>; ++ usb3-dmp-syscon = <&usb3_dmp>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; +@@ -467,6 +490,10 @@ + brcm,nand-has-wp; + }; + ++ usb3_dmp: syscon@18105000 { ++ reg = <0x18105000 0x1000>; ++ }; ++ + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; +--- a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi +@@ -62,33 +62,6 @@ + }; + }; + +- mdio-mux@18003000 { +- compatible = "mdio-mux-mmioreg", "mdio-mux"; +- mdio-parent-bus = <&mdio>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x18003000 0x4>; +- mux-mask = <0x200>; +- +- mdio@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- usb3_phy: usb3-phy@10 { +- compatible = "brcm,ns-ax-usb3-phy"; +- reg = <0x10>; +- usb3-dmp-syscon = <&usb3_dmp>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- usb3_dmp: syscon@18105000 { +- reg = <0x18105000 0x1000>; +- }; +- + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0005-ARM-dts-BCM5301X-Explicitly-disable-unused-switch-CP.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0005-ARM-dts-BCM5301X-Explicitly-disable-unused-switch-CP.patch new file mode 100644 index 0000000000..28f4d2b743 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0005-ARM-dts-BCM5301X-Explicitly-disable-unused-switch-CP.patch @@ -0,0 +1,377 @@ +From 473baeab929444295b0530f8766e4becb6a08973 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 13 Oct 2023 12:33:13 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Explicitly disable unused switch CPU + ports +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When redescribing ports I assumed that missing "label" (like "cpu") +means switch port isn't used. That was incorrect and I realized my +change made Linux always use the first (5) CPU port (there are 3 of +them). + +While above should technically be possible it often isn't correct: +1. Non-default switch ports are often connected to Ethernet interfaces + not fully covered by vendor setup (they may miss MACs) +2. On some devices non-default ports require specifying fixed link + +This fixes network connectivity for some devices. It was reported & +tested for Netgear R8000. It also affects Linksys EA9200 with its +downstream DTS. + +Fixes: ba4aebce23b2 ("ARM: dts: BCM5301X: Describe switch ports in the main DTS") +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20231013103314.10306-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts | 8 ++++++++ + .../boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts | 8 ++++++++ + arch/arm/boot/dts/broadcom/bcm953012er.dts | 8 ++++++++ + 20 files changed, 160 insertions(+) + +--- a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi +@@ -189,5 +189,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts +@@ -93,5 +93,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts +@@ -96,5 +96,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts +@@ -130,5 +130,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts +@@ -153,6 +153,14 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts +@@ -153,5 +153,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts +@@ -89,5 +89,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts +@@ -156,5 +156,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts +@@ -235,6 +235,14 @@ + status = "disabled"; + }; + ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ + port@8 { + label = "cpu"; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts +@@ -168,6 +168,14 @@ + status = "disabled"; + }; + ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ + port@8 { + label = "cpu"; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts +@@ -200,6 +200,14 @@ + status = "disabled"; + }; + ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ + port@8 { + label = "cpu"; + phy-mode = "rgmii"; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts +@@ -115,5 +115,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts +@@ -128,5 +128,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts +@@ -115,5 +115,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts +@@ -83,5 +83,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts +@@ -155,5 +155,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts +@@ -166,5 +166,13 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts ++++ b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts +@@ -132,6 +132,14 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts +@@ -193,6 +193,14 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/broadcom/bcm953012er.dts ++++ b/arch/arm/boot/dts/broadcom/bcm953012er.dts +@@ -92,6 +92,14 @@ + port@8 { + status = "disabled"; + }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; + }; + }; + diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0006-ARM-dts-BCM5301X-Set-fixed-link-for-extra-Netgear-R8.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0006-ARM-dts-BCM5301X-Set-fixed-link-for-extra-Netgear-R8.patch new file mode 100644 index 0000000000..85f093ff0d --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0006-ARM-dts-BCM5301X-Set-fixed-link-for-extra-Netgear-R8.patch @@ -0,0 +1,47 @@ +From d313b0e9070a7100ca55e64fe3b081d176d8806d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 13 Oct 2023 12:33:14 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 + CPU ports +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Ports 5 and 7 are disabled by default because the standard use case is +for port 8 to manage all CPU directed traffic. For experimentation +purposes however it is desirable to provide adequate properties such +that people can experiment with using different ports without having to +figure out their configuration. Some of the use cases include but are +not limited to doubling or tripling the bandwidth by leveraging the +additional ports/Ethernet MAC combinations. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20231013103314.10306-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts +@@ -237,10 +237,20 @@ + + port@5 { + status = "disabled"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + + port@7 { + status = "disabled"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; + }; + + port@8 { diff --git a/target/linux/bcm53xx/patches-6.6/030-v6.7-0007-ARM-dts-BCM5301X-Set-switch-ports-for-Linksys-EA9200.patch b/target/linux/bcm53xx/patches-6.6/030-v6.7-0007-ARM-dts-BCM5301X-Set-switch-ports-for-Linksys-EA9200.patch new file mode 100644 index 0000000000..87b6ade5f6 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/030-v6.7-0007-ARM-dts-BCM5301X-Set-switch-ports-for-Linksys-EA9200.patch @@ -0,0 +1,63 @@ +From 253358f373492608348136e569366d73cb969f6a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 24 Oct 2023 09:26:05 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Set switch ports for Linksys EA9200 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch was developed as OpenWrt downstream change and was recently +confirmed to work as expected. + +Tested-by: Rani Hod +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20231024072605.32517-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli +--- + .../dts/broadcom/bcm4709-linksys-ea9200.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts +@@ -47,3 +47,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ label = "cpu"; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-6.6/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch b/target/linux/bcm53xx/patches-6.6/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch new file mode 100644 index 0000000000..e1933e75c7 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch @@ -0,0 +1,43 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 13 Apr 2021 18:25:20 +0200 +Subject: [PATCH] mtd: parsers: trx: parse "firmware" MTD partitions only +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Parsing every partition with "compatible" set to "brcm,trx" results in +parsing both: firmware partition and failsafe partition on devices that +implement failsafe booting. This affects e.g. Linksys EA9500 which has: + +partition@200000 { + reg = <0x0200000 0x01d00000>; + compatible = "linksys,ns-firmware", "brcm,trx"; +}; + +partition@1f00000 { + reg = <0x01f00000 0x01d00000>; + compatible = "linksys,ns-firmware", "brcm,trx"; +}; + +Check for MTD partition name "firmware" before parsing. Recently added +ofpart_linksys_ns.c creates "firmware" and "failsafe" depending on +bootloader setup. + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/parsers/parser_trx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/parsers/parser_trx.c ++++ b/drivers/mtd/parsers/parser_trx.c +@@ -92,6 +92,10 @@ static int parser_trx_parse(struct mtd_i + if (err != 0 && err != -EINVAL) + pr_err("failed to parse \"brcm,trx-magic\" DT attribute, using default: %d\n", err); + ++ /* Don't parse any failsafe / backup partitions */ ++ if (strcmp(mtd->name, "firmware")) ++ return -EINVAL; ++ + parts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition), + GFP_KERNEL); + if (!parts) diff --git a/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch new file mode 100644 index 0000000000..3b2a7a476a --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -0,0 +1,113 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 1 Oct 2016 22:54:48 +0200 +Subject: [PATCH] usb: xhci: add support for performing fake doorbell + +Broadcom's Northstar XHCI controllers seem to need a special start +procedure to work correctly. There isn't any official documentation of +this, the problem is that controller doesn't detect any connected +devices with default setup. Moreover connecting USB device to controller +that doesn't run properly can cause SoC's watchdog issues. + +A workaround that was successfully tested on multiple devices is to +perform a fake doorbell. This patch adds code for doing this and enables +it on BCM4708 family. +--- + drivers/usb/host/xhci-plat.c | 6 +++++ + drivers/usb/host/xhci.c | 63 +++++++++++++++++++++++++++++++++++++++++--- + drivers/usb/host/xhci.h | 1 + + 3 files changed, 67 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -77,8 +77,13 @@ static int xhci_priv_resume_quirk(struct + static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) + { + struct xhci_plat_priv *priv = xhci_to_priv(xhci); ++ struct platform_device*pdev = to_platform_device(dev); ++ struct device_node *node = pdev->dev.of_node; + + xhci->quirks |= priv->quirks; ++ ++ if (node && of_machine_is_compatible("brcm,bcm4708")) ++ xhci->quirks |= XHCI_FAKE_DOORBELL; + } + + /* called during probe() after chip reset completes */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -161,6 +161,49 @@ int xhci_start(struct xhci_hcd *xhci) + return ret; + } + ++/** ++ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot ++ * ++ * Some controllers require a fake doorbell to start correctly. Without that ++ * they simply don't detect any devices. ++ */ ++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) ++{ ++ u32 temp; ++ ++ /* Alloc a virt device for that slot */ ++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { ++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); ++ return -ENOMEM; ++ } ++ ++ /* Ring fake doorbell for slot_id ep 0 */ ++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); ++ usleep_range(1000, 1500); ++ ++ /* Read the status to check if HSE is set or not */ ++ temp = readl(&xhci->op_regs->status); ++ ++ /* Clear HSE if set */ ++ if (temp & STS_FATAL) { ++ xhci_dbg(xhci, "HSE problem detected, status: 0x%08x\n", temp); ++ temp &= ~0x1fff; ++ temp |= STS_FATAL; ++ writel(temp, &xhci->op_regs->status); ++ usleep_range(1000, 1500); ++ readl(&xhci->op_regs->status); ++ } ++ ++ /* Free virt device */ ++ xhci_free_virt_device(xhci, slot_id); ++ ++ /* We're done if controller is already running */ ++ if (readl(&xhci->op_regs->command) & CMD_RUN) ++ return 0; ++ ++ return xhci_start(xhci); ++} ++ + /* + * Reset a halted HC. + * +@@ -480,6 +523,15 @@ static int xhci_run_finished(struct xhci + return -ENODEV; + } + ++ if (xhci->quirks & XHCI_FAKE_DOORBELL) { ++ int err = xhci_fake_doorbell(xhci, 1); ++ if (err) { ++ xhci_halt(xhci); ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ return err; ++ } ++ } ++ + xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; + + if (xhci->quirks & XHCI_NEC_HOST) +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1907,6 +1907,7 @@ struct xhci_hcd { + #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) + #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) ++#define XHCI_FAKE_DOORBELL BIT_ULL(47) + + unsigned int num_active_eps; + unsigned int limit_active_eps; diff --git a/target/linux/bcm53xx/patches-6.6/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch b/target/linux/bcm53xx/patches-6.6/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch new file mode 100644 index 0000000000..0247a66ccc --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch @@ -0,0 +1,101 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 24 Sep 2014 22:14:07 +0200 +Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Broadcom devices have broken CFE (bootloader) that leaves hardware in an +invalid state. It causes problems with booting Linux. On Northstar +devices kernel was randomly hanging in ~25% of tries during early init. +Hangs used to happen at random places in the start_kernel. On BCM53573 +kernel doesn't even seem to start booting. + +To workaround this problem we need to do following very early: +1) Clear 2 following bits in the SCTLR register: +#define CR_M (1 << 0) /* MMU enable */ +#define CR_C (1 << 2) /* Dcache enable */ +2) Flush the whole D-cache +3) Disable L2 cache + +Unfortunately this patch is not upstreamable as it does above things +unconditionally. We can't check if we are running on Broadcom platform +in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable +as it could break other devices support. + +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -36,6 +36,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y) + OBJS += ll_char_wr.o font.o + endif + ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++OBJS += head-bcm_5301x-mpcore.o ++OBJS += cache-v7-min.o ++endif ++ + ifeq ($(CONFIG_ARCH_SA1100),y) + OBJS += head-sa1100.o + endif +--- /dev/null ++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +@@ -0,0 +1,37 @@ ++/* ++ * ++ * Platform specific tweaks. This is merged into head.S by the linker. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .section ".start", "ax" ++ ++/* ++ * This code section is spliced into the head code by the linker ++ */ ++ ++__plat_uncompress_start: ++ ++ @ Preserve r8/r7 i.e. kernel entry values ++ mov r12, r8 ++ ++ @ Clear MMU enable and Dcache enable bits ++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR ++ bic r0, #CR_C|CR_M ++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR ++ nop ++ ++ @ Call the cache invalidation routine ++ bl v7_flush_dcache_all ++ nop ++ mov r0,#0 ++ ldr r3, =0x19022000 @ L2 cache controller, control reg ++ str r0, [r3, #0x100] @ Disable L2 cache ++ nop ++ ++ @ Restore ++ mov r8, r12 +--- a/arch/arm/boot/compressed/cache-v7-min.S ++++ b/arch/arm/boot/compressed/cache-v7-min.S +@@ -12,6 +12,7 @@ + + #include + #include ++#include + + __INIT + +@@ -63,7 +64,7 @@ loop2: + ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 + THUMB( lsl r6, r9, r2 ) + THUMB( orr r11, r11, r6 ) @ factor index number into r11 +- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way ++ mcr p15, 0, r11, c7, c6, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way diff --git a/target/linux/bcm53xx/patches-6.6/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch b/target/linux/bcm53xx/patches-6.6/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch new file mode 100644 index 0000000000..9cfc3aac15 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch @@ -0,0 +1,675 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for remaining + devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts +@@ -92,3 +92,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts +@@ -83,3 +83,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts +@@ -149,3 +149,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts +@@ -46,3 +46,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts +@@ -43,3 +43,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts +@@ -86,3 +86,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts +@@ -77,3 +77,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts +@@ -77,6 +77,40 @@ + status = "okay"; + }; + ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ label = "cpu"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; ++ + &nandcs { + partitions { + compatible = "fixed-partitions"; +--- a/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts +@@ -130,3 +130,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts +@@ -104,3 +104,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts +@@ -94,3 +94,41 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ status = "disabled"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ label = "cpu"; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts +@@ -38,6 +38,40 @@ + status = "okay"; + }; + ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; ++ + &nandcs { + partitions { + compatible = "fixed-partitions"; +--- a/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts +@@ -91,6 +91,44 @@ + }; + }; + ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; ++ + &spi_nor { + status = "okay"; + +--- a/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts ++++ b/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts +@@ -100,6 +100,44 @@ + vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "wan"; ++ }; ++ ++ port@1 { ++ label = "lan1"; ++ }; ++ ++ port@2 { ++ label = "lan2"; ++ }; ++ ++ port@3 { ++ label = "lan3"; ++ }; ++ ++ port@4 { ++ label = "lan4"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; ++ + &spi_nor { + status = "okay"; + +--- a/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts +@@ -107,3 +107,42 @@ + &usb3_phy { + status = "okay"; + }; ++ ++&srab { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ label = "lan1"; ++ }; ++ ++ port@1 { ++ label = "lan2"; ++ }; ++ ++ port@2 { ++ label = "lan3"; ++ }; ++ ++ port@3 { ++ label = "lan4"; ++ }; ++ ++ port@4 { ++ label = "wan"; ++ }; ++ ++ port@5 { ++ label = "cpu"; ++ }; ++ ++ port@7 { ++ status = "disabled"; ++ }; ++ ++ port@8 { ++ status = "disabled"; ++ }; ++ }; ++}; ++ diff --git a/target/linux/bcm53xx/patches-6.6/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch b/target/linux/bcm53xx/patches-6.6/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch new file mode 100644 index 0000000000..053e5347d1 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch @@ -0,0 +1,64 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm/boot/dts/broadcom/Makefile ++++ b/arch/arm/boot/dts/broadcom/Makefile +@@ -68,6 +68,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-linksys-ea9200.dtb \ + bcm4709-netgear-r7000.dtb \ ++ bcm4709-netgear-r7900.dtb \ + bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ + bcm47094-asus-rt-ac3100.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7900.dts +@@ -0,0 +1,42 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Netgear R7900 ++ * ++ * Copyright (C) 2016 Rafał Miłecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4709.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "netgear,r7900", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Netgear R7900"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; ++ }; ++ ++ axi@18000000 { ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-6.6/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-6.6/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch new file mode 100644 index 0000000000..e6140d9a70 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch @@ -0,0 +1,59 @@ +From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 16 Oct 2014 20:52:16 +0200 +Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/ubi/attach.c | 5 +++++ + drivers/mtd/ubi/io.c | 4 ++++ + drivers/mtd/ubi/ubi.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -82,6 +82,9 @@ static int self_check_ai(struct ubi_devi + #define AV_ADD BIT(1) + #define AV_FIND_OR_ADD (AV_FIND | AV_ADD) + ++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ ++bool erase_all_next; ++ + /** + * find_or_add_av - internal function to find a volume, add a volume or do + * both (find and add if missing). +@@ -1580,6 +1583,8 @@ int ubi_attach(struct ubi_device *ubi, i + if (!ai) + return -ENOMEM; + ++ erase_all_next = false; ++ + #ifdef CONFIG_MTD_UBI_FASTMAP + /* On small flash devices we disable fastmap in any case. */ + if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { +--- a/drivers/mtd/ubi/io.c ++++ b/drivers/mtd/ubi/io.c +@@ -717,6 +717,10 @@ int ubi_io_read_ec_hdr(struct ubi_device + } + + magic = be32_to_cpu(ec_hdr->magic); ++ if (magic == 0xdeadc0de) ++ erase_all_next = true; ++ if (erase_all_next) ++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; + if (magic != UBI_EC_HDR_MAGIC) { + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex; + extern struct blocking_notifier_head ubi_notifiers; + + /* attach.c */ ++extern bool erase_all_next; + struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum, + int ec); + void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb); diff --git a/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch b/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch new file mode 100644 index 0000000000..9f6343c791 --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch @@ -0,0 +1,36 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 20 Jun 2022 10:01:18 +0200 +Subject: [PATCH] net: disable GRO by default +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In many cases GRO improves network performance however it comes at a +cost of chacksums calculations. In case of slow CPU and missing hardware +csum calculation support GRO can actually decrease network speed. + +On BCM4708 *disabling* GRO results in following NAT masquarade speed +changes: +1. 364 Mb/s → 396 Mb/s (packet steering disabled) +2. 341 Mb/s → 566 Mb/s (packet steering enabled) + +Signed-off-by: Rafał Miłecki +--- + include/linux/netdev_features.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/include/linux/netdev_features.h ++++ b/include/linux/netdev_features.h +@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu + #define NETIF_F_UPPER_DISABLES NETIF_F_LRO + + /* changeable features with no special hardware requirements */ +-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO) ++#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO) + + /* Changeable features with no special hardware requirements that defaults to off. */ +-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD) ++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO) + + #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ + NETIF_F_HW_VLAN_CTAG_RX | \ diff --git a/target/linux/bcm53xx/patches-6.6/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch b/target/linux/bcm53xx/patches-6.6/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch new file mode 100644 index 0000000000..3a2f4b06ed --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch @@ -0,0 +1,33 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 10 Jun 2022 13:10:47 +0200 +Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +bgmac allocates new replacement buffer before handling each received +frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU +time. Ideally bgmac should just respect currently set MTU but it isn't +the case right now. For now just revert back to the old limited frame +size. + +This change bumps NAT masquarade speed by ~95%. + +Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size") +Signed-off-by: Rafał Miłecki +--- + drivers/net/ethernet/broadcom/bgmac.h | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -328,8 +328,7 @@ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ + #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ + BGMAC_RX_FRAME_OFFSET) +-/* Jumbo frame size with FCS */ +-#define BGMAC_RX_MAX_FRAME_SIZE 9724 ++#define BGMAC_RX_MAX_FRAME_SIZE 1536 + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) + #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) diff --git a/target/linux/bcm53xx/patches-6.6/905-BCM53573-minor-hacks.patch b/target/linux/bcm53xx/patches-6.6/905-BCM53573-minor-hacks.patch new file mode 100644 index 0000000000..44573cb46a --- /dev/null +++ b/target/linux/bcm53xx/patches-6.6/905-BCM53573-minor-hacks.patch @@ -0,0 +1,80 @@ +From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 15 Aug 2016 10:30:41 +0200 +Subject: [PATCH] BCM53573 minor hacks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + +--- a/arch/arm/boot/dts/broadcom/bcm53573.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm53573.dtsi +@@ -54,6 +54,7 @@ + , + , + ; ++ clocks = <&ilp>; + }; + + clocks { +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -331,14 +331,6 @@ static int bcma_register_devices(struct + } + #endif + +-#ifdef CONFIG_BCMA_SFLASH +- if (bus->drv_cc.sflash.present) { +- err = platform_device_register(&bcma_sflash_dev); +- if (err) +- bcma_err(bus, "Error registering serial flash\n"); +- } +-#endif +- + #ifdef CONFIG_BCMA_NFLASH + if (bus->drv_cc.nflash.present) { + err = platform_device_register(&bcma_nflash_dev); +@@ -418,6 +410,14 @@ int bcma_bus_register(struct bcma_bus *b + bcma_register_core(bus, core); + } + ++#ifdef CONFIG_BCMA_SFLASH ++ if (bus->drv_cc.sflash.present) { ++ err = platform_device_register(&bcma_sflash_dev); ++ if (err) ++ bcma_err(bus, "Error registering serial flash\n"); ++ } ++#endif ++ + /* Try to get SPROM */ + err = bcma_sprom_get(bus); + if (err == -ENOENT) { +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1048,6 +1049,16 @@ static void __init arch_timer_of_configu + if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) + arch_timer_rate = rate; + ++ /* Get clk rate through clk driver if present */ ++ if (!arch_timer_rate) { ++ struct clk *clk = of_clk_get(np, 0); ++ ++ if (!IS_ERR(clk)) { ++ if (!clk_prepare_enable(clk)) ++ arch_timer_rate = clk_get_rate(clk); ++ } ++ } ++ + /* Check the timer frequency. */ + if (validate_timer_rate()) + pr_warn("frequency not available\n"); diff --git a/target/linux/generic/backport-5.15/411-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch b/target/linux/generic/backport-5.15/411-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch new file mode 100644 index 0000000000..dce2c91fd3 --- /dev/null +++ b/target/linux/generic/backport-5.15/411-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch @@ -0,0 +1,36 @@ +From 8e7daa85641c9559c113f6b217bdc923397de77c Mon Sep 17 00:00:00 2001 +From: William Zhang +Date: Thu, 22 Feb 2024 19:47:58 -0800 +Subject: [PATCH] mtd: rawnand: brcmnand: Support write protection setting from + dts + +The write protection feature is controlled by the module parameter wp_on +with default set to enabled. But not all the board use this feature +especially in BCMBCA broadband board. And module parameter is not +sufficient as different board can have different option. Add a device +tree property and allow this feature to be configured through the board +dts on per board basis. + +Signed-off-by: William Zhang +Reviewed-by: Florian Fainelli +Reviewed-by: Kamal Dasu +Reviewed-by: David Regan +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-william.zhang@broadcom.com +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -3184,6 +3184,10 @@ int brcmnand_probe(struct platform_devic + /* Disable XOR addressing */ + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); + ++ /* Check if the board connects the WP pin */ ++ if (of_property_read_bool(dn, "brcm,wp-not-connected")) ++ wp_on = 0; ++ + if (ctrl->features & BRCMNAND_HAS_WP) { + /* Permanently disable write protection */ + if (wp_on == 2) diff --git a/target/linux/generic/backport-6.1/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch b/target/linux/generic/backport-6.1/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch new file mode 100644 index 0000000000..ba01bac8d2 --- /dev/null +++ b/target/linux/generic/backport-6.1/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch @@ -0,0 +1,36 @@ +From 8e7daa85641c9559c113f6b217bdc923397de77c Mon Sep 17 00:00:00 2001 +From: William Zhang +Date: Thu, 22 Feb 2024 19:47:58 -0800 +Subject: [PATCH] mtd: rawnand: brcmnand: Support write protection setting from + dts + +The write protection feature is controlled by the module parameter wp_on +with default set to enabled. But not all the board use this feature +especially in BCMBCA broadband board. And module parameter is not +sufficient as different board can have different option. Add a device +tree property and allow this feature to be configured through the board +dts on per board basis. + +Signed-off-by: William Zhang +Reviewed-by: Florian Fainelli +Reviewed-by: Kamal Dasu +Reviewed-by: David Regan +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-william.zhang@broadcom.com +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -3188,6 +3188,10 @@ int brcmnand_probe(struct platform_devic + /* Disable XOR addressing */ + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); + ++ /* Check if the board connects the WP pin */ ++ if (of_property_read_bool(dn, "brcm,wp-not-connected")) ++ wp_on = 0; ++ + if (ctrl->features & BRCMNAND_HAS_WP) { + /* Permanently disable write protection */ + if (wp_on == 2) diff --git a/target/linux/generic/backport-6.6/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch b/target/linux/generic/backport-6.6/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch new file mode 100644 index 0000000000..257624164a --- /dev/null +++ b/target/linux/generic/backport-6.6/400-v6.9-mtd-rawnand-brcmnand-Support-write-protection-settin.patch @@ -0,0 +1,36 @@ +From 8e7daa85641c9559c113f6b217bdc923397de77c Mon Sep 17 00:00:00 2001 +From: William Zhang +Date: Thu, 22 Feb 2024 19:47:58 -0800 +Subject: [PATCH] mtd: rawnand: brcmnand: Support write protection setting from + dts + +The write protection feature is controlled by the module parameter wp_on +with default set to enabled. But not all the board use this feature +especially in BCMBCA broadband board. And module parameter is not +sufficient as different board can have different option. Add a device +tree property and allow this feature to be configured through the board +dts on per board basis. + +Signed-off-by: William Zhang +Reviewed-by: Florian Fainelli +Reviewed-by: Kamal Dasu +Reviewed-by: David Regan +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-william.zhang@broadcom.com +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -3189,6 +3189,10 @@ int brcmnand_probe(struct platform_devic + /* Disable XOR addressing */ + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); + ++ /* Check if the board connects the WP pin */ ++ if (of_property_read_bool(dn, "brcm,wp-not-connected")) ++ wp_on = 0; ++ + if (ctrl->features & BRCMNAND_HAS_WP) { + /* Permanently disable write protection */ + if (wp_on == 2) diff --git a/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch b/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch new file mode 100644 index 0000000000..d9d15a4048 --- /dev/null +++ b/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch @@ -0,0 +1,44 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 27 Mar 2024 23:18:51 +0100 +Subject: [PATCH] mtd: don't look for OTP legacy NVMEM cells if proper node + doesn't exist +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If node with "user-otp" / "factory-otp" compatible doesn't exist it's +important to prevent NVMEM core from looking for legacy NVMEM cells. +Otherwise it would look for them in the device node. + +This fixes treating NAND controller attached chips as NVMEM cell. +Problem example: +[ 0.410107] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xdc +[ 0.416531] nand: Macronix MX30LF4G18AC +[ 0.420409] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 +[ 0.428022] iproc_nand 18028000.nand-controller: detected 512MiB total, 128KiB blocks, 2KiB pages, 16B OOB, 8-bit, BCH-8 +[ 0.438991] Scanning device for bad blocks +(...) +[ 2.848418] nvmem user-otp1: nvmem: invalid reg on /nand-controller@18028000/nand@0 +[ 2.856126] iproc_nand 18028000.nand-controller: error -EINVAL: Failed to register OTP NVMEM device + +This long standing issue was exposed by the support for Macronix OTP. + +Reported-by: Christian Marangi +Fixes: 4b361cfa8624 ("mtd: core: add OTP nvmem provider support") +Fixes: e87161321a40 ("mtd: rawnand: macronix: OTP access for MX30LFxG18AC") +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/mtdcore.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -931,7 +931,7 @@ static struct nvmem_device *mtd_otp_nvme + config.name = compatible; + config.id = NVMEM_DEVID_AUTO; + config.owner = THIS_MODULE; +- config.add_legacy_fixed_of_cells = true; ++ config.add_legacy_fixed_of_cells = !!np; + config.type = NVMEM_TYPE_OTP; + config.root_only = true; + config.ignore_wp = true; diff --git a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts index dc8a218f51..0c1059b56e 100644 --- a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts +++ b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts @@ -137,14 +137,14 @@ conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = ; - bias-pull-up = ; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = ; - bias-pull-down = ; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ }; }; }; diff --git a/tools/xz/Makefile b/tools/xz/Makefile index a90cec86bf..b7b9429244 100644 --- a/tools/xz/Makefile +++ b/tools/xz/Makefile @@ -7,12 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=xz -PKG_VERSION:=5.4.6 +PKG_VERSION:=5.6.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=@SF/lzmautils \ - http://tukaani.org/xz -PKG_HASH:=913851b274e8e1d31781ec949f1c23e8dbcf0ecf6e73a2436dc21769dd3e6f49 +PKG_SOURCE_URL:=https://github.com/tukaani-project/xz/releases/download/v$(PKG_VERSION) +PKG_HASH:=d300422649a0124b1121630be559c890ceedf32667d7064b8128933166c217c8 PKG_CPE_ID:=cpe:/a:tukaani:xz HOST_BUILD_PARALLEL:=1