diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2bdf8c7e97..ba67b58f05 100644 --- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x7f000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, + <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0xbf000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, + <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c similarity index 84% rename from target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c rename to target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 457648c210..1917edda6b 100644 --- a/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -2,7 +2,7 @@ /* * Rockchip PCIE3.0 phy driver * - * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. */ #include @@ -20,10 +20,11 @@ /* Register for RK3568 */ #define GRF_PCIE30PHY_CON1 0x4 -#define GRF_PCIE30PHY_CON4 0x10 #define GRF_PCIE30PHY_CON6 0x18 #define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) #define GRF_PCIE30PHY_STATUS0 0x80 +#define GRF_PCIE30PHY_WR_EN (0xf << 16) #define SRAM_INIT_DONE(reg) (reg & BIT(14)) #define RK3568_BIFURCATION_LANE_0_1 BIT(0) @@ -62,10 +63,6 @@ struct rockchip_p3phy_ops { int (*phy_init)(struct rockchip_p3phy_priv *priv); }; -static u16 phy_fw[] = { - #include "p3phy.fw" -}; - static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); @@ -91,13 +88,12 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) struct phy *phy = priv->phy; bool bifurcation = false; int ret; - int i; u32 reg; /* Deassert PCIe PMA output clamp mode */ - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); - for (i = 0; i < priv->num_lanes; i++) { + for (int i = 0; i < priv->num_lanes; i++) { dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); if (priv->lanes[i] > 1) bifurcation = true; @@ -107,44 +103,25 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) if (bifurcation) { dev_info(&phy->dev, "bifurcation enabled\n"); regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, - (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); + GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1); regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, - BIT(15) | BIT(31)); + GRF_PCIE30PHY_DA_OCM); } else { - dev_info(&phy->dev, "bifurcation disabled\n"); + dev_dbg(&phy->dev, "bifurcation disabled\n"); regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, - (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); + GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); } - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass - reset_control_deassert(priv->p30phy); ret = regmap_read_poll_timeout(priv->phy_grf, GRF_PCIE30PHY_STATUS0, reg, SRAM_INIT_DONE(reg), 0, 500); - if (ret) { + if (ret) dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", __func__, reg); - return ret; - } - - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, - (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram - for (i = 0; i < 8192; i++) - writel(phy_fw[i], priv->mmio + (i<<2)); - - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, - (0x0 << 8) | (0x3 << (8 + 16))); - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done - - dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n"); - return 0; + return ret; } static const struct rockchip_p3phy_ops rk3568_ops = { @@ -156,13 +133,12 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) u32 reg = 0; u8 mode = 0; int ret; - int i; /* Deassert PCIe PMA output clamp mode */ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); /* Set bifurcation if needed */ - for (i = 0; i < priv->num_lanes; i++) { + for (int i = 0; i < priv->num_lanes; i++) { if (!priv->lanes[i]) mode |= (BIT(i) << 3); @@ -201,8 +177,8 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) reg, RK3588_SRAM_INIT_DONE(reg), 0, 500); if (ret) - pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", - __func__, reg); + dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", + reg); return ret; } @@ -217,7 +193,7 @@ static int rochchip_p3phy_init(struct phy *phy) ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); if (ret) { - pr_err("failed to enable PCIe bulk clks %d\n", ret); + dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); return ret; } @@ -271,7 +247,7 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) priv->ops = of_device_get_match_data(&pdev->dev); if (!priv->ops) { - dev_err(&pdev->dev, "no of match data provided\n"); + dev_err(dev, "no of match data provided\n"); return -EINVAL; } diff --git a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch deleted file mode 100644 index 6513c17c38..0000000000 --- a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch +++ /dev/null @@ -1,174 +0,0 @@ -From: Frank Wunderlich -To: linux-rockchip@lists.infradead.org -Cc: Frank Wunderlich , - Kishon Vijay Abraham I , - Vinod Koul , Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Johan Jonker , - Yifeng Zhao , - Peter Geis , - Michael Riesch , - Liang Chen , Simon Xue , - Shawn Lin , - linux-phy@lists.infradead.org, devicetree@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org -Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes -Date: Sun, 19 Jun 2022 10:26:04 +0200 [thread overview] -Message-ID: <20220619082605.7935-5-linux@fw-web.de> (raw) -In-Reply-To: <20220619082605.7935-1-linux@fw-web.de> - -From: Frank Wunderlich - -Add nodes to rk356x devicetree to support PCIe v3. - -Co-developed-by: Peter Geis -Signed-off-by: Frank Wunderlich ---- -v4: -- update pcie3 reg/ranges - -v3: -- fix from Peter: change bus-range and msi-map, msi-map needs - to start from 0x0 - -v2: -- change to compatible with soc-part -- change rockchip,bifurcation to vendor unspecific bifurcation ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ - 1 file changed, 122 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -42,6 +42,128 @@ - reg = <0x0 0xfe190200 0x0 0x20>; - }; - -+ pcie30_phy_grf: syscon@fdcb8000 { -+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfdcb8000 0x0 0x10000>; -+ }; -+ -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie3x1: pcie@fe270000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, -+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, -+ <&cru CLK_PCIE30X1_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, -+ <0 0 0 2 &pcie3x1_intc 1>, -+ <0 0 0 3 &pcie3x1_intc 2>, -+ <0 0 0 4 &pcie3x1_intc 3>; -+ linux,pci-domain = <1>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x1000 0x1000>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0400000 0x0 0x00400000>, -+ <0x0 0xfe270000 0x0 0x00010000>, -+ <0x3 0x7f000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X1_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane1 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe280000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, -+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, -+ <&cru CLK_PCIE30X2_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <2>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x2000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0800000 0x0 0x00400000>, -+ <0x0 0xfe280000 0x0 0x00010000>, -+ <0x3 0xbf000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X2_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane0 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.15/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch b/target/linux/rockchip/patches-5.15/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch new file mode 100644 index 0000000000..b5a65fe646 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch @@ -0,0 +1,76 @@ +From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Mon, 11 Jul 2022 20:35:52 +0800 +Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init + +This fw fix some RX issue: +1. connect detect error; +2. transfer error in ssd huge data write(more than 10GB). + +Signed-off-by: Kever Yang +Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2 +--- + drivers/phy/phy-rockchip-snps-pcie3.c | 36 +- + drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++ + 2 files changed, 8225 insertions(+), 3 deletions(-) + create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw + +--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c ++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +@@ -20,6 +20,7 @@ + + /* Register for RK3568 */ + #define GRF_PCIE30PHY_CON1 0x4 ++#define GRF_PCIE30PHY_CON4 0x10 + #define GRF_PCIE30PHY_CON6 0x18 + #define GRF_PCIE30PHY_CON9 0x24 + #define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) +@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); + }; + ++static u16 phy_fw[] = { ++ #include "p3phy.fw" ++}; ++ + static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) + { + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); +@@ -112,16 +117,35 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) + GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); + } + ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, ++ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, ++ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass ++ + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); +- if (ret) ++ if (ret) { + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); +- return ret; ++ return ret; ++ } ++ ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, ++ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram ++ for (int i = 0; i < 8192; i++) ++ writel(phy_fw[i], priv->mmio + (i<<2)); ++ ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, ++ (0x0 << 8) | (0x3 << (8 + 16))); ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, ++ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done ++ ++ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n"); ++ return 0; + } + + static const struct rockchip_p3phy_ops rk3568_ops = {