From 9744bf7093be17cef23c37336759b82f1e76b7a8 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@immortalwrt.org>
Date: Fri, 17 May 2024 17:28:45 +0800
Subject: [PATCH] rockchip: configure ETH LED for FastRhino R66S/R68S

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 8d4ca6128839a1d93f301cedebbb308c5718f8c3)
---
 ...0-arm64-rockchip-add-OF-node-for-eth.patch | 87 ++++++++++++-------
 1 file changed, 58 insertions(+), 29 deletions(-)

diff --git a/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch
index 798f29a7cf..b3f2fb050d 100644
--- a/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch
+++ b/target/linux/rockchip/patches-5.15/610-arm64-rockchip-add-OF-node-for-eth.patch
@@ -101,6 +101,48 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +	};
  };
  
+ &pinctrl {
+--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+@@ -376,6 +376,19 @@
+ 	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00100000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_1: pcie-eth@10,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x200 0x2b 0x0 0x0>;
++		};
++	};
+ };
+ 
+ &pcie3x2 {
+@@ -383,6 +396,19 @@
+ 	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00200000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_2: pcie-eth@20,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x200 0x2b 0x0 0x0>;
++		};
++ 	};
+ };
+ 
  &pinctrl {
 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -128,42 +170,29 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	};
  };
  
-@@ -85,6 +88,35 @@
+@@ -85,6 +88,7 @@
  		reg = <0>;
  		pinctrl-0 = <&eth_phy1_reset_pin>;
  		pinctrl-names = "default";
 +		realtek,led-data = <0x6d60>;
-+	};
-+};
-+
-+&pcie3x1 {
-+	pcie@0,0 {
-+		reg = <0x00100000 0 0 0 0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+
-+		pcie-eth@10,0 {
-+			compatible = "pci10ec,8125";
-+			reg = <0x000000 0 0 0 0>;
-+			label = "eth3";
-+		};
-+	};
-+};
-+
-+&pcie3x2 {
-+	pcie@0,0 {
-+		reg = <0x00200000 0 0 0 0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+
-+		pcie-eth@20,0 {
-+			compatible = "pci10ec,8125";
-+			reg = <0x000000 0 0 0 0>;
-+			label = "eth2";
-+		};
  	};
  };
  
+@@ -102,6 +106,14 @@
+ 	};
+ };
+ 
++&rtl8125_1 {
++	label = "eth4";
++};
++
++&rtl8125_2 {
++	label = "eth3";
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
 @@ -72,6 +72,7 @@