From 0c161764c4a37feac1ec202c8abb2d37afc202b8 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 26 Jul 2024 00:23:08 +0200 Subject: [PATCH 01/19] kernel/zynq: Create kernel files for v6.6 (from v6.1) This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Mieczyslaw Nalewaj --- target/linux/zynq/{config-6.1 => config-6.6} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename target/linux/zynq/{config-6.1 => config-6.6} (100%) diff --git a/target/linux/zynq/config-6.1 b/target/linux/zynq/config-6.6 similarity index 100% rename from target/linux/zynq/config-6.1 rename to target/linux/zynq/config-6.6 From b7690e4bd5f1353e119fc1bd8a607ffc7996fc58 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 26 Jul 2024 00:23:15 +0200 Subject: [PATCH 02/19] kernel/zynq: Restore kernel files for v6.1 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Mieczyslaw Nalewaj --- target/linux/zynq/config-6.1 | 566 +++++++++++++++++++++++++++++++++++ 1 file changed, 566 insertions(+) create mode 100644 target/linux/zynq/config-6.1 diff --git a/target/linux/zynq/config-6.1 b/target/linux/zynq/config-6.1 new file mode 100644 index 0000000000..b6318a776c --- /dev/null +++ b/target/linux/zynq/config-6.1 @@ -0,0 +1,566 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ALTERA_FREEZE_BRIDGE is not set +# CONFIG_ALTERA_PR_IP_CORE is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=1024 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_SPC is not set +CONFIG_ARCH_ZYNQ=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2 +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_PL172_MPMC is not set +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_TIMER_SP804=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ARM_ZYNQ_CPUIDLE=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_AXI_DMAC is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CADENCE_TTC_TIMER=y +CONFIG_CADENCE_WATCHDOG=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_VERSATILE=y +CONFIG_CLK_ICST=y +CONFIG_CLK_SP810=y +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_SI570=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_NOMODESET=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_E1000E=y +CONFIG_EDAC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC_SYNOPSYS is not set +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FB=y +CONFIG_FB_CMDLINE=y +# CONFIG_FB_XILINX is not set +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=y +# CONFIG_FPGA_DFL is not set +# CONFIG_FPGA_MGR_ALTERA_CVP is not set +# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set +# CONFIG_FPGA_MGR_ICE40_SPI is not set +# CONFIG_FPGA_MGR_MACHXO2_SPI is not set +# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set +# CONFIG_FPGA_MGR_XILINX_SPI is not set +CONFIG_FPGA_MGR_ZYNQ_FPGA=y +CONFIG_FPGA_REGION=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_ZYNQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HID_MICROSOFT=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CADENCE=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_SPARSEKMAP=y +CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_VEXPRESS_SYSREG=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODULE_STRIPPED is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +# CONFIG_OF_FPGA_REGION is not set +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PCI=y +CONFIG_PCIE_XILINX=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_ZYNQ=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_PL330_DMA=y +# CONFIG_PL353_SMC is not set +CONFIG_PLAT_VERSATILE=y +CONFIG_PM=y +CONFIG_PMBUS=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PROC_EVENTS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_R8169=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VEXPRESS is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_ZYNQ=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SCHED_CORE is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_SENSORS_PMBUS=y +CONFIG_SENSORS_UCD9000=y +CONFIG_SENSORS_UCD9200=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_SERPORT=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQ_QSPI=y +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UIO=y +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_CIF is not set +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_PCI_GENERIC is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_SERCOS3 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_XILINX=y +CONFIG_USB_HID=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USE_OF=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VITESSE_PHY=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XILINX_EMACLITE=y +# CONFIG_XILINX_PR_DECOUPLER is not set +CONFIG_XILINX_WATCHDOG=y +CONFIG_XILINX_XADC=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y From f295d3fbceaad5a1c9d411a4dab895902c19277e Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 26 Jul 2024 02:15:53 +0200 Subject: [PATCH 03/19] zynq: refresh config-6.6 Refresh kernel config for Linux 6.6. Signed-off-by: Mieczyslaw Nalewaj --- target/linux/zynq/config-6.6 | 38 ++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/target/linux/zynq/config-6.6 b/target/linux/zynq/config-6.6 index b6318a776c..15716a12cd 100644 --- a/target/linux/zynq/config-6.6 +++ b/target/linux/zynq/config-6.6 @@ -8,11 +8,11 @@ CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MULTIPLATFORM=y CONFIG_ARCH_MULTI_V6_V7=y CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=1024 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y @@ -54,6 +54,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y CONFIG_BOUNCE=y +CONFIG_BUFFER_HEAD=y CONFIG_CACHE_L2X0=y CONFIG_CADENCE_TTC_TIMER=y CONFIG_CADENCE_WATCHDOG=y @@ -88,7 +89,6 @@ CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y CONFIG_CONTIG_ALLOC=y CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y @@ -113,6 +113,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_PABRT_V7=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y @@ -129,9 +130,9 @@ CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_INFO=y @@ -144,7 +145,6 @@ CONFIG_DMA_OPS=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DRM=y CONFIG_DRM_BRIDGE=y -CONFIG_DRM_NOMODESET=y CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_BRIDGE=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -165,7 +165,8 @@ CONFIG_EXT4_FS=y CONFIG_EXTCON=y CONFIG_F2FS_FS=y CONFIG_FB=y -CONFIG_FB_CMDLINE=y +CONFIG_FB_CORE=y +CONFIG_FB_IOMEM_FOPS=y # CONFIG_FB_XILINX is not set CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y @@ -176,6 +177,7 @@ CONFIG_FPGA_BRIDGE=y # CONFIG_FPGA_MGR_ALTERA_CVP is not set # CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set # CONFIG_FPGA_MGR_ICE40_SPI is not set +# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set # CONFIG_FPGA_MGR_MACHXO2_SPI is not set # CONFIG_FPGA_MGR_MICROCHIP_SPI is not set # CONFIG_FPGA_MGR_XILINX_SPI is not set @@ -184,12 +186,12 @@ CONFIG_FPGA_REGION=y CONFIG_FREEZER=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_GCC10_NO_ARRAY_BOUNDS=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -207,7 +209,6 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_SCHED_CLOCK=y @@ -226,19 +227,18 @@ CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y CONFIG_HAVE_SMP=y CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HID_MICROSOFT=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_HOTPLUG_CPU=y CONFIG_HWMON=y CONFIG_HW_CONSOLE=y CONFIG_HZ_FIXED=0 CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CADENCE=y CONFIG_I2C_CHARDEV=y @@ -263,6 +263,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_IOMMUFD is not set # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set @@ -293,7 +294,6 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LIBFDT=y @@ -308,7 +308,6 @@ CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y CONFIG_MEMORY=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_CORE=y @@ -323,6 +322,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_OF_ARASAN=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_STRIPPED is not set @@ -352,8 +352,11 @@ CONFIG_MTD_SPLIT_FIRMWARE=y # CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y CONFIG_NEON=y +CONFIG_NET_EGRESS=y CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y # CONFIG_NET_VENDOR_CIRRUS is not set @@ -366,6 +369,7 @@ CONFIG_NET_SELFTESTS=y # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_VIA is not set +CONFIG_NET_XGRESS=y CONFIG_NLS=y CONFIG_NLS_ASCII=y CONFIG_NLS_CODEPAGE_437=y @@ -397,14 +401,12 @@ CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_PAGE_POOL=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y # CONFIG_PARTITION_ADVANCED is not set CONFIG_PCI=y CONFIG_PCIE_XILINX=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y @@ -434,6 +436,7 @@ CONFIG_PROC_EVENTS=y CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_R8169=y +CONFIG_R8169_LEDS=y CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y @@ -478,9 +481,9 @@ CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_XILINX=y CONFIG_SPI_ZYNQ_QSPI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y CONFIG_SRAM=y CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y # CONFIG_STRIP_ASM_SYMS is not set CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y @@ -524,7 +527,6 @@ CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_TT_NEWSCHED is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_XILINX=y -CONFIG_USB_HID=y CONFIG_USB_NET_DRIVERS=y CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=y @@ -540,6 +542,8 @@ CONFIG_VFP=y CONFIG_VFPv3=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y CONFIG_VITESSE_PHY=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_VT=y From 0f093391ebf296b0acef6766a8a80ef2616ba241 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 26 Jul 2024 02:17:57 +0200 Subject: [PATCH 04/19] zynq: change location of zynq dts files Upstream change location of zynq dts files. Signed-off-by: Mieczyslaw Nalewaj --- target/linux/zynq/image/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/zynq/image/Makefile b/target/linux/zynq/image/Makefile index 0931871624..50301cf2a8 100644 --- a/target/linux/zynq/image/Makefile +++ b/target/linux/zynq/image/Makefile @@ -29,6 +29,9 @@ endef define Device/Default PROFILES := Default +ifdef CONFIG_LINUX_6_6 + DTS_DIR := $(DTS_DIR)/xilinx +endif DEVICE_DTS := $(lastword $(subst _, ,$(1))) KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) KERNEL_LOADADDR := 0x8000 From 7686ce4a9138b44943f927e97f2cbf8e111a5522 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 26 Jul 2024 02:19:46 +0200 Subject: [PATCH 05/19] zynq: enable 6.6 testing kernel The zynq now supports 6.6 kernel as testing. Signed-off-by: Mieczyslaw Nalewaj --- target/linux/zynq/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/zynq/Makefile b/target/linux/zynq/Makefile index 90e49df878..29995e43bf 100644 --- a/target/linux/zynq/Makefile +++ b/target/linux/zynq/Makefile @@ -19,6 +19,7 @@ define Target/Description endef KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk From 649bc715b2e8cce32e3cfad5057ccc70ee944937 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Jul 2024 08:38:25 +0900 Subject: [PATCH 06/19] rockchip: add support for Radxa ROCK Pi E v3.0 Radxa ROCK Pi E v3.0 is a compact networking SBC[1] using the Rockchip RK3328 SoC. Hardware -------- - Rockchip RK3328 SoC - Quad A53 CPU - 512MB/1GB/2GB DDR4 RAM - 4/8/16/32GB eMMC - Micro SD Card slot - WiFi 4 and BT 4, or WiFi 5 and BT 5 (not supported yet) - 1x 1000M Ethernet with PoE support (additional PoE HAT required) - 1x 100M Ethernet - 1x USB 3.0 Type-A port (Host) - 1x 4-ring 3.5mm headphone jack - 40 Pin GPIO header [1] https://radxa.com/products/rockpi/pie Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/15984 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-rockchip/Makefile | 8 + ...add-support-for-Radxa-ROCK-Pi-E-v3.0.patch | 248 ++++++++++++++++++ .../armv8/base-files/etc/board.d/02_network | 1 + target/linux/rockchip/image/armv8.mk | 9 + ...e-add-led-aliases-and-stop-heartbeat.patch | 27 ++ 5 files changed, 293 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch create mode 100644 target/linux/rockchip/patches-6.6/114-rock-pi-e-add-led-aliases-and-stop-heartbeat.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cf650cb82a..307fcff5f7 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -106,6 +106,13 @@ define U-Boot/rock-pi-e-rk3328 radxa_rock-pi-e endef +define U-Boot/rock-pi-e-v3-rk3328 + $(U-Boot/rk3328/Default) + NAME:=ROCK Pi E v3.0 + BUILD_DEVICES:= \ + radxa_rock-pi-e-v3 +endef + # RK3399 boards define U-Boot/rk3399/Default @@ -220,6 +227,7 @@ UBOOT_TARGETS := \ roc-cc-rk3328 \ rock64-rk3328 \ rock-pi-e-rk3328 \ + rock-pi-e-v3-rk3328 \ radxa-cm3-io-rk3566 \ bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ diff --git a/package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch b/package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch new file mode 100644 index 0000000000..515e07c3f8 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch @@ -0,0 +1,248 @@ +From 8ca5e0e4d6ed084d2321584e8cdc8105c60b9aa1 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Tue, 25 Jun 2024 05:45:29 +0900 +Subject: [PATCH] rockchip: add support for Radxa ROCK Pi E v3.0 + +ROCK Pi E v3.0 uses DDR4 SDRAM instead of DDR3 SDRAM used in v1.2x. + +prepare new rk3328-rock-pi-e-v3.dts in u-boot which just includes +upstream rk3328-rock-pi-e.dts. + +defconfig still uses + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" + +because v3.0 and prior are compatible. + +Suggested-by: Jonas Karlman +Signed-off-by: FUKAUMI Naoki +Reviewed-by: Kever Yang +--- + ...dtsi => rk3328-rock-pi-e-base-u-boot.dtsi} | 1 - + arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 47 +-------- + arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi | 4 + + arch/arm/dts/rk3328-rock-pi-e-v3.dts | 4 + + board/rockchip/evb_rk3328/MAINTAINERS | 4 +- + configs/rock-pi-e-v3-rk3328_defconfig | 97 +++++++++++++++++++ + 6 files changed, 111 insertions(+), 46 deletions(-) + copy arch/arm/dts/{rk3328-rock-pi-e-u-boot.dtsi => rk3328-rock-pi-e-base-u-boot.dtsi} (94%) + rewrite arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi (88%) + create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts + create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig + +--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi ++++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +@@ -1,43 +1,4 @@ + // SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2020 Radxa +- */ + +-#include "rk3328-u-boot.dtsi" ++#include "rk3328-rock-pi-e-base-u-boot.dtsi" + #include "rk3328-sdram-ddr3-666.dtsi" +- +-/ { +- smbios { +- compatible = "u-boot,sysinfo-smbios"; +- +- smbios { +- system { +- manufacturer = "radxa"; +- product = "rock-pi-e_rk3328"; +- }; +- +- baseboard { +- manufacturer = "radxa"; +- product = "rock-pi-e_rk3328"; +- }; +- +- chassis { +- manufacturer = "radxa"; +- product = "rock-pi-e_rk3328"; +- }; +- }; +- }; +-}; +- +-&u2phy_host { +- phy-supply = <&vcc_host_5v>; +-}; +- +-&vcc_host_5v { +- /delete-property/ regulator-always-on; +- /delete-property/ regulator-boot-on; +-}; +- +-&vcc_sd { +- bootph-pre-ram; +-}; +--- /dev/null ++++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi +@@ -0,0 +1,42 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 Radxa ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++ ++/ { ++ smbios { ++ compatible = "u-boot,sysinfo-smbios"; ++ ++ smbios { ++ system { ++ manufacturer = "radxa"; ++ product = "rock-pi-e_rk3328"; ++ }; ++ ++ baseboard { ++ manufacturer = "radxa"; ++ product = "rock-pi-e_rk3328"; ++ }; ++ ++ chassis { ++ manufacturer = "radxa"; ++ product = "rock-pi-e_rk3328"; ++ }; ++ }; ++ }; ++}; ++ ++&u2phy_host { ++ phy-supply = <&vcc_host_5v>; ++}; ++ ++&vcc_host_5v { ++ /delete-property/ regulator-always-on; ++ /delete-property/ regulator-boot-on; ++}; ++ ++&vcc_sd { ++ bootph-pre-ram; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi +@@ -0,0 +1,4 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "rk3328-rock-pi-e-base-u-boot.dtsi" ++#include "rk3328-sdram-ddr4-666.dtsi" +--- /dev/null ++++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts +@@ -0,0 +1,4 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include "rk3328-rock-pi-e.dts" +--- a/board/rockchip/evb_rk3328/MAINTAINERS ++++ b/board/rockchip/evb_rk3328/MAINTAINERS +@@ -64,5 +64,5 @@ M: Banglang Huang + S: Maintained + F: configs/rock-pi-e-rk3328_defconfig +-F: arch/arm/dts/rk3328-rock-pi-e.dts +-F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi ++F: configs/rock-pi-e-v3-rk3328_defconfig ++F: arch/arm/dts/rk3328-rock-pi-e* +--- /dev/null ++++ b/configs/rock-pi-e-v3-rk3328_defconfig +@@ -0,0 +1,97 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3" ++CONFIG_DM_RESET=y ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_POWER=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_TPL_DM=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_PHY_GIGE=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 8729bd52f2..f1192c9371 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -12,6 +12,7 @@ rockchip_setup_interfaces() friendlyarm,nanopi-r2s|\ friendlyarm,nanopi-r4s|\ friendlyarm,nanopi-r4s-enterprise|\ + radxa,rockpi-e|\ xunlong,orangepi-r1-plus|\ xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 23519b43ee..ff66cba939 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -139,6 +139,15 @@ define Device/radxa_rock-pi-e endef TARGET_DEVICES += radxa_rock-pi-e +define Device/radxa_rock-pi-e-v3 + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK Pi E v3.0 + SOC := rk3328 + DEVICE_DTS := rockchip/rk3328-rock-pi-e + DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis +endef +TARGET_DEVICES += radxa_rock-pi-e-v3 + define Device/radxa_rock-pi-s DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK Pi S diff --git a/target/linux/rockchip/patches-6.6/114-rock-pi-e-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/114-rock-pi-e-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..e2ea7fdd63 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/114-rock-pi-e-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,27 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +@@ -23,6 +23,10 @@ + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen { +@@ -55,10 +59,11 @@ + pinctrl-0 = <&led_pin>; + pinctrl-names = "default"; + +- led-0 { ++ led_blue: led-0 { + color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; + }; + }; + From fe9c99806f6c11d3bac5f5046253ecdabea62952 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Jul 2024 09:09:09 +0900 Subject: [PATCH 07/19] rockchip: drop redundant definitions for ROCK Pi S default values should be fine. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/16029 Signed-off-by: Hauke Mehrtens --- target/linux/rockchip/image/armv8.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index ff66cba939..2f0d6371dc 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -152,9 +152,7 @@ define Device/radxa_rock-pi-s DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK Pi S SOC := rk3308 - DEVICE_DTS := rockchip/rk3308-rock-pi-s BOOT_SCRIPT := rock-pi-s - UBOOT_DEVICE_NAME := rock-pi-s-rk3308 DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis endef TARGET_DEVICES += radxa_rock-pi-s From 249b949a26c1a3e39c06a64541c2460eab4c662e Mon Sep 17 00:00:00 2001 From: Mark Mentovai Date: Thu, 25 Jul 2024 13:10:24 -0400 Subject: [PATCH 08/19] kernel: rtl8366s: don't handle unsupported MMD register operations This is a backport of netdev/net [1]/[2], expected to be in kernel 6.11 (if not backported to a stable branch). Since 4fdc7bb8f13f (2024-06-14, switching ath79 from kernel 6.1 to 6.6), the rtl8366s driver was made to write to bogus PHY MII registers on ath79/netgear,wndr3800 and family, and likely on other systems using this switch in a similar manner. The writes were directed to PHY 4 MII registers 0x0d (13) and 0x0e (14). The rtl8366s data sheet claims these registers are reserved. These register writes were causing the device to not maintain link, track link status, or pass traffic on eth1 (labeled WAN), as eth1 is connected to PHY 4. 0x0d is MII_MMD_CTRL, and 0x0e is MII_MMD_DATA. rtl8366s doesn't appear to support MMD in any way, and certainly not via the IEEE 802.3 annex 22D "clause 45 over clause 22" protocol implemented by mmd_phy_indirect. This patch intercepts those attempted register accesses and returns -EOPNOTSUPP without touching the switch chip. This is implemented by defining phy_driver::{read,write}_mmd as genphy_{read,write}_mmd_unsupported for this PHY. A new PHY driver for this PHY is introduced to achieve that, because this PHY was previously using genphy_driver, and there is otherwise no clean way to declare lack of support for these operations. This was caused by kernel 9b01c885be36 (2023-02-13, in 6.3). The new genphy_c45_read_eee_abilities call in genphy_read_abilities (called during phy_probe) was causing an attempted MMD read of (MMIO_MMD_PCS, MDIO_PCS_EEE_ABLE), which was transformed into an annex 22D mmd_phy_indirect operation that performed MII register writes to MII_MMD_CTRL, MII_MMD_DATA, and MII_MMD_CTRL again, followed by another read from MII_MMD_DATA. This was enough to "scramble" the state of those two MII registers, which are in fact not used for annex 22D MMD register access on this device but are reserved and have some other function, rendering the PHY unusable while so configured. The result of the bungled MMD read attempt caused the genphy driver to incorrectly believe that the PHY supported standard EEE, which led to several more attempted MMD writes and reads, in turn being transformed into writes to these two MII registers. rtl8366s does support some pre-IEEE 802.3az EEE standard form of "Green Ethernet" which the switch driver (local to OpenWrt) already has some support for. No attempt is made to map the standard operations for this device. [1] https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=225990c487c1 [2] https://lore.kernel.org/netdev/20240725204147.69730-1-mark@mentovai.com/ Fixes: https://github.com/openwrt/openwrt/issues/15981 Link: https://github.com/openwrt/openwrt/issues/15739 Reported-by: Russell Senior Signed-off-by: Mark Mentovai Link: https://github.com/openwrt/openwrt/pull/16012 Signed-off-by: Hauke Mehrtens --- ...add-support-for-RTL8366S-Gigabit-PHY.patch | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 target/linux/generic/backport-6.6/719-v6.11-net-phy-realtek-add-support-for-RTL8366S-Gigabit-PHY.patch diff --git a/target/linux/generic/backport-6.6/719-v6.11-net-phy-realtek-add-support-for-RTL8366S-Gigabit-PHY.patch b/target/linux/generic/backport-6.6/719-v6.11-net-phy-realtek-add-support-for-RTL8366S-Gigabit-PHY.patch new file mode 100644 index 0000000000..f6bc97a60b --- /dev/null +++ b/target/linux/generic/backport-6.6/719-v6.11-net-phy-realtek-add-support-for-RTL8366S-Gigabit-PHY.patch @@ -0,0 +1,48 @@ +From 225990c487c1023e7b3aa89beb6a68011fbc0461 Mon Sep 17 00:00:00 2001 +From: Mark Mentovai +Date: Thu, 25 Jul 2024 16:41:44 -0400 +Subject: [PATCH] net: phy: realtek: add support for RTL8366S Gigabit PHY + +The PHY built in to the Realtek RTL8366S switch controller was +previously supported by genphy_driver. This PHY does not implement MMD +operations. Since commit 9b01c885be36 ("net: phy: c22: migrate to +genphy_c45_write_eee_adv()"), MMD register reads have been made during +phy_probe to determine EEE support. For genphy_driver, these reads are +transformed into 802.3 annex 22D clause 45-over-clause 22 +mmd_phy_indirect operations that perform MII register writes to +MII_MMD_CTRL and MII_MMD_DATA. This overwrites those two MII registers, +which on this PHY are reserved and have another function, rendering the +PHY unusable while so configured. + +Proper support for this PHY is restored by providing a phy_driver that +declares MMD operations as unsupported by using the helper functions +provided for that purpose, while remaining otherwise identical to +genphy_driver. + +Fixes: 9b01c885be36 ("net: phy: c22: migrate to genphy_c45_write_eee_adv()") +Reported-by: Russell Senior +Closes: https://github.com/openwrt/openwrt/issues/15981 +Link: https://github.com/openwrt/openwrt/issues/15739 +Signed-off-by: Mark Mentovai +Reviewed-by: Maxime Chevallier +Signed-off-by: David S. Miller +--- + drivers/net/phy/realtek.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -1083,6 +1083,13 @@ static struct phy_driver realtek_drvs[] + .handle_interrupt = genphy_handle_interrupt_no_ack, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ }, { ++ PHY_ID_MATCH_EXACT(0x001cc960), ++ .name = "RTL8366S Gigabit Ethernet", ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_mmd = genphy_read_mmd_unsupported, ++ .write_mmd = genphy_write_mmd_unsupported, + }, + }; + From a158e7ed4397ae0239c880f408cc12a89a3f18d8 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 30 Jul 2024 00:29:53 +0100 Subject: [PATCH 09/19] rockchip: only use HWRNG on RK3568 for now Testing turned out that the HWRNG quality varies greatly on RK3566, even on supposedly identical boards and SoC revisions. Hence enable the HWRNG driver only on RK3568 for now. Allow users to simply tune sample_count and quality to allow easily testing results on different boards and SoCs. Link: https://patchwork.kernel.org/project/linux-arm-kernel/cover/cover.1720969799.git.daniel@makrotopia.org/ Signed-off-by: Daniel Golle --- ...wrng-driver-for-Rockchip-RK3568-SoC.patch} | 188 +++++++----------- ...kchip-add-DT-entry-for-RNG-to-RK3568.patch | 49 +++++ ...kchip-add-DT-entry-for-RNG-to-RK356x.patch | 56 ------ 3 files changed, 118 insertions(+), 175 deletions(-) rename target/linux/rockchip/patches-6.6/{300-hwrng-add-Rockchip-SoC-hwrng-driver.patch => 300-hwrng-add-hwrng-driver-for-Rockchip-RK3568-SoC.patch} (57%) create mode 100644 target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK3568.patch delete mode 100644 target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch diff --git a/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.6/300-hwrng-add-hwrng-driver-for-Rockchip-RK3568-SoC.patch similarity index 57% rename from target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch rename to target/linux/rockchip/patches-6.6/300-hwrng-add-hwrng-driver-for-Rockchip-RK3568-SoC.patch index 0be9a7300b..683d1b1d5e 100644 --- a/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch +++ b/target/linux/rockchip/patches-6.6/300-hwrng-add-hwrng-driver-for-Rockchip-RK3568-SoC.patch @@ -1,56 +1,27 @@ -From patchwork Sat Nov 12 14:10:58 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Aurelien Jarno -X-Patchwork-Id: 13041222 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org +From cea47ad1fbd46d3096fcf5c6905db3d12b5da960 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno -To: Olivia Mackall , - Herbert Xu , - Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Lin Jinhan -Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR - CORE), - devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE - BINDINGS), - linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC - support), - linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), - linux-kernel@vger.kernel.org (open list), - Aurelien Jarno -Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver -Date: Sat, 12 Nov 2022 15:10:58 +0100 -Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net> -In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> -References: <20221112141059.3802506-1-aurelien@aurel32.net> -MIME-Version: 1.0 -List-Id: +Date: Sun, 21 Jul 2024 01:48:04 +0100 +Subject: [PATCH 2/3] hwrng: add hwrng driver for Rockchip RK3568 SoC Rockchip SoCs used to have a random number generator as part of their crypto device, and support for it has to be added to the corresponding -driver. However newer Rockchip SoCs like the RK356x have an independent +driver. However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patch adds a driver for it, greatly inspired from the downstream driver. The TRNG device does not seem to have a signal conditionner and the FIPS 140-2 test returns a lot of failures. They can be reduced by increasing -RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value -has been adjusted to get ~90% of successes and the quality value has -been set accordingly. +rockchip,sample-count in DT, in a tradeoff between quality and speed. Signed-off-by: Aurelien Jarno +[daniel@makrotpia.org: code style fixes, add DT properties] +Signed-off-by: Daniel Golle +Acked-by: Krzysztof Kozlowski --- drivers/char/hw_random/Kconfig | 14 ++ drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++ - 3 files changed, 266 insertions(+) + drivers/char/hw_random/rockchip-rng.c | 230 ++++++++++++++++++++++++++ + 4 files changed, 246 insertions(+) create mode 100644 drivers/char/hw_random/rockchip-rng.c --- a/drivers/char/hw_random/Kconfig @@ -60,18 +31,18 @@ Signed-off-by: Aurelien Jarno The module will be called jh7110-trng. +config HW_RANDOM_ROCKCHIP -+ tristate "Rockchip True Random Number Generator" -+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) -+ depends on HAS_IOMEM -+ default HW_RANDOM -+ help -+ This driver provides kernel-side support for the True Random Number -+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. ++ tristate "Rockchip True Random Number Generator" ++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) ++ depends on HAS_IOMEM ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the True Random Number ++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. + -+ To compile this driver as a module, choose M here: the -+ module will be called rockchip-rng. ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. + -+ If unsure, say Y. ++ If unsure, say Y. + endif # HW_RANDOM @@ -86,10 +57,10 @@ Signed-off-by: Aurelien Jarno obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o --- /dev/null +++ b/drivers/char/hw_random/rockchip-rng.c -@@ -0,0 +1,251 @@ +@@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* -+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs ++ * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC + * + * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2022, Aurelien Jarno @@ -103,7 +74,8 @@ Signed-off-by: Aurelien Jarno +#include +#include +#include -+#include ++#include ++#include +#include +#include +#include @@ -113,13 +85,6 @@ Signed-off-by: Aurelien Jarno +#define RK_RNG_POLL_PERIOD_US 100 +#define RK_RNG_POLL_TIMEOUT_US 10000 + -+/* -+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is -+ * a tradeoff between speed and quality and has been adjusted to get a quality -+ * of ~900 (~90% of FIPS 140-2 successes). -+ */ -+#define RK_RNG_SAMPLE_CNT 1000 -+ +/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ +#define TRNG_RST_CTL 0x0004 +#define TRNG_RNG_CTL 0x0400 @@ -131,17 +96,11 @@ Signed-off-by: Aurelien Jarno +#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) +#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) +#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) ++#define TRNG_RNG_CTL_MASK GENMASK(15, 0) +#define TRNG_RNG_CTL_ENABLE BIT(1) +#define TRNG_RNG_CTL_START BIT(0) +#define TRNG_RNG_SAMPLE_CNT 0x0404 -+#define TRNG_RNG_DOUT_0 0x0410 -+#define TRNG_RNG_DOUT_1 0x0414 -+#define TRNG_RNG_DOUT_2 0x0418 -+#define TRNG_RNG_DOUT_3 0x041c -+#define TRNG_RNG_DOUT_4 0x0420 -+#define TRNG_RNG_DOUT_5 0x0424 -+#define TRNG_RNG_DOUT_6 0x0428 -+#define TRNG_RNG_DOUT_7 0x042c ++#define TRNG_RNG_DOUT 0x0410 + +struct rk_rng { + struct hwrng rng; @@ -149,18 +108,18 @@ Signed-off-by: Aurelien Jarno + struct reset_control *rst; + int clk_num; + struct clk_bulk_data *clk_bulks; ++ u32 sample_cnt; +}; + -+/* The mask determine the bits that are updated */ ++/* The mask in the upper 16 bits determines the bits that are updated */ +static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) +{ -+ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL); ++ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL); +} + +static int rk_rng_init(struct hwrng *rng) +{ + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg; + int ret; + + /* start clocks */ @@ -172,13 +131,13 @@ Signed-off-by: Aurelien Jarno + } + + /* set the sample period */ -+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); ++ writel(rk_rng->sample_cnt, rk_rng->base + TRNG_RNG_SAMPLE_CNT); + + /* set osc ring speed and enable it */ -+ reg = TRNG_RNG_CTL_LEN_256_BIT | -+ TRNG_RNG_CTL_OSC_RING_SPEED_0 | -+ TRNG_RNG_CTL_ENABLE; -+ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT | ++ TRNG_RNG_CTL_OSC_RING_SPEED_0 | ++ TRNG_RNG_CTL_ENABLE, ++ TRNG_RNG_CTL_MASK); + + return 0; +} @@ -186,11 +145,9 @@ Signed-off-by: Aurelien Jarno +static void rk_rng_cleanup(struct hwrng *rng) +{ + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg; + + /* stop TRNG */ -+ reg = 0; -+ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK); + + /* stop clocks */ + clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); @@ -199,15 +156,16 @@ Signed-off-by: Aurelien Jarno +static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) +{ + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); + u32 reg; + int ret = 0; -+ int i; + -+ pm_runtime_get_sync((struct device *) rk_rng->rng.priv); ++ ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv); ++ if (ret < 0) ++ return ret; + + /* Start collecting random data */ -+ reg = TRNG_RNG_CTL_START; -+ rk_rng_write_ctl(rk_rng, reg, reg); ++ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START); + + ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, + !(reg & TRNG_RNG_CTL_START), @@ -216,27 +174,23 @@ Signed-off-by: Aurelien Jarno + if (ret < 0) + goto out; + -+ /* Read random data stored in big endian in the registers */ -+ ret = min_t(size_t, max, RK_RNG_MAX_BYTE); -+ for (i = 0; i < ret; i += 4) { -+ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i); -+ *(u32 *)(buf + i) = be32_to_cpu(reg); -+ } -+ ++ /* Read random data stored in the registers */ ++ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read); +out: + pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); + pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); + -+ return ret; ++ return (ret < 0) ? ret : to_read; +} + +static int rk_rng_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rk_rng *rk_rng; ++ u32 quality; + int ret; + -+ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL); ++ rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL); + if (!rk_rng) + return -ENOMEM; + @@ -249,11 +203,19 @@ Signed-off-by: Aurelien Jarno + return dev_err_probe(dev, rk_rng->clk_num, + "Failed to get clks property\n"); + -+ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); ++ rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(rk_rng->rst)) + return dev_err_probe(dev, PTR_ERR(rk_rng->rst), + "Failed to get reset property\n"); + ++ ret = of_property_read_u32(dev->of_node, "rockchip,sample-count", &rk_rng->sample_cnt); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to get sample-count property\n"); ++ ++ ret = of_property_read_u32(dev->of_node, "quality", &quality); ++ if (ret || quality > 1024) ++ return dev_err_probe(dev, ret, "Failed to get quality property\n"); ++ + reset_control_assert(rk_rng->rst); + udelay(2); + reset_control_deassert(rk_rng->rst); @@ -261,36 +223,26 @@ Signed-off-by: Aurelien Jarno + platform_set_drvdata(pdev, rk_rng); + + rk_rng->rng.name = dev_driver_string(dev); -+#ifndef CONFIG_PM -+ rk_rng->rng.init = rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng_cleanup; -+#endif ++ if (!IS_ENABLED(CONFIG_PM)) { ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup; ++ } + rk_rng->rng.read = rk_rng_read; + rk_rng->rng.priv = (unsigned long) dev; -+ rk_rng->rng.quality = 900; ++ rk_rng->rng.quality = quality; + + pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(dev); -+ pm_runtime_enable(dev); ++ devm_pm_runtime_enable(dev); + + ret = devm_hwrng_register(dev, &rk_rng->rng); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); + -+ dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); -+ + return 0; +} + -+static int rk_rng_remove(struct platform_device *pdev) -+{ -+ pm_runtime_disable(&pdev->dev); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int rk_rng_runtime_suspend(struct device *dev) ++static int __maybe_unused rk_rng_runtime_suspend(struct device *dev) +{ + struct rk_rng *rk_rng = dev_get_drvdata(dev); + @@ -299,13 +251,12 @@ Signed-off-by: Aurelien Jarno + return 0; +} + -+static int rk_rng_runtime_resume(struct device *dev) ++static int __maybe_unused rk_rng_runtime_resume(struct device *dev) +{ + struct rk_rng *rk_rng = dev_get_drvdata(dev); + + return rk_rng_init(&rk_rng->rng); +} -+#endif + +static const struct dev_pm_ops rk_rng_pm_ops = { + SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, @@ -315,10 +266,8 @@ Signed-off-by: Aurelien Jarno +}; + +static const struct of_device_id rk_rng_dt_match[] = { -+ { -+ .compatible = "rockchip,rk3568-rng", -+ }, -+ {}, ++ { .compatible = "rockchip,rk3568-rng", }, ++ { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rk_rng_dt_match); @@ -330,11 +279,12 @@ Signed-off-by: Aurelien Jarno + .of_match_table = rk_rng_dt_match, + }, + .probe = rk_rng_probe, -+ .remove = rk_rng_remove, +}; + +module_platform_driver(rk_rng_driver); + -+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); -+MODULE_AUTHOR("Lin Jinhan , Aurelien Jarno "); -+MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan "); ++MODULE_AUTHOR("Aurelien Jarno "); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK3568.patch b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK3568.patch new file mode 100644 index 0000000000..c5e1eb44f6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK3568.patch @@ -0,0 +1,49 @@ +From 756e7d3251ad8f6c72e7bf4c476537a89f673e38 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Sun, 21 Jul 2024 01:48:38 +0100 +Subject: [PATCH 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x + +Enable the just added Rockchip RNG driver for RK356x SoCs. + +Signed-off-by: Aurelien Jarno +Signed-off-by: Daniel Golle +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 7 +++++++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++ + 2 files changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -257,6 +257,13 @@ + }; + }; + ++&rng { ++ rockchip,sample-count = <1000>; ++ quality = <900>; ++ ++ status = "okay"; ++}; ++ + &usb_host0_xhci { + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1105,6 +1105,16 @@ + status = "disabled"; + }; + ++ rng: rng@fe388000 { ++ compatible = "rockchip,rk3568-rng"; ++ reg = <0x0 0xfe388000 0x0 0x4000>; ++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; ++ clock-names = "core", "ahb"; ++ resets = <&cru SRST_TRNG_NS>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch deleted file mode 100644 index 3e65de7a20..0000000000 --- a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch +++ /dev/null @@ -1,56 +0,0 @@ -From patchwork Sat Nov 12 14:10:59 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Aurelien Jarno -X-Patchwork-Id: 13041221 -From: Aurelien Jarno -To: Olivia Mackall , - Herbert Xu , - Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Lin Jinhan -Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR - CORE), - devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE - BINDINGS), - linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC - support), - linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), - linux-kernel@vger.kernel.org (open list), - Aurelien Jarno -Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x -Date: Sat, 12 Nov 2022 15:10:59 +0100 -Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> -In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> -References: <20221112141059.3802506-1-aurelien@aurel32.net> -MIME-Version: 1.0 -List-Id: - -Enable the just added Rockchip RNG driver for RK356x SoCs. - -Signed-off-by: Aurelien Jarno ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1848,6 +1848,15 @@ - }; - }; - -+ rng: rng@fe388000 { -+ compatible = "rockchip,rk3568-rng"; -+ reg = <0x0 0xfe388000 0x0 0x4000>; -+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; -+ clock-names = "trng_clk", "trng_hclk"; -+ resets = <&cru SRST_TRNG_NS>; -+ reset-names = "reset"; -+ }; -+ - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; From 940f83cc8d899551dec22e3d9142e9e7022c29ac Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 30 Jul 2024 00:37:21 +0100 Subject: [PATCH 10/19] rockchip: dw-rockchip: Fix initial PERST# GPIO value Import patch from mainline Linux to fix issue with PERST# signal polarity. Quote from commit message: "This extra, very short, PERST# assertion + deassertion has been reported to cause issues with certain WLAN controllers, e.g. RTL8822CE." Signed-off-by: Daniel Golle --- ...ockchip-Fix-initial-PERST-GPIO-value.patch | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 target/linux/rockchip/patches-6.6/310-PCI-dw-rockchip-Fix-initial-PERST-GPIO-value.patch diff --git a/target/linux/rockchip/patches-6.6/310-PCI-dw-rockchip-Fix-initial-PERST-GPIO-value.patch b/target/linux/rockchip/patches-6.6/310-PCI-dw-rockchip-Fix-initial-PERST-GPIO-value.patch new file mode 100644 index 0000000000..5ebf04bb33 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/310-PCI-dw-rockchip-Fix-initial-PERST-GPIO-value.patch @@ -0,0 +1,76 @@ +From 28b8d7793b8573563b3d45321376f36168d77b1e Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Wed, 17 Apr 2024 18:42:26 +0200 +Subject: [PATCH] PCI: dw-rockchip: Fix initial PERST# GPIO value +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PERST# is active low according to the PCIe specification. + +However, the existing pcie-dw-rockchip.c driver does: + + gpiod_set_value(..., 0); msleep(100); gpiod_set_value(..., 1); + +when asserting + deasserting PERST#. + +This is of course wrong, but because all the device trees for this +compatible string have also incorrectly marked this GPIO as ACTIVE_HIGH: + + $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3568* + $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3588* + +The actual toggling of PERST# is correct, and we cannot change it anyway, +since that would break device tree compatibility. + +However, this driver does request the GPIO to be initialized as +GPIOD_OUT_HIGH, which does cause a silly sequence where PERST# gets +toggled back and forth for no good reason. + +Fix this by requesting the GPIO to be initialized as GPIOD_OUT_LOW (which +for this driver means PERST# asserted). + +This will avoid an unnecessary signal change where PERST# gets deasserted +(by devm_gpiod_get_optional()) and then gets asserted (by +rockchip_pcie_start_link()) just a few instructions later. + +Before patch, debug prints on EP side, when booting RC: + + [ 845.606810] pci: PERST# asserted by host! + [ 852.483985] pci: PERST# de-asserted by host! + [ 852.503041] pci: PERST# asserted by host! + [ 852.610318] pci: PERST# de-asserted by host! + +After patch, debug prints on EP side, when booting RC: + + [ 125.107921] pci: PERST# asserted by host! + [ 132.111429] pci: PERST# de-asserted by host! + +This extra, very short, PERST# assertion + deassertion has been reported to +cause issues with certain WLAN controllers, e.g. RTL8822CE. + +Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver") +Link: https://lore.kernel.org/linux-pci/20240417164227.398901-1-cassel@kernel.org +Tested-by: Heiko Stuebner +Tested-by: Jianfeng Liu +Signed-off-by: Niklas Cassel +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +Reviewed-by: Heiko Stuebner +Reviewed-by: Manivannan Sadhasivam +Cc: stable@vger.kernel.org # v5.15+ +--- + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c ++++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +@@ -240,7 +240,7 @@ static int rockchip_pcie_resource_get(st + return PTR_ERR(rockchip->apb_base); + + rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", +- GPIOD_OUT_HIGH); ++ GPIOD_OUT_LOW); + if (IS_ERR(rockchip->rst_gpio)) + return PTR_ERR(rockchip->rst_gpio); + From fe62370e5534e04b3866ffee63142187b6680230 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 29 Jul 2024 23:43:06 +0200 Subject: [PATCH 11/19] firmware: Mark Intel/Lantiq firmware packages as nonshared Package the firmware files in the target specific build step and not in the architecture common step. The architecture common step is not necessary build for the ipq40xx target. If it is build for a different target these packages are not packaged at all. This moves the build to the ipq40xx target specific build step. This change is needed to make the firmware files show up in the buildbot images. Fixes: 02db8a19cb8d ("firmware: add Intel/Lantiq VRX518 ACA firmware package") Fixes: 07b0e6f3d9bc ("firmware: add Intel/Lantiq VRX518 PPE firmware package") Fixes: 13eb1f564ad7 ("firmware: add Intel/Lantiq VRX518 DSL firmware package") Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/firmware/lantiq/dsl_vr11_firmware_xdsl/Makefile | 1 + package/firmware/lantiq/vrx518_aca_fw/Makefile | 1 + package/firmware/lantiq/vrx518_ppe_fw/Makefile | 1 + 3 files changed, 3 insertions(+) diff --git a/package/firmware/lantiq/dsl_vr11_firmware_xdsl/Makefile b/package/firmware/lantiq/dsl_vr11_firmware_xdsl/Makefile index 777edb0e75..c219e16bbb 100644 --- a/package/firmware/lantiq/dsl_vr11_firmware_xdsl/Makefile +++ b/package/firmware/lantiq/dsl_vr11_firmware_xdsl/Makefile @@ -11,6 +11,7 @@ PKG_SOURCE_URL:=https://gitlab.com/prpl-foundation/intel/dsl_vr11_firmware_xdsl. PKG_SOURCE_VERSION:=99cf1fe7a1711b9aa128eeb8419eab698448df9f PKG_MIRROR_HASH:=7fb37723f8db2558d774ba972f011598d2399609158c5dbc287eca0873b040f1 +PKG_FLAGS:=nonshared PKG_LICENSE:=MaxLinear-Software-License-Agreement PKG_LICENSE_FILES:=LICENSE diff --git a/package/firmware/lantiq/vrx518_aca_fw/Makefile b/package/firmware/lantiq/vrx518_aca_fw/Makefile index 6b2361ec10..60fb5b76a6 100644 --- a/package/firmware/lantiq/vrx518_aca_fw/Makefile +++ b/package/firmware/lantiq/vrx518_aca_fw/Makefile @@ -11,6 +11,7 @@ PKG_SOURCE_URL:=https://gitlab.com/prpl-foundation/intel/vrx518_aca_fw.git PKG_SOURCE_VERSION:=c509b89c77c26a7df0f0999aabf78b82ca9c9ff0 PKG_MIRROR_HASH:=fba91071f18599617434d93e78c67dad91b3e4c5811b77c15961e3a13b506d2e +PKG_FLAGS:=nonshared PKG_LICENSE:=MaxLinear-Software-License-Agreement PKG_LICENSE_FILES:=platform/xrx500/LICENSE diff --git a/package/firmware/lantiq/vrx518_ppe_fw/Makefile b/package/firmware/lantiq/vrx518_ppe_fw/Makefile index 4c50521fbe..90a6f73daa 100644 --- a/package/firmware/lantiq/vrx518_ppe_fw/Makefile +++ b/package/firmware/lantiq/vrx518_ppe_fw/Makefile @@ -11,6 +11,7 @@ PKG_SOURCE_URL:=https://gitlab.com/prpl-foundation/intel/vrx518_ppe_fw.git PKG_SOURCE_VERSION:=47c48d52ba59df733ab21fd0c18f6d1a7b0e7229 PKG_MIRROR_HASH:=33dd15b6c6205b5031498aac9a5a4876f8217aefea06dc511ac60ca1343b50d1 +PKG_FLAGS:=nonshared PKG_LICENSE:=MaxLinear-Software-License-Agreement PKG_LICENSE_FILES:=platform/xrx500/LICENSE From 9a981ffb515964ee69a014b4f085ace764169f73 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 Jul 2024 00:29:11 +0200 Subject: [PATCH 12/19] imx-bootlets: Mark as nonshared to build in step 1 Mark the package as nonshared to build it in the target specific build step 1 of the build bots instead of the architecture generic build step 2. In the build step 2 it may be left out if we build it using a different target. Fixes: 07043a853a34 ("imx23: rename imx23 to mxs for upcoming imx23/28 support") Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/boot/imx-bootlets/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/package/boot/imx-bootlets/Makefile b/package/boot/imx-bootlets/Makefile index 742c8a3bd0..de976c249a 100644 --- a/package/boot/imx-bootlets/Makefile +++ b/package/boot/imx-bootlets/Makefile @@ -13,6 +13,8 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=http://trabant.uid0.hu/openwrt/ PKG_HASH:=09ecd81a64db5166a235932146faf08d0689bfc7ac04ac9fcc3a5bd809fba74a +PKG_FLAGS:=nonshared + include $(INCLUDE_DIR)/package.mk define Package/imx-bootlets From 54258c396f8ff0b159870a610d9ce16aee02c342 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 Jul 2024 00:32:10 +0200 Subject: [PATCH 13/19] kobs-ng: Mark as nonshared to build in step 1 Mark the package as nonshared to build it in the target specific build step 1 of the build bots instead of the architecture generic build step 2. In the build step 2 it may be left out if we build it using a different target. Fixes: 1eb21b87bdd6 ("kobs-ng: add new package") Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/boot/kobs-ng/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/kobs-ng/Makefile b/package/boot/kobs-ng/Makefile index 68e6ff170c..261cd92eab 100644 --- a/package/boot/kobs-ng/Makefile +++ b/package/boot/kobs-ng/Makefile @@ -18,6 +18,7 @@ PKG_BUILD_DIR:=$(BUILD_DIR)/imx-kobs-$(PKG_VERSION) PKG_LICENSE:=GPLv2 PKG_LICENSE_FILES:=COPYING +PKG_FLAGS:=nonshared include $(INCLUDE_DIR)/package.mk From 9ac50c0aa33f0d0add63a49433147b813b4ce44d Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 Jul 2024 00:33:21 +0200 Subject: [PATCH 14/19] dns320l-mcu: Mark as nonshared to build in step 1 Mark the package as nonshared to build it in the target specific build step 1 of the build bots instead of the architecture generic build step 2. In the build step 2 it may be left out if we build it using a different target. Fixes: 8619d7af67c2 ("kirkwood: add D-Link DNS-320L support") Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/utils/dns320l-mcu/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/package/utils/dns320l-mcu/Makefile b/package/utils/dns320l-mcu/Makefile index 724a664a8b..5124f5323d 100644 --- a/package/utils/dns320l-mcu/Makefile +++ b/package/utils/dns320l-mcu/Makefile @@ -11,6 +11,8 @@ PKG_MIRROR_HASH:=e0f186a0c139ccfac3d311f49e2fecdbd02fa3f9fe6ced4b1ce0baa603d49fc PKG_MAINTAINER:=Zoltan HERPAI PKG_LICENSE:=GPL-3.0+ +PKG_FLAGS:=nonshared + include $(INCLUDE_DIR)/package.mk define Package/dns320l-mcu From 4992946bc9a40f9df4594bb05163dc34c2039400 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 Jul 2024 00:34:14 +0200 Subject: [PATCH 15/19] firmware-utils: Mark as nonshared to build in step 1 Mark the package as nonshared to build it in the target specific build step 1 of the build bots instead of the architecture generic build step 2. In the build step 2 it may be left out if we build it using a different target. Fixes: 24d6abe2d7cd ("firmware-utils: new package replacing otrx") Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/utils/firmware-utils/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/utils/firmware-utils/Makefile b/package/utils/firmware-utils/Makefile index 2d9dbc5fce..3dcac6bcf1 100644 --- a/package/utils/firmware-utils/Makefile +++ b/package/utils/firmware-utils/Makefile @@ -11,6 +11,7 @@ PKG_SOURCE_DATE:=2024-06-20 PKG_SOURCE_VERSION:=6ac44974185a3e7dc7848e97b964339948e817a7 PKG_MIRROR_HASH:=ee5b29f45593750a6806cfa7cad3fd766b321b44107a6b481b890efe82a7dbf5 +PKG_FLAGS:=nonshared PKG_BUILD_DEPENDS:=openssl zlib include $(INCLUDE_DIR)/package.mk From 4e6212e62fc57535fe8270b8524509ea337dd2a6 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 Jul 2024 00:36:06 +0200 Subject: [PATCH 16/19] linux-firmware: amd64-microcode: Remove TARGET_x86 dependency Build the amd64-microcode package on all architectures even if it only makes sense to use it on x86. If the package build is done by a builder not building for x86 it will not include the package otherwise. Link: https://github.com/openwrt/openwrt/pull/16031 Signed-off-by: Hauke Mehrtens --- package/firmware/linux-firmware/amd.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/firmware/linux-firmware/amd.mk b/package/firmware/linux-firmware/amd.mk index b669cf1b35..c1f5711e92 100644 --- a/package/firmware/linux-firmware/amd.mk +++ b/package/firmware/linux-firmware/amd.mk @@ -1,4 +1,4 @@ -Package/amd64-microcode = $(call Package/firmware-default,AMD64 CPU microcode,@TARGET_x86,LICENSE.amd-ucode) +Package/amd64-microcode = $(call Package/firmware-default,AMD64 CPU microcode,,LICENSE.amd-ucode) define Package/amd64-microcode/install $(INSTALL_DIR) $(1)/lib/firmware/amd-ucode $(CP) \ From 7e06815257b623f104493bf85da1164d2f26277b Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 31 Jul 2024 05:30:01 +0900 Subject: [PATCH 17/19] mac80211: realtek: rtw88: add support for RTL8723DS and RTL8723DU add Realtek RTL8723DS and RTL8723DU support to rtw88 package. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/15910 Signed-off-by: Hauke Mehrtens --- package/kernel/mac80211/realtek.mk | 36 ++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/package/kernel/mac80211/realtek.mk b/package/kernel/mac80211/realtek.mk index 28ea6a6571..b53d08b24a 100644 --- a/package/kernel/mac80211/realtek.mk +++ b/package/kernel/mac80211/realtek.mk @@ -1,9 +1,9 @@ PKG_DRIVERS += \ rtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \ rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \ - rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \ + rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-sdio rtw88-8821c rtw88-8822b rtw88-8822c \ rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \ - rtw88-8822ce rtw88-8822cu rtw88-8723de + rtw88-8822ce rtw88-8822cu rtw88-8723de rtw88-8723ds rtw88-8723du config-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI config-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI @@ -29,6 +29,7 @@ config-y += STAGING config-$(call config_package,rtw88) += RTW88 RTW88_CORE config-$(call config_package,rtw88-pci) += RTW88_PCI config-$(call config_package,rtw88-usb) += RTW88_USB +config-$(call config_package,rtw88-sdio) += RTW88_SDIO config-$(call config_package,rtw88-8821c) += RTW88_8821C config-$(call config_package,rtw88-8821ce) += RTW88_8821CE config-$(call config_package,rtw88-8821cu) += RTW88_8821CU @@ -40,6 +41,8 @@ config-$(call config_package,rtw88-8822ce) += RTW88_8822CE config-$(call config_package,rtw88-8822cu) += RTW88_8822CU config-$(call config_package,rtw88-8723d) += RTW88_8723D config-$(call config_package,rtw88-8723de) += RTW88_8723DE +config-$(call config_package,rtw88-8723ds) += RTW88_8723DS +config-$(call config_package,rtw88-8723du) += RTW88_8723DU config-$(CONFIG_PACKAGE_RTW88_DEBUG) += RTW88_DEBUG config-$(CONFIG_PACKAGE_RTW88_DEBUGFS) += RTW88_DEBUGFS @@ -186,7 +189,7 @@ endef define KernelPackage/rtw88 $(call KernelPackage/mac80211/Default) TITLE:=Realtek RTW88 common part - DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 + DEPENDS+= +kmod-mac80211 FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_core.ko AUTOLOAD:=$(call AutoProbe,rtw88_core) HIDDEN:=1 @@ -201,6 +204,15 @@ define KernelPackage/rtw88-pci HIDDEN:=1 endef +define KernelPackage/rtw88-sdio + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTW88 SDIO chips support + DEPENDS+= +kmod-mmc +kmod-rtw88 + FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_sdio.ko + AUTOLOAD:=$(call AutoProbe,rtw88_sdio) + HIDDEN:=1 +endef + define KernelPackage/rtw88-usb $(call KernelPackage/mac80211/Default) TITLE:=Realtek RTW88 USB chips support @@ -299,7 +311,23 @@ define KernelPackage/rtw88-8723de TITLE:=Realtek RTL8723DE support DEPENDS+= +kmod-rtw88-pci +kmod-rtw88-8723d FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723de.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8723) + AUTOLOAD:=$(call AutoProbe,rtw88_8723de) +endef + +define KernelPackage/rtw88-8723ds + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8723DS support + DEPENDS+= +kmod-rtw88-sdio +kmod-rtw88-8723d + FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723ds.ko + AUTOLOAD:=$(call AutoProbe,rtw88_8723ds) +endef + +define KernelPackage/rtw88-8723du + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8723DU support + DEPENDS+= +kmod-rtw88-usb +kmod-rtw88-8723d + FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723du.ko + AUTOLOAD:=$(call AutoProbe,rtw88_8723du) endef define KernelPackage/rtl8723-common From 4c1fe83bd5c839ccecabfe7c72ef0d532d30d8b3 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 26 Jul 2024 07:03:18 +0900 Subject: [PATCH 18/19] rockchip: add RTL8723DS support for Radxa ROCK Pi S Radxa ROCK Pi S has a RTL8723DS Wi-Fi 4 on-board device. enable it. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/15910 Signed-off-by: Hauke Mehrtens --- target/linux/rockchip/image/armv8.mk | 2 +- ...domain-Add-RK3308-IO-voltage-domains.patch | 86 ++++++++++++++++ ...ckchip-Add-rk3308-IO-voltage-domains.patch | 28 ++++++ ...ip-Add-io-domains-to-rk3308-rock-pi-.patch | 35 +++++++ ...ip-Update-WIFi-BT-related-nodes-on-r.patch | 97 +++++++++++++++++++ ...s-add-led-aliases-and-stop-heartbeat.patch | 6 +- 6 files changed, 250 insertions(+), 4 deletions(-) create mode 100644 target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch create mode 100644 target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch create mode 100644 target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch create mode 100644 target/linux/rockchip/patches-6.6/048-v6.11-arm64-dts-rockchip-Update-WIFi-BT-related-nodes-on-r.patch diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 2f0d6371dc..52702959e1 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -153,7 +153,7 @@ define Device/radxa_rock-pi-s DEVICE_MODEL := ROCK Pi S SOC := rk3308 BOOT_SCRIPT := rock-pi-s - DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis + DEVICE_PACKAGES := kmod-rtw88-8723ds kmod-usb-net-cdc-ncm kmod-usb-net-rndis wpad-basic-mbedtls endef TARGET_DEVICES += radxa_rock-pi-s diff --git a/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch new file mode 100644 index 0000000000..bb7f833977 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch @@ -0,0 +1,86 @@ +From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Tue, 21 May 2024 21:10:13 +0000 +Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains + +Add IO voltage domains support for the RK3308 SoC. + +Signed-off-by: David Wu +Signed-off-by: Jianqun Xu +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/drivers/soc/rockchip/io-domain.c ++++ b/drivers/soc/rockchip/io-domain.c +@@ -39,6 +39,10 @@ + #define RK3288_SOC_CON2_FLASH0 BIT(7) + #define RK3288_SOC_FLASH_SUPPLY_NUM 2 + ++#define RK3308_SOC_CON0 0x300 ++#define RK3308_SOC_CON0_VCCIO3 BIT(8) ++#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 ++ + #define RK3328_SOC_CON4 0x410 + #define RK3328_SOC_CON4_VCCIO2 BIT(7) + #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 +@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct + dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); + } + ++static void rk3308_iodomain_init(struct rockchip_iodomain *iod) ++{ ++ int ret; ++ u32 val; ++ ++ /* if no vccio3 supply we should leave things alone */ ++ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) ++ return; ++ ++ /* ++ * set vccio3 iodomain to also use this framework ++ * instead of a special gpio. ++ */ ++ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); ++ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val); ++ if (ret < 0) ++ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); ++} ++ + static void rk3328_iodomain_init(struct rockchip_iodomain *iod) + { + int ret; +@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so + .init = rk3288_iodomain_init, + }; + ++static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { ++ .grf_offset = 0x300, ++ .supply_names = { ++ "vccio0", ++ "vccio1", ++ "vccio2", ++ "vccio3", ++ "vccio4", ++ "vccio5", ++ }, ++ .init = rk3308_iodomain_init, ++}; ++ + static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { + .grf_offset = 0x410, + .supply_names = { +@@ -529,6 +565,10 @@ static const struct of_device_id rockchi + .data = &soc_data_rk3288 + }, + { ++ .compatible = "rockchip,rk3308-io-voltage-domain", ++ .data = &soc_data_rk3308 ++ }, ++ { + .compatible = "rockchip,rk3328-io-voltage-domain", + .data = &soc_data_rk3328 + }, diff --git a/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch new file mode 100644 index 0000000000..3565acd2e4 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch @@ -0,0 +1,28 @@ +From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 21:10:14 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains + +Add a disabled RK3308 IO voltage domains node to SoC DT. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -168,6 +168,11 @@ + compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff000000 0x0 0x08000>; + ++ io_domains: io-domains { ++ compatible = "rockchip,rk3308-io-voltage-domain"; ++ status = "disabled"; ++ }; ++ + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x500>; diff --git a/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch b/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch new file mode 100644 index 0000000000..149cadf863 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch @@ -0,0 +1,35 @@ +From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 21:10:15 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s + +The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage. + +Add io-domains node with the VCCIO supplies connected on the board. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -231,6 +231,16 @@ + status = "okay"; + }; + ++&io_domains { ++ vccio0-supply = <&vcc_io>; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc_io>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ + &pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; diff --git a/target/linux/rockchip/patches-6.6/048-v6.11-arm64-dts-rockchip-Update-WIFi-BT-related-nodes-on-r.patch b/target/linux/rockchip/patches-6.6/048-v6.11-arm64-dts-rockchip-Update-WIFi-BT-related-nodes-on-r.patch new file mode 100644 index 0000000000..976e5f4cdf --- /dev/null +++ b/target/linux/rockchip/patches-6.6/048-v6.11-arm64-dts-rockchip-Update-WIFi-BT-related-nodes-on-r.patch @@ -0,0 +1,97 @@ +From 12c3ec878cbe3709782e85b88124abecc3bb8617 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 21:10:16 +0000 +Subject: [PATCH] arm64: dts: rockchip: Update WIFi/BT related nodes on + rk3308-rock-pi-s + +Update WiFi SDIO and BT UART related props to better reflect details +about the optional onboard RTL8723DS WiFi/BT module. + +Also correct the compatible used for bluetooth to match the WiFi/BT +module used on the board. + +Fixes: bc3753aed81f ("arm64: dts: rockchip: rock-pi-s add more peripherals") +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-14-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 40 +++++++++++++++++-- + 1 file changed, 36 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -17,6 +17,7 @@ + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; ++ mmc2 = &sdio; + }; + + chosen { +@@ -245,6 +246,20 @@ + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; + ++ bluetooth { ++ bt_reg_on: bt-reg-on { ++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host: bt-wake-host { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ host_wake_bt: host-wake-bt { ++ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -294,11 +309,24 @@ + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; +- max-frequency = <1000000>; ++ max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; ++ no-mmc; ++ no-sd; + non-removable; +- sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc_io>; ++ vqmmc-supply = <&vcc_1v8>; + status = "okay"; ++ ++ rtl8723ds: wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake>; ++ }; + }; + + &sdmmc { +@@ -330,12 +358,16 @@ + }; + + &uart4 { ++ uart-has-rtscts; + status = "okay"; + + bluetooth { +- compatible = "realtek,rtl8723bs-bt"; +- device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; ++ compatible = "realtek,rtl8723ds-bt"; ++ device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; ++ enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.6/113-rock-pi-s-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/113-rock-pi-s-add-led-aliases-and-stop-heartbeat.patch index 9564c900a2..48a617b09a 100644 --- a/target/linux/rockchip/patches-6.6/113-rock-pi-s-add-led-aliases-and-stop-heartbeat.patch +++ b/target/linux/rockchip/patches-6.6/113-rock-pi-s-add-led-aliases-and-stop-heartbeat.patch @@ -1,9 +1,9 @@ --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -17,6 +17,10 @@ - ethernet0 = &gmac; +@@ -18,6 +18,10 @@ mmc0 = &emmc; mmc1 = &sdmmc; + mmc2 = &sdio; + led-boot = &blue_led; + led-failsafe = &blue_led; + led-running = &blue_led; @@ -11,7 +11,7 @@ }; chosen { -@@ -28,22 +32,19 @@ +@@ -29,22 +33,19 @@ pinctrl-names = "default"; pinctrl-0 = <&green_led>, <&heartbeat_led>; From e6fec638d2791547c45c9a5267be07a722e03cd9 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 26 Jul 2024 07:03:21 +0900 Subject: [PATCH 19/19] rockchip: add RTL8723DU support for Radxa ROCK Pi E v3.0 Radxa ROCK Pi E v3.0 has a RTL8723DU Wi-Fi 4 on-board device. enable it. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/15910 Signed-off-by: Hauke Mehrtens --- target/linux/rockchip/image/armv8.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 52702959e1..d8d180a214 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -144,7 +144,7 @@ define Device/radxa_rock-pi-e-v3 DEVICE_MODEL := ROCK Pi E v3.0 SOC := rk3328 DEVICE_DTS := rockchip/rk3328-rock-pi-e - DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis + DEVICE_PACKAGES := kmod-rtw88-8723du kmod-usb-net-cdc-ncm kmod-usb-net-rndis wpad-basic-mbedtls endef TARGET_DEVICES += radxa_rock-pi-e-v3