From 6d27032a37f53e60e08d492883d42d10fcc926cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 1 Feb 2024 09:42:04 +0100 Subject: [PATCH 01/20] bcm27xx: base-files: set_preinit_iface: add RPi 5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing Rasoberry Pi 5 board_name to set_preinit_iface in order to get ethernet working on failsafe mode. Fixes: 8b63d9a ("bcm27xx: add new bcm2712 subtarget") Signed-off-by: Álvaro Fernández Rojas --- .../bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 b/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 index c52995bd17..120475b55d 100644 --- a/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 +++ b/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 @@ -12,6 +12,7 @@ set_preinit_iface() { raspberrypi,400 |\ raspberrypi,4-compute-module |\ raspberrypi,4-model-b |\ + raspberrypi,5-model-b |\ raspberrypi,model-b |\ raspberrypi,model-b-plus |\ raspberrypi,model-b-rev2) From a39176010299f3ad7d325b03d892fbf65e6dd23b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 30 Jan 2024 21:41:26 +0100 Subject: [PATCH 02/20] bcm27xx: base-files: properly detect boot partition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Automatically detect boot partition instead of forcing /dev/mmcblk0p1. This way users can still get /boot mounted when booting from USB. Signed-off-by: Álvaro Fernández Rojas --- .../bcm27xx/base-files/lib/preinit/79_move_config | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/linux/bcm27xx/base-files/lib/preinit/79_move_config b/target/linux/bcm27xx/base-files/lib/preinit/79_move_config index c9fb59a64f..db5bf93b62 100644 --- a/target/linux/bcm27xx/base-files/lib/preinit/79_move_config +++ b/target/linux/bcm27xx/base-files/lib/preinit/79_move_config @@ -2,16 +2,20 @@ . /lib/upgrade/common.sh -BOOTPART=/dev/mmcblk0p1 - move_config() { - if [ -b $BOOTPART ]; then + local partdev + + export_bootdevice && export_partdevice partdev 1 || { + partdev=mmcblk0p1 + } + + if [ -b "/dev/$partdev" ]; then insmod nls_cp437 insmod nls_iso8859-1 insmod fat insmod vfat mkdir -p /boot - mount -t vfat -o rw,noatime $BOOTPART /boot + mount -t vfat -o rw,noatime /dev/$partdev /boot [ -f "/boot/$BACKUP_FILE" ] && mv -f "/boot/$BACKUP_FILE" / fi } From 96b03ff2476edb4d08fb4b91fdf80be7aa95ddd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 30 Jan 2024 20:12:25 +0100 Subject: [PATCH 03/20] bcm27xx: improve image generation script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Exit immediately on a non-zero status. - Remove empty lines. - Remove unused variables. - Add missing ptgen variables for readability. - Refactor SYNTAX if block. Signed-off-by: Álvaro Fernández Rojas --- .../linux/bcm27xx/image/gen_rpi_sdcard_img.sh | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh b/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh index 5e8fb2769c..488a3517c7 100755 --- a/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh +++ b/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh @@ -1,10 +1,11 @@ #!/bin/sh -set -x -[ $# -eq 5 ] || { +set -e -x + +if [ $# -ne 5 ]; then echo "SYNTAX: $0 " exit 1 -} +fi OUTPUT="$1" BOOTFS="$2" @@ -12,18 +13,16 @@ ROOTFS="$3" BOOTFSSIZE="$4" ROOTFSSIZE="$5" +align=4096 head=4 +kernel_type=c +rootfs_type=83 sect=63 -set $(ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M) +set $(ptgen -o $OUTPUT -h $head -s $sect -l $align -t $kernel_type -p ${BOOTFSSIZE}M -t $rootfs_type -p ${ROOTFSSIZE}M) BOOTOFFSET="$(($1 / 512))" -BOOTSIZE="$(($2 / 512))" ROOTFSOFFSET="$(($3 / 512))" -ROOTFSSIZE="$(($4 / 512))" dd bs=512 if="$BOOTFS" of="$OUTPUT" seek="$BOOTOFFSET" conv=notrunc dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFSOFFSET" conv=notrunc - - - From 1a5e51ab0011796fae5b08d03de3994c767517c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 31 Jan 2024 12:36:49 +0100 Subject: [PATCH 04/20] bcm27xx: base-files: fix platform_copy_config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only bcm2708 and bcm2709 use "kernel.img" file name. bcm2710 and bcm2711 use "kernel8.img" and bcm2712 uses "kernel_2712.img". Signed-off-by: Álvaro Fernández Rojas --- target/linux/bcm27xx/base-files/lib/upgrade/platform.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh index a48b7cc08a..956bc1c788 100644 --- a/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh @@ -90,7 +90,7 @@ platform_copy_config() { if export_partdevice partdev 1; then mkdir -p /boot - [ -f /boot/kernel.img ] || mount -t vfat -o rw,noatime "/dev/$partdev" /boot + [ -f "/boot/kernel*.img" ] || mount -t vfat -o rw,noatime "/dev/$partdev" /boot cp -af "$UPGRADE_BACKUP" "/boot/$BACKUP_FILE" tar -C / -zxvf "$UPGRADE_BACKUP" boot/cmdline.txt boot/config.txt sync From 0a65787675c106fba935074a2b7d7f5717f176ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 1 Feb 2024 11:54:22 +0100 Subject: [PATCH 05/20] bcm27xx: bcm2712: remove boot-2711 image files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Raspberry Pi documentation, the RPi 5 First Stage Bootloader loads the linux kernel instead of loading the Second Stage Bootloader (start.elf): https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#differences-on-raspberry-pi-5 Fixes: 8b63d9a ("bcm27xx: add new bcm2712 subtarget") Signed-off-by: Álvaro Fernández Rojas --- target/linux/bcm27xx/image/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/bcm27xx/image/Makefile b/target/linux/bcm27xx/image/Makefile index e5c2d15499..12ac0012a4 100644 --- a/target/linux/bcm27xx/image/Makefile +++ b/target/linux/bcm27xx/image/Makefile @@ -182,8 +182,8 @@ define Device/rpi-5 brcmfmac-nvram-43455-sdio \ kmod-brcmfmac wpad-basic-mbedtls \ kmod-hwmon-pwmfan kmod-thermal - IMAGE/sysupgrade.img.gz := boot-common | boot-2711 | sdcard-img | gzip | append-metadata - IMAGE/factory.img.gz := boot-common | boot-2711 | sdcard-img | gzip + IMAGE/sysupgrade.img.gz := boot-common | sdcard-img | gzip | append-metadata + IMAGE/factory.img.gz := boot-common | sdcard-img | gzip endef ifeq ($(SUBTARGET),bcm2712) TARGET_DEVICES += rpi-5 From 997acc7f86ca985cba52f7ea8b72f0661a1e3c52 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 1 Feb 2024 14:13:23 +0100 Subject: [PATCH 06/20] generic: 6.1: backport at803x split patches Backport at803x split patches merged upstream to tidy things up for the at803x PHY driver. New Kernel config are introduced hence any user needs to be updated. Downstream ipq40xx patch require rework to correctly move them to the qcom specific PHY directory. All affected patch automatically refreshed. Signed-off-by: Christian Marangi --- ...03x-PHY-driver-to-dedicated-director.patch | 5598 +++++++++++++++++ ...ate-and-move-functions-to-shared-lib.patch | 243 + ...eatch-qca83xx-PHY-driver-from-at803x.patch | 638 ++ ...e-additional-functions-to-shared-lib.patch | 1014 +++ ...etach-qca808x-PHY-driver-from-at803x.patch | 1936 ++++++ target/linux/generic/config-6.1 | 2 + .../drivers/net/phy/{ => qcom}/qca807x.c | 0 ...9-net-phy-Add-Qualcom-QCA807x-driver.patch | 32 +- target/linux/ipq806x/config-6.1 | 2 +- .../500-gsw-rtl8367s-mt7622-support.patch | 2 +- ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 2 +- ...phy-add-driver-for-MediaTek-2.5G-PHY.patch | 2 +- 12 files changed, 9450 insertions(+), 21 deletions(-) create mode 100644 target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch create mode 100644 target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch create mode 100644 target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch create mode 100644 target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch create mode 100644 target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch rename target/linux/ipq40xx/files/drivers/net/phy/{ => qcom}/qca807x.c (100%) diff --git a/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch new file mode 100644 index 0000000000..8c9babea7b --- /dev/null +++ b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch @@ -0,0 +1,5598 @@ +From 9e56ff53b4115875667760445b028357848b4748 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 29 Jan 2024 15:15:19 +0100 +Subject: [PATCH 1/5] net: phy: move at803x PHY driver to dedicated directory + +In preparation for addition of other Qcom PHY and to tidy things up, +move the at803x PHY driver to dedicated directory. + +The same order in the Kconfig selection is saved. + +Signed-off-by: Christian Marangi +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/Kconfig | 7 +------ + drivers/net/phy/Makefile | 2 +- + drivers/net/phy/qcom/Kconfig | 7 +++++++ + drivers/net/phy/qcom/Makefile | 2 ++ + drivers/net/phy/{ => qcom}/at803x.c | 0 + 5 files changed, 11 insertions(+), 7 deletions(-) + create mode 100644 drivers/net/phy/qcom/Kconfig + create mode 100644 drivers/net/phy/qcom/Makefile + rename drivers/net/phy/{ => qcom}/at803x.c (100%) + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -277,12 +277,7 @@ config NXP_TJA11XX_PHY + help + Currently supports the NXP TJA1100 and TJA1101 PHY. + +-config AT803X_PHY +- tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" +- depends on REGULATOR +- help +- Currently supports the AR8030, AR8031, AR8033, AR8035 and internal +- QCA8337(Internal qca8k PHY) model ++source "drivers/net/phy/qcom/Kconfig" + + config QSEMI_PHY + tristate "Quality Semiconductor PHYs" +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -34,7 +34,6 @@ obj-$(CONFIG_ADIN_PHY) += adin.o + obj-$(CONFIG_ADIN1100_PHY) += adin1100.o + obj-$(CONFIG_AMD_PHY) += amd.o + obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ +-obj-$(CONFIG_AT803X_PHY) += at803x.o + obj-$(CONFIG_AX88796B_PHY) += ax88796b.o + obj-$(CONFIG_BCM54140_PHY) += bcm54140.o + obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o +@@ -75,6 +74,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm + obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o + obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o ++obj-y += qcom/ + obj-$(CONFIG_QSEMI_PHY) += qsemi.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_RENESAS_PHY) += uPD60620.o +--- /dev/null ++++ b/drivers/net/phy/qcom/Kconfig +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config AT803X_PHY ++ tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" ++ depends on REGULATOR ++ help ++ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal ++ QCA8337(Internal qca8k PHY) model +--- /dev/null ++++ b/drivers/net/phy/qcom/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_AT803X_PHY) += at803x.o +--- a/drivers/net/phy/at803x.c ++++ /dev/null +@@ -1,2759 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * drivers/net/phy/at803x.c +- * +- * Driver for Qualcomm Atheros AR803x PHY +- * +- * Author: Matus Ujhelyi +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 +-#define AT803X_SFC_ASSERT_CRS BIT(11) +-#define AT803X_SFC_FORCE_LINK BIT(10) +-#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) +-#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 +-#define AT803X_SFC_MANUAL_MDIX 0x1 +-#define AT803X_SFC_MANUAL_MDI 0x0 +-#define AT803X_SFC_SQE_TEST BIT(2) +-#define AT803X_SFC_POLARITY_REVERSAL BIT(1) +-#define AT803X_SFC_DISABLE_JABBER BIT(0) +- +-#define AT803X_SPECIFIC_STATUS 0x11 +-#define AT803X_SS_SPEED_MASK GENMASK(15, 14) +-#define AT803X_SS_SPEED_1000 2 +-#define AT803X_SS_SPEED_100 1 +-#define AT803X_SS_SPEED_10 0 +-#define AT803X_SS_DUPLEX BIT(13) +-#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) +-#define AT803X_SS_MDIX BIT(6) +- +-#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) +-#define QCA808X_SS_SPEED_2500 4 +- +-#define AT803X_INTR_ENABLE 0x12 +-#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) +-#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) +-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) +-#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) +-#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) +-#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) +-#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) +-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) +-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) +-#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) +-#define AT803X_INTR_ENABLE_WOL BIT(0) +- +-#define AT803X_INTR_STATUS 0x13 +- +-#define AT803X_SMART_SPEED 0x14 +-#define AT803X_SMART_SPEED_ENABLE BIT(5) +-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) +-#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) +-#define AT803X_CDT 0x16 +-#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) +-#define AT803X_CDT_ENABLE_TEST BIT(0) +-#define AT803X_CDT_STATUS 0x1c +-#define AT803X_CDT_STATUS_STAT_NORMAL 0 +-#define AT803X_CDT_STATUS_STAT_SHORT 1 +-#define AT803X_CDT_STATUS_STAT_OPEN 2 +-#define AT803X_CDT_STATUS_STAT_FAIL 3 +-#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) +-#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) +-#define AT803X_LED_CONTROL 0x18 +- +-#define AT803X_PHY_MMD3_WOL_CTRL 0x8012 +-#define AT803X_WOL_EN BIT(5) +-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C +-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B +-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A +-#define AT803X_REG_CHIP_CONFIG 0x1f +-#define AT803X_BT_BX_REG_SEL 0x8000 +- +-#define AT803X_DEBUG_ADDR 0x1D +-#define AT803X_DEBUG_DATA 0x1E +- +-#define AT803X_MODE_CFG_MASK 0x0F +-#define AT803X_MODE_CFG_BASET_RGMII 0x00 +-#define AT803X_MODE_CFG_BASET_SGMII 0x01 +-#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 +-#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 +-#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 +-#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 +-#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 +-#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 +-#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B +-#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E +-#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F +- +-#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ +-#define AT803X_PSSR_MR_AN_COMPLETE 0x0200 +- +-#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 +-#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) +-#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) +-#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) +- +-#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 +-#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) +- +-#define AT803X_DEBUG_REG_HIB_CTRL 0x0b +-#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) +-#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) +-#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) +- +-#define AT803X_DEBUG_REG_3C 0x3C +- +-#define AT803X_DEBUG_REG_GREEN 0x3D +-#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) +- +-#define AT803X_DEBUG_REG_1F 0x1F +-#define AT803X_DEBUG_PLL_ON BIT(2) +-#define AT803X_DEBUG_RGMII_1V8 BIT(3) +- +-#define MDIO_AZ_DEBUG 0x800D +- +-/* AT803x supports either the XTAL input pad, an internal PLL or the +- * DSP as clock reference for the clock output pad. The XTAL reference +- * is only used for 25 MHz output, all other frequencies need the PLL. +- * The DSP as a clock reference is used in synchronous ethernet +- * applications. +- * +- * By default the PLL is only enabled if there is a link. Otherwise +- * the PHY will go into low power state and disabled the PLL. You can +- * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always +- * enabled. +- */ +-#define AT803X_MMD7_CLK25M 0x8016 +-#define AT803X_CLK_OUT_MASK GENMASK(4, 2) +-#define AT803X_CLK_OUT_25MHZ_XTAL 0 +-#define AT803X_CLK_OUT_25MHZ_DSP 1 +-#define AT803X_CLK_OUT_50MHZ_PLL 2 +-#define AT803X_CLK_OUT_50MHZ_DSP 3 +-#define AT803X_CLK_OUT_62_5MHZ_PLL 4 +-#define AT803X_CLK_OUT_62_5MHZ_DSP 5 +-#define AT803X_CLK_OUT_125MHZ_PLL 6 +-#define AT803X_CLK_OUT_125MHZ_DSP 7 +- +-/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask +- * but doesn't support choosing between XTAL/PLL and DSP. +- */ +-#define AT8035_CLK_OUT_MASK GENMASK(4, 3) +- +-#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) +-#define AT803X_CLK_OUT_STRENGTH_FULL 0 +-#define AT803X_CLK_OUT_STRENGTH_HALF 1 +-#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 +- +-#define AT803X_DEFAULT_DOWNSHIFT 5 +-#define AT803X_MIN_DOWNSHIFT 2 +-#define AT803X_MAX_DOWNSHIFT 9 +- +-#define AT803X_MMD3_SMARTEEE_CTL1 0x805b +-#define AT803X_MMD3_SMARTEEE_CTL2 0x805c +-#define AT803X_MMD3_SMARTEEE_CTL3 0x805d +-#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) +- +-#define ATH9331_PHY_ID 0x004dd041 +-#define ATH8030_PHY_ID 0x004dd076 +-#define ATH8031_PHY_ID 0x004dd074 +-#define ATH8032_PHY_ID 0x004dd023 +-#define ATH8035_PHY_ID 0x004dd072 +-#define AT8030_PHY_ID_MASK 0xffffffef +- +-#define QCA8081_PHY_ID 0x004dd101 +- +-#define QCA8327_A_PHY_ID 0x004dd033 +-#define QCA8327_B_PHY_ID 0x004dd034 +-#define QCA8337_PHY_ID 0x004dd036 +-#define QCA9561_PHY_ID 0x004dd042 +-#define QCA8K_PHY_ID_MASK 0xffffffff +- +-#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) +- +-#define AT803X_PAGE_FIBER 0 +-#define AT803X_PAGE_COPPER 1 +- +-/* don't turn off internal PLL */ +-#define AT803X_KEEP_PLL_ENABLED BIT(0) +-#define AT803X_DISABLE_SMARTEEE BIT(1) +- +-/* disable hibernation mode */ +-#define AT803X_DISABLE_HIBERNATION_MODE BIT(2) +- +-/* ADC threshold */ +-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 +-#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) +-#define QCA808X_ADC_THRESHOLD_80MV 0 +-#define QCA808X_ADC_THRESHOLD_100MV 0xf0 +-#define QCA808X_ADC_THRESHOLD_200MV 0x0f +-#define QCA808X_ADC_THRESHOLD_300MV 0xff +- +-/* CLD control */ +-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 +-#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) +-#define QCA808X_8023AZ_AFE_EN 0x90 +- +-/* AZ control */ +-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 +-#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 +-#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E +-#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E +-#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 +-#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 +- +-#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c +-#define QCA808X_TOP_OPTION1_DATA 0x0 +- +-#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 +-#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 +-#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 +-#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad +-#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 +-#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 +-#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 +-#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 +-#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 +-#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 +-#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 +-#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 +- +-/* master/slave seed config */ +-#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 +-#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) +-#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) +-#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 +- +-/* Hibernation yields lower power consumpiton in contrast with normal operation mode. +- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. +- */ +-#define QCA808X_DBG_AN_TEST 0xb +-#define QCA808X_HIBERNATION_EN BIT(15) +- +-#define QCA808X_CDT_ENABLE_TEST BIT(15) +-#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) +-#define QCA808X_CDT_STATUS BIT(11) +-#define QCA808X_CDT_LENGTH_UNIT BIT(10) +- +-#define QCA808X_MMD3_CDT_STATUS 0x8064 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 +-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) +-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) +- +-#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) +-#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) +-#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) +-#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) +- +-#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) +-#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) +-#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) +-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) +-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) +- +-#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) +-#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) +-#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) +-#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) +- +-/* NORMAL are MDI with type set to 0 */ +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI1) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI1) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI2) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI2) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI3) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI3) +- +-/* Added for reference of existence but should be handled by wait_for_completion already */ +-#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) +- +-#define QCA808X_MMD7_LED_GLOBAL 0x8073 +-#define QCA808X_LED_BLINK_1 GENMASK(11, 6) +-#define QCA808X_LED_BLINK_2 GENMASK(5, 0) +-/* Values are the same for both BLINK_1 and BLINK_2 */ +-#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) +-#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) +-#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) +-#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) +-#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) +-#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) +-#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) +-#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) +-#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) +-#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) +-#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) +-#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) +-#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) +-#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) +-#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) +-#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) +-#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) +-#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) +- +-#define QCA808X_MMD7_LED2_CTRL 0x8074 +-#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 +-#define QCA808X_MMD7_LED1_CTRL 0x8076 +-#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 +-#define QCA808X_MMD7_LED0_CTRL 0x8078 +-#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) +- +-/* LED hw control pattern is the same for every LED */ +-#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) +-#define QCA808X_LED_SPEED2500_ON BIT(15) +-#define QCA808X_LED_SPEED2500_BLINK BIT(14) +-/* Follow blink trigger even if duplex or speed condition doesn't match */ +-#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) +-#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) +-#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) +-#define QCA808X_LED_TX_BLINK BIT(10) +-#define QCA808X_LED_RX_BLINK BIT(9) +-#define QCA808X_LED_TX_ON_10MS BIT(8) +-#define QCA808X_LED_RX_ON_10MS BIT(7) +-#define QCA808X_LED_SPEED1000_ON BIT(6) +-#define QCA808X_LED_SPEED100_ON BIT(5) +-#define QCA808X_LED_SPEED10_ON BIT(4) +-#define QCA808X_LED_COLLISION_BLINK BIT(3) +-#define QCA808X_LED_SPEED1000_BLINK BIT(2) +-#define QCA808X_LED_SPEED100_BLINK BIT(1) +-#define QCA808X_LED_SPEED10_BLINK BIT(0) +- +-#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 +-#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) +- +-/* LED force ctrl is the same for every LED +- * No documentation exist for this, not even internal one +- * with NDA as QCOM gives only info about configuring +- * hw control pattern rules and doesn't indicate any way +- * to force the LED to specific mode. +- * These define comes from reverse and testing and maybe +- * lack of some info or some info are not entirely correct. +- * For the basic LED control and hw control these finding +- * are enough to support LED control in all the required APIs. +- * +- * On doing some comparison with implementation with qca807x, +- * it was found that it's 1:1 equal to it and confirms all the +- * reverse done. It was also found further specification with the +- * force mode and the blink modes. +- */ +-#define QCA808X_LED_FORCE_EN BIT(15) +-#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) +-#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) +-#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) +-#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) +-#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) +- +-#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a +-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for +- * LED to active high. It's not clear what BIT 3 and BIT 4 does. +- */ +-#define QCA808X_LED_ACTIVE_HIGH BIT(6) +- +-/* QCA808X 1G chip type */ +-#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d +-#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) +- +-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 +-#define QCA8081_PHY_FIFO_RSTN BIT(11) +- +-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); +-MODULE_AUTHOR("Matus Ujhelyi"); +-MODULE_LICENSE("GPL"); +- +-enum stat_access_type { +- PHY, +- MMD +-}; +- +-struct at803x_hw_stat { +- const char *string; +- u8 reg; +- u32 mask; +- enum stat_access_type access_type; +-}; +- +-static struct at803x_hw_stat qca83xx_hw_stats[] = { +- { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, +- { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, +- { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, +-}; +- +-struct at803x_ss_mask { +- u16 speed_mask; +- u8 speed_shift; +-}; +- +-struct at803x_priv { +- int flags; +- u16 clk_25m_reg; +- u16 clk_25m_mask; +- u8 smarteee_lpi_tw_1g; +- u8 smarteee_lpi_tw_100m; +- bool is_fiber; +- bool is_1000basex; +- struct regulator_dev *vddio_rdev; +- struct regulator_dev *vddh_rdev; +- u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; +- int led_polarity_mode; +-}; +- +-struct at803x_context { +- u16 bmcr; +- u16 advertise; +- u16 control1000; +- u16 int_enable; +- u16 smart_speed; +- u16 led_control; +-}; +- +-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) +-{ +- int ret; +- +- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); +- if (ret < 0) +- return ret; +- +- return phy_write(phydev, AT803X_DEBUG_DATA, data); +-} +- +-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) +-{ +- int ret; +- +- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); +- if (ret < 0) +- return ret; +- +- return phy_read(phydev, AT803X_DEBUG_DATA); +-} +- +-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, +- u16 clear, u16 set) +-{ +- u16 val; +- int ret; +- +- ret = at803x_debug_reg_read(phydev, reg); +- if (ret < 0) +- return ret; +- +- val = ret & 0xffff; +- val &= ~clear; +- val |= set; +- +- return phy_write(phydev, AT803X_DEBUG_DATA, val); +-} +- +-static int at803x_write_page(struct phy_device *phydev, int page) +-{ +- int mask; +- int set; +- +- if (page == AT803X_PAGE_COPPER) { +- set = AT803X_BT_BX_REG_SEL; +- mask = 0; +- } else { +- set = 0; +- mask = AT803X_BT_BX_REG_SEL; +- } +- +- return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); +-} +- +-static int at803x_read_page(struct phy_device *phydev) +-{ +- int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); +- +- if (ccr < 0) +- return ccr; +- +- if (ccr & AT803X_BT_BX_REG_SEL) +- return AT803X_PAGE_COPPER; +- +- return AT803X_PAGE_FIBER; +-} +- +-static int at803x_enable_rx_delay(struct phy_device *phydev) +-{ +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, +- AT803X_DEBUG_RX_CLK_DLY_EN); +-} +- +-static int at803x_enable_tx_delay(struct phy_device *phydev) +-{ +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, +- AT803X_DEBUG_TX_CLK_DLY_EN); +-} +- +-static int at803x_disable_rx_delay(struct phy_device *phydev) +-{ +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- AT803X_DEBUG_RX_CLK_DLY_EN, 0); +-} +- +-static int at803x_disable_tx_delay(struct phy_device *phydev) +-{ +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, +- AT803X_DEBUG_TX_CLK_DLY_EN, 0); +-} +- +-/* save relevant PHY registers to private copy */ +-static void at803x_context_save(struct phy_device *phydev, +- struct at803x_context *context) +-{ +- context->bmcr = phy_read(phydev, MII_BMCR); +- context->advertise = phy_read(phydev, MII_ADVERTISE); +- context->control1000 = phy_read(phydev, MII_CTRL1000); +- context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); +- context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); +- context->led_control = phy_read(phydev, AT803X_LED_CONTROL); +-} +- +-/* restore relevant PHY registers from private copy */ +-static void at803x_context_restore(struct phy_device *phydev, +- const struct at803x_context *context) +-{ +- phy_write(phydev, MII_BMCR, context->bmcr); +- phy_write(phydev, MII_ADVERTISE, context->advertise); +- phy_write(phydev, MII_CTRL1000, context->control1000); +- phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); +- phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); +- phy_write(phydev, AT803X_LED_CONTROL, context->led_control); +-} +- +-static int at803x_set_wol(struct phy_device *phydev, +- struct ethtool_wolinfo *wol) +-{ +- int ret, irq_enabled; +- +- if (wol->wolopts & WAKE_MAGIC) { +- struct net_device *ndev = phydev->attached_dev; +- const u8 *mac; +- unsigned int i; +- static const unsigned int offsets[] = { +- AT803X_LOC_MAC_ADDR_32_47_OFFSET, +- AT803X_LOC_MAC_ADDR_16_31_OFFSET, +- AT803X_LOC_MAC_ADDR_0_15_OFFSET, +- }; +- +- if (!ndev) +- return -ENODEV; +- +- mac = (const u8 *)ndev->dev_addr; +- +- if (!is_valid_ether_addr(mac)) +- return -EINVAL; +- +- for (i = 0; i < 3; i++) +- phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], +- mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); +- +- /* Enable WOL interrupt */ +- ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); +- if (ret) +- return ret; +- } else { +- /* Disable WOL interrupt */ +- ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); +- if (ret) +- return ret; +- } +- +- /* Clear WOL status */ +- ret = phy_read(phydev, AT803X_INTR_STATUS); +- if (ret < 0) +- return ret; +- +- /* Check if there are other interrupts except for WOL triggered when PHY is +- * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can +- * be passed up to the interrupt PIN. +- */ +- irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); +- if (irq_enabled < 0) +- return irq_enabled; +- +- irq_enabled &= ~AT803X_INTR_ENABLE_WOL; +- if (ret & irq_enabled && !phy_polling_mode(phydev)) +- phy_trigger_machine(phydev); +- +- return 0; +-} +- +-static void at803x_get_wol(struct phy_device *phydev, +- struct ethtool_wolinfo *wol) +-{ +- int value; +- +- wol->supported = WAKE_MAGIC; +- wol->wolopts = 0; +- +- value = phy_read(phydev, AT803X_INTR_ENABLE); +- if (value < 0) +- return; +- +- if (value & AT803X_INTR_ENABLE_WOL) +- wol->wolopts |= WAKE_MAGIC; +-} +- +-static int qca83xx_get_sset_count(struct phy_device *phydev) +-{ +- return ARRAY_SIZE(qca83xx_hw_stats); +-} +- +-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { +- strscpy(data + i * ETH_GSTRING_LEN, +- qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); +- } +-} +- +-static u64 qca83xx_get_stat(struct phy_device *phydev, int i) +-{ +- struct at803x_hw_stat stat = qca83xx_hw_stats[i]; +- struct at803x_priv *priv = phydev->priv; +- int val; +- u64 ret; +- +- if (stat.access_type == MMD) +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); +- else +- val = phy_read(phydev, stat.reg); +- +- if (val < 0) { +- ret = U64_MAX; +- } else { +- val = val & stat.mask; +- priv->stats[i] += val; +- ret = priv->stats[i]; +- } +- +- return ret; +-} +- +-static void qca83xx_get_stats(struct phy_device *phydev, +- struct ethtool_stats *stats, u64 *data) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) +- data[i] = qca83xx_get_stat(phydev, i); +-} +- +-static int at803x_suspend(struct phy_device *phydev) +-{ +- int value; +- int wol_enabled; +- +- value = phy_read(phydev, AT803X_INTR_ENABLE); +- wol_enabled = value & AT803X_INTR_ENABLE_WOL; +- +- if (wol_enabled) +- value = BMCR_ISOLATE; +- else +- value = BMCR_PDOWN; +- +- phy_modify(phydev, MII_BMCR, 0, value); +- +- return 0; +-} +- +-static int at803x_resume(struct phy_device *phydev) +-{ +- return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); +-} +- +-static int at803x_parse_dt(struct phy_device *phydev) +-{ +- struct device_node *node = phydev->mdio.dev.of_node; +- struct at803x_priv *priv = phydev->priv; +- u32 freq, strength, tw; +- unsigned int sel; +- int ret; +- +- if (!IS_ENABLED(CONFIG_OF_MDIO)) +- return 0; +- +- if (of_property_read_bool(node, "qca,disable-smarteee")) +- priv->flags |= AT803X_DISABLE_SMARTEEE; +- +- if (of_property_read_bool(node, "qca,disable-hibernation-mode")) +- priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; +- +- if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { +- if (!tw || tw > 255) { +- phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); +- return -EINVAL; +- } +- priv->smarteee_lpi_tw_1g = tw; +- } +- +- if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { +- if (!tw || tw > 255) { +- phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); +- return -EINVAL; +- } +- priv->smarteee_lpi_tw_100m = tw; +- } +- +- ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); +- if (!ret) { +- switch (freq) { +- case 25000000: +- sel = AT803X_CLK_OUT_25MHZ_XTAL; +- break; +- case 50000000: +- sel = AT803X_CLK_OUT_50MHZ_PLL; +- break; +- case 62500000: +- sel = AT803X_CLK_OUT_62_5MHZ_PLL; +- break; +- case 125000000: +- sel = AT803X_CLK_OUT_125MHZ_PLL; +- break; +- default: +- phydev_err(phydev, "invalid qca,clk-out-frequency\n"); +- return -EINVAL; +- } +- +- priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); +- priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; +- } +- +- ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); +- if (!ret) { +- priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; +- switch (strength) { +- case AR803X_STRENGTH_FULL: +- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; +- break; +- case AR803X_STRENGTH_HALF: +- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; +- break; +- case AR803X_STRENGTH_QUARTER: +- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; +- break; +- default: +- phydev_err(phydev, "invalid qca,clk-out-strength\n"); +- return -EINVAL; +- } +- } +- +- return 0; +-} +- +-static int at803x_probe(struct phy_device *phydev) +-{ +- struct device *dev = &phydev->mdio.dev; +- struct at803x_priv *priv; +- int ret; +- +- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- /* Init LED polarity mode to -1 */ +- priv->led_polarity_mode = -1; +- +- phydev->priv = priv; +- +- ret = at803x_parse_dt(phydev); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int at803x_get_features(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- int err; +- +- err = genphy_read_abilities(phydev); +- if (err) +- return err; +- +- if (phydev->drv->phy_id != ATH8031_PHY_ID) +- return 0; +- +- /* AR8031/AR8033 have different status registers +- * for copper and fiber operation. However, the +- * extended status register is the same for both +- * operation modes. +- * +- * As a result of that, ESTATUS_1000_XFULL is set +- * to 1 even when operating in copper TP mode. +- * +- * Remove this mode from the supported link modes +- * when not operating in 1000BaseX mode. +- */ +- if (!priv->is_1000basex) +- linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, +- phydev->supported); +- +- return 0; +-} +- +-static int at803x_smarteee_config(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- u16 mask = 0, val = 0; +- int ret; +- +- if (priv->flags & AT803X_DISABLE_SMARTEEE) +- return phy_modify_mmd(phydev, MDIO_MMD_PCS, +- AT803X_MMD3_SMARTEEE_CTL3, +- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); +- +- if (priv->smarteee_lpi_tw_1g) { +- mask |= 0xff00; +- val |= priv->smarteee_lpi_tw_1g << 8; +- } +- if (priv->smarteee_lpi_tw_100m) { +- mask |= 0x00ff; +- val |= priv->smarteee_lpi_tw_100m; +- } +- if (!mask) +- return 0; +- +- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, +- mask, val); +- if (ret) +- return ret; +- +- return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, +- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, +- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); +-} +- +-static int at803x_clk_out_config(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- +- if (!priv->clk_25m_mask) +- return 0; +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, +- priv->clk_25m_mask, priv->clk_25m_reg); +-} +- +-static int at8031_pll_config(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- +- /* The default after hardware reset is PLL OFF. After a soft reset, the +- * values are retained. +- */ +- if (priv->flags & AT803X_KEEP_PLL_ENABLED) +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, +- 0, AT803X_DEBUG_PLL_ON); +- else +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, +- AT803X_DEBUG_PLL_ON, 0); +-} +- +-static int at803x_hibernation_mode_config(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- +- /* The default after hardware reset is hibernation mode enabled. After +- * software reset, the value is retained. +- */ +- if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) +- return 0; +- +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, +- AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); +-} +- +-static int at803x_config_init(struct phy_device *phydev) +-{ +- int ret; +- +- /* The RX and TX delay default is: +- * after HW reset: RX delay enabled and TX delay disabled +- * after SW reset: RX delay enabled, while TX delay retains the +- * value before reset. +- */ +- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || +- phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) +- ret = at803x_enable_rx_delay(phydev); +- else +- ret = at803x_disable_rx_delay(phydev); +- if (ret < 0) +- return ret; +- +- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || +- phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) +- ret = at803x_enable_tx_delay(phydev); +- else +- ret = at803x_disable_tx_delay(phydev); +- if (ret < 0) +- return ret; +- +- ret = at803x_smarteee_config(phydev); +- if (ret < 0) +- return ret; +- +- ret = at803x_clk_out_config(phydev); +- if (ret < 0) +- return ret; +- +- ret = at803x_hibernation_mode_config(phydev); +- if (ret < 0) +- return ret; +- +- /* Ar803x extended next page bit is enabled by default. Cisco +- * multigig switches read this bit and attempt to negotiate 10Gbps +- * rates even if the next page bit is disabled. This is incorrect +- * behaviour but we still need to accommodate it. XNP is only needed +- * for 10Gbps support, so disable XNP. +- */ +- return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); +-} +- +-static int at803x_ack_interrupt(struct phy_device *phydev) +-{ +- int err; +- +- err = phy_read(phydev, AT803X_INTR_STATUS); +- +- return (err < 0) ? err : 0; +-} +- +-static int at803x_config_intr(struct phy_device *phydev) +-{ +- int err; +- int value; +- +- value = phy_read(phydev, AT803X_INTR_ENABLE); +- +- if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { +- /* Clear any pending interrupts */ +- err = at803x_ack_interrupt(phydev); +- if (err) +- return err; +- +- value |= AT803X_INTR_ENABLE_AUTONEG_ERR; +- value |= AT803X_INTR_ENABLE_SPEED_CHANGED; +- value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; +- value |= AT803X_INTR_ENABLE_LINK_FAIL; +- value |= AT803X_INTR_ENABLE_LINK_SUCCESS; +- +- err = phy_write(phydev, AT803X_INTR_ENABLE, value); +- } else { +- err = phy_write(phydev, AT803X_INTR_ENABLE, 0); +- if (err) +- return err; +- +- /* Clear any pending interrupts */ +- err = at803x_ack_interrupt(phydev); +- } +- +- return err; +-} +- +-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) +-{ +- int irq_status, int_enabled; +- +- irq_status = phy_read(phydev, AT803X_INTR_STATUS); +- if (irq_status < 0) { +- phy_error(phydev); +- return IRQ_NONE; +- } +- +- /* Read the current enabled interrupts */ +- int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); +- if (int_enabled < 0) { +- phy_error(phydev); +- return IRQ_NONE; +- } +- +- /* See if this was one of our enabled interrupts */ +- if (!(irq_status & int_enabled)) +- return IRQ_NONE; +- +- phy_trigger_machine(phydev); +- +- return IRQ_HANDLED; +-} +- +-static void at803x_link_change_notify(struct phy_device *phydev) +-{ +- /* +- * Conduct a hardware reset for AT8030 every time a link loss is +- * signalled. This is necessary to circumvent a hardware bug that +- * occurs when the cable is unplugged while TX packets are pending +- * in the FIFO. In such cases, the FIFO enters an error mode it +- * cannot recover from by software. +- */ +- if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { +- struct at803x_context context; +- +- at803x_context_save(phydev, &context); +- +- phy_device_reset(phydev, 1); +- usleep_range(1000, 2000); +- phy_device_reset(phydev, 0); +- usleep_range(1000, 2000); +- +- at803x_context_restore(phydev, &context); +- +- phydev_dbg(phydev, "%s(): phy was reset\n", __func__); +- } +-} +- +-static int at803x_read_specific_status(struct phy_device *phydev, +- struct at803x_ss_mask ss_mask) +-{ +- int ss; +- +- /* Read the AT8035 PHY-Specific Status register, which indicates the +- * speed and duplex that the PHY is actually using, irrespective of +- * whether we are in autoneg mode or not. +- */ +- ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); +- if (ss < 0) +- return ss; +- +- if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { +- int sfc, speed; +- +- sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); +- if (sfc < 0) +- return sfc; +- +- speed = ss & ss_mask.speed_mask; +- speed >>= ss_mask.speed_shift; +- +- switch (speed) { +- case AT803X_SS_SPEED_10: +- phydev->speed = SPEED_10; +- break; +- case AT803X_SS_SPEED_100: +- phydev->speed = SPEED_100; +- break; +- case AT803X_SS_SPEED_1000: +- phydev->speed = SPEED_1000; +- break; +- case QCA808X_SS_SPEED_2500: +- phydev->speed = SPEED_2500; +- break; +- } +- if (ss & AT803X_SS_DUPLEX) +- phydev->duplex = DUPLEX_FULL; +- else +- phydev->duplex = DUPLEX_HALF; +- +- if (ss & AT803X_SS_MDIX) +- phydev->mdix = ETH_TP_MDI_X; +- else +- phydev->mdix = ETH_TP_MDI; +- +- switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { +- case AT803X_SFC_MANUAL_MDI: +- phydev->mdix_ctrl = ETH_TP_MDI; +- break; +- case AT803X_SFC_MANUAL_MDIX: +- phydev->mdix_ctrl = ETH_TP_MDI_X; +- break; +- case AT803X_SFC_AUTOMATIC_CROSSOVER: +- phydev->mdix_ctrl = ETH_TP_MDI_AUTO; +- break; +- } +- } +- +- return 0; +-} +- +-static int at803x_read_status(struct phy_device *phydev) +-{ +- struct at803x_ss_mask ss_mask = { 0 }; +- int err, old_link = phydev->link; +- +- /* Update the link, but return if there was an error */ +- err = genphy_update_link(phydev); +- if (err) +- return err; +- +- /* why bother the PHY if nothing can have changed */ +- if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) +- return 0; +- +- phydev->speed = SPEED_UNKNOWN; +- phydev->duplex = DUPLEX_UNKNOWN; +- phydev->pause = 0; +- phydev->asym_pause = 0; +- +- err = genphy_read_lpa(phydev); +- if (err < 0) +- return err; +- +- ss_mask.speed_mask = AT803X_SS_SPEED_MASK; +- ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK); +- err = at803x_read_specific_status(phydev, ss_mask); +- if (err < 0) +- return err; +- +- if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) +- phy_resolve_aneg_pause(phydev); +- +- return 0; +-} +- +-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) +-{ +- u16 val; +- +- switch (ctrl) { +- case ETH_TP_MDI: +- val = AT803X_SFC_MANUAL_MDI; +- break; +- case ETH_TP_MDI_X: +- val = AT803X_SFC_MANUAL_MDIX; +- break; +- case ETH_TP_MDI_AUTO: +- val = AT803X_SFC_AUTOMATIC_CROSSOVER; +- break; +- default: +- return 0; +- } +- +- return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, +- AT803X_SFC_MDI_CROSSOVER_MODE_M, +- FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); +-} +- +-static int at803x_prepare_config_aneg(struct phy_device *phydev) +-{ +- int ret; +- +- ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); +- if (ret < 0) +- return ret; +- +- /* Changes of the midx bits are disruptive to the normal operation; +- * therefore any changes to these registers must be followed by a +- * software reset to take effect. +- */ +- if (ret == 1) { +- ret = genphy_soft_reset(phydev); +- if (ret < 0) +- return ret; +- } +- +- return 0; +-} +- +-static int at803x_config_aneg(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- int ret; +- +- ret = at803x_prepare_config_aneg(phydev); +- if (ret) +- return ret; +- +- if (priv->is_1000basex) +- return genphy_c37_config_aneg(phydev); +- +- return genphy_config_aneg(phydev); +-} +- +-static int at803x_get_downshift(struct phy_device *phydev, u8 *d) +-{ +- int val; +- +- val = phy_read(phydev, AT803X_SMART_SPEED); +- if (val < 0) +- return val; +- +- if (val & AT803X_SMART_SPEED_ENABLE) +- *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; +- else +- *d = DOWNSHIFT_DEV_DISABLE; +- +- return 0; +-} +- +-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) +-{ +- u16 mask, set; +- int ret; +- +- switch (cnt) { +- case DOWNSHIFT_DEV_DEFAULT_COUNT: +- cnt = AT803X_DEFAULT_DOWNSHIFT; +- fallthrough; +- case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: +- set = AT803X_SMART_SPEED_ENABLE | +- AT803X_SMART_SPEED_BYPASS_TIMER | +- FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); +- mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; +- break; +- case DOWNSHIFT_DEV_DISABLE: +- set = 0; +- mask = AT803X_SMART_SPEED_ENABLE | +- AT803X_SMART_SPEED_BYPASS_TIMER; +- break; +- default: +- return -EINVAL; +- } +- +- ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); +- +- /* After changing the smart speed settings, we need to perform a +- * software reset, use phy_init_hw() to make sure we set the +- * reapply any values which might got lost during software reset. +- */ +- if (ret == 1) +- ret = phy_init_hw(phydev); +- +- return ret; +-} +- +-static int at803x_get_tunable(struct phy_device *phydev, +- struct ethtool_tunable *tuna, void *data) +-{ +- switch (tuna->id) { +- case ETHTOOL_PHY_DOWNSHIFT: +- return at803x_get_downshift(phydev, data); +- default: +- return -EOPNOTSUPP; +- } +-} +- +-static int at803x_set_tunable(struct phy_device *phydev, +- struct ethtool_tunable *tuna, const void *data) +-{ +- switch (tuna->id) { +- case ETHTOOL_PHY_DOWNSHIFT: +- return at803x_set_downshift(phydev, *(const u8 *)data); +- default: +- return -EOPNOTSUPP; +- } +-} +- +-static int at803x_cable_test_result_trans(u16 status) +-{ +- switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { +- case AT803X_CDT_STATUS_STAT_NORMAL: +- return ETHTOOL_A_CABLE_RESULT_CODE_OK; +- case AT803X_CDT_STATUS_STAT_SHORT: +- return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; +- case AT803X_CDT_STATUS_STAT_OPEN: +- return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; +- case AT803X_CDT_STATUS_STAT_FAIL: +- default: +- return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; +- } +-} +- +-static bool at803x_cdt_test_failed(u16 status) +-{ +- return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == +- AT803X_CDT_STATUS_STAT_FAIL; +-} +- +-static bool at803x_cdt_fault_length_valid(u16 status) +-{ +- switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { +- case AT803X_CDT_STATUS_STAT_OPEN: +- case AT803X_CDT_STATUS_STAT_SHORT: +- return true; +- } +- return false; +-} +- +-static int at803x_cdt_fault_length(int dt) +-{ +- /* According to the datasheet the distance to the fault is +- * DELTA_TIME * 0.824 meters. +- * +- * The author suspect the correct formula is: +- * +- * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 +- * +- * where c is the speed of light, VF is the velocity factor of +- * the twisted pair cable, 125MHz the counter frequency and +- * we need to divide by 2 because the hardware will measure the +- * round trip time to the fault and back to the PHY. +- * +- * With a VF of 0.69 we get the factor 0.824 mentioned in the +- * datasheet. +- */ +- return (dt * 824) / 10; +-} +- +-static int at803x_cdt_start(struct phy_device *phydev, +- u32 cdt_start) +-{ +- return phy_write(phydev, AT803X_CDT, cdt_start); +-} +- +-static int at803x_cdt_wait_for_completion(struct phy_device *phydev, +- u32 cdt_en) +-{ +- int val, ret; +- +- /* One test run takes about 25ms */ +- ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, +- !(val & cdt_en), +- 30000, 100000, true); +- +- return ret < 0 ? ret : 0; +-} +- +-static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) +-{ +- static const int ethtool_pair[] = { +- ETHTOOL_A_CABLE_PAIR_A, +- ETHTOOL_A_CABLE_PAIR_B, +- ETHTOOL_A_CABLE_PAIR_C, +- ETHTOOL_A_CABLE_PAIR_D, +- }; +- int ret, val; +- +- val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | +- AT803X_CDT_ENABLE_TEST; +- ret = at803x_cdt_start(phydev, val); +- if (ret) +- return ret; +- +- ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); +- if (ret) +- return ret; +- +- val = phy_read(phydev, AT803X_CDT_STATUS); +- if (val < 0) +- return val; +- +- if (at803x_cdt_test_failed(val)) +- return 0; +- +- ethnl_cable_test_result(phydev, ethtool_pair[pair], +- at803x_cable_test_result_trans(val)); +- +- if (at803x_cdt_fault_length_valid(val)) { +- val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); +- ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], +- at803x_cdt_fault_length(val)); +- } +- +- return 1; +-} +- +-static int at803x_cable_test_get_status(struct phy_device *phydev, +- bool *finished, unsigned long pair_mask) +-{ +- int retries = 20; +- int pair, ret; +- +- *finished = false; +- +- /* According to the datasheet the CDT can be performed when +- * there is no link partner or when the link partner is +- * auto-negotiating. Starting the test will restart the AN +- * automatically. It seems that doing this repeatedly we will +- * get a slot where our link partner won't disturb our +- * measurement. +- */ +- while (pair_mask && retries--) { +- for_each_set_bit(pair, &pair_mask, 4) { +- ret = at803x_cable_test_one_pair(phydev, pair); +- if (ret < 0) +- return ret; +- if (ret) +- clear_bit(pair, &pair_mask); +- } +- if (pair_mask) +- msleep(250); +- } +- +- *finished = true; +- +- return 0; +-} +- +-static void at803x_cable_test_autoneg(struct phy_device *phydev) +-{ +- /* Enable auto-negotiation, but advertise no capabilities, no link +- * will be established. A restart of the auto-negotiation is not +- * required, because the cable test will automatically break the link. +- */ +- phy_write(phydev, MII_BMCR, BMCR_ANENABLE); +- phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); +-} +- +-static int at803x_cable_test_start(struct phy_device *phydev) +-{ +- at803x_cable_test_autoneg(phydev); +- /* we do all the (time consuming) work later */ +- return 0; +-} +- +-static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, +- unsigned int selector) +-{ +- struct phy_device *phydev = rdev_get_drvdata(rdev); +- +- if (selector) +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, +- 0, AT803X_DEBUG_RGMII_1V8); +- else +- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, +- AT803X_DEBUG_RGMII_1V8, 0); +-} +- +-static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) +-{ +- struct phy_device *phydev = rdev_get_drvdata(rdev); +- int val; +- +- val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); +- if (val < 0) +- return val; +- +- return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; +-} +- +-static const struct regulator_ops vddio_regulator_ops = { +- .list_voltage = regulator_list_voltage_table, +- .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, +- .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, +-}; +- +-static const unsigned int vddio_voltage_table[] = { +- 1500000, +- 1800000, +-}; +- +-static const struct regulator_desc vddio_desc = { +- .name = "vddio", +- .of_match = of_match_ptr("vddio-regulator"), +- .n_voltages = ARRAY_SIZE(vddio_voltage_table), +- .volt_table = vddio_voltage_table, +- .ops = &vddio_regulator_ops, +- .type = REGULATOR_VOLTAGE, +- .owner = THIS_MODULE, +-}; +- +-static const struct regulator_ops vddh_regulator_ops = { +-}; +- +-static const struct regulator_desc vddh_desc = { +- .name = "vddh", +- .of_match = of_match_ptr("vddh-regulator"), +- .n_voltages = 1, +- .fixed_uV = 2500000, +- .ops = &vddh_regulator_ops, +- .type = REGULATOR_VOLTAGE, +- .owner = THIS_MODULE, +-}; +- +-static int at8031_register_regulators(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- struct device *dev = &phydev->mdio.dev; +- struct regulator_config config = { }; +- +- config.dev = dev; +- config.driver_data = phydev; +- +- priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); +- if (IS_ERR(priv->vddio_rdev)) { +- phydev_err(phydev, "failed to register VDDIO regulator\n"); +- return PTR_ERR(priv->vddio_rdev); +- } +- +- priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); +- if (IS_ERR(priv->vddh_rdev)) { +- phydev_err(phydev, "failed to register VDDH regulator\n"); +- return PTR_ERR(priv->vddh_rdev); +- } +- +- return 0; +-} +- +-static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) +-{ +- struct phy_device *phydev = upstream; +- __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); +- __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); +- DECLARE_PHY_INTERFACE_MASK(interfaces); +- phy_interface_t iface; +- +- linkmode_zero(phy_support); +- phylink_set(phy_support, 1000baseX_Full); +- phylink_set(phy_support, 1000baseT_Full); +- phylink_set(phy_support, Autoneg); +- phylink_set(phy_support, Pause); +- phylink_set(phy_support, Asym_Pause); +- +- linkmode_zero(sfp_support); +- sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); +- /* Some modules support 10G modes as well as others we support. +- * Mask out non-supported modes so the correct interface is picked. +- */ +- linkmode_and(sfp_support, phy_support, sfp_support); +- +- if (linkmode_empty(sfp_support)) { +- dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); +- return -EINVAL; +- } +- +- iface = sfp_select_interface(phydev->sfp_bus, sfp_support); +- +- /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes +- * interface for use with SFP modules. +- * However, some copper modules detected as having a preferred SGMII +- * interface do default to and function in 1000Base-X mode, so just +- * print a warning and allow such modules, as they may have some chance +- * of working. +- */ +- if (iface == PHY_INTERFACE_MODE_SGMII) +- dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); +- else if (iface != PHY_INTERFACE_MODE_1000BASEX) +- return -EINVAL; +- +- return 0; +-} +- +-static const struct sfp_upstream_ops at8031_sfp_ops = { +- .attach = phy_sfp_attach, +- .detach = phy_sfp_detach, +- .module_insert = at8031_sfp_insert, +-}; +- +-static int at8031_parse_dt(struct phy_device *phydev) +-{ +- struct device_node *node = phydev->mdio.dev.of_node; +- struct at803x_priv *priv = phydev->priv; +- int ret; +- +- if (of_property_read_bool(node, "qca,keep-pll-enabled")) +- priv->flags |= AT803X_KEEP_PLL_ENABLED; +- +- ret = at8031_register_regulators(phydev); +- if (ret < 0) +- return ret; +- +- ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, +- "vddio"); +- if (ret) { +- phydev_err(phydev, "failed to get VDDIO regulator\n"); +- return ret; +- } +- +- /* Only AR8031/8033 support 1000Base-X for SFP modules */ +- return phy_sfp_probe(phydev, &at8031_sfp_ops); +-} +- +-static int at8031_probe(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- int mode_cfg; +- int ccr; +- int ret; +- +- ret = at803x_probe(phydev); +- if (ret) +- return ret; +- +- /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping +- * options. +- */ +- ret = at8031_parse_dt(phydev); +- if (ret) +- return ret; +- +- ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); +- if (ccr < 0) +- return ccr; +- mode_cfg = ccr & AT803X_MODE_CFG_MASK; +- +- switch (mode_cfg) { +- case AT803X_MODE_CFG_BX1000_RGMII_50OHM: +- case AT803X_MODE_CFG_BX1000_RGMII_75OHM: +- priv->is_1000basex = true; +- fallthrough; +- case AT803X_MODE_CFG_FX100_RGMII_50OHM: +- case AT803X_MODE_CFG_FX100_RGMII_75OHM: +- priv->is_fiber = true; +- break; +- } +- +- /* Disable WoL in 1588 register which is enabled +- * by default +- */ +- return phy_modify_mmd(phydev, MDIO_MMD_PCS, +- AT803X_PHY_MMD3_WOL_CTRL, +- AT803X_WOL_EN, 0); +-} +- +-static int at8031_config_init(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- int ret; +- +- /* Some bootloaders leave the fiber page selected. +- * Switch to the appropriate page (fiber or copper), as otherwise we +- * read the PHY capabilities from the wrong page. +- */ +- phy_lock_mdio_bus(phydev); +- ret = at803x_write_page(phydev, +- priv->is_fiber ? AT803X_PAGE_FIBER : +- AT803X_PAGE_COPPER); +- phy_unlock_mdio_bus(phydev); +- if (ret) +- return ret; +- +- ret = at8031_pll_config(phydev); +- if (ret < 0) +- return ret; +- +- return at803x_config_init(phydev); +-} +- +-static int at8031_set_wol(struct phy_device *phydev, +- struct ethtool_wolinfo *wol) +-{ +- int ret; +- +- /* First setup MAC address and enable WOL interrupt */ +- ret = at803x_set_wol(phydev, wol); +- if (ret) +- return ret; +- +- if (wol->wolopts & WAKE_MAGIC) +- /* Enable WOL function for 1588 */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, +- AT803X_PHY_MMD3_WOL_CTRL, +- 0, AT803X_WOL_EN); +- else +- /* Disable WoL function for 1588 */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, +- AT803X_PHY_MMD3_WOL_CTRL, +- AT803X_WOL_EN, 0); +- +- return ret; +-} +- +-static int at8031_config_intr(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- int err, value = 0; +- +- if (phydev->interrupts == PHY_INTERRUPT_ENABLED && +- priv->is_fiber) { +- /* Clear any pending interrupts */ +- err = at803x_ack_interrupt(phydev); +- if (err) +- return err; +- +- value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; +- value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; +- +- err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); +- if (err) +- return err; +- } +- +- return at803x_config_intr(phydev); +-} +- +-/* AR8031 and AR8033 share the same read status logic */ +-static int at8031_read_status(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- +- if (priv->is_1000basex) +- return genphy_c37_read_status(phydev); +- +- return at803x_read_status(phydev); +-} +- +-/* AR8031 and AR8035 share the same cable test get status reg */ +-static int at8031_cable_test_get_status(struct phy_device *phydev, +- bool *finished) +-{ +- return at803x_cable_test_get_status(phydev, finished, 0xf); +-} +- +-/* AR8031 and AR8035 share the same cable test start logic */ +-static int at8031_cable_test_start(struct phy_device *phydev) +-{ +- at803x_cable_test_autoneg(phydev); +- phy_write(phydev, MII_CTRL1000, 0); +- /* we do all the (time consuming) work later */ +- return 0; +-} +- +-/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ +-static int at8032_cable_test_get_status(struct phy_device *phydev, +- bool *finished) +-{ +- return at803x_cable_test_get_status(phydev, finished, 0x3); +-} +- +-static int at8035_parse_dt(struct phy_device *phydev) +-{ +- struct at803x_priv *priv = phydev->priv; +- +- /* Mask is set by the generic at803x_parse_dt +- * if property is set. Assume property is set +- * with the mask not zero. +- */ +- if (priv->clk_25m_mask) { +- /* Fixup for the AR8030/AR8035. This chip has another mask and +- * doesn't support the DSP reference. Eg. the lowest bit of the +- * mask. The upper two bits select the same frequencies. Mask +- * the lowest bit here. +- * +- * Warning: +- * There was no datasheet for the AR8030 available so this is +- * just a guess. But the AR8035 is listed as pin compatible +- * to the AR8030 so there might be a good chance it works on +- * the AR8030 too. +- */ +- priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; +- priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; +- } +- +- return 0; +-} +- +-/* AR8030 and AR8035 shared the same special mask for clk_25m */ +-static int at8035_probe(struct phy_device *phydev) +-{ +- int ret; +- +- ret = at803x_probe(phydev); +- if (ret) +- return ret; +- +- return at8035_parse_dt(phydev); +-} +- +-static int qca83xx_config_init(struct phy_device *phydev) +-{ +- u8 switch_revision; +- +- switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; +- +- switch (switch_revision) { +- case 1: +- /* For 100M waveform */ +- at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); +- /* Turn on Gigabit clock */ +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); +- break; +- +- case 2: +- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); +- fallthrough; +- case 4: +- phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); +- break; +- } +- +- /* Following original QCA sourcecode set port to prefer master */ +- phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); +- +- return 0; +-} +- +-static int qca8327_config_init(struct phy_device *phydev) +-{ +- /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. +- * Disable on init and enable only with 100m speed following +- * qca original source code. +- */ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, 0); +- +- return qca83xx_config_init(phydev); +-} +- +-static void qca83xx_link_change_notify(struct phy_device *phydev) +-{ +- /* Set DAC Amplitude adjustment to +6% for 100m on link running */ +- if (phydev->state == PHY_RUNNING) { +- if (phydev->speed == SPEED_100) +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, +- QCA8327_DEBUG_MANU_CTRL_EN); +- } else { +- /* Reset DAC Amplitude adjustment */ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, 0); +- } +-} +- +-static int qca83xx_resume(struct phy_device *phydev) +-{ +- int ret, val; +- +- /* Skip reset if not suspended */ +- if (!phydev->suspended) +- return 0; +- +- /* Reinit the port, reset values set by suspend */ +- qca83xx_config_init(phydev); +- +- /* Reset the port on port resume */ +- phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); +- +- /* On resume from suspend the switch execute a reset and +- * restart auto-negotiation. Wait for reset to complete. +- */ +- ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), +- 50000, 600000, true); +- if (ret) +- return ret; +- +- usleep_range(1000, 2000); +- +- return 0; +-} +- +-static int qca83xx_suspend(struct phy_device *phydev) +-{ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, +- AT803X_DEBUG_GATE_CLK_IN1000, 0); +- +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, +- AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | +- AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); +- +- return 0; +-} +- +-static int qca8337_suspend(struct phy_device *phydev) +-{ +- /* Only QCA8337 support actual suspend. */ +- genphy_suspend(phydev); +- +- return qca83xx_suspend(phydev); +-} +- +-static int qca8327_suspend(struct phy_device *phydev) +-{ +- u16 mask = 0; +- +- /* QCA8327 cause port unreliability when phy suspend +- * is set. +- */ +- mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); +- phy_modify(phydev, MII_BMCR, mask, 0); +- +- return qca83xx_suspend(phydev); +-} +- +-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) +-{ +- int ret; +- +- /* Enable fast retrain */ +- ret = genphy_c45_fast_retrain(phydev, true); +- if (ret) +- return ret; +- +- phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, +- QCA808X_TOP_OPTION1_DATA); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, +- QCA808X_MSE_THRESHOLD_20DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, +- QCA808X_MSE_THRESHOLD_17DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, +- QCA808X_MSE_THRESHOLD_27DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, +- QCA808X_MSE_THRESHOLD_28DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, +- QCA808X_MMD3_DEBUG_1_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, +- QCA808X_MMD3_DEBUG_4_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, +- QCA808X_MMD3_DEBUG_5_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, +- QCA808X_MMD3_DEBUG_3_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, +- QCA808X_MMD3_DEBUG_6_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, +- QCA808X_MMD3_DEBUG_2_VALUE); +- +- return 0; +-} +- +-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) +-{ +- u16 seed_value; +- +- if (!enable) +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +- QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); +- +- seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE); +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +- QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, +- FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | +- QCA808X_MASTER_SLAVE_SEED_ENABLE); +-} +- +-static bool qca808x_is_prefer_master(struct phy_device *phydev) +-{ +- return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || +- (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); +-} +- +-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) +-{ +- return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); +-} +- +-static int qca808x_config_init(struct phy_device *phydev) +-{ +- int ret; +- +- /* Active adc&vga on 802.3az for the link 1000M and 100M */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, +- QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); +- if (ret) +- return ret; +- +- /* Adjust the threshold on 802.3az for the link 1000M */ +- ret = phy_write_mmd(phydev, MDIO_MMD_PCS, +- QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, +- QCA808X_MMD3_AZ_TRAINING_VAL); +- if (ret) +- return ret; +- +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { +- /* Config the fast retrain for the link 2500M */ +- ret = qca808x_phy_fast_retrain_config(phydev); +- if (ret) +- return ret; +- +- ret = genphy_read_master_slave(phydev); +- if (ret < 0) +- return ret; +- +- if (!qca808x_is_prefer_master(phydev)) { +- /* Enable seed and configure lower ramdom seed to make phy +- * linked as slave mode. +- */ +- ret = qca808x_phy_ms_seed_enable(phydev, true); +- if (ret) +- return ret; +- } +- } +- +- /* Configure adc threshold as 100mv for the link 10M */ +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, +- QCA808X_ADC_THRESHOLD_MASK, +- QCA808X_ADC_THRESHOLD_100MV); +-} +- +-static int qca808x_read_status(struct phy_device *phydev) +-{ +- struct at803x_ss_mask ss_mask = { 0 }; +- int ret; +- +- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); +- if (ret < 0) +- return ret; +- +- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, +- ret & MDIO_AN_10GBT_STAT_LP2_5G); +- +- ret = genphy_read_status(phydev); +- if (ret) +- return ret; +- +- /* qca8081 takes the different bits for speed value from at803x */ +- ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; +- ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); +- ret = at803x_read_specific_status(phydev, ss_mask); +- if (ret < 0) +- return ret; +- +- if (phydev->link) { +- if (phydev->speed == SPEED_2500) +- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- else +- phydev->interface = PHY_INTERFACE_MODE_SGMII; +- } else { +- /* generate seed as a lower random value to make PHY linked as SLAVE easily, +- * except for master/slave configuration fault detected or the master mode +- * preferred. +- * +- * the reason for not putting this code into the function link_change_notify is +- * the corner case where the link partner is also the qca8081 PHY and the seed +- * value is configured as the same value, the link can't be up and no link change +- * occurs. +- */ +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { +- if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || +- qca808x_is_prefer_master(phydev)) { +- qca808x_phy_ms_seed_enable(phydev, false); +- } else { +- qca808x_phy_ms_seed_enable(phydev, true); +- } +- } +- } +- +- return 0; +-} +- +-static int qca808x_soft_reset(struct phy_device *phydev) +-{ +- int ret; +- +- ret = genphy_soft_reset(phydev); +- if (ret < 0) +- return ret; +- +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) +- ret = qca808x_phy_ms_seed_enable(phydev, true); +- +- return ret; +-} +- +-static bool qca808x_cdt_fault_length_valid(int cdt_code) +-{ +- switch (cdt_code) { +- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: +- return true; +- default: +- return false; +- } +-} +- +-static int qca808x_cable_test_result_trans(int cdt_code) +-{ +- switch (cdt_code) { +- case QCA808X_CDT_STATUS_STAT_NORMAL: +- return ETHTOOL_A_CABLE_RESULT_CODE_OK; +- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: +- return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; +- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: +- return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: +- return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; +- case QCA808X_CDT_STATUS_STAT_FAIL: +- default: +- return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; +- } +-} +- +-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, +- int result) +-{ +- int val; +- u32 cdt_length_reg = 0; +- +- switch (pair) { +- case ETHTOOL_A_CABLE_PAIR_A: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; +- break; +- case ETHTOOL_A_CABLE_PAIR_B: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; +- break; +- case ETHTOOL_A_CABLE_PAIR_C: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; +- break; +- case ETHTOOL_A_CABLE_PAIR_D: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; +- break; +- default: +- return -EINVAL; +- } +- +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); +- if (val < 0) +- return val; +- +- if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) +- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); +- else +- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); +- +- return at803x_cdt_fault_length(val); +-} +- +-static int qca808x_cable_test_start(struct phy_device *phydev) +-{ +- int ret; +- +- /* perform CDT with the following configs: +- * 1. disable hibernation. +- * 2. force PHY working in MDI mode. +- * 3. for PHY working in 1000BaseT. +- * 4. configure the threshold. +- */ +- +- ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); +- if (ret < 0) +- return ret; +- +- ret = at803x_config_mdix(phydev, ETH_TP_MDI); +- if (ret < 0) +- return ret; +- +- /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ +- phydev->duplex = DUPLEX_FULL; +- phydev->speed = SPEED_1000; +- ret = genphy_c45_pma_setup_forced(phydev); +- if (ret < 0) +- return ret; +- +- ret = genphy_setup_forced(phydev); +- if (ret < 0) +- return ret; +- +- /* configure the thresholds for open, short, pair ok test */ +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); +- +- return 0; +-} +- +-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, +- u16 status) +-{ +- int length, result; +- u16 pair_code; +- +- switch (pair) { +- case ETHTOOL_A_CABLE_PAIR_A: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_B: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_C: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_D: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); +- break; +- default: +- return -EINVAL; +- } +- +- result = qca808x_cable_test_result_trans(pair_code); +- ethnl_cable_test_result(phydev, pair, result); +- +- if (qca808x_cdt_fault_length_valid(pair_code)) { +- length = qca808x_cdt_fault_length(phydev, pair, result); +- ethnl_cable_test_fault_length(phydev, pair, length); +- } +- +- return 0; +-} +- +-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) +-{ +- int ret, val; +- +- *finished = false; +- +- val = QCA808X_CDT_ENABLE_TEST | +- QCA808X_CDT_LENGTH_UNIT; +- ret = at803x_cdt_start(phydev, val); +- if (ret) +- return ret; +- +- ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); +- if (ret) +- return ret; +- +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); +- if (val < 0) +- return val; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); +- if (ret) +- return ret; +- +- *finished = true; +- +- return 0; +-} +- +-static int qca808x_get_features(struct phy_device *phydev) +-{ +- int ret; +- +- ret = genphy_c45_pma_read_abilities(phydev); +- if (ret) +- return ret; +- +- /* The autoneg ability is not existed in bit3 of MMD7.1, +- * but it is supported by qca808x PHY, so we add it here +- * manually. +- */ +- linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); +- +- /* As for the qca8081 1G version chip, the 2500baseT ability is also +- * existed in the bit0 of MMD1.21, we need to remove it manually if +- * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. +- */ +- ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); +- if (ret < 0) +- return ret; +- +- if (QCA808X_PHY_CHIP_TYPE_1G & ret) +- linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); +- +- return 0; +-} +- +-static int qca808x_config_aneg(struct phy_device *phydev) +-{ +- int phy_ctrl = 0; +- int ret; +- +- ret = at803x_prepare_config_aneg(phydev); +- if (ret) +- return ret; +- +- /* The reg MII_BMCR also needs to be configured for force mode, the +- * genphy_config_aneg is also needed. +- */ +- if (phydev->autoneg == AUTONEG_DISABLE) +- genphy_c45_pma_setup_forced(phydev); +- +- if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) +- phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; +- +- ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, +- MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); +- if (ret < 0) +- return ret; +- +- return __genphy_config_aneg(phydev, ret); +-} +- +-static void qca808x_link_change_notify(struct phy_device *phydev) +-{ +- /* Assert interface sgmii fifo on link down, deassert it on link up, +- * the interface device address is always phy address added by 1. +- */ +- mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, +- MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, +- QCA8081_PHY_FIFO_RSTN, +- phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); +-} +- +-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, +- u16 *offload_trigger) +-{ +- /* Parsing specific to netdev trigger */ +- if (test_bit(TRIGGER_NETDEV_TX, &rules)) +- *offload_trigger |= QCA808X_LED_TX_BLINK; +- if (test_bit(TRIGGER_NETDEV_RX, &rules)) +- *offload_trigger |= QCA808X_LED_RX_BLINK; +- if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED10_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED100_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED1000_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED2500_ON; +- if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) +- *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; +- if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) +- *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; +- +- if (rules && !*offload_trigger) +- return -EOPNOTSUPP; +- +- /* Enable BLINK_CHECK_BYPASS by default to make the LED +- * blink even with duplex or speed mode not enabled. +- */ +- *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; +- +- return 0; +-} +- +-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN); +-} +- +-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- u16 offload_trigger = 0; +- +- if (index > 2) +- return -EINVAL; +- +- return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +-} +- +-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- u16 reg, offload_trigger = 0; +- int ret; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +- if (ret) +- return ret; +- +- ret = qca808x_led_hw_control_enable(phydev, index); +- if (ret) +- return ret; +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_PATTERN_MASK, +- offload_trigger); +-} +- +-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- int val; +- +- if (index > 2) +- return false; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); +- +- return !(val & QCA808X_LED_FORCE_EN); +-} +- +-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, +- unsigned long *rules) +-{ +- u16 reg; +- int val; +- +- if (index > 2) +- return -EINVAL; +- +- /* Check if we have hw control enabled */ +- if (qca808x_led_hw_control_status(phydev, index)) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); +- if (val & QCA808X_LED_TX_BLINK) +- set_bit(TRIGGER_NETDEV_TX, rules); +- if (val & QCA808X_LED_RX_BLINK) +- set_bit(TRIGGER_NETDEV_RX, rules); +- if (val & QCA808X_LED_SPEED10_ON) +- set_bit(TRIGGER_NETDEV_LINK_10, rules); +- if (val & QCA808X_LED_SPEED100_ON) +- set_bit(TRIGGER_NETDEV_LINK_100, rules); +- if (val & QCA808X_LED_SPEED1000_ON) +- set_bit(TRIGGER_NETDEV_LINK_1000, rules); +- if (val & QCA808X_LED_SPEED2500_ON) +- set_bit(TRIGGER_NETDEV_LINK_2500, rules); +- if (val & QCA808X_LED_HALF_DUPLEX_ON) +- set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); +- if (val & QCA808X_LED_FULL_DUPLEX_ON) +- set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); +- +- return 0; +-} +- +-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_PATTERN_MASK); +-} +- +-static int qca808x_led_brightness_set(struct phy_device *phydev, +- u8 index, enum led_brightness value) +-{ +- u16 reg; +- int ret; +- +- if (index > 2) +- return -EINVAL; +- +- if (!value) { +- ret = qca808x_led_hw_control_reset(phydev, index); +- if (ret) +- return ret; +- } +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, +- QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : +- QCA808X_LED_FORCE_OFF); +-} +- +-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, +- unsigned long *delay_on, +- unsigned long *delay_off) +-{ +- int ret; +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- /* Set blink to 50% off, 50% on at 4Hz by default */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, +- QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, +- QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); +- if (ret) +- return ret; +- +- /* We use BLINK_1 for normal blinking */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); +- if (ret) +- return ret; +- +- /* We set blink to 4Hz, aka 250ms */ +- *delay_on = 250 / 2; +- *delay_off = 250 / 2; +- +- return 0; +-} +- +-static int qca808x_led_polarity_set(struct phy_device *phydev, int index, +- unsigned long modes) +-{ +- struct at803x_priv *priv = phydev->priv; +- bool active_low = false; +- u32 mode; +- +- for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { +- switch (mode) { +- case PHY_LED_ACTIVE_LOW: +- active_low = true; +- break; +- default: +- return -EINVAL; +- } +- } +- +- /* PHY polarity is global and can't be set per LED. +- * To detect this, check if last requested polarity mode +- * match the new one. +- */ +- if (priv->led_polarity_mode >= 0 && +- priv->led_polarity_mode != active_low) { +- phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); +- return -EINVAL; +- } +- +- /* Save the last PHY polarity mode */ +- priv->led_polarity_mode = active_low; +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, +- QCA808X_MMD7_LED_POLARITY_CTRL, +- QCA808X_LED_ACTIVE_HIGH, +- active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); +-} +- +-static struct phy_driver at803x_driver[] = { +-{ +- /* Qualcomm Atheros AR8035 */ +- PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), +- .name = "Qualcomm Atheros AR8035", +- .flags = PHY_POLL_CABLE_TEST, +- .probe = at8035_probe, +- .config_aneg = at803x_config_aneg, +- .config_init = at803x_config_init, +- .soft_reset = genphy_soft_reset, +- .set_wol = at803x_set_wol, +- .get_wol = at803x_get_wol, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- /* PHY_GBIT_FEATURES */ +- .read_status = at803x_read_status, +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .get_tunable = at803x_get_tunable, +- .set_tunable = at803x_set_tunable, +- .cable_test_start = at8031_cable_test_start, +- .cable_test_get_status = at8031_cable_test_get_status, +-}, { +- /* Qualcomm Atheros AR8030 */ +- .phy_id = ATH8030_PHY_ID, +- .name = "Qualcomm Atheros AR8030", +- .phy_id_mask = AT8030_PHY_ID_MASK, +- .probe = at8035_probe, +- .config_init = at803x_config_init, +- .link_change_notify = at803x_link_change_notify, +- .set_wol = at803x_set_wol, +- .get_wol = at803x_get_wol, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- /* PHY_BASIC_FEATURES */ +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +-}, { +- /* Qualcomm Atheros AR8031/AR8033 */ +- PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), +- .name = "Qualcomm Atheros AR8031/AR8033", +- .flags = PHY_POLL_CABLE_TEST, +- .probe = at8031_probe, +- .config_init = at8031_config_init, +- .config_aneg = at803x_config_aneg, +- .soft_reset = genphy_soft_reset, +- .set_wol = at8031_set_wol, +- .get_wol = at803x_get_wol, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- .read_page = at803x_read_page, +- .write_page = at803x_write_page, +- .get_features = at803x_get_features, +- .read_status = at8031_read_status, +- .config_intr = at8031_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .get_tunable = at803x_get_tunable, +- .set_tunable = at803x_set_tunable, +- .cable_test_start = at8031_cable_test_start, +- .cable_test_get_status = at8031_cable_test_get_status, +-}, { +- /* Qualcomm Atheros AR8032 */ +- PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), +- .name = "Qualcomm Atheros AR8032", +- .probe = at803x_probe, +- .flags = PHY_POLL_CABLE_TEST, +- .config_init = at803x_config_init, +- .link_change_notify = at803x_link_change_notify, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- /* PHY_BASIC_FEATURES */ +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .cable_test_start = at803x_cable_test_start, +- .cable_test_get_status = at8032_cable_test_get_status, +-}, { +- /* ATHEROS AR9331 */ +- PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), +- .name = "Qualcomm Atheros AR9331 built-in PHY", +- .probe = at803x_probe, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- .flags = PHY_POLL_CABLE_TEST, +- /* PHY_BASIC_FEATURES */ +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .cable_test_start = at803x_cable_test_start, +- .cable_test_get_status = at8032_cable_test_get_status, +- .read_status = at803x_read_status, +- .soft_reset = genphy_soft_reset, +- .config_aneg = at803x_config_aneg, +-}, { +- /* Qualcomm Atheros QCA9561 */ +- PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), +- .name = "Qualcomm Atheros QCA9561 built-in PHY", +- .probe = at803x_probe, +- .suspend = at803x_suspend, +- .resume = at803x_resume, +- .flags = PHY_POLL_CABLE_TEST, +- /* PHY_BASIC_FEATURES */ +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .cable_test_start = at803x_cable_test_start, +- .cable_test_get_status = at8032_cable_test_get_status, +- .read_status = at803x_read_status, +- .soft_reset = genphy_soft_reset, +- .config_aneg = at803x_config_aneg, +-}, { +- /* QCA8337 */ +- .phy_id = QCA8337_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8337 internal PHY", +- /* PHY_GBIT_FEATURES */ +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca83xx_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8337_suspend, +- .resume = qca83xx_resume, +-}, { +- /* QCA8327-A from switch QCA8327-AL1A */ +- .phy_id = QCA8327_A_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8327-A internal PHY", +- /* PHY_GBIT_FEATURES */ +- .link_change_notify = qca83xx_link_change_notify, +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca8327_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8327_suspend, +- .resume = qca83xx_resume, +-}, { +- /* QCA8327-B from switch QCA8327-BL1A */ +- .phy_id = QCA8327_B_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8327-B internal PHY", +- /* PHY_GBIT_FEATURES */ +- .link_change_notify = qca83xx_link_change_notify, +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca8327_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8327_suspend, +- .resume = qca83xx_resume, +-}, { +- /* Qualcomm QCA8081 */ +- PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), +- .name = "Qualcomm QCA8081", +- .flags = PHY_POLL_CABLE_TEST, +- .probe = at803x_probe, +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .get_tunable = at803x_get_tunable, +- .set_tunable = at803x_set_tunable, +- .set_wol = at803x_set_wol, +- .get_wol = at803x_get_wol, +- .get_features = qca808x_get_features, +- .config_aneg = qca808x_config_aneg, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_status = qca808x_read_status, +- .config_init = qca808x_config_init, +- .soft_reset = qca808x_soft_reset, +- .cable_test_start = qca808x_cable_test_start, +- .cable_test_get_status = qca808x_cable_test_get_status, +- .link_change_notify = qca808x_link_change_notify, +- .led_brightness_set = qca808x_led_brightness_set, +- .led_blink_set = qca808x_led_blink_set, +- .led_hw_is_supported = qca808x_led_hw_is_supported, +- .led_hw_control_set = qca808x_led_hw_control_set, +- .led_hw_control_get = qca808x_led_hw_control_get, +- .led_polarity_set = qca808x_led_polarity_set, +-}, }; +- +-module_phy_driver(at803x_driver); +- +-static struct mdio_device_id __maybe_unused atheros_tbl[] = { +- { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, +- { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, +- { } +-}; +- +-MODULE_DEVICE_TABLE(mdio, atheros_tbl); +--- /dev/null ++++ b/drivers/net/phy/qcom/at803x.c +@@ -0,0 +1,2759 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * drivers/net/phy/at803x.c ++ * ++ * Driver for Qualcomm Atheros AR803x PHY ++ * ++ * Author: Matus Ujhelyi ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 ++#define AT803X_SFC_ASSERT_CRS BIT(11) ++#define AT803X_SFC_FORCE_LINK BIT(10) ++#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) ++#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 ++#define AT803X_SFC_MANUAL_MDIX 0x1 ++#define AT803X_SFC_MANUAL_MDI 0x0 ++#define AT803X_SFC_SQE_TEST BIT(2) ++#define AT803X_SFC_POLARITY_REVERSAL BIT(1) ++#define AT803X_SFC_DISABLE_JABBER BIT(0) ++ ++#define AT803X_SPECIFIC_STATUS 0x11 ++#define AT803X_SS_SPEED_MASK GENMASK(15, 14) ++#define AT803X_SS_SPEED_1000 2 ++#define AT803X_SS_SPEED_100 1 ++#define AT803X_SS_SPEED_10 0 ++#define AT803X_SS_DUPLEX BIT(13) ++#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) ++#define AT803X_SS_MDIX BIT(6) ++ ++#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) ++#define QCA808X_SS_SPEED_2500 4 ++ ++#define AT803X_INTR_ENABLE 0x12 ++#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) ++#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) ++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) ++#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) ++#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) ++#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) ++#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) ++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) ++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) ++#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) ++#define AT803X_INTR_ENABLE_WOL BIT(0) ++ ++#define AT803X_INTR_STATUS 0x13 ++ ++#define AT803X_SMART_SPEED 0x14 ++#define AT803X_SMART_SPEED_ENABLE BIT(5) ++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) ++#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) ++#define AT803X_CDT 0x16 ++#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) ++#define AT803X_CDT_ENABLE_TEST BIT(0) ++#define AT803X_CDT_STATUS 0x1c ++#define AT803X_CDT_STATUS_STAT_NORMAL 0 ++#define AT803X_CDT_STATUS_STAT_SHORT 1 ++#define AT803X_CDT_STATUS_STAT_OPEN 2 ++#define AT803X_CDT_STATUS_STAT_FAIL 3 ++#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) ++#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) ++#define AT803X_LED_CONTROL 0x18 ++ ++#define AT803X_PHY_MMD3_WOL_CTRL 0x8012 ++#define AT803X_WOL_EN BIT(5) ++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C ++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B ++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A ++#define AT803X_REG_CHIP_CONFIG 0x1f ++#define AT803X_BT_BX_REG_SEL 0x8000 ++ ++#define AT803X_DEBUG_ADDR 0x1D ++#define AT803X_DEBUG_DATA 0x1E ++ ++#define AT803X_MODE_CFG_MASK 0x0F ++#define AT803X_MODE_CFG_BASET_RGMII 0x00 ++#define AT803X_MODE_CFG_BASET_SGMII 0x01 ++#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 ++#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 ++#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 ++#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 ++#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 ++#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 ++#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B ++#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E ++#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F ++ ++#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ ++#define AT803X_PSSR_MR_AN_COMPLETE 0x0200 ++ ++#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 ++#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) ++#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) ++#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) ++ ++#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 ++#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) ++ ++#define AT803X_DEBUG_REG_HIB_CTRL 0x0b ++#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) ++#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) ++#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) ++ ++#define AT803X_DEBUG_REG_3C 0x3C ++ ++#define AT803X_DEBUG_REG_GREEN 0x3D ++#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) ++ ++#define AT803X_DEBUG_REG_1F 0x1F ++#define AT803X_DEBUG_PLL_ON BIT(2) ++#define AT803X_DEBUG_RGMII_1V8 BIT(3) ++ ++#define MDIO_AZ_DEBUG 0x800D ++ ++/* AT803x supports either the XTAL input pad, an internal PLL or the ++ * DSP as clock reference for the clock output pad. The XTAL reference ++ * is only used for 25 MHz output, all other frequencies need the PLL. ++ * The DSP as a clock reference is used in synchronous ethernet ++ * applications. ++ * ++ * By default the PLL is only enabled if there is a link. Otherwise ++ * the PHY will go into low power state and disabled the PLL. You can ++ * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always ++ * enabled. ++ */ ++#define AT803X_MMD7_CLK25M 0x8016 ++#define AT803X_CLK_OUT_MASK GENMASK(4, 2) ++#define AT803X_CLK_OUT_25MHZ_XTAL 0 ++#define AT803X_CLK_OUT_25MHZ_DSP 1 ++#define AT803X_CLK_OUT_50MHZ_PLL 2 ++#define AT803X_CLK_OUT_50MHZ_DSP 3 ++#define AT803X_CLK_OUT_62_5MHZ_PLL 4 ++#define AT803X_CLK_OUT_62_5MHZ_DSP 5 ++#define AT803X_CLK_OUT_125MHZ_PLL 6 ++#define AT803X_CLK_OUT_125MHZ_DSP 7 ++ ++/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask ++ * but doesn't support choosing between XTAL/PLL and DSP. ++ */ ++#define AT8035_CLK_OUT_MASK GENMASK(4, 3) ++ ++#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) ++#define AT803X_CLK_OUT_STRENGTH_FULL 0 ++#define AT803X_CLK_OUT_STRENGTH_HALF 1 ++#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 ++ ++#define AT803X_DEFAULT_DOWNSHIFT 5 ++#define AT803X_MIN_DOWNSHIFT 2 ++#define AT803X_MAX_DOWNSHIFT 9 ++ ++#define AT803X_MMD3_SMARTEEE_CTL1 0x805b ++#define AT803X_MMD3_SMARTEEE_CTL2 0x805c ++#define AT803X_MMD3_SMARTEEE_CTL3 0x805d ++#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) ++ ++#define ATH9331_PHY_ID 0x004dd041 ++#define ATH8030_PHY_ID 0x004dd076 ++#define ATH8031_PHY_ID 0x004dd074 ++#define ATH8032_PHY_ID 0x004dd023 ++#define ATH8035_PHY_ID 0x004dd072 ++#define AT8030_PHY_ID_MASK 0xffffffef ++ ++#define QCA8081_PHY_ID 0x004dd101 ++ ++#define QCA8327_A_PHY_ID 0x004dd033 ++#define QCA8327_B_PHY_ID 0x004dd034 ++#define QCA8337_PHY_ID 0x004dd036 ++#define QCA9561_PHY_ID 0x004dd042 ++#define QCA8K_PHY_ID_MASK 0xffffffff ++ ++#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) ++ ++#define AT803X_PAGE_FIBER 0 ++#define AT803X_PAGE_COPPER 1 ++ ++/* don't turn off internal PLL */ ++#define AT803X_KEEP_PLL_ENABLED BIT(0) ++#define AT803X_DISABLE_SMARTEEE BIT(1) ++ ++/* disable hibernation mode */ ++#define AT803X_DISABLE_HIBERNATION_MODE BIT(2) ++ ++/* ADC threshold */ ++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 ++#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) ++#define QCA808X_ADC_THRESHOLD_80MV 0 ++#define QCA808X_ADC_THRESHOLD_100MV 0xf0 ++#define QCA808X_ADC_THRESHOLD_200MV 0x0f ++#define QCA808X_ADC_THRESHOLD_300MV 0xff ++ ++/* CLD control */ ++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 ++#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) ++#define QCA808X_8023AZ_AFE_EN 0x90 ++ ++/* AZ control */ ++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 ++#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 ++#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E ++#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E ++#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 ++#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 ++ ++#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c ++#define QCA808X_TOP_OPTION1_DATA 0x0 ++ ++#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 ++#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 ++#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 ++#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad ++#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 ++#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 ++#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 ++#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 ++#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 ++#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 ++#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 ++#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 ++ ++/* master/slave seed config */ ++#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 ++#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) ++#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) ++#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 ++ ++/* Hibernation yields lower power consumpiton in contrast with normal operation mode. ++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. ++ */ ++#define QCA808X_DBG_AN_TEST 0xb ++#define QCA808X_HIBERNATION_EN BIT(15) ++ ++#define QCA808X_CDT_ENABLE_TEST BIT(15) ++#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) ++#define QCA808X_CDT_STATUS BIT(11) ++#define QCA808X_CDT_LENGTH_UNIT BIT(10) ++ ++#define QCA808X_MMD3_CDT_STATUS 0x8064 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 ++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) ++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) ++ ++#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) ++#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) ++#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) ++#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) ++ ++#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) ++#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) ++#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) ++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) ++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) ++ ++#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) ++#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) ++#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) ++#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) ++ ++/* NORMAL are MDI with type set to 0 */ ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI1) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI1) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI2) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI2) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI3) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI3) ++ ++/* Added for reference of existence but should be handled by wait_for_completion already */ ++#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) ++ ++#define QCA808X_MMD7_LED_GLOBAL 0x8073 ++#define QCA808X_LED_BLINK_1 GENMASK(11, 6) ++#define QCA808X_LED_BLINK_2 GENMASK(5, 0) ++/* Values are the same for both BLINK_1 and BLINK_2 */ ++#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) ++#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) ++#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) ++#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) ++#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) ++#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) ++#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) ++#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) ++#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) ++#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) ++#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) ++#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) ++#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) ++#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) ++#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) ++#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) ++#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) ++#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) ++ ++#define QCA808X_MMD7_LED2_CTRL 0x8074 ++#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 ++#define QCA808X_MMD7_LED1_CTRL 0x8076 ++#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 ++#define QCA808X_MMD7_LED0_CTRL 0x8078 ++#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) ++ ++/* LED hw control pattern is the same for every LED */ ++#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) ++#define QCA808X_LED_SPEED2500_ON BIT(15) ++#define QCA808X_LED_SPEED2500_BLINK BIT(14) ++/* Follow blink trigger even if duplex or speed condition doesn't match */ ++#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) ++#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) ++#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) ++#define QCA808X_LED_TX_BLINK BIT(10) ++#define QCA808X_LED_RX_BLINK BIT(9) ++#define QCA808X_LED_TX_ON_10MS BIT(8) ++#define QCA808X_LED_RX_ON_10MS BIT(7) ++#define QCA808X_LED_SPEED1000_ON BIT(6) ++#define QCA808X_LED_SPEED100_ON BIT(5) ++#define QCA808X_LED_SPEED10_ON BIT(4) ++#define QCA808X_LED_COLLISION_BLINK BIT(3) ++#define QCA808X_LED_SPEED1000_BLINK BIT(2) ++#define QCA808X_LED_SPEED100_BLINK BIT(1) ++#define QCA808X_LED_SPEED10_BLINK BIT(0) ++ ++#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 ++#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) ++ ++/* LED force ctrl is the same for every LED ++ * No documentation exist for this, not even internal one ++ * with NDA as QCOM gives only info about configuring ++ * hw control pattern rules and doesn't indicate any way ++ * to force the LED to specific mode. ++ * These define comes from reverse and testing and maybe ++ * lack of some info or some info are not entirely correct. ++ * For the basic LED control and hw control these finding ++ * are enough to support LED control in all the required APIs. ++ * ++ * On doing some comparison with implementation with qca807x, ++ * it was found that it's 1:1 equal to it and confirms all the ++ * reverse done. It was also found further specification with the ++ * force mode and the blink modes. ++ */ ++#define QCA808X_LED_FORCE_EN BIT(15) ++#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) ++#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) ++#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) ++#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) ++#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) ++ ++#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a ++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for ++ * LED to active high. It's not clear what BIT 3 and BIT 4 does. ++ */ ++#define QCA808X_LED_ACTIVE_HIGH BIT(6) ++ ++/* QCA808X 1G chip type */ ++#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d ++#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) ++ ++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 ++#define QCA8081_PHY_FIFO_RSTN BIT(11) ++ ++MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++MODULE_AUTHOR("Matus Ujhelyi"); ++MODULE_LICENSE("GPL"); ++ ++enum stat_access_type { ++ PHY, ++ MMD ++}; ++ ++struct at803x_hw_stat { ++ const char *string; ++ u8 reg; ++ u32 mask; ++ enum stat_access_type access_type; ++}; ++ ++static struct at803x_hw_stat qca83xx_hw_stats[] = { ++ { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, ++ { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, ++ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, ++}; ++ ++struct at803x_ss_mask { ++ u16 speed_mask; ++ u8 speed_shift; ++}; ++ ++struct at803x_priv { ++ int flags; ++ u16 clk_25m_reg; ++ u16 clk_25m_mask; ++ u8 smarteee_lpi_tw_1g; ++ u8 smarteee_lpi_tw_100m; ++ bool is_fiber; ++ bool is_1000basex; ++ struct regulator_dev *vddio_rdev; ++ struct regulator_dev *vddh_rdev; ++ u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; ++ int led_polarity_mode; ++}; ++ ++struct at803x_context { ++ u16 bmcr; ++ u16 advertise; ++ u16 control1000; ++ u16 int_enable; ++ u16 smart_speed; ++ u16 led_control; ++}; ++ ++static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); ++ if (ret < 0) ++ return ret; ++ ++ return phy_write(phydev, AT803X_DEBUG_DATA, data); ++} ++ ++static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); ++ if (ret < 0) ++ return ret; ++ ++ return phy_read(phydev, AT803X_DEBUG_DATA); ++} ++ ++static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, ++ u16 clear, u16 set) ++{ ++ u16 val; ++ int ret; ++ ++ ret = at803x_debug_reg_read(phydev, reg); ++ if (ret < 0) ++ return ret; ++ ++ val = ret & 0xffff; ++ val &= ~clear; ++ val |= set; ++ ++ return phy_write(phydev, AT803X_DEBUG_DATA, val); ++} ++ ++static int at803x_write_page(struct phy_device *phydev, int page) ++{ ++ int mask; ++ int set; ++ ++ if (page == AT803X_PAGE_COPPER) { ++ set = AT803X_BT_BX_REG_SEL; ++ mask = 0; ++ } else { ++ set = 0; ++ mask = AT803X_BT_BX_REG_SEL; ++ } ++ ++ return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); ++} ++ ++static int at803x_read_page(struct phy_device *phydev) ++{ ++ int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); ++ ++ if (ccr < 0) ++ return ccr; ++ ++ if (ccr & AT803X_BT_BX_REG_SEL) ++ return AT803X_PAGE_COPPER; ++ ++ return AT803X_PAGE_FIBER; ++} ++ ++static int at803x_enable_rx_delay(struct phy_device *phydev) ++{ ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, ++ AT803X_DEBUG_RX_CLK_DLY_EN); ++} ++ ++static int at803x_enable_tx_delay(struct phy_device *phydev) ++{ ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, ++ AT803X_DEBUG_TX_CLK_DLY_EN); ++} ++ ++static int at803x_disable_rx_delay(struct phy_device *phydev) ++{ ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ AT803X_DEBUG_RX_CLK_DLY_EN, 0); ++} ++ ++static int at803x_disable_tx_delay(struct phy_device *phydev) ++{ ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, ++ AT803X_DEBUG_TX_CLK_DLY_EN, 0); ++} ++ ++/* save relevant PHY registers to private copy */ ++static void at803x_context_save(struct phy_device *phydev, ++ struct at803x_context *context) ++{ ++ context->bmcr = phy_read(phydev, MII_BMCR); ++ context->advertise = phy_read(phydev, MII_ADVERTISE); ++ context->control1000 = phy_read(phydev, MII_CTRL1000); ++ context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); ++ context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); ++ context->led_control = phy_read(phydev, AT803X_LED_CONTROL); ++} ++ ++/* restore relevant PHY registers from private copy */ ++static void at803x_context_restore(struct phy_device *phydev, ++ const struct at803x_context *context) ++{ ++ phy_write(phydev, MII_BMCR, context->bmcr); ++ phy_write(phydev, MII_ADVERTISE, context->advertise); ++ phy_write(phydev, MII_CTRL1000, context->control1000); ++ phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); ++ phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); ++ phy_write(phydev, AT803X_LED_CONTROL, context->led_control); ++} ++ ++static int at803x_set_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ int ret, irq_enabled; ++ ++ if (wol->wolopts & WAKE_MAGIC) { ++ struct net_device *ndev = phydev->attached_dev; ++ const u8 *mac; ++ unsigned int i; ++ static const unsigned int offsets[] = { ++ AT803X_LOC_MAC_ADDR_32_47_OFFSET, ++ AT803X_LOC_MAC_ADDR_16_31_OFFSET, ++ AT803X_LOC_MAC_ADDR_0_15_OFFSET, ++ }; ++ ++ if (!ndev) ++ return -ENODEV; ++ ++ mac = (const u8 *)ndev->dev_addr; ++ ++ if (!is_valid_ether_addr(mac)) ++ return -EINVAL; ++ ++ for (i = 0; i < 3; i++) ++ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], ++ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); ++ ++ /* Enable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); ++ if (ret) ++ return ret; ++ } else { ++ /* Disable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); ++ if (ret) ++ return ret; ++ } ++ ++ /* Clear WOL status */ ++ ret = phy_read(phydev, AT803X_INTR_STATUS); ++ if (ret < 0) ++ return ret; ++ ++ /* Check if there are other interrupts except for WOL triggered when PHY is ++ * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can ++ * be passed up to the interrupt PIN. ++ */ ++ irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (irq_enabled < 0) ++ return irq_enabled; ++ ++ irq_enabled &= ~AT803X_INTR_ENABLE_WOL; ++ if (ret & irq_enabled && !phy_polling_mode(phydev)) ++ phy_trigger_machine(phydev); ++ ++ return 0; ++} ++ ++static void at803x_get_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ int value; ++ ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = 0; ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (value < 0) ++ return; ++ ++ if (value & AT803X_INTR_ENABLE_WOL) ++ wol->wolopts |= WAKE_MAGIC; ++} ++ ++static int qca83xx_get_sset_count(struct phy_device *phydev) ++{ ++ return ARRAY_SIZE(qca83xx_hw_stats); ++} ++ ++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { ++ strscpy(data + i * ETH_GSTRING_LEN, ++ qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); ++ } ++} ++ ++static u64 qca83xx_get_stat(struct phy_device *phydev, int i) ++{ ++ struct at803x_hw_stat stat = qca83xx_hw_stats[i]; ++ struct at803x_priv *priv = phydev->priv; ++ int val; ++ u64 ret; ++ ++ if (stat.access_type == MMD) ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); ++ else ++ val = phy_read(phydev, stat.reg); ++ ++ if (val < 0) { ++ ret = U64_MAX; ++ } else { ++ val = val & stat.mask; ++ priv->stats[i] += val; ++ ret = priv->stats[i]; ++ } ++ ++ return ret; ++} ++ ++static void qca83xx_get_stats(struct phy_device *phydev, ++ struct ethtool_stats *stats, u64 *data) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) ++ data[i] = qca83xx_get_stat(phydev, i); ++} ++ ++static int at803x_suspend(struct phy_device *phydev) ++{ ++ int value; ++ int wol_enabled; ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++ wol_enabled = value & AT803X_INTR_ENABLE_WOL; ++ ++ if (wol_enabled) ++ value = BMCR_ISOLATE; ++ else ++ value = BMCR_PDOWN; ++ ++ phy_modify(phydev, MII_BMCR, 0, value); ++ ++ return 0; ++} ++ ++static int at803x_resume(struct phy_device *phydev) ++{ ++ return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); ++} ++ ++static int at803x_parse_dt(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ struct at803x_priv *priv = phydev->priv; ++ u32 freq, strength, tw; ++ unsigned int sel; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_OF_MDIO)) ++ return 0; ++ ++ if (of_property_read_bool(node, "qca,disable-smarteee")) ++ priv->flags |= AT803X_DISABLE_SMARTEEE; ++ ++ if (of_property_read_bool(node, "qca,disable-hibernation-mode")) ++ priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; ++ ++ if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { ++ if (!tw || tw > 255) { ++ phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); ++ return -EINVAL; ++ } ++ priv->smarteee_lpi_tw_1g = tw; ++ } ++ ++ if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { ++ if (!tw || tw > 255) { ++ phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); ++ return -EINVAL; ++ } ++ priv->smarteee_lpi_tw_100m = tw; ++ } ++ ++ ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); ++ if (!ret) { ++ switch (freq) { ++ case 25000000: ++ sel = AT803X_CLK_OUT_25MHZ_XTAL; ++ break; ++ case 50000000: ++ sel = AT803X_CLK_OUT_50MHZ_PLL; ++ break; ++ case 62500000: ++ sel = AT803X_CLK_OUT_62_5MHZ_PLL; ++ break; ++ case 125000000: ++ sel = AT803X_CLK_OUT_125MHZ_PLL; ++ break; ++ default: ++ phydev_err(phydev, "invalid qca,clk-out-frequency\n"); ++ return -EINVAL; ++ } ++ ++ priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); ++ priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; ++ } ++ ++ ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); ++ if (!ret) { ++ priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; ++ switch (strength) { ++ case AR803X_STRENGTH_FULL: ++ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; ++ break; ++ case AR803X_STRENGTH_HALF: ++ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; ++ break; ++ case AR803X_STRENGTH_QUARTER: ++ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; ++ break; ++ default: ++ phydev_err(phydev, "invalid qca,clk-out-strength\n"); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static int at803x_probe(struct phy_device *phydev) ++{ ++ struct device *dev = &phydev->mdio.dev; ++ struct at803x_priv *priv; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ /* Init LED polarity mode to -1 */ ++ priv->led_polarity_mode = -1; ++ ++ phydev->priv = priv; ++ ++ ret = at803x_parse_dt(phydev); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int at803x_get_features(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ int err; ++ ++ err = genphy_read_abilities(phydev); ++ if (err) ++ return err; ++ ++ if (phydev->drv->phy_id != ATH8031_PHY_ID) ++ return 0; ++ ++ /* AR8031/AR8033 have different status registers ++ * for copper and fiber operation. However, the ++ * extended status register is the same for both ++ * operation modes. ++ * ++ * As a result of that, ESTATUS_1000_XFULL is set ++ * to 1 even when operating in copper TP mode. ++ * ++ * Remove this mode from the supported link modes ++ * when not operating in 1000BaseX mode. ++ */ ++ if (!priv->is_1000basex) ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, ++ phydev->supported); ++ ++ return 0; ++} ++ ++static int at803x_smarteee_config(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ u16 mask = 0, val = 0; ++ int ret; ++ ++ if (priv->flags & AT803X_DISABLE_SMARTEEE) ++ return phy_modify_mmd(phydev, MDIO_MMD_PCS, ++ AT803X_MMD3_SMARTEEE_CTL3, ++ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); ++ ++ if (priv->smarteee_lpi_tw_1g) { ++ mask |= 0xff00; ++ val |= priv->smarteee_lpi_tw_1g << 8; ++ } ++ if (priv->smarteee_lpi_tw_100m) { ++ mask |= 0x00ff; ++ val |= priv->smarteee_lpi_tw_100m; ++ } ++ if (!mask) ++ return 0; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, ++ mask, val); ++ if (ret) ++ return ret; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, ++ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, ++ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); ++} ++ ++static int at803x_clk_out_config(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ ++ if (!priv->clk_25m_mask) ++ return 0; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, ++ priv->clk_25m_mask, priv->clk_25m_reg); ++} ++ ++static int at8031_pll_config(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ ++ /* The default after hardware reset is PLL OFF. After a soft reset, the ++ * values are retained. ++ */ ++ if (priv->flags & AT803X_KEEP_PLL_ENABLED) ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, ++ 0, AT803X_DEBUG_PLL_ON); ++ else ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, ++ AT803X_DEBUG_PLL_ON, 0); ++} ++ ++static int at803x_hibernation_mode_config(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ ++ /* The default after hardware reset is hibernation mode enabled. After ++ * software reset, the value is retained. ++ */ ++ if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) ++ return 0; ++ ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, ++ AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); ++} ++ ++static int at803x_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* The RX and TX delay default is: ++ * after HW reset: RX delay enabled and TX delay disabled ++ * after SW reset: RX delay enabled, while TX delay retains the ++ * value before reset. ++ */ ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || ++ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ++ ret = at803x_enable_rx_delay(phydev); ++ else ++ ret = at803x_disable_rx_delay(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || ++ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) ++ ret = at803x_enable_tx_delay(phydev); ++ else ++ ret = at803x_disable_tx_delay(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = at803x_smarteee_config(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = at803x_clk_out_config(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = at803x_hibernation_mode_config(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Ar803x extended next page bit is enabled by default. Cisco ++ * multigig switches read this bit and attempt to negotiate 10Gbps ++ * rates even if the next page bit is disabled. This is incorrect ++ * behaviour but we still need to accommodate it. XNP is only needed ++ * for 10Gbps support, so disable XNP. ++ */ ++ return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); ++} ++ ++static int at803x_ack_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = phy_read(phydev, AT803X_INTR_STATUS); ++ ++ return (err < 0) ? err : 0; ++} ++ ++static int at803x_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ int value; ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { ++ /* Clear any pending interrupts */ ++ err = at803x_ack_interrupt(phydev); ++ if (err) ++ return err; ++ ++ value |= AT803X_INTR_ENABLE_AUTONEG_ERR; ++ value |= AT803X_INTR_ENABLE_SPEED_CHANGED; ++ value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; ++ value |= AT803X_INTR_ENABLE_LINK_FAIL; ++ value |= AT803X_INTR_ENABLE_LINK_SUCCESS; ++ ++ err = phy_write(phydev, AT803X_INTR_ENABLE, value); ++ } else { ++ err = phy_write(phydev, AT803X_INTR_ENABLE, 0); ++ if (err) ++ return err; ++ ++ /* Clear any pending interrupts */ ++ err = at803x_ack_interrupt(phydev); ++ } ++ ++ return err; ++} ++ ++static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) ++{ ++ int irq_status, int_enabled; ++ ++ irq_status = phy_read(phydev, AT803X_INTR_STATUS); ++ if (irq_status < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* Read the current enabled interrupts */ ++ int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (int_enabled < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* See if this was one of our enabled interrupts */ ++ if (!(irq_status & int_enabled)) ++ return IRQ_NONE; ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++ ++static void at803x_link_change_notify(struct phy_device *phydev) ++{ ++ /* ++ * Conduct a hardware reset for AT8030 every time a link loss is ++ * signalled. This is necessary to circumvent a hardware bug that ++ * occurs when the cable is unplugged while TX packets are pending ++ * in the FIFO. In such cases, the FIFO enters an error mode it ++ * cannot recover from by software. ++ */ ++ if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { ++ struct at803x_context context; ++ ++ at803x_context_save(phydev, &context); ++ ++ phy_device_reset(phydev, 1); ++ usleep_range(1000, 2000); ++ phy_device_reset(phydev, 0); ++ usleep_range(1000, 2000); ++ ++ at803x_context_restore(phydev, &context); ++ ++ phydev_dbg(phydev, "%s(): phy was reset\n", __func__); ++ } ++} ++ ++static int at803x_read_specific_status(struct phy_device *phydev, ++ struct at803x_ss_mask ss_mask) ++{ ++ int ss; ++ ++ /* Read the AT8035 PHY-Specific Status register, which indicates the ++ * speed and duplex that the PHY is actually using, irrespective of ++ * whether we are in autoneg mode or not. ++ */ ++ ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); ++ if (ss < 0) ++ return ss; ++ ++ if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { ++ int sfc, speed; ++ ++ sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); ++ if (sfc < 0) ++ return sfc; ++ ++ speed = ss & ss_mask.speed_mask; ++ speed >>= ss_mask.speed_shift; ++ ++ switch (speed) { ++ case AT803X_SS_SPEED_10: ++ phydev->speed = SPEED_10; ++ break; ++ case AT803X_SS_SPEED_100: ++ phydev->speed = SPEED_100; ++ break; ++ case AT803X_SS_SPEED_1000: ++ phydev->speed = SPEED_1000; ++ break; ++ case QCA808X_SS_SPEED_2500: ++ phydev->speed = SPEED_2500; ++ break; ++ } ++ if (ss & AT803X_SS_DUPLEX) ++ phydev->duplex = DUPLEX_FULL; ++ else ++ phydev->duplex = DUPLEX_HALF; ++ ++ if (ss & AT803X_SS_MDIX) ++ phydev->mdix = ETH_TP_MDI_X; ++ else ++ phydev->mdix = ETH_TP_MDI; ++ ++ switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { ++ case AT803X_SFC_MANUAL_MDI: ++ phydev->mdix_ctrl = ETH_TP_MDI; ++ break; ++ case AT803X_SFC_MANUAL_MDIX: ++ phydev->mdix_ctrl = ETH_TP_MDI_X; ++ break; ++ case AT803X_SFC_AUTOMATIC_CROSSOVER: ++ phydev->mdix_ctrl = ETH_TP_MDI_AUTO; ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static int at803x_read_status(struct phy_device *phydev) ++{ ++ struct at803x_ss_mask ss_mask = { 0 }; ++ int err, old_link = phydev->link; ++ ++ /* Update the link, but return if there was an error */ ++ err = genphy_update_link(phydev); ++ if (err) ++ return err; ++ ++ /* why bother the PHY if nothing can have changed */ ++ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) ++ return 0; ++ ++ phydev->speed = SPEED_UNKNOWN; ++ phydev->duplex = DUPLEX_UNKNOWN; ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ ++ err = genphy_read_lpa(phydev); ++ if (err < 0) ++ return err; ++ ++ ss_mask.speed_mask = AT803X_SS_SPEED_MASK; ++ ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK); ++ err = at803x_read_specific_status(phydev, ss_mask); ++ if (err < 0) ++ return err; ++ ++ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) ++ phy_resolve_aneg_pause(phydev); ++ ++ return 0; ++} ++ ++static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) ++{ ++ u16 val; ++ ++ switch (ctrl) { ++ case ETH_TP_MDI: ++ val = AT803X_SFC_MANUAL_MDI; ++ break; ++ case ETH_TP_MDI_X: ++ val = AT803X_SFC_MANUAL_MDIX; ++ break; ++ case ETH_TP_MDI_AUTO: ++ val = AT803X_SFC_AUTOMATIC_CROSSOVER; ++ break; ++ default: ++ return 0; ++ } ++ ++ return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, ++ AT803X_SFC_MDI_CROSSOVER_MODE_M, ++ FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); ++} ++ ++static int at803x_prepare_config_aneg(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); ++ if (ret < 0) ++ return ret; ++ ++ /* Changes of the midx bits are disruptive to the normal operation; ++ * therefore any changes to these registers must be followed by a ++ * software reset to take effect. ++ */ ++ if (ret == 1) { ++ ret = genphy_soft_reset(phydev); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int at803x_config_aneg(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ int ret; ++ ++ ret = at803x_prepare_config_aneg(phydev); ++ if (ret) ++ return ret; ++ ++ if (priv->is_1000basex) ++ return genphy_c37_config_aneg(phydev); ++ ++ return genphy_config_aneg(phydev); ++} ++ ++static int at803x_get_downshift(struct phy_device *phydev, u8 *d) ++{ ++ int val; ++ ++ val = phy_read(phydev, AT803X_SMART_SPEED); ++ if (val < 0) ++ return val; ++ ++ if (val & AT803X_SMART_SPEED_ENABLE) ++ *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; ++ else ++ *d = DOWNSHIFT_DEV_DISABLE; ++ ++ return 0; ++} ++ ++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) ++{ ++ u16 mask, set; ++ int ret; ++ ++ switch (cnt) { ++ case DOWNSHIFT_DEV_DEFAULT_COUNT: ++ cnt = AT803X_DEFAULT_DOWNSHIFT; ++ fallthrough; ++ case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: ++ set = AT803X_SMART_SPEED_ENABLE | ++ AT803X_SMART_SPEED_BYPASS_TIMER | ++ FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); ++ mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; ++ break; ++ case DOWNSHIFT_DEV_DISABLE: ++ set = 0; ++ mask = AT803X_SMART_SPEED_ENABLE | ++ AT803X_SMART_SPEED_BYPASS_TIMER; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); ++ ++ /* After changing the smart speed settings, we need to perform a ++ * software reset, use phy_init_hw() to make sure we set the ++ * reapply any values which might got lost during software reset. ++ */ ++ if (ret == 1) ++ ret = phy_init_hw(phydev); ++ ++ return ret; ++} ++ ++static int at803x_get_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return at803x_get_downshift(phydev, data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static int at803x_set_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, const void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return at803x_set_downshift(phydev, *(const u8 *)data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static int at803x_cable_test_result_trans(u16 status) ++{ ++ switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { ++ case AT803X_CDT_STATUS_STAT_NORMAL: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OK; ++ case AT803X_CDT_STATUS_STAT_SHORT: ++ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; ++ case AT803X_CDT_STATUS_STAT_OPEN: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; ++ case AT803X_CDT_STATUS_STAT_FAIL: ++ default: ++ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; ++ } ++} ++ ++static bool at803x_cdt_test_failed(u16 status) ++{ ++ return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == ++ AT803X_CDT_STATUS_STAT_FAIL; ++} ++ ++static bool at803x_cdt_fault_length_valid(u16 status) ++{ ++ switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { ++ case AT803X_CDT_STATUS_STAT_OPEN: ++ case AT803X_CDT_STATUS_STAT_SHORT: ++ return true; ++ } ++ return false; ++} ++ ++static int at803x_cdt_fault_length(int dt) ++{ ++ /* According to the datasheet the distance to the fault is ++ * DELTA_TIME * 0.824 meters. ++ * ++ * The author suspect the correct formula is: ++ * ++ * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 ++ * ++ * where c is the speed of light, VF is the velocity factor of ++ * the twisted pair cable, 125MHz the counter frequency and ++ * we need to divide by 2 because the hardware will measure the ++ * round trip time to the fault and back to the PHY. ++ * ++ * With a VF of 0.69 we get the factor 0.824 mentioned in the ++ * datasheet. ++ */ ++ return (dt * 824) / 10; ++} ++ ++static int at803x_cdt_start(struct phy_device *phydev, ++ u32 cdt_start) ++{ ++ return phy_write(phydev, AT803X_CDT, cdt_start); ++} ++ ++static int at803x_cdt_wait_for_completion(struct phy_device *phydev, ++ u32 cdt_en) ++{ ++ int val, ret; ++ ++ /* One test run takes about 25ms */ ++ ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, ++ !(val & cdt_en), ++ 30000, 100000, true); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) ++{ ++ static const int ethtool_pair[] = { ++ ETHTOOL_A_CABLE_PAIR_A, ++ ETHTOOL_A_CABLE_PAIR_B, ++ ETHTOOL_A_CABLE_PAIR_C, ++ ETHTOOL_A_CABLE_PAIR_D, ++ }; ++ int ret, val; ++ ++ val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | ++ AT803X_CDT_ENABLE_TEST; ++ ret = at803x_cdt_start(phydev, val); ++ if (ret) ++ return ret; ++ ++ ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); ++ if (ret) ++ return ret; ++ ++ val = phy_read(phydev, AT803X_CDT_STATUS); ++ if (val < 0) ++ return val; ++ ++ if (at803x_cdt_test_failed(val)) ++ return 0; ++ ++ ethnl_cable_test_result(phydev, ethtool_pair[pair], ++ at803x_cable_test_result_trans(val)); ++ ++ if (at803x_cdt_fault_length_valid(val)) { ++ val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); ++ ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], ++ at803x_cdt_fault_length(val)); ++ } ++ ++ return 1; ++} ++ ++static int at803x_cable_test_get_status(struct phy_device *phydev, ++ bool *finished, unsigned long pair_mask) ++{ ++ int retries = 20; ++ int pair, ret; ++ ++ *finished = false; ++ ++ /* According to the datasheet the CDT can be performed when ++ * there is no link partner or when the link partner is ++ * auto-negotiating. Starting the test will restart the AN ++ * automatically. It seems that doing this repeatedly we will ++ * get a slot where our link partner won't disturb our ++ * measurement. ++ */ ++ while (pair_mask && retries--) { ++ for_each_set_bit(pair, &pair_mask, 4) { ++ ret = at803x_cable_test_one_pair(phydev, pair); ++ if (ret < 0) ++ return ret; ++ if (ret) ++ clear_bit(pair, &pair_mask); ++ } ++ if (pair_mask) ++ msleep(250); ++ } ++ ++ *finished = true; ++ ++ return 0; ++} ++ ++static void at803x_cable_test_autoneg(struct phy_device *phydev) ++{ ++ /* Enable auto-negotiation, but advertise no capabilities, no link ++ * will be established. A restart of the auto-negotiation is not ++ * required, because the cable test will automatically break the link. ++ */ ++ phy_write(phydev, MII_BMCR, BMCR_ANENABLE); ++ phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); ++} ++ ++static int at803x_cable_test_start(struct phy_device *phydev) ++{ ++ at803x_cable_test_autoneg(phydev); ++ /* we do all the (time consuming) work later */ ++ return 0; ++} ++ ++static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, ++ unsigned int selector) ++{ ++ struct phy_device *phydev = rdev_get_drvdata(rdev); ++ ++ if (selector) ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, ++ 0, AT803X_DEBUG_RGMII_1V8); ++ else ++ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, ++ AT803X_DEBUG_RGMII_1V8, 0); ++} ++ ++static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) ++{ ++ struct phy_device *phydev = rdev_get_drvdata(rdev); ++ int val; ++ ++ val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); ++ if (val < 0) ++ return val; ++ ++ return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; ++} ++ ++static const struct regulator_ops vddio_regulator_ops = { ++ .list_voltage = regulator_list_voltage_table, ++ .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, ++ .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, ++}; ++ ++static const unsigned int vddio_voltage_table[] = { ++ 1500000, ++ 1800000, ++}; ++ ++static const struct regulator_desc vddio_desc = { ++ .name = "vddio", ++ .of_match = of_match_ptr("vddio-regulator"), ++ .n_voltages = ARRAY_SIZE(vddio_voltage_table), ++ .volt_table = vddio_voltage_table, ++ .ops = &vddio_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct regulator_ops vddh_regulator_ops = { ++}; ++ ++static const struct regulator_desc vddh_desc = { ++ .name = "vddh", ++ .of_match = of_match_ptr("vddh-regulator"), ++ .n_voltages = 1, ++ .fixed_uV = 2500000, ++ .ops = &vddh_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++}; ++ ++static int at8031_register_regulators(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ struct device *dev = &phydev->mdio.dev; ++ struct regulator_config config = { }; ++ ++ config.dev = dev; ++ config.driver_data = phydev; ++ ++ priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); ++ if (IS_ERR(priv->vddio_rdev)) { ++ phydev_err(phydev, "failed to register VDDIO regulator\n"); ++ return PTR_ERR(priv->vddio_rdev); ++ } ++ ++ priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); ++ if (IS_ERR(priv->vddh_rdev)) { ++ phydev_err(phydev, "failed to register VDDH regulator\n"); ++ return PTR_ERR(priv->vddh_rdev); ++ } ++ ++ return 0; ++} ++ ++static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) ++{ ++ struct phy_device *phydev = upstream; ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); ++ DECLARE_PHY_INTERFACE_MASK(interfaces); ++ phy_interface_t iface; ++ ++ linkmode_zero(phy_support); ++ phylink_set(phy_support, 1000baseX_Full); ++ phylink_set(phy_support, 1000baseT_Full); ++ phylink_set(phy_support, Autoneg); ++ phylink_set(phy_support, Pause); ++ phylink_set(phy_support, Asym_Pause); ++ ++ linkmode_zero(sfp_support); ++ sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); ++ /* Some modules support 10G modes as well as others we support. ++ * Mask out non-supported modes so the correct interface is picked. ++ */ ++ linkmode_and(sfp_support, phy_support, sfp_support); ++ ++ if (linkmode_empty(sfp_support)) { ++ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); ++ return -EINVAL; ++ } ++ ++ iface = sfp_select_interface(phydev->sfp_bus, sfp_support); ++ ++ /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes ++ * interface for use with SFP modules. ++ * However, some copper modules detected as having a preferred SGMII ++ * interface do default to and function in 1000Base-X mode, so just ++ * print a warning and allow such modules, as they may have some chance ++ * of working. ++ */ ++ if (iface == PHY_INTERFACE_MODE_SGMII) ++ dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); ++ else if (iface != PHY_INTERFACE_MODE_1000BASEX) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct sfp_upstream_ops at8031_sfp_ops = { ++ .attach = phy_sfp_attach, ++ .detach = phy_sfp_detach, ++ .module_insert = at8031_sfp_insert, ++}; ++ ++static int at8031_parse_dt(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ struct at803x_priv *priv = phydev->priv; ++ int ret; ++ ++ if (of_property_read_bool(node, "qca,keep-pll-enabled")) ++ priv->flags |= AT803X_KEEP_PLL_ENABLED; ++ ++ ret = at8031_register_regulators(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, ++ "vddio"); ++ if (ret) { ++ phydev_err(phydev, "failed to get VDDIO regulator\n"); ++ return ret; ++ } ++ ++ /* Only AR8031/8033 support 1000Base-X for SFP modules */ ++ return phy_sfp_probe(phydev, &at8031_sfp_ops); ++} ++ ++static int at8031_probe(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ int mode_cfg; ++ int ccr; ++ int ret; ++ ++ ret = at803x_probe(phydev); ++ if (ret) ++ return ret; ++ ++ /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping ++ * options. ++ */ ++ ret = at8031_parse_dt(phydev); ++ if (ret) ++ return ret; ++ ++ ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); ++ if (ccr < 0) ++ return ccr; ++ mode_cfg = ccr & AT803X_MODE_CFG_MASK; ++ ++ switch (mode_cfg) { ++ case AT803X_MODE_CFG_BX1000_RGMII_50OHM: ++ case AT803X_MODE_CFG_BX1000_RGMII_75OHM: ++ priv->is_1000basex = true; ++ fallthrough; ++ case AT803X_MODE_CFG_FX100_RGMII_50OHM: ++ case AT803X_MODE_CFG_FX100_RGMII_75OHM: ++ priv->is_fiber = true; ++ break; ++ } ++ ++ /* Disable WoL in 1588 register which is enabled ++ * by default ++ */ ++ return phy_modify_mmd(phydev, MDIO_MMD_PCS, ++ AT803X_PHY_MMD3_WOL_CTRL, ++ AT803X_WOL_EN, 0); ++} ++ ++static int at8031_config_init(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Some bootloaders leave the fiber page selected. ++ * Switch to the appropriate page (fiber or copper), as otherwise we ++ * read the PHY capabilities from the wrong page. ++ */ ++ phy_lock_mdio_bus(phydev); ++ ret = at803x_write_page(phydev, ++ priv->is_fiber ? AT803X_PAGE_FIBER : ++ AT803X_PAGE_COPPER); ++ phy_unlock_mdio_bus(phydev); ++ if (ret) ++ return ret; ++ ++ ret = at8031_pll_config(phydev); ++ if (ret < 0) ++ return ret; ++ ++ return at803x_config_init(phydev); ++} ++ ++static int at8031_set_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ int ret; ++ ++ /* First setup MAC address and enable WOL interrupt */ ++ ret = at803x_set_wol(phydev, wol); ++ if (ret) ++ return ret; ++ ++ if (wol->wolopts & WAKE_MAGIC) ++ /* Enable WOL function for 1588 */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, ++ AT803X_PHY_MMD3_WOL_CTRL, ++ 0, AT803X_WOL_EN); ++ else ++ /* Disable WoL function for 1588 */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, ++ AT803X_PHY_MMD3_WOL_CTRL, ++ AT803X_WOL_EN, 0); ++ ++ return ret; ++} ++ ++static int at8031_config_intr(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ int err, value = 0; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED && ++ priv->is_fiber) { ++ /* Clear any pending interrupts */ ++ err = at803x_ack_interrupt(phydev); ++ if (err) ++ return err; ++ ++ value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; ++ value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; ++ ++ err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); ++ if (err) ++ return err; ++ } ++ ++ return at803x_config_intr(phydev); ++} ++ ++/* AR8031 and AR8033 share the same read status logic */ ++static int at8031_read_status(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ ++ if (priv->is_1000basex) ++ return genphy_c37_read_status(phydev); ++ ++ return at803x_read_status(phydev); ++} ++ ++/* AR8031 and AR8035 share the same cable test get status reg */ ++static int at8031_cable_test_get_status(struct phy_device *phydev, ++ bool *finished) ++{ ++ return at803x_cable_test_get_status(phydev, finished, 0xf); ++} ++ ++/* AR8031 and AR8035 share the same cable test start logic */ ++static int at8031_cable_test_start(struct phy_device *phydev) ++{ ++ at803x_cable_test_autoneg(phydev); ++ phy_write(phydev, MII_CTRL1000, 0); ++ /* we do all the (time consuming) work later */ ++ return 0; ++} ++ ++/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ ++static int at8032_cable_test_get_status(struct phy_device *phydev, ++ bool *finished) ++{ ++ return at803x_cable_test_get_status(phydev, finished, 0x3); ++} ++ ++static int at8035_parse_dt(struct phy_device *phydev) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ ++ /* Mask is set by the generic at803x_parse_dt ++ * if property is set. Assume property is set ++ * with the mask not zero. ++ */ ++ if (priv->clk_25m_mask) { ++ /* Fixup for the AR8030/AR8035. This chip has another mask and ++ * doesn't support the DSP reference. Eg. the lowest bit of the ++ * mask. The upper two bits select the same frequencies. Mask ++ * the lowest bit here. ++ * ++ * Warning: ++ * There was no datasheet for the AR8030 available so this is ++ * just a guess. But the AR8035 is listed as pin compatible ++ * to the AR8030 so there might be a good chance it works on ++ * the AR8030 too. ++ */ ++ priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; ++ priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; ++ } ++ ++ return 0; ++} ++ ++/* AR8030 and AR8035 shared the same special mask for clk_25m */ ++static int at8035_probe(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = at803x_probe(phydev); ++ if (ret) ++ return ret; ++ ++ return at8035_parse_dt(phydev); ++} ++ ++static int qca83xx_config_init(struct phy_device *phydev) ++{ ++ u8 switch_revision; ++ ++ switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; ++ ++ switch (switch_revision) { ++ case 1: ++ /* For 100M waveform */ ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); ++ /* Turn on Gigabit clock */ ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); ++ break; ++ ++ case 2: ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); ++ fallthrough; ++ case 4: ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); ++ break; ++ } ++ ++ /* Following original QCA sourcecode set port to prefer master */ ++ phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); ++ ++ return 0; ++} ++ ++static int qca8327_config_init(struct phy_device *phydev) ++{ ++ /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. ++ * Disable on init and enable only with 100m speed following ++ * qca original source code. ++ */ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, 0); ++ ++ return qca83xx_config_init(phydev); ++} ++ ++static void qca83xx_link_change_notify(struct phy_device *phydev) ++{ ++ /* Set DAC Amplitude adjustment to +6% for 100m on link running */ ++ if (phydev->state == PHY_RUNNING) { ++ if (phydev->speed == SPEED_100) ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, ++ QCA8327_DEBUG_MANU_CTRL_EN); ++ } else { ++ /* Reset DAC Amplitude adjustment */ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, 0); ++ } ++} ++ ++static int qca83xx_resume(struct phy_device *phydev) ++{ ++ int ret, val; ++ ++ /* Skip reset if not suspended */ ++ if (!phydev->suspended) ++ return 0; ++ ++ /* Reinit the port, reset values set by suspend */ ++ qca83xx_config_init(phydev); ++ ++ /* Reset the port on port resume */ ++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); ++ ++ /* On resume from suspend the switch execute a reset and ++ * restart auto-negotiation. Wait for reset to complete. ++ */ ++ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), ++ 50000, 600000, true); ++ if (ret) ++ return ret; ++ ++ usleep_range(1000, 2000); ++ ++ return 0; ++} ++ ++static int qca83xx_suspend(struct phy_device *phydev) ++{ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, ++ AT803X_DEBUG_GATE_CLK_IN1000, 0); ++ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, ++ AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | ++ AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); ++ ++ return 0; ++} ++ ++static int qca8337_suspend(struct phy_device *phydev) ++{ ++ /* Only QCA8337 support actual suspend. */ ++ genphy_suspend(phydev); ++ ++ return qca83xx_suspend(phydev); ++} ++ ++static int qca8327_suspend(struct phy_device *phydev) ++{ ++ u16 mask = 0; ++ ++ /* QCA8327 cause port unreliability when phy suspend ++ * is set. ++ */ ++ mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); ++ phy_modify(phydev, MII_BMCR, mask, 0); ++ ++ return qca83xx_suspend(phydev); ++} ++ ++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Enable fast retrain */ ++ ret = genphy_c45_fast_retrain(phydev, true); ++ if (ret) ++ return ret; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, ++ QCA808X_TOP_OPTION1_DATA); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, ++ QCA808X_MSE_THRESHOLD_20DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, ++ QCA808X_MSE_THRESHOLD_17DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, ++ QCA808X_MSE_THRESHOLD_27DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, ++ QCA808X_MSE_THRESHOLD_28DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, ++ QCA808X_MMD3_DEBUG_1_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, ++ QCA808X_MMD3_DEBUG_4_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, ++ QCA808X_MMD3_DEBUG_5_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, ++ QCA808X_MMD3_DEBUG_3_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, ++ QCA808X_MMD3_DEBUG_6_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, ++ QCA808X_MMD3_DEBUG_2_VALUE); ++ ++ return 0; ++} ++ ++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) ++{ ++ u16 seed_value; ++ ++ if (!enable) ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, ++ QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); ++ ++ seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE); ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, ++ QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, ++ FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | ++ QCA808X_MASTER_SLAVE_SEED_ENABLE); ++} ++ ++static bool qca808x_is_prefer_master(struct phy_device *phydev) ++{ ++ return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || ++ (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); ++} ++ ++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) ++{ ++ return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); ++} ++ ++static int qca808x_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Active adc&vga on 802.3az for the link 1000M and 100M */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, ++ QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); ++ if (ret) ++ return ret; ++ ++ /* Adjust the threshold on 802.3az for the link 1000M */ ++ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, ++ QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, ++ QCA808X_MMD3_AZ_TRAINING_VAL); ++ if (ret) ++ return ret; ++ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { ++ /* Config the fast retrain for the link 2500M */ ++ ret = qca808x_phy_fast_retrain_config(phydev); ++ if (ret) ++ return ret; ++ ++ ret = genphy_read_master_slave(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (!qca808x_is_prefer_master(phydev)) { ++ /* Enable seed and configure lower ramdom seed to make phy ++ * linked as slave mode. ++ */ ++ ret = qca808x_phy_ms_seed_enable(phydev, true); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ /* Configure adc threshold as 100mv for the link 10M */ ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, ++ QCA808X_ADC_THRESHOLD_MASK, ++ QCA808X_ADC_THRESHOLD_100MV); ++} ++ ++static int qca808x_read_status(struct phy_device *phydev) ++{ ++ struct at803x_ss_mask ss_mask = { 0 }; ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); ++ if (ret < 0) ++ return ret; ++ ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, ++ ret & MDIO_AN_10GBT_STAT_LP2_5G); ++ ++ ret = genphy_read_status(phydev); ++ if (ret) ++ return ret; ++ ++ /* qca8081 takes the different bits for speed value from at803x */ ++ ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; ++ ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); ++ ret = at803x_read_specific_status(phydev, ss_mask); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->link) { ++ if (phydev->speed == SPEED_2500) ++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ else ++ phydev->interface = PHY_INTERFACE_MODE_SGMII; ++ } else { ++ /* generate seed as a lower random value to make PHY linked as SLAVE easily, ++ * except for master/slave configuration fault detected or the master mode ++ * preferred. ++ * ++ * the reason for not putting this code into the function link_change_notify is ++ * the corner case where the link partner is also the qca8081 PHY and the seed ++ * value is configured as the same value, the link can't be up and no link change ++ * occurs. ++ */ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { ++ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || ++ qca808x_is_prefer_master(phydev)) { ++ qca808x_phy_ms_seed_enable(phydev, false); ++ } else { ++ qca808x_phy_ms_seed_enable(phydev, true); ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int qca808x_soft_reset(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_soft_reset(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) ++ ret = qca808x_phy_ms_seed_enable(phydev, true); ++ ++ return ret; ++} ++ ++static bool qca808x_cdt_fault_length_valid(int cdt_code) ++{ ++ switch (cdt_code) { ++ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static int qca808x_cable_test_result_trans(int cdt_code) ++{ ++ switch (cdt_code) { ++ case QCA808X_CDT_STATUS_STAT_NORMAL: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OK; ++ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: ++ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; ++ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: ++ return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; ++ case QCA808X_CDT_STATUS_STAT_FAIL: ++ default: ++ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; ++ } ++} ++ ++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, ++ int result) ++{ ++ int val; ++ u32 cdt_length_reg = 0; ++ ++ switch (pair) { ++ case ETHTOOL_A_CABLE_PAIR_A: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_B: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_C: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_D: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); ++ if (val < 0) ++ return val; ++ ++ if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) ++ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); ++ else ++ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); ++ ++ return at803x_cdt_fault_length(val); ++} ++ ++static int qca808x_cable_test_start(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* perform CDT with the following configs: ++ * 1. disable hibernation. ++ * 2. force PHY working in MDI mode. ++ * 3. for PHY working in 1000BaseT. ++ * 4. configure the threshold. ++ */ ++ ++ ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); ++ if (ret < 0) ++ return ret; ++ ++ ret = at803x_config_mdix(phydev, ETH_TP_MDI); ++ if (ret < 0) ++ return ret; ++ ++ /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ ++ phydev->duplex = DUPLEX_FULL; ++ phydev->speed = SPEED_1000; ++ ret = genphy_c45_pma_setup_forced(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = genphy_setup_forced(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* configure the thresholds for open, short, pair ok test */ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); ++ ++ return 0; ++} ++ ++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, ++ u16 status) ++{ ++ int length, result; ++ u16 pair_code; ++ ++ switch (pair) { ++ case ETHTOOL_A_CABLE_PAIR_A: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_B: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_C: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_D: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ result = qca808x_cable_test_result_trans(pair_code); ++ ethnl_cable_test_result(phydev, pair, result); ++ ++ if (qca808x_cdt_fault_length_valid(pair_code)) { ++ length = qca808x_cdt_fault_length(phydev, pair, result); ++ ethnl_cable_test_fault_length(phydev, pair, length); ++ } ++ ++ return 0; ++} ++ ++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) ++{ ++ int ret, val; ++ ++ *finished = false; ++ ++ val = QCA808X_CDT_ENABLE_TEST | ++ QCA808X_CDT_LENGTH_UNIT; ++ ret = at803x_cdt_start(phydev, val); ++ if (ret) ++ return ret; ++ ++ ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); ++ if (ret) ++ return ret; ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); ++ if (val < 0) ++ return val; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); ++ if (ret) ++ return ret; ++ ++ *finished = true; ++ ++ return 0; ++} ++ ++static int qca808x_get_features(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_c45_pma_read_abilities(phydev); ++ if (ret) ++ return ret; ++ ++ /* The autoneg ability is not existed in bit3 of MMD7.1, ++ * but it is supported by qca808x PHY, so we add it here ++ * manually. ++ */ ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); ++ ++ /* As for the qca8081 1G version chip, the 2500baseT ability is also ++ * existed in the bit0 of MMD1.21, we need to remove it manually if ++ * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. ++ */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); ++ if (ret < 0) ++ return ret; ++ ++ if (QCA808X_PHY_CHIP_TYPE_1G & ret) ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); ++ ++ return 0; ++} ++ ++static int qca808x_config_aneg(struct phy_device *phydev) ++{ ++ int phy_ctrl = 0; ++ int ret; ++ ++ ret = at803x_prepare_config_aneg(phydev); ++ if (ret) ++ return ret; ++ ++ /* The reg MII_BMCR also needs to be configured for force mode, the ++ * genphy_config_aneg is also needed. ++ */ ++ if (phydev->autoneg == AUTONEG_DISABLE) ++ genphy_c45_pma_setup_forced(phydev); ++ ++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) ++ phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; ++ ++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ++ MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); ++ if (ret < 0) ++ return ret; ++ ++ return __genphy_config_aneg(phydev, ret); ++} ++ ++static void qca808x_link_change_notify(struct phy_device *phydev) ++{ ++ /* Assert interface sgmii fifo on link down, deassert it on link up, ++ * the interface device address is always phy address added by 1. ++ */ ++ mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, ++ MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, ++ QCA8081_PHY_FIFO_RSTN, ++ phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); ++} ++ ++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, ++ u16 *offload_trigger) ++{ ++ /* Parsing specific to netdev trigger */ ++ if (test_bit(TRIGGER_NETDEV_TX, &rules)) ++ *offload_trigger |= QCA808X_LED_TX_BLINK; ++ if (test_bit(TRIGGER_NETDEV_RX, &rules)) ++ *offload_trigger |= QCA808X_LED_RX_BLINK; ++ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED10_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED100_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED1000_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED2500_ON; ++ if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) ++ *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; ++ if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) ++ *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; ++ ++ if (rules && !*offload_trigger) ++ return -EOPNOTSUPP; ++ ++ /* Enable BLINK_CHECK_BYPASS by default to make the LED ++ * blink even with duplex or speed mode not enabled. ++ */ ++ *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; ++ ++ return 0; ++} ++ ++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN); ++} ++ ++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 offload_trigger = 0; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); ++} ++ ++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 reg, offload_trigger = 0; ++ int ret; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_led_hw_control_enable(phydev, index); ++ if (ret) ++ return ret; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_PATTERN_MASK, ++ offload_trigger); ++} ++ ++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ int val; ++ ++ if (index > 2) ++ return false; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); ++ ++ return !(val & QCA808X_LED_FORCE_EN); ++} ++ ++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ u16 reg; ++ int val; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ /* Check if we have hw control enabled */ ++ if (qca808x_led_hw_control_status(phydev, index)) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); ++ if (val & QCA808X_LED_TX_BLINK) ++ set_bit(TRIGGER_NETDEV_TX, rules); ++ if (val & QCA808X_LED_RX_BLINK) ++ set_bit(TRIGGER_NETDEV_RX, rules); ++ if (val & QCA808X_LED_SPEED10_ON) ++ set_bit(TRIGGER_NETDEV_LINK_10, rules); ++ if (val & QCA808X_LED_SPEED100_ON) ++ set_bit(TRIGGER_NETDEV_LINK_100, rules); ++ if (val & QCA808X_LED_SPEED1000_ON) ++ set_bit(TRIGGER_NETDEV_LINK_1000, rules); ++ if (val & QCA808X_LED_SPEED2500_ON) ++ set_bit(TRIGGER_NETDEV_LINK_2500, rules); ++ if (val & QCA808X_LED_HALF_DUPLEX_ON) ++ set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); ++ if (val & QCA808X_LED_FULL_DUPLEX_ON) ++ set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); ++ ++ return 0; ++} ++ ++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_PATTERN_MASK); ++} ++ ++static int qca808x_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ u16 reg; ++ int ret; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ if (!value) { ++ ret = qca808x_led_hw_control_reset(phydev, index); ++ if (ret) ++ return ret; ++ } ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, ++ QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : ++ QCA808X_LED_FORCE_OFF); ++} ++ ++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, ++ unsigned long *delay_on, ++ unsigned long *delay_off) ++{ ++ int ret; ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ /* Set blink to 50% off, 50% on at 4Hz by default */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, ++ QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, ++ QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); ++ if (ret) ++ return ret; ++ ++ /* We use BLINK_1 for normal blinking */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); ++ if (ret) ++ return ret; ++ ++ /* We set blink to 4Hz, aka 250ms */ ++ *delay_on = 250 / 2; ++ *delay_off = 250 / 2; ++ ++ return 0; ++} ++ ++static int qca808x_led_polarity_set(struct phy_device *phydev, int index, ++ unsigned long modes) ++{ ++ struct at803x_priv *priv = phydev->priv; ++ bool active_low = false; ++ u32 mode; ++ ++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { ++ switch (mode) { ++ case PHY_LED_ACTIVE_LOW: ++ active_low = true; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ /* PHY polarity is global and can't be set per LED. ++ * To detect this, check if last requested polarity mode ++ * match the new one. ++ */ ++ if (priv->led_polarity_mode >= 0 && ++ priv->led_polarity_mode != active_low) { ++ phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); ++ return -EINVAL; ++ } ++ ++ /* Save the last PHY polarity mode */ ++ priv->led_polarity_mode = active_low; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, ++ QCA808X_MMD7_LED_POLARITY_CTRL, ++ QCA808X_LED_ACTIVE_HIGH, ++ active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); ++} ++ ++static struct phy_driver at803x_driver[] = { ++{ ++ /* Qualcomm Atheros AR8035 */ ++ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), ++ .name = "Qualcomm Atheros AR8035", ++ .flags = PHY_POLL_CABLE_TEST, ++ .probe = at8035_probe, ++ .config_aneg = at803x_config_aneg, ++ .config_init = at803x_config_init, ++ .soft_reset = genphy_soft_reset, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ /* PHY_GBIT_FEATURES */ ++ .read_status = at803x_read_status, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++ .set_tunable = at803x_set_tunable, ++ .cable_test_start = at8031_cable_test_start, ++ .cable_test_get_status = at8031_cable_test_get_status, ++}, { ++ /* Qualcomm Atheros AR8030 */ ++ .phy_id = ATH8030_PHY_ID, ++ .name = "Qualcomm Atheros AR8030", ++ .phy_id_mask = AT8030_PHY_ID_MASK, ++ .probe = at8035_probe, ++ .config_init = at803x_config_init, ++ .link_change_notify = at803x_link_change_notify, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ /* PHY_BASIC_FEATURES */ ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++}, { ++ /* Qualcomm Atheros AR8031/AR8033 */ ++ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), ++ .name = "Qualcomm Atheros AR8031/AR8033", ++ .flags = PHY_POLL_CABLE_TEST, ++ .probe = at8031_probe, ++ .config_init = at8031_config_init, ++ .config_aneg = at803x_config_aneg, ++ .soft_reset = genphy_soft_reset, ++ .set_wol = at8031_set_wol, ++ .get_wol = at803x_get_wol, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ .read_page = at803x_read_page, ++ .write_page = at803x_write_page, ++ .get_features = at803x_get_features, ++ .read_status = at8031_read_status, ++ .config_intr = at8031_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++ .set_tunable = at803x_set_tunable, ++ .cable_test_start = at8031_cable_test_start, ++ .cable_test_get_status = at8031_cable_test_get_status, ++}, { ++ /* Qualcomm Atheros AR8032 */ ++ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), ++ .name = "Qualcomm Atheros AR8032", ++ .probe = at803x_probe, ++ .flags = PHY_POLL_CABLE_TEST, ++ .config_init = at803x_config_init, ++ .link_change_notify = at803x_link_change_notify, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ /* PHY_BASIC_FEATURES */ ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .cable_test_start = at803x_cable_test_start, ++ .cable_test_get_status = at8032_cable_test_get_status, ++}, { ++ /* ATHEROS AR9331 */ ++ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), ++ .name = "Qualcomm Atheros AR9331 built-in PHY", ++ .probe = at803x_probe, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ .flags = PHY_POLL_CABLE_TEST, ++ /* PHY_BASIC_FEATURES */ ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .cable_test_start = at803x_cable_test_start, ++ .cable_test_get_status = at8032_cable_test_get_status, ++ .read_status = at803x_read_status, ++ .soft_reset = genphy_soft_reset, ++ .config_aneg = at803x_config_aneg, ++}, { ++ /* Qualcomm Atheros QCA9561 */ ++ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), ++ .name = "Qualcomm Atheros QCA9561 built-in PHY", ++ .probe = at803x_probe, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ .flags = PHY_POLL_CABLE_TEST, ++ /* PHY_BASIC_FEATURES */ ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .cable_test_start = at803x_cable_test_start, ++ .cable_test_get_status = at8032_cable_test_get_status, ++ .read_status = at803x_read_status, ++ .soft_reset = genphy_soft_reset, ++ .config_aneg = at803x_config_aneg, ++}, { ++ /* QCA8337 */ ++ .phy_id = QCA8337_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8337 internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .probe = at803x_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca83xx_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8337_suspend, ++ .resume = qca83xx_resume, ++}, { ++ /* QCA8327-A from switch QCA8327-AL1A */ ++ .phy_id = QCA8327_A_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8327-A internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .link_change_notify = qca83xx_link_change_notify, ++ .probe = at803x_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca8327_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8327_suspend, ++ .resume = qca83xx_resume, ++}, { ++ /* QCA8327-B from switch QCA8327-BL1A */ ++ .phy_id = QCA8327_B_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8327-B internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .link_change_notify = qca83xx_link_change_notify, ++ .probe = at803x_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca8327_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8327_suspend, ++ .resume = qca83xx_resume, ++}, { ++ /* Qualcomm QCA8081 */ ++ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), ++ .name = "Qualcomm QCA8081", ++ .flags = PHY_POLL_CABLE_TEST, ++ .probe = at803x_probe, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++ .set_tunable = at803x_set_tunable, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .get_features = qca808x_get_features, ++ .config_aneg = qca808x_config_aneg, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++ .config_init = qca808x_config_init, ++ .soft_reset = qca808x_soft_reset, ++ .cable_test_start = qca808x_cable_test_start, ++ .cable_test_get_status = qca808x_cable_test_get_status, ++ .link_change_notify = qca808x_link_change_notify, ++ .led_brightness_set = qca808x_led_brightness_set, ++ .led_blink_set = qca808x_led_blink_set, ++ .led_hw_is_supported = qca808x_led_hw_is_supported, ++ .led_hw_control_set = qca808x_led_hw_control_set, ++ .led_hw_control_get = qca808x_led_hw_control_get, ++ .led_polarity_set = qca808x_led_polarity_set, ++}, }; ++ ++module_phy_driver(at803x_driver); ++ ++static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++ { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, ++ { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, atheros_tbl); diff --git a/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch new file mode 100644 index 0000000000..7d0e1f4a28 --- /dev/null +++ b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch @@ -0,0 +1,243 @@ +From 6fb760972c49490b03f3db2ad64cf30bdd28c54a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 29 Jan 2024 15:15:20 +0100 +Subject: [PATCH 2/5] net: phy: qcom: create and move functions to shared + library + +Create and move functions to shared library in preparation for qca83xx +PHY Family to be detached from at803x driver. + +Only the shared defines are moved to the shared qcom.h header. + +Signed-off-by: Christian Marangi +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/qcom/Kconfig | 4 ++ + drivers/net/phy/qcom/Makefile | 1 + + drivers/net/phy/qcom/at803x.c | 69 +---------------------------- + drivers/net/phy/qcom/qcom-phy-lib.c | 53 ++++++++++++++++++++++ + drivers/net/phy/qcom/qcom.h | 34 ++++++++++++++ + 5 files changed, 94 insertions(+), 67 deletions(-) + create mode 100644 drivers/net/phy/qcom/qcom-phy-lib.c + create mode 100644 drivers/net/phy/qcom/qcom.h + +--- a/drivers/net/phy/qcom/Kconfig ++++ b/drivers/net/phy/qcom/Kconfig +@@ -1,6 +1,10 @@ + # SPDX-License-Identifier: GPL-2.0-only ++config QCOM_NET_PHYLIB ++ tristate ++ + config AT803X_PHY + tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" ++ select QCOM_NET_PHYLIB + depends on REGULATOR + help + Currently supports the AR8030, AR8031, AR8033, AR8035 and internal +--- a/drivers/net/phy/qcom/Makefile ++++ b/drivers/net/phy/qcom/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o + obj-$(CONFIG_AT803X_PHY) += at803x.o +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -22,6 +22,8 @@ + #include + #include + ++#include "qcom.h" ++ + #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 + #define AT803X_SFC_ASSERT_CRS BIT(11) + #define AT803X_SFC_FORCE_LINK BIT(10) +@@ -84,9 +86,6 @@ + #define AT803X_REG_CHIP_CONFIG 0x1f + #define AT803X_BT_BX_REG_SEL 0x8000 + +-#define AT803X_DEBUG_ADDR 0x1D +-#define AT803X_DEBUG_DATA 0x1E +- + #define AT803X_MODE_CFG_MASK 0x0F + #define AT803X_MODE_CFG_BASET_RGMII 0x00 + #define AT803X_MODE_CFG_BASET_SGMII 0x01 +@@ -103,19 +102,6 @@ + #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ + #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 + +-#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 +-#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) +-#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) +-#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) +- +-#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 +-#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) +- +-#define AT803X_DEBUG_REG_HIB_CTRL 0x0b +-#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) +-#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) +-#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) +- + #define AT803X_DEBUG_REG_3C 0x3C + + #define AT803X_DEBUG_REG_GREEN 0x3D +@@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8 + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); + +-enum stat_access_type { +- PHY, +- MMD +-}; +- +-struct at803x_hw_stat { +- const char *string; +- u8 reg; +- u32 mask; +- enum stat_access_type access_type; +-}; +- + static struct at803x_hw_stat qca83xx_hw_stats[] = { + { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, + { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, +@@ -439,45 +413,6 @@ struct at803x_context { + u16 led_control; + }; + +-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) +-{ +- int ret; +- +- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); +- if (ret < 0) +- return ret; +- +- return phy_write(phydev, AT803X_DEBUG_DATA, data); +-} +- +-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) +-{ +- int ret; +- +- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); +- if (ret < 0) +- return ret; +- +- return phy_read(phydev, AT803X_DEBUG_DATA); +-} +- +-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, +- u16 clear, u16 set) +-{ +- u16 val; +- int ret; +- +- ret = at803x_debug_reg_read(phydev, reg); +- if (ret < 0) +- return ret; +- +- val = ret & 0xffff; +- val &= ~clear; +- val |= set; +- +- return phy_write(phydev, AT803X_DEBUG_DATA, val); +-} +- + static int at803x_write_page(struct phy_device *phydev, int page) + { + int mask; +--- /dev/null ++++ b/drivers/net/phy/qcom/qcom-phy-lib.c +@@ -0,0 +1,53 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++ ++#include "qcom.h" ++ ++MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions"); ++MODULE_AUTHOR("Matus Ujhelyi"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL"); ++ ++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); ++ if (ret < 0) ++ return ret; ++ ++ return phy_read(phydev, AT803X_DEBUG_DATA); ++} ++EXPORT_SYMBOL_GPL(at803x_debug_reg_read); ++ ++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, ++ u16 clear, u16 set) ++{ ++ u16 val; ++ int ret; ++ ++ ret = at803x_debug_reg_read(phydev, reg); ++ if (ret < 0) ++ return ret; ++ ++ val = ret & 0xffff; ++ val &= ~clear; ++ val |= set; ++ ++ return phy_write(phydev, AT803X_DEBUG_DATA, val); ++} ++EXPORT_SYMBOL_GPL(at803x_debug_reg_mask); ++ ++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); ++ if (ret < 0) ++ return ret; ++ ++ return phy_write(phydev, AT803X_DEBUG_DATA, data); ++} ++EXPORT_SYMBOL_GPL(at803x_debug_reg_write); +--- /dev/null ++++ b/drivers/net/phy/qcom/qcom.h +@@ -0,0 +1,34 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#define AT803X_DEBUG_ADDR 0x1D ++#define AT803X_DEBUG_DATA 0x1E ++ ++#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 ++#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) ++#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) ++#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) ++ ++#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 ++#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) ++ ++#define AT803X_DEBUG_REG_HIB_CTRL 0x0b ++#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) ++#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) ++#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) ++ ++enum stat_access_type { ++ PHY, ++ MMD ++}; ++ ++struct at803x_hw_stat { ++ const char *string; ++ u8 reg; ++ u32 mask; ++ enum stat_access_type access_type; ++}; ++ ++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg); ++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, ++ u16 clear, u16 set); ++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data); diff --git a/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch new file mode 100644 index 0000000000..6ac09dcb9a --- /dev/null +++ b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch @@ -0,0 +1,638 @@ +From 2e45d404d99d43bb7127b74b5dea8818df64996c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 29 Jan 2024 15:15:21 +0100 +Subject: [PATCH 3/5] net: phy: qcom: deatch qca83xx PHY driver from at803x + +Deatch qca83xx PHY driver from at803x. + +The QCA83xx PHYs implement specific function and doesn't use generic +at803x so it can be detached from the driver and moved to a dedicated +one. + +Probe function and priv struct is reimplemented to allocate and use +only the qca83xx specific data. Unused data from at803x PHY driver +are dropped from at803x priv struct. + +This is to make slimmer PHY drivers instead of including lots of bloat +that would never be used in specific SoC. + +A new Kconfig flag QCA83XX_PHY is introduced to compile the new +introduced PHY driver. + +As the Kconfig name starts with Qualcomm the same order is kept. + +Signed-off-by: Christian Marangi +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240129141600.2592-4-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/qcom/Kconfig | 11 +- + drivers/net/phy/qcom/Makefile | 1 + + drivers/net/phy/qcom/at803x.c | 235 ---------------------------- + drivers/net/phy/qcom/qca83xx.c | 275 +++++++++++++++++++++++++++++++++ + 4 files changed, 284 insertions(+), 238 deletions(-) + create mode 100644 drivers/net/phy/qcom/qca83xx.c + +--- a/drivers/net/phy/qcom/Kconfig ++++ b/drivers/net/phy/qcom/Kconfig +@@ -3,9 +3,14 @@ config QCOM_NET_PHYLIB + tristate + + config AT803X_PHY +- tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" ++ tristate "Qualcomm Atheros AR803X PHYs" + select QCOM_NET_PHYLIB + depends on REGULATOR + help +- Currently supports the AR8030, AR8031, AR8033, AR8035 and internal +- QCA8337(Internal qca8k PHY) model ++ Currently supports the AR8030, AR8031, AR8033, AR8035 model ++ ++config QCA83XX_PHY ++ tristate "Qualcomm Atheros QCA833x PHYs" ++ select QCOM_NET_PHYLIB ++ help ++ Currently supports the internal QCA8337(Internal qca8k PHY) model +--- a/drivers/net/phy/qcom/Makefile ++++ b/drivers/net/phy/qcom/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o + obj-$(CONFIG_AT803X_PHY) += at803x.o ++obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -102,17 +102,10 @@ + #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ + #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 + +-#define AT803X_DEBUG_REG_3C 0x3C +- +-#define AT803X_DEBUG_REG_GREEN 0x3D +-#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) +- + #define AT803X_DEBUG_REG_1F 0x1F + #define AT803X_DEBUG_PLL_ON BIT(2) + #define AT803X_DEBUG_RGMII_1V8 BIT(3) + +-#define MDIO_AZ_DEBUG 0x800D +- + /* AT803x supports either the XTAL input pad, an internal PLL or the + * DSP as clock reference for the clock output pad. The XTAL reference + * is only used for 25 MHz output, all other frequencies need the PLL. +@@ -163,13 +156,7 @@ + + #define QCA8081_PHY_ID 0x004dd101 + +-#define QCA8327_A_PHY_ID 0x004dd033 +-#define QCA8327_B_PHY_ID 0x004dd034 +-#define QCA8337_PHY_ID 0x004dd036 + #define QCA9561_PHY_ID 0x004dd042 +-#define QCA8K_PHY_ID_MASK 0xffffffff +- +-#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) + + #define AT803X_PAGE_FIBER 0 + #define AT803X_PAGE_COPPER 1 +@@ -379,12 +366,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8 + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); + +-static struct at803x_hw_stat qca83xx_hw_stats[] = { +- { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, +- { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, +- { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, +-}; +- + struct at803x_ss_mask { + u16 speed_mask; + u8 speed_shift; +@@ -400,7 +381,6 @@ struct at803x_priv { + bool is_1000basex; + struct regulator_dev *vddio_rdev; + struct regulator_dev *vddh_rdev; +- u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; + int led_polarity_mode; + }; + +@@ -564,53 +544,6 @@ static void at803x_get_wol(struct phy_de + wol->wolopts |= WAKE_MAGIC; + } + +-static int qca83xx_get_sset_count(struct phy_device *phydev) +-{ +- return ARRAY_SIZE(qca83xx_hw_stats); +-} +- +-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { +- strscpy(data + i * ETH_GSTRING_LEN, +- qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); +- } +-} +- +-static u64 qca83xx_get_stat(struct phy_device *phydev, int i) +-{ +- struct at803x_hw_stat stat = qca83xx_hw_stats[i]; +- struct at803x_priv *priv = phydev->priv; +- int val; +- u64 ret; +- +- if (stat.access_type == MMD) +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); +- else +- val = phy_read(phydev, stat.reg); +- +- if (val < 0) { +- ret = U64_MAX; +- } else { +- val = val & stat.mask; +- priv->stats[i] += val; +- ret = priv->stats[i]; +- } +- +- return ret; +-} +- +-static void qca83xx_get_stats(struct phy_device *phydev, +- struct ethtool_stats *stats, u64 *data) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) +- data[i] = qca83xx_get_stat(phydev, i); +-} +- + static int at803x_suspend(struct phy_device *phydev) + { + int value; +@@ -1707,124 +1640,6 @@ static int at8035_probe(struct phy_devic + return at8035_parse_dt(phydev); + } + +-static int qca83xx_config_init(struct phy_device *phydev) +-{ +- u8 switch_revision; +- +- switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; +- +- switch (switch_revision) { +- case 1: +- /* For 100M waveform */ +- at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); +- /* Turn on Gigabit clock */ +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); +- break; +- +- case 2: +- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); +- fallthrough; +- case 4: +- phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); +- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); +- break; +- } +- +- /* Following original QCA sourcecode set port to prefer master */ +- phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); +- +- return 0; +-} +- +-static int qca8327_config_init(struct phy_device *phydev) +-{ +- /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. +- * Disable on init and enable only with 100m speed following +- * qca original source code. +- */ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, 0); +- +- return qca83xx_config_init(phydev); +-} +- +-static void qca83xx_link_change_notify(struct phy_device *phydev) +-{ +- /* Set DAC Amplitude adjustment to +6% for 100m on link running */ +- if (phydev->state == PHY_RUNNING) { +- if (phydev->speed == SPEED_100) +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, +- QCA8327_DEBUG_MANU_CTRL_EN); +- } else { +- /* Reset DAC Amplitude adjustment */ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, +- QCA8327_DEBUG_MANU_CTRL_EN, 0); +- } +-} +- +-static int qca83xx_resume(struct phy_device *phydev) +-{ +- int ret, val; +- +- /* Skip reset if not suspended */ +- if (!phydev->suspended) +- return 0; +- +- /* Reinit the port, reset values set by suspend */ +- qca83xx_config_init(phydev); +- +- /* Reset the port on port resume */ +- phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); +- +- /* On resume from suspend the switch execute a reset and +- * restart auto-negotiation. Wait for reset to complete. +- */ +- ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), +- 50000, 600000, true); +- if (ret) +- return ret; +- +- usleep_range(1000, 2000); +- +- return 0; +-} +- +-static int qca83xx_suspend(struct phy_device *phydev) +-{ +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, +- AT803X_DEBUG_GATE_CLK_IN1000, 0); +- +- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, +- AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | +- AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); +- +- return 0; +-} +- +-static int qca8337_suspend(struct phy_device *phydev) +-{ +- /* Only QCA8337 support actual suspend. */ +- genphy_suspend(phydev); +- +- return qca83xx_suspend(phydev); +-} +- +-static int qca8327_suspend(struct phy_device *phydev) +-{ +- u16 mask = 0; +- +- /* QCA8327 cause port unreliability when phy suspend +- * is set. +- */ +- mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); +- phy_modify(phydev, MII_BMCR, mask, 0); +- +- return qca83xx_suspend(phydev); +-} +- + static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) + { + int ret; +@@ -2599,53 +2414,6 @@ static struct phy_driver at803x_driver[] + .soft_reset = genphy_soft_reset, + .config_aneg = at803x_config_aneg, + }, { +- /* QCA8337 */ +- .phy_id = QCA8337_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8337 internal PHY", +- /* PHY_GBIT_FEATURES */ +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca83xx_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8337_suspend, +- .resume = qca83xx_resume, +-}, { +- /* QCA8327-A from switch QCA8327-AL1A */ +- .phy_id = QCA8327_A_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8327-A internal PHY", +- /* PHY_GBIT_FEATURES */ +- .link_change_notify = qca83xx_link_change_notify, +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca8327_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8327_suspend, +- .resume = qca83xx_resume, +-}, { +- /* QCA8327-B from switch QCA8327-BL1A */ +- .phy_id = QCA8327_B_PHY_ID, +- .phy_id_mask = QCA8K_PHY_ID_MASK, +- .name = "Qualcomm Atheros 8327-B internal PHY", +- /* PHY_GBIT_FEATURES */ +- .link_change_notify = qca83xx_link_change_notify, +- .probe = at803x_probe, +- .flags = PHY_IS_INTERNAL, +- .config_init = qca8327_config_init, +- .soft_reset = genphy_soft_reset, +- .get_sset_count = qca83xx_get_sset_count, +- .get_strings = qca83xx_get_strings, +- .get_stats = qca83xx_get_stats, +- .suspend = qca8327_suspend, +- .resume = qca83xx_resume, +-}, { + /* Qualcomm QCA8081 */ + PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), + .name = "Qualcomm QCA8081", +@@ -2683,9 +2451,6 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, + { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, + { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { } +--- /dev/null ++++ b/drivers/net/phy/qcom/qca83xx.c +@@ -0,0 +1,275 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++ ++#include "qcom.h" ++ ++#define AT803X_DEBUG_REG_3C 0x3C ++ ++#define AT803X_DEBUG_REG_GREEN 0x3D ++#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) ++ ++#define MDIO_AZ_DEBUG 0x800D ++ ++#define QCA8327_A_PHY_ID 0x004dd033 ++#define QCA8327_B_PHY_ID 0x004dd034 ++#define QCA8337_PHY_ID 0x004dd036 ++#define QCA8K_PHY_ID_MASK 0xffffffff ++ ++#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) ++ ++static struct at803x_hw_stat qca83xx_hw_stats[] = { ++ { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, ++ { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, ++ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, ++}; ++ ++struct qca83xx_priv { ++ u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; ++}; ++ ++MODULE_DESCRIPTION("Qualcomm Atheros QCA83XX PHY driver"); ++MODULE_AUTHOR("Matus Ujhelyi"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL"); ++ ++static int qca83xx_get_sset_count(struct phy_device *phydev) ++{ ++ return ARRAY_SIZE(qca83xx_hw_stats); ++} ++ ++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { ++ strscpy(data + i * ETH_GSTRING_LEN, ++ qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); ++ } ++} ++ ++static u64 qca83xx_get_stat(struct phy_device *phydev, int i) ++{ ++ struct at803x_hw_stat stat = qca83xx_hw_stats[i]; ++ struct qca83xx_priv *priv = phydev->priv; ++ int val; ++ u64 ret; ++ ++ if (stat.access_type == MMD) ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); ++ else ++ val = phy_read(phydev, stat.reg); ++ ++ if (val < 0) { ++ ret = U64_MAX; ++ } else { ++ val = val & stat.mask; ++ priv->stats[i] += val; ++ ret = priv->stats[i]; ++ } ++ ++ return ret; ++} ++ ++static void qca83xx_get_stats(struct phy_device *phydev, ++ struct ethtool_stats *stats, u64 *data) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) ++ data[i] = qca83xx_get_stat(phydev, i); ++} ++ ++static int qca83xx_probe(struct phy_device *phydev) ++{ ++ struct device *dev = &phydev->mdio.dev; ++ struct qca83xx_priv *priv; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ phydev->priv = priv; ++ ++ return 0; ++} ++ ++static int qca83xx_config_init(struct phy_device *phydev) ++{ ++ u8 switch_revision; ++ ++ switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; ++ ++ switch (switch_revision) { ++ case 1: ++ /* For 100M waveform */ ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); ++ /* Turn on Gigabit clock */ ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); ++ break; ++ ++ case 2: ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); ++ fallthrough; ++ case 4: ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); ++ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); ++ break; ++ } ++ ++ /* Following original QCA sourcecode set port to prefer master */ ++ phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); ++ ++ return 0; ++} ++ ++static int qca8327_config_init(struct phy_device *phydev) ++{ ++ /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. ++ * Disable on init and enable only with 100m speed following ++ * qca original source code. ++ */ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, 0); ++ ++ return qca83xx_config_init(phydev); ++} ++ ++static void qca83xx_link_change_notify(struct phy_device *phydev) ++{ ++ /* Set DAC Amplitude adjustment to +6% for 100m on link running */ ++ if (phydev->state == PHY_RUNNING) { ++ if (phydev->speed == SPEED_100) ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, ++ QCA8327_DEBUG_MANU_CTRL_EN); ++ } else { ++ /* Reset DAC Amplitude adjustment */ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, ++ QCA8327_DEBUG_MANU_CTRL_EN, 0); ++ } ++} ++ ++static int qca83xx_resume(struct phy_device *phydev) ++{ ++ int ret, val; ++ ++ /* Skip reset if not suspended */ ++ if (!phydev->suspended) ++ return 0; ++ ++ /* Reinit the port, reset values set by suspend */ ++ qca83xx_config_init(phydev); ++ ++ /* Reset the port on port resume */ ++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); ++ ++ /* On resume from suspend the switch execute a reset and ++ * restart auto-negotiation. Wait for reset to complete. ++ */ ++ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), ++ 50000, 600000, true); ++ if (ret) ++ return ret; ++ ++ usleep_range(1000, 2000); ++ ++ return 0; ++} ++ ++static int qca83xx_suspend(struct phy_device *phydev) ++{ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, ++ AT803X_DEBUG_GATE_CLK_IN1000, 0); ++ ++ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, ++ AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | ++ AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); ++ ++ return 0; ++} ++ ++static int qca8337_suspend(struct phy_device *phydev) ++{ ++ /* Only QCA8337 support actual suspend. */ ++ genphy_suspend(phydev); ++ ++ return qca83xx_suspend(phydev); ++} ++ ++static int qca8327_suspend(struct phy_device *phydev) ++{ ++ u16 mask = 0; ++ ++ /* QCA8327 cause port unreliability when phy suspend ++ * is set. ++ */ ++ mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); ++ phy_modify(phydev, MII_BMCR, mask, 0); ++ ++ return qca83xx_suspend(phydev); ++} ++ ++static struct phy_driver qca83xx_driver[] = { ++{ ++ /* QCA8337 */ ++ .phy_id = QCA8337_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8337 internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .probe = qca83xx_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca83xx_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8337_suspend, ++ .resume = qca83xx_resume, ++}, { ++ /* QCA8327-A from switch QCA8327-AL1A */ ++ .phy_id = QCA8327_A_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8327-A internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .link_change_notify = qca83xx_link_change_notify, ++ .probe = qca83xx_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca8327_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8327_suspend, ++ .resume = qca83xx_resume, ++}, { ++ /* QCA8327-B from switch QCA8327-BL1A */ ++ .phy_id = QCA8327_B_PHY_ID, ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++ .name = "Qualcomm Atheros 8327-B internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .link_change_notify = qca83xx_link_change_notify, ++ .probe = qca83xx_probe, ++ .flags = PHY_IS_INTERNAL, ++ .config_init = qca8327_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_sset_count = qca83xx_get_sset_count, ++ .get_strings = qca83xx_get_strings, ++ .get_stats = qca83xx_get_stats, ++ .suspend = qca8327_suspend, ++ .resume = qca83xx_resume, ++}, }; ++ ++module_phy_driver(qca83xx_driver); ++ ++static struct mdio_device_id __maybe_unused qca83xx_tbl[] = { ++ { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, qca83xx_tbl); diff --git a/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch new file mode 100644 index 0000000000..9c43ad13b4 --- /dev/null +++ b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch @@ -0,0 +1,1014 @@ +From 249d2b80e4db0e38503ed0ec2af6c7401bc099b9 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 29 Jan 2024 15:15:22 +0100 +Subject: [PATCH 4/5] net: phy: qcom: move additional functions to shared + library + +Move additional functions to shared library in preparation for qca808x +PHY Family to be detached from at803x driver. + +Only the shared defines are moved to the shared qcom.h header. + +Signed-off-by: Christian Marangi +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240129141600.2592-5-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/qcom/at803x.c | 426 +--------------------------- + drivers/net/phy/qcom/qcom-phy-lib.c | 376 ++++++++++++++++++++++++ + drivers/net/phy/qcom/qcom.h | 86 ++++++ + 3 files changed, 463 insertions(+), 425 deletions(-) + +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -24,65 +24,11 @@ + + #include "qcom.h" + +-#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 +-#define AT803X_SFC_ASSERT_CRS BIT(11) +-#define AT803X_SFC_FORCE_LINK BIT(10) +-#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) +-#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 +-#define AT803X_SFC_MANUAL_MDIX 0x1 +-#define AT803X_SFC_MANUAL_MDI 0x0 +-#define AT803X_SFC_SQE_TEST BIT(2) +-#define AT803X_SFC_POLARITY_REVERSAL BIT(1) +-#define AT803X_SFC_DISABLE_JABBER BIT(0) +- +-#define AT803X_SPECIFIC_STATUS 0x11 +-#define AT803X_SS_SPEED_MASK GENMASK(15, 14) +-#define AT803X_SS_SPEED_1000 2 +-#define AT803X_SS_SPEED_100 1 +-#define AT803X_SS_SPEED_10 0 +-#define AT803X_SS_DUPLEX BIT(13) +-#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) +-#define AT803X_SS_MDIX BIT(6) +- +-#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) +-#define QCA808X_SS_SPEED_2500 4 +- +-#define AT803X_INTR_ENABLE 0x12 +-#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) +-#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) +-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) +-#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) +-#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) +-#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) +-#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) +-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) +-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) +-#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) +-#define AT803X_INTR_ENABLE_WOL BIT(0) +- +-#define AT803X_INTR_STATUS 0x13 +- +-#define AT803X_SMART_SPEED 0x14 +-#define AT803X_SMART_SPEED_ENABLE BIT(5) +-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) +-#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) +-#define AT803X_CDT 0x16 +-#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) +-#define AT803X_CDT_ENABLE_TEST BIT(0) +-#define AT803X_CDT_STATUS 0x1c +-#define AT803X_CDT_STATUS_STAT_NORMAL 0 +-#define AT803X_CDT_STATUS_STAT_SHORT 1 +-#define AT803X_CDT_STATUS_STAT_OPEN 2 +-#define AT803X_CDT_STATUS_STAT_FAIL 3 +-#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) +-#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) + #define AT803X_LED_CONTROL 0x18 + + #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 + #define AT803X_WOL_EN BIT(5) +-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C +-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B +-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A ++ + #define AT803X_REG_CHIP_CONFIG 0x1f + #define AT803X_BT_BX_REG_SEL 0x8000 + +@@ -138,10 +84,6 @@ + #define AT803X_CLK_OUT_STRENGTH_HALF 1 + #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 + +-#define AT803X_DEFAULT_DOWNSHIFT 5 +-#define AT803X_MIN_DOWNSHIFT 2 +-#define AT803X_MAX_DOWNSHIFT 9 +- + #define AT803X_MMD3_SMARTEEE_CTL1 0x805b + #define AT803X_MMD3_SMARTEEE_CTL2 0x805c + #define AT803X_MMD3_SMARTEEE_CTL3 0x805d +@@ -366,11 +308,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8 + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); + +-struct at803x_ss_mask { +- u16 speed_mask; +- u8 speed_shift; +-}; +- + struct at803x_priv { + int flags; + u16 clk_25m_reg; +@@ -470,80 +407,6 @@ static void at803x_context_restore(struc + phy_write(phydev, AT803X_LED_CONTROL, context->led_control); + } + +-static int at803x_set_wol(struct phy_device *phydev, +- struct ethtool_wolinfo *wol) +-{ +- int ret, irq_enabled; +- +- if (wol->wolopts & WAKE_MAGIC) { +- struct net_device *ndev = phydev->attached_dev; +- const u8 *mac; +- unsigned int i; +- static const unsigned int offsets[] = { +- AT803X_LOC_MAC_ADDR_32_47_OFFSET, +- AT803X_LOC_MAC_ADDR_16_31_OFFSET, +- AT803X_LOC_MAC_ADDR_0_15_OFFSET, +- }; +- +- if (!ndev) +- return -ENODEV; +- +- mac = (const u8 *)ndev->dev_addr; +- +- if (!is_valid_ether_addr(mac)) +- return -EINVAL; +- +- for (i = 0; i < 3; i++) +- phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], +- mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); +- +- /* Enable WOL interrupt */ +- ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); +- if (ret) +- return ret; +- } else { +- /* Disable WOL interrupt */ +- ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); +- if (ret) +- return ret; +- } +- +- /* Clear WOL status */ +- ret = phy_read(phydev, AT803X_INTR_STATUS); +- if (ret < 0) +- return ret; +- +- /* Check if there are other interrupts except for WOL triggered when PHY is +- * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can +- * be passed up to the interrupt PIN. +- */ +- irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); +- if (irq_enabled < 0) +- return irq_enabled; +- +- irq_enabled &= ~AT803X_INTR_ENABLE_WOL; +- if (ret & irq_enabled && !phy_polling_mode(phydev)) +- phy_trigger_machine(phydev); +- +- return 0; +-} +- +-static void at803x_get_wol(struct phy_device *phydev, +- struct ethtool_wolinfo *wol) +-{ +- int value; +- +- wol->supported = WAKE_MAGIC; +- wol->wolopts = 0; +- +- value = phy_read(phydev, AT803X_INTR_ENABLE); +- if (value < 0) +- return; +- +- if (value & AT803X_INTR_ENABLE_WOL) +- wol->wolopts |= WAKE_MAGIC; +-} +- + static int at803x_suspend(struct phy_device *phydev) + { + int value; +@@ -816,73 +679,6 @@ static int at803x_config_init(struct phy + return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); + } + +-static int at803x_ack_interrupt(struct phy_device *phydev) +-{ +- int err; +- +- err = phy_read(phydev, AT803X_INTR_STATUS); +- +- return (err < 0) ? err : 0; +-} +- +-static int at803x_config_intr(struct phy_device *phydev) +-{ +- int err; +- int value; +- +- value = phy_read(phydev, AT803X_INTR_ENABLE); +- +- if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { +- /* Clear any pending interrupts */ +- err = at803x_ack_interrupt(phydev); +- if (err) +- return err; +- +- value |= AT803X_INTR_ENABLE_AUTONEG_ERR; +- value |= AT803X_INTR_ENABLE_SPEED_CHANGED; +- value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; +- value |= AT803X_INTR_ENABLE_LINK_FAIL; +- value |= AT803X_INTR_ENABLE_LINK_SUCCESS; +- +- err = phy_write(phydev, AT803X_INTR_ENABLE, value); +- } else { +- err = phy_write(phydev, AT803X_INTR_ENABLE, 0); +- if (err) +- return err; +- +- /* Clear any pending interrupts */ +- err = at803x_ack_interrupt(phydev); +- } +- +- return err; +-} +- +-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) +-{ +- int irq_status, int_enabled; +- +- irq_status = phy_read(phydev, AT803X_INTR_STATUS); +- if (irq_status < 0) { +- phy_error(phydev); +- return IRQ_NONE; +- } +- +- /* Read the current enabled interrupts */ +- int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); +- if (int_enabled < 0) { +- phy_error(phydev); +- return IRQ_NONE; +- } +- +- /* See if this was one of our enabled interrupts */ +- if (!(irq_status & int_enabled)) +- return IRQ_NONE; +- +- phy_trigger_machine(phydev); +- +- return IRQ_HANDLED; +-} +- + static void at803x_link_change_notify(struct phy_device *phydev) + { + /* +@@ -908,69 +704,6 @@ static void at803x_link_change_notify(st + } + } + +-static int at803x_read_specific_status(struct phy_device *phydev, +- struct at803x_ss_mask ss_mask) +-{ +- int ss; +- +- /* Read the AT8035 PHY-Specific Status register, which indicates the +- * speed and duplex that the PHY is actually using, irrespective of +- * whether we are in autoneg mode or not. +- */ +- ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); +- if (ss < 0) +- return ss; +- +- if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { +- int sfc, speed; +- +- sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); +- if (sfc < 0) +- return sfc; +- +- speed = ss & ss_mask.speed_mask; +- speed >>= ss_mask.speed_shift; +- +- switch (speed) { +- case AT803X_SS_SPEED_10: +- phydev->speed = SPEED_10; +- break; +- case AT803X_SS_SPEED_100: +- phydev->speed = SPEED_100; +- break; +- case AT803X_SS_SPEED_1000: +- phydev->speed = SPEED_1000; +- break; +- case QCA808X_SS_SPEED_2500: +- phydev->speed = SPEED_2500; +- break; +- } +- if (ss & AT803X_SS_DUPLEX) +- phydev->duplex = DUPLEX_FULL; +- else +- phydev->duplex = DUPLEX_HALF; +- +- if (ss & AT803X_SS_MDIX) +- phydev->mdix = ETH_TP_MDI_X; +- else +- phydev->mdix = ETH_TP_MDI; +- +- switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { +- case AT803X_SFC_MANUAL_MDI: +- phydev->mdix_ctrl = ETH_TP_MDI; +- break; +- case AT803X_SFC_MANUAL_MDIX: +- phydev->mdix_ctrl = ETH_TP_MDI_X; +- break; +- case AT803X_SFC_AUTOMATIC_CROSSOVER: +- phydev->mdix_ctrl = ETH_TP_MDI_AUTO; +- break; +- } +- } +- +- return 0; +-} +- + static int at803x_read_status(struct phy_device *phydev) + { + struct at803x_ss_mask ss_mask = { 0 }; +@@ -1006,50 +739,6 @@ static int at803x_read_status(struct phy + return 0; + } + +-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) +-{ +- u16 val; +- +- switch (ctrl) { +- case ETH_TP_MDI: +- val = AT803X_SFC_MANUAL_MDI; +- break; +- case ETH_TP_MDI_X: +- val = AT803X_SFC_MANUAL_MDIX; +- break; +- case ETH_TP_MDI_AUTO: +- val = AT803X_SFC_AUTOMATIC_CROSSOVER; +- break; +- default: +- return 0; +- } +- +- return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, +- AT803X_SFC_MDI_CROSSOVER_MODE_M, +- FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); +-} +- +-static int at803x_prepare_config_aneg(struct phy_device *phydev) +-{ +- int ret; +- +- ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); +- if (ret < 0) +- return ret; +- +- /* Changes of the midx bits are disruptive to the normal operation; +- * therefore any changes to these registers must be followed by a +- * software reset to take effect. +- */ +- if (ret == 1) { +- ret = genphy_soft_reset(phydev); +- if (ret < 0) +- return ret; +- } +- +- return 0; +-} +- + static int at803x_config_aneg(struct phy_device *phydev) + { + struct at803x_priv *priv = phydev->priv; +@@ -1065,80 +754,6 @@ static int at803x_config_aneg(struct phy + return genphy_config_aneg(phydev); + } + +-static int at803x_get_downshift(struct phy_device *phydev, u8 *d) +-{ +- int val; +- +- val = phy_read(phydev, AT803X_SMART_SPEED); +- if (val < 0) +- return val; +- +- if (val & AT803X_SMART_SPEED_ENABLE) +- *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; +- else +- *d = DOWNSHIFT_DEV_DISABLE; +- +- return 0; +-} +- +-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) +-{ +- u16 mask, set; +- int ret; +- +- switch (cnt) { +- case DOWNSHIFT_DEV_DEFAULT_COUNT: +- cnt = AT803X_DEFAULT_DOWNSHIFT; +- fallthrough; +- case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: +- set = AT803X_SMART_SPEED_ENABLE | +- AT803X_SMART_SPEED_BYPASS_TIMER | +- FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); +- mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; +- break; +- case DOWNSHIFT_DEV_DISABLE: +- set = 0; +- mask = AT803X_SMART_SPEED_ENABLE | +- AT803X_SMART_SPEED_BYPASS_TIMER; +- break; +- default: +- return -EINVAL; +- } +- +- ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); +- +- /* After changing the smart speed settings, we need to perform a +- * software reset, use phy_init_hw() to make sure we set the +- * reapply any values which might got lost during software reset. +- */ +- if (ret == 1) +- ret = phy_init_hw(phydev); +- +- return ret; +-} +- +-static int at803x_get_tunable(struct phy_device *phydev, +- struct ethtool_tunable *tuna, void *data) +-{ +- switch (tuna->id) { +- case ETHTOOL_PHY_DOWNSHIFT: +- return at803x_get_downshift(phydev, data); +- default: +- return -EOPNOTSUPP; +- } +-} +- +-static int at803x_set_tunable(struct phy_device *phydev, +- struct ethtool_tunable *tuna, const void *data) +-{ +- switch (tuna->id) { +- case ETHTOOL_PHY_DOWNSHIFT: +- return at803x_set_downshift(phydev, *(const u8 *)data); +- default: +- return -EOPNOTSUPP; +- } +-} +- + static int at803x_cable_test_result_trans(u16 status) + { + switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { +@@ -1170,45 +785,6 @@ static bool at803x_cdt_fault_length_vali + return false; + } + +-static int at803x_cdt_fault_length(int dt) +-{ +- /* According to the datasheet the distance to the fault is +- * DELTA_TIME * 0.824 meters. +- * +- * The author suspect the correct formula is: +- * +- * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 +- * +- * where c is the speed of light, VF is the velocity factor of +- * the twisted pair cable, 125MHz the counter frequency and +- * we need to divide by 2 because the hardware will measure the +- * round trip time to the fault and back to the PHY. +- * +- * With a VF of 0.69 we get the factor 0.824 mentioned in the +- * datasheet. +- */ +- return (dt * 824) / 10; +-} +- +-static int at803x_cdt_start(struct phy_device *phydev, +- u32 cdt_start) +-{ +- return phy_write(phydev, AT803X_CDT, cdt_start); +-} +- +-static int at803x_cdt_wait_for_completion(struct phy_device *phydev, +- u32 cdt_en) +-{ +- int val, ret; +- +- /* One test run takes about 25ms */ +- ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, +- !(val & cdt_en), +- 30000, 100000, true); +- +- return ret < 0 ? ret : 0; +-} +- + static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) + { + static const int ethtool_pair[] = { +--- a/drivers/net/phy/qcom/qcom-phy-lib.c ++++ b/drivers/net/phy/qcom/qcom-phy-lib.c +@@ -3,6 +3,9 @@ + #include + #include + ++#include ++#include ++ + #include "qcom.h" + + MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions"); +@@ -51,3 +54,376 @@ int at803x_debug_reg_write(struct phy_de + return phy_write(phydev, AT803X_DEBUG_DATA, data); + } + EXPORT_SYMBOL_GPL(at803x_debug_reg_write); ++ ++int at803x_set_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ int ret, irq_enabled; ++ ++ if (wol->wolopts & WAKE_MAGIC) { ++ struct net_device *ndev = phydev->attached_dev; ++ const u8 *mac; ++ unsigned int i; ++ static const unsigned int offsets[] = { ++ AT803X_LOC_MAC_ADDR_32_47_OFFSET, ++ AT803X_LOC_MAC_ADDR_16_31_OFFSET, ++ AT803X_LOC_MAC_ADDR_0_15_OFFSET, ++ }; ++ ++ if (!ndev) ++ return -ENODEV; ++ ++ mac = (const u8 *)ndev->dev_addr; ++ ++ if (!is_valid_ether_addr(mac)) ++ return -EINVAL; ++ ++ for (i = 0; i < 3; i++) ++ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], ++ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); ++ ++ /* Enable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); ++ if (ret) ++ return ret; ++ } else { ++ /* Disable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); ++ if (ret) ++ return ret; ++ } ++ ++ /* Clear WOL status */ ++ ret = phy_read(phydev, AT803X_INTR_STATUS); ++ if (ret < 0) ++ return ret; ++ ++ /* Check if there are other interrupts except for WOL triggered when PHY is ++ * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can ++ * be passed up to the interrupt PIN. ++ */ ++ irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (irq_enabled < 0) ++ return irq_enabled; ++ ++ irq_enabled &= ~AT803X_INTR_ENABLE_WOL; ++ if (ret & irq_enabled && !phy_polling_mode(phydev)) ++ phy_trigger_machine(phydev); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(at803x_set_wol); ++ ++void at803x_get_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ int value; ++ ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = 0; ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (value < 0) ++ return; ++ ++ if (value & AT803X_INTR_ENABLE_WOL) ++ wol->wolopts |= WAKE_MAGIC; ++} ++EXPORT_SYMBOL_GPL(at803x_get_wol); ++ ++int at803x_ack_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = phy_read(phydev, AT803X_INTR_STATUS); ++ ++ return (err < 0) ? err : 0; ++} ++EXPORT_SYMBOL_GPL(at803x_ack_interrupt); ++ ++int at803x_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ int value; ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { ++ /* Clear any pending interrupts */ ++ err = at803x_ack_interrupt(phydev); ++ if (err) ++ return err; ++ ++ value |= AT803X_INTR_ENABLE_AUTONEG_ERR; ++ value |= AT803X_INTR_ENABLE_SPEED_CHANGED; ++ value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; ++ value |= AT803X_INTR_ENABLE_LINK_FAIL; ++ value |= AT803X_INTR_ENABLE_LINK_SUCCESS; ++ ++ err = phy_write(phydev, AT803X_INTR_ENABLE, value); ++ } else { ++ err = phy_write(phydev, AT803X_INTR_ENABLE, 0); ++ if (err) ++ return err; ++ ++ /* Clear any pending interrupts */ ++ err = at803x_ack_interrupt(phydev); ++ } ++ ++ return err; ++} ++EXPORT_SYMBOL_GPL(at803x_config_intr); ++ ++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) ++{ ++ int irq_status, int_enabled; ++ ++ irq_status = phy_read(phydev, AT803X_INTR_STATUS); ++ if (irq_status < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* Read the current enabled interrupts */ ++ int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); ++ if (int_enabled < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* See if this was one of our enabled interrupts */ ++ if (!(irq_status & int_enabled)) ++ return IRQ_NONE; ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++EXPORT_SYMBOL_GPL(at803x_handle_interrupt); ++ ++int at803x_read_specific_status(struct phy_device *phydev, ++ struct at803x_ss_mask ss_mask) ++{ ++ int ss; ++ ++ /* Read the AT8035 PHY-Specific Status register, which indicates the ++ * speed and duplex that the PHY is actually using, irrespective of ++ * whether we are in autoneg mode or not. ++ */ ++ ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); ++ if (ss < 0) ++ return ss; ++ ++ if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { ++ int sfc, speed; ++ ++ sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); ++ if (sfc < 0) ++ return sfc; ++ ++ speed = ss & ss_mask.speed_mask; ++ speed >>= ss_mask.speed_shift; ++ ++ switch (speed) { ++ case AT803X_SS_SPEED_10: ++ phydev->speed = SPEED_10; ++ break; ++ case AT803X_SS_SPEED_100: ++ phydev->speed = SPEED_100; ++ break; ++ case AT803X_SS_SPEED_1000: ++ phydev->speed = SPEED_1000; ++ break; ++ case QCA808X_SS_SPEED_2500: ++ phydev->speed = SPEED_2500; ++ break; ++ } ++ if (ss & AT803X_SS_DUPLEX) ++ phydev->duplex = DUPLEX_FULL; ++ else ++ phydev->duplex = DUPLEX_HALF; ++ ++ if (ss & AT803X_SS_MDIX) ++ phydev->mdix = ETH_TP_MDI_X; ++ else ++ phydev->mdix = ETH_TP_MDI; ++ ++ switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { ++ case AT803X_SFC_MANUAL_MDI: ++ phydev->mdix_ctrl = ETH_TP_MDI; ++ break; ++ case AT803X_SFC_MANUAL_MDIX: ++ phydev->mdix_ctrl = ETH_TP_MDI_X; ++ break; ++ case AT803X_SFC_AUTOMATIC_CROSSOVER: ++ phydev->mdix_ctrl = ETH_TP_MDI_AUTO; ++ break; ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(at803x_read_specific_status); ++ ++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) ++{ ++ u16 val; ++ ++ switch (ctrl) { ++ case ETH_TP_MDI: ++ val = AT803X_SFC_MANUAL_MDI; ++ break; ++ case ETH_TP_MDI_X: ++ val = AT803X_SFC_MANUAL_MDIX; ++ break; ++ case ETH_TP_MDI_AUTO: ++ val = AT803X_SFC_AUTOMATIC_CROSSOVER; ++ break; ++ default: ++ return 0; ++ } ++ ++ return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, ++ AT803X_SFC_MDI_CROSSOVER_MODE_M, ++ FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); ++} ++EXPORT_SYMBOL_GPL(at803x_config_mdix); ++ ++int at803x_prepare_config_aneg(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); ++ if (ret < 0) ++ return ret; ++ ++ /* Changes of the midx bits are disruptive to the normal operation; ++ * therefore any changes to these registers must be followed by a ++ * software reset to take effect. ++ */ ++ if (ret == 1) { ++ ret = genphy_soft_reset(phydev); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(at803x_prepare_config_aneg); ++ ++static int at803x_get_downshift(struct phy_device *phydev, u8 *d) ++{ ++ int val; ++ ++ val = phy_read(phydev, AT803X_SMART_SPEED); ++ if (val < 0) ++ return val; ++ ++ if (val & AT803X_SMART_SPEED_ENABLE) ++ *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; ++ else ++ *d = DOWNSHIFT_DEV_DISABLE; ++ ++ return 0; ++} ++ ++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) ++{ ++ u16 mask, set; ++ int ret; ++ ++ switch (cnt) { ++ case DOWNSHIFT_DEV_DEFAULT_COUNT: ++ cnt = AT803X_DEFAULT_DOWNSHIFT; ++ fallthrough; ++ case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: ++ set = AT803X_SMART_SPEED_ENABLE | ++ AT803X_SMART_SPEED_BYPASS_TIMER | ++ FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); ++ mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; ++ break; ++ case DOWNSHIFT_DEV_DISABLE: ++ set = 0; ++ mask = AT803X_SMART_SPEED_ENABLE | ++ AT803X_SMART_SPEED_BYPASS_TIMER; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); ++ ++ /* After changing the smart speed settings, we need to perform a ++ * software reset, use phy_init_hw() to make sure we set the ++ * reapply any values which might got lost during software reset. ++ */ ++ if (ret == 1) ++ ret = phy_init_hw(phydev); ++ ++ return ret; ++} ++ ++int at803x_get_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return at803x_get_downshift(phydev, data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++EXPORT_SYMBOL_GPL(at803x_get_tunable); ++ ++int at803x_set_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, const void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return at803x_set_downshift(phydev, *(const u8 *)data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++EXPORT_SYMBOL_GPL(at803x_set_tunable); ++ ++int at803x_cdt_fault_length(int dt) ++{ ++ /* According to the datasheet the distance to the fault is ++ * DELTA_TIME * 0.824 meters. ++ * ++ * The author suspect the correct formula is: ++ * ++ * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 ++ * ++ * where c is the speed of light, VF is the velocity factor of ++ * the twisted pair cable, 125MHz the counter frequency and ++ * we need to divide by 2 because the hardware will measure the ++ * round trip time to the fault and back to the PHY. ++ * ++ * With a VF of 0.69 we get the factor 0.824 mentioned in the ++ * datasheet. ++ */ ++ return (dt * 824) / 10; ++} ++EXPORT_SYMBOL_GPL(at803x_cdt_fault_length); ++ ++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start) ++{ ++ return phy_write(phydev, AT803X_CDT, cdt_start); ++} ++EXPORT_SYMBOL_GPL(at803x_cdt_start); ++ ++int at803x_cdt_wait_for_completion(struct phy_device *phydev, ++ u32 cdt_en) ++{ ++ int val, ret; ++ ++ /* One test run takes about 25ms */ ++ ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, ++ !(val & cdt_en), ++ 30000, 100000, true); ++ ++ return ret < 0 ? ret : 0; ++} ++EXPORT_SYMBOL_GPL(at803x_cdt_wait_for_completion); +--- a/drivers/net/phy/qcom/qcom.h ++++ b/drivers/net/phy/qcom/qcom.h +@@ -1,5 +1,63 @@ + /* SPDX-License-Identifier: GPL-2.0 */ + ++#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 ++#define AT803X_SFC_ASSERT_CRS BIT(11) ++#define AT803X_SFC_FORCE_LINK BIT(10) ++#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) ++#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 ++#define AT803X_SFC_MANUAL_MDIX 0x1 ++#define AT803X_SFC_MANUAL_MDI 0x0 ++#define AT803X_SFC_SQE_TEST BIT(2) ++#define AT803X_SFC_POLARITY_REVERSAL BIT(1) ++#define AT803X_SFC_DISABLE_JABBER BIT(0) ++ ++#define AT803X_SPECIFIC_STATUS 0x11 ++#define AT803X_SS_SPEED_MASK GENMASK(15, 14) ++#define AT803X_SS_SPEED_1000 2 ++#define AT803X_SS_SPEED_100 1 ++#define AT803X_SS_SPEED_10 0 ++#define AT803X_SS_DUPLEX BIT(13) ++#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) ++#define AT803X_SS_MDIX BIT(6) ++ ++#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) ++#define QCA808X_SS_SPEED_2500 4 ++ ++#define AT803X_INTR_ENABLE 0x12 ++#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) ++#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) ++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) ++#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) ++#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) ++#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) ++#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) ++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) ++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) ++#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) ++#define AT803X_INTR_ENABLE_WOL BIT(0) ++ ++#define AT803X_INTR_STATUS 0x13 ++ ++#define AT803X_SMART_SPEED 0x14 ++#define AT803X_SMART_SPEED_ENABLE BIT(5) ++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) ++#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) ++ ++#define AT803X_CDT 0x16 ++#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) ++#define AT803X_CDT_ENABLE_TEST BIT(0) ++#define AT803X_CDT_STATUS 0x1c ++#define AT803X_CDT_STATUS_STAT_NORMAL 0 ++#define AT803X_CDT_STATUS_STAT_SHORT 1 ++#define AT803X_CDT_STATUS_STAT_OPEN 2 ++#define AT803X_CDT_STATUS_STAT_FAIL 3 ++#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) ++#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) ++ ++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C ++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B ++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A ++ + #define AT803X_DEBUG_ADDR 0x1D + #define AT803X_DEBUG_DATA 0x1E + +@@ -16,6 +74,10 @@ + #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) + #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) + ++#define AT803X_DEFAULT_DOWNSHIFT 5 ++#define AT803X_MIN_DOWNSHIFT 2 ++#define AT803X_MAX_DOWNSHIFT 9 ++ + enum stat_access_type { + PHY, + MMD +@@ -28,7 +90,31 @@ struct at803x_hw_stat { + enum stat_access_type access_type; + }; + ++struct at803x_ss_mask { ++ u16 speed_mask; ++ u8 speed_shift; ++}; ++ + int at803x_debug_reg_read(struct phy_device *phydev, u16 reg); + int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, + u16 clear, u16 set); + int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data); ++int at803x_set_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol); ++void at803x_get_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol); ++int at803x_ack_interrupt(struct phy_device *phydev); ++int at803x_config_intr(struct phy_device *phydev); ++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev); ++int at803x_read_specific_status(struct phy_device *phydev, ++ struct at803x_ss_mask ss_mask); ++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl); ++int at803x_prepare_config_aneg(struct phy_device *phydev); ++int at803x_get_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, void *data); ++int at803x_set_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, const void *data); ++int at803x_cdt_fault_length(int dt); ++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start); ++int at803x_cdt_wait_for_completion(struct phy_device *phydev, ++ u32 cdt_en); diff --git a/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch new file mode 100644 index 0000000000..597dcea4c0 --- /dev/null +++ b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch @@ -0,0 +1,1936 @@ +From c89414adf2ec7cd9e7080c419aa5847f1db1009c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 29 Jan 2024 15:15:23 +0100 +Subject: [PATCH 5/5] net: phy: qcom: detach qca808x PHY driver from at803x + +Almost all the QCA8081 PHY driver OPs are specific and only some of them +use the generic at803x. + +To make the at803x code slimmer, move all the specific qca808x regs and +functions to a dedicated PHY driver. + +Probe function and priv struct is reworked to allocate and use only the +qca808x specific data. Unused data from at803x PHY driver are dropped +from at803x priv struct. + +Also a new Kconfig is introduced QCA808X_PHY, to compile the newly +introduced PHY driver for QCA8081 PHY. + +As the Kconfig name starts with Qualcomm the same order is kept. + +Signed-off-by: Christian Marangi +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240129141600.2592-6-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/qcom/Kconfig | 6 + + drivers/net/phy/qcom/Makefile | 1 + + drivers/net/phy/qcom/at803x.c | 897 +------------------------------ + drivers/net/phy/qcom/qca808x.c | 934 +++++++++++++++++++++++++++++++++ + 4 files changed, 942 insertions(+), 896 deletions(-) + create mode 100644 drivers/net/phy/qcom/qca808x.c + +--- a/drivers/net/phy/qcom/Kconfig ++++ b/drivers/net/phy/qcom/Kconfig +@@ -14,3 +14,9 @@ config QCA83XX_PHY + select QCOM_NET_PHYLIB + help + Currently supports the internal QCA8337(Internal qca8k PHY) model ++ ++config QCA808X_PHY ++ tristate "Qualcomm QCA808x PHYs" ++ select QCOM_NET_PHYLIB ++ help ++ Currently supports the QCA8081 model +--- a/drivers/net/phy/qcom/Makefile ++++ b/drivers/net/phy/qcom/Makefile +@@ -2,3 +2,4 @@ + obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o + obj-$(CONFIG_AT803X_PHY) += at803x.o + obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o ++obj-$(CONFIG_QCA808X_PHY) += qca808x.o +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -96,8 +96,6 @@ + #define ATH8035_PHY_ID 0x004dd072 + #define AT8030_PHY_ID_MASK 0xffffffef + +-#define QCA8081_PHY_ID 0x004dd101 +- + #define QCA9561_PHY_ID 0x004dd042 + + #define AT803X_PAGE_FIBER 0 +@@ -110,201 +108,7 @@ + /* disable hibernation mode */ + #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) + +-/* ADC threshold */ +-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 +-#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) +-#define QCA808X_ADC_THRESHOLD_80MV 0 +-#define QCA808X_ADC_THRESHOLD_100MV 0xf0 +-#define QCA808X_ADC_THRESHOLD_200MV 0x0f +-#define QCA808X_ADC_THRESHOLD_300MV 0xff +- +-/* CLD control */ +-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 +-#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) +-#define QCA808X_8023AZ_AFE_EN 0x90 +- +-/* AZ control */ +-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 +-#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 +-#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E +-#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E +-#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 +- +-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 +-#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 +- +-#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c +-#define QCA808X_TOP_OPTION1_DATA 0x0 +- +-#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 +-#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 +-#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 +-#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad +-#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 +-#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 +-#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 +-#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 +-#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 +-#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 +-#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 +-#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 +- +-/* master/slave seed config */ +-#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 +-#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) +-#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) +-#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 +- +-/* Hibernation yields lower power consumpiton in contrast with normal operation mode. +- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. +- */ +-#define QCA808X_DBG_AN_TEST 0xb +-#define QCA808X_HIBERNATION_EN BIT(15) +- +-#define QCA808X_CDT_ENABLE_TEST BIT(15) +-#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) +-#define QCA808X_CDT_STATUS BIT(11) +-#define QCA808X_CDT_LENGTH_UNIT BIT(10) +- +-#define QCA808X_MMD3_CDT_STATUS 0x8064 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 +-#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 +-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) +-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) +- +-#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) +-#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) +-#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) +-#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) +- +-#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) +-#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) +-#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) +-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) +-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) +- +-#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) +-#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) +-#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) +-#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) +- +-/* NORMAL are MDI with type set to 0 */ +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI1) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI1) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI2) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI2) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ +- QCA808X_CDT_STATUS_STAT_MDI3) +-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ +- QCA808X_CDT_STATUS_STAT_MDI3) +- +-/* Added for reference of existence but should be handled by wait_for_completion already */ +-#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) +- +-#define QCA808X_MMD7_LED_GLOBAL 0x8073 +-#define QCA808X_LED_BLINK_1 GENMASK(11, 6) +-#define QCA808X_LED_BLINK_2 GENMASK(5, 0) +-/* Values are the same for both BLINK_1 and BLINK_2 */ +-#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) +-#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) +-#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) +-#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) +-#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) +-#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) +-#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) +-#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) +-#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) +-#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) +-#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) +-#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) +-#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) +-#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) +-#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) +-#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) +-#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) +-#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) +- +-#define QCA808X_MMD7_LED2_CTRL 0x8074 +-#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 +-#define QCA808X_MMD7_LED1_CTRL 0x8076 +-#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 +-#define QCA808X_MMD7_LED0_CTRL 0x8078 +-#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) +- +-/* LED hw control pattern is the same for every LED */ +-#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) +-#define QCA808X_LED_SPEED2500_ON BIT(15) +-#define QCA808X_LED_SPEED2500_BLINK BIT(14) +-/* Follow blink trigger even if duplex or speed condition doesn't match */ +-#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) +-#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) +-#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) +-#define QCA808X_LED_TX_BLINK BIT(10) +-#define QCA808X_LED_RX_BLINK BIT(9) +-#define QCA808X_LED_TX_ON_10MS BIT(8) +-#define QCA808X_LED_RX_ON_10MS BIT(7) +-#define QCA808X_LED_SPEED1000_ON BIT(6) +-#define QCA808X_LED_SPEED100_ON BIT(5) +-#define QCA808X_LED_SPEED10_ON BIT(4) +-#define QCA808X_LED_COLLISION_BLINK BIT(3) +-#define QCA808X_LED_SPEED1000_BLINK BIT(2) +-#define QCA808X_LED_SPEED100_BLINK BIT(1) +-#define QCA808X_LED_SPEED10_BLINK BIT(0) +- +-#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 +-#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) +- +-/* LED force ctrl is the same for every LED +- * No documentation exist for this, not even internal one +- * with NDA as QCOM gives only info about configuring +- * hw control pattern rules and doesn't indicate any way +- * to force the LED to specific mode. +- * These define comes from reverse and testing and maybe +- * lack of some info or some info are not entirely correct. +- * For the basic LED control and hw control these finding +- * are enough to support LED control in all the required APIs. +- * +- * On doing some comparison with implementation with qca807x, +- * it was found that it's 1:1 equal to it and confirms all the +- * reverse done. It was also found further specification with the +- * force mode and the blink modes. +- */ +-#define QCA808X_LED_FORCE_EN BIT(15) +-#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) +-#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) +-#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) +-#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) +-#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) +- +-#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a +-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for +- * LED to active high. It's not clear what BIT 3 and BIT 4 does. +- */ +-#define QCA808X_LED_ACTIVE_HIGH BIT(6) +- +-/* QCA808X 1G chip type */ +-#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d +-#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) +- +-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 +-#define QCA8081_PHY_FIFO_RSTN BIT(11) +- +-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); + +@@ -318,7 +122,6 @@ struct at803x_priv { + bool is_1000basex; + struct regulator_dev *vddio_rdev; + struct regulator_dev *vddh_rdev; +- int led_polarity_mode; + }; + + struct at803x_context { +@@ -519,9 +322,6 @@ static int at803x_probe(struct phy_devic + if (!priv) + return -ENOMEM; + +- /* Init LED polarity mode to -1 */ +- priv->led_polarity_mode = -1; +- + phydev->priv = priv; + + ret = at803x_parse_dt(phydev); +@@ -1216,672 +1016,6 @@ static int at8035_probe(struct phy_devic + return at8035_parse_dt(phydev); + } + +-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) +-{ +- int ret; +- +- /* Enable fast retrain */ +- ret = genphy_c45_fast_retrain(phydev, true); +- if (ret) +- return ret; +- +- phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, +- QCA808X_TOP_OPTION1_DATA); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, +- QCA808X_MSE_THRESHOLD_20DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, +- QCA808X_MSE_THRESHOLD_17DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, +- QCA808X_MSE_THRESHOLD_27DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, +- QCA808X_MSE_THRESHOLD_28DB_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, +- QCA808X_MMD3_DEBUG_1_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, +- QCA808X_MMD3_DEBUG_4_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, +- QCA808X_MMD3_DEBUG_5_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, +- QCA808X_MMD3_DEBUG_3_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, +- QCA808X_MMD3_DEBUG_6_VALUE); +- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, +- QCA808X_MMD3_DEBUG_2_VALUE); +- +- return 0; +-} +- +-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) +-{ +- u16 seed_value; +- +- if (!enable) +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +- QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); +- +- seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE); +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +- QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, +- FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | +- QCA808X_MASTER_SLAVE_SEED_ENABLE); +-} +- +-static bool qca808x_is_prefer_master(struct phy_device *phydev) +-{ +- return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || +- (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); +-} +- +-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) +-{ +- return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); +-} +- +-static int qca808x_config_init(struct phy_device *phydev) +-{ +- int ret; +- +- /* Active adc&vga on 802.3az for the link 1000M and 100M */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, +- QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); +- if (ret) +- return ret; +- +- /* Adjust the threshold on 802.3az for the link 1000M */ +- ret = phy_write_mmd(phydev, MDIO_MMD_PCS, +- QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, +- QCA808X_MMD3_AZ_TRAINING_VAL); +- if (ret) +- return ret; +- +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { +- /* Config the fast retrain for the link 2500M */ +- ret = qca808x_phy_fast_retrain_config(phydev); +- if (ret) +- return ret; +- +- ret = genphy_read_master_slave(phydev); +- if (ret < 0) +- return ret; +- +- if (!qca808x_is_prefer_master(phydev)) { +- /* Enable seed and configure lower ramdom seed to make phy +- * linked as slave mode. +- */ +- ret = qca808x_phy_ms_seed_enable(phydev, true); +- if (ret) +- return ret; +- } +- } +- +- /* Configure adc threshold as 100mv for the link 10M */ +- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, +- QCA808X_ADC_THRESHOLD_MASK, +- QCA808X_ADC_THRESHOLD_100MV); +-} +- +-static int qca808x_read_status(struct phy_device *phydev) +-{ +- struct at803x_ss_mask ss_mask = { 0 }; +- int ret; +- +- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); +- if (ret < 0) +- return ret; +- +- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, +- ret & MDIO_AN_10GBT_STAT_LP2_5G); +- +- ret = genphy_read_status(phydev); +- if (ret) +- return ret; +- +- /* qca8081 takes the different bits for speed value from at803x */ +- ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; +- ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); +- ret = at803x_read_specific_status(phydev, ss_mask); +- if (ret < 0) +- return ret; +- +- if (phydev->link) { +- if (phydev->speed == SPEED_2500) +- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- else +- phydev->interface = PHY_INTERFACE_MODE_SGMII; +- } else { +- /* generate seed as a lower random value to make PHY linked as SLAVE easily, +- * except for master/slave configuration fault detected or the master mode +- * preferred. +- * +- * the reason for not putting this code into the function link_change_notify is +- * the corner case where the link partner is also the qca8081 PHY and the seed +- * value is configured as the same value, the link can't be up and no link change +- * occurs. +- */ +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { +- if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || +- qca808x_is_prefer_master(phydev)) { +- qca808x_phy_ms_seed_enable(phydev, false); +- } else { +- qca808x_phy_ms_seed_enable(phydev, true); +- } +- } +- } +- +- return 0; +-} +- +-static int qca808x_soft_reset(struct phy_device *phydev) +-{ +- int ret; +- +- ret = genphy_soft_reset(phydev); +- if (ret < 0) +- return ret; +- +- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) +- ret = qca808x_phy_ms_seed_enable(phydev, true); +- +- return ret; +-} +- +-static bool qca808x_cdt_fault_length_valid(int cdt_code) +-{ +- switch (cdt_code) { +- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: +- return true; +- default: +- return false; +- } +-} +- +-static int qca808x_cable_test_result_trans(int cdt_code) +-{ +- switch (cdt_code) { +- case QCA808X_CDT_STATUS_STAT_NORMAL: +- return ETHTOOL_A_CABLE_RESULT_CODE_OK; +- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: +- return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; +- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: +- return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: +- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: +- return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; +- case QCA808X_CDT_STATUS_STAT_FAIL: +- default: +- return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; +- } +-} +- +-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, +- int result) +-{ +- int val; +- u32 cdt_length_reg = 0; +- +- switch (pair) { +- case ETHTOOL_A_CABLE_PAIR_A: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; +- break; +- case ETHTOOL_A_CABLE_PAIR_B: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; +- break; +- case ETHTOOL_A_CABLE_PAIR_C: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; +- break; +- case ETHTOOL_A_CABLE_PAIR_D: +- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; +- break; +- default: +- return -EINVAL; +- } +- +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); +- if (val < 0) +- return val; +- +- if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) +- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); +- else +- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); +- +- return at803x_cdt_fault_length(val); +-} +- +-static int qca808x_cable_test_start(struct phy_device *phydev) +-{ +- int ret; +- +- /* perform CDT with the following configs: +- * 1. disable hibernation. +- * 2. force PHY working in MDI mode. +- * 3. for PHY working in 1000BaseT. +- * 4. configure the threshold. +- */ +- +- ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); +- if (ret < 0) +- return ret; +- +- ret = at803x_config_mdix(phydev, ETH_TP_MDI); +- if (ret < 0) +- return ret; +- +- /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ +- phydev->duplex = DUPLEX_FULL; +- phydev->speed = SPEED_1000; +- ret = genphy_c45_pma_setup_forced(phydev); +- if (ret < 0) +- return ret; +- +- ret = genphy_setup_forced(phydev); +- if (ret < 0) +- return ret; +- +- /* configure the thresholds for open, short, pair ok test */ +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); +- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); +- +- return 0; +-} +- +-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, +- u16 status) +-{ +- int length, result; +- u16 pair_code; +- +- switch (pair) { +- case ETHTOOL_A_CABLE_PAIR_A: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_B: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_C: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); +- break; +- case ETHTOOL_A_CABLE_PAIR_D: +- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); +- break; +- default: +- return -EINVAL; +- } +- +- result = qca808x_cable_test_result_trans(pair_code); +- ethnl_cable_test_result(phydev, pair, result); +- +- if (qca808x_cdt_fault_length_valid(pair_code)) { +- length = qca808x_cdt_fault_length(phydev, pair, result); +- ethnl_cable_test_fault_length(phydev, pair, length); +- } +- +- return 0; +-} +- +-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) +-{ +- int ret, val; +- +- *finished = false; +- +- val = QCA808X_CDT_ENABLE_TEST | +- QCA808X_CDT_LENGTH_UNIT; +- ret = at803x_cdt_start(phydev, val); +- if (ret) +- return ret; +- +- ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); +- if (ret) +- return ret; +- +- val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); +- if (val < 0) +- return val; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); +- if (ret) +- return ret; +- +- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); +- if (ret) +- return ret; +- +- *finished = true; +- +- return 0; +-} +- +-static int qca808x_get_features(struct phy_device *phydev) +-{ +- int ret; +- +- ret = genphy_c45_pma_read_abilities(phydev); +- if (ret) +- return ret; +- +- /* The autoneg ability is not existed in bit3 of MMD7.1, +- * but it is supported by qca808x PHY, so we add it here +- * manually. +- */ +- linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); +- +- /* As for the qca8081 1G version chip, the 2500baseT ability is also +- * existed in the bit0 of MMD1.21, we need to remove it manually if +- * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. +- */ +- ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); +- if (ret < 0) +- return ret; +- +- if (QCA808X_PHY_CHIP_TYPE_1G & ret) +- linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); +- +- return 0; +-} +- +-static int qca808x_config_aneg(struct phy_device *phydev) +-{ +- int phy_ctrl = 0; +- int ret; +- +- ret = at803x_prepare_config_aneg(phydev); +- if (ret) +- return ret; +- +- /* The reg MII_BMCR also needs to be configured for force mode, the +- * genphy_config_aneg is also needed. +- */ +- if (phydev->autoneg == AUTONEG_DISABLE) +- genphy_c45_pma_setup_forced(phydev); +- +- if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) +- phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; +- +- ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, +- MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); +- if (ret < 0) +- return ret; +- +- return __genphy_config_aneg(phydev, ret); +-} +- +-static void qca808x_link_change_notify(struct phy_device *phydev) +-{ +- /* Assert interface sgmii fifo on link down, deassert it on link up, +- * the interface device address is always phy address added by 1. +- */ +- mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, +- MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, +- QCA8081_PHY_FIFO_RSTN, +- phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); +-} +- +-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, +- u16 *offload_trigger) +-{ +- /* Parsing specific to netdev trigger */ +- if (test_bit(TRIGGER_NETDEV_TX, &rules)) +- *offload_trigger |= QCA808X_LED_TX_BLINK; +- if (test_bit(TRIGGER_NETDEV_RX, &rules)) +- *offload_trigger |= QCA808X_LED_RX_BLINK; +- if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED10_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED100_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED1000_ON; +- if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) +- *offload_trigger |= QCA808X_LED_SPEED2500_ON; +- if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) +- *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; +- if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) +- *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; +- +- if (rules && !*offload_trigger) +- return -EOPNOTSUPP; +- +- /* Enable BLINK_CHECK_BYPASS by default to make the LED +- * blink even with duplex or speed mode not enabled. +- */ +- *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; +- +- return 0; +-} +- +-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN); +-} +- +-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- u16 offload_trigger = 0; +- +- if (index > 2) +- return -EINVAL; +- +- return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +-} +- +-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- u16 reg, offload_trigger = 0; +- int ret; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +- if (ret) +- return ret; +- +- ret = qca808x_led_hw_control_enable(phydev, index); +- if (ret) +- return ret; +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_PATTERN_MASK, +- offload_trigger); +-} +- +-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- int val; +- +- if (index > 2) +- return false; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); +- +- return !(val & QCA808X_LED_FORCE_EN); +-} +- +-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, +- unsigned long *rules) +-{ +- u16 reg; +- int val; +- +- if (index > 2) +- return -EINVAL; +- +- /* Check if we have hw control enabled */ +- if (qca808x_led_hw_control_status(phydev, index)) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); +- if (val & QCA808X_LED_TX_BLINK) +- set_bit(TRIGGER_NETDEV_TX, rules); +- if (val & QCA808X_LED_RX_BLINK) +- set_bit(TRIGGER_NETDEV_RX, rules); +- if (val & QCA808X_LED_SPEED10_ON) +- set_bit(TRIGGER_NETDEV_LINK_10, rules); +- if (val & QCA808X_LED_SPEED100_ON) +- set_bit(TRIGGER_NETDEV_LINK_100, rules); +- if (val & QCA808X_LED_SPEED1000_ON) +- set_bit(TRIGGER_NETDEV_LINK_1000, rules); +- if (val & QCA808X_LED_SPEED2500_ON) +- set_bit(TRIGGER_NETDEV_LINK_2500, rules); +- if (val & QCA808X_LED_HALF_DUPLEX_ON) +- set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); +- if (val & QCA808X_LED_FULL_DUPLEX_ON) +- set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); +- +- return 0; +-} +- +-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) +-{ +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_CTRL(index); +- +- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_PATTERN_MASK); +-} +- +-static int qca808x_led_brightness_set(struct phy_device *phydev, +- u8 index, enum led_brightness value) +-{ +- u16 reg; +- int ret; +- +- if (index > 2) +- return -EINVAL; +- +- if (!value) { +- ret = qca808x_led_hw_control_reset(phydev, index); +- if (ret) +- return ret; +- } +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, +- QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : +- QCA808X_LED_FORCE_OFF); +-} +- +-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, +- unsigned long *delay_on, +- unsigned long *delay_off) +-{ +- int ret; +- u16 reg; +- +- if (index > 2) +- return -EINVAL; +- +- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); +- +- /* Set blink to 50% off, 50% on at 4Hz by default */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, +- QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, +- QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); +- if (ret) +- return ret; +- +- /* We use BLINK_1 for normal blinking */ +- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, +- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); +- if (ret) +- return ret; +- +- /* We set blink to 4Hz, aka 250ms */ +- *delay_on = 250 / 2; +- *delay_off = 250 / 2; +- +- return 0; +-} +- +-static int qca808x_led_polarity_set(struct phy_device *phydev, int index, +- unsigned long modes) +-{ +- struct at803x_priv *priv = phydev->priv; +- bool active_low = false; +- u32 mode; +- +- for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { +- switch (mode) { +- case PHY_LED_ACTIVE_LOW: +- active_low = true; +- break; +- default: +- return -EINVAL; +- } +- } +- +- /* PHY polarity is global and can't be set per LED. +- * To detect this, check if last requested polarity mode +- * match the new one. +- */ +- if (priv->led_polarity_mode >= 0 && +- priv->led_polarity_mode != active_low) { +- phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); +- return -EINVAL; +- } +- +- /* Save the last PHY polarity mode */ +- priv->led_polarity_mode = active_low; +- +- return phy_modify_mmd(phydev, MDIO_MMD_AN, +- QCA808X_MMD7_LED_POLARITY_CTRL, +- QCA808X_LED_ACTIVE_HIGH, +- active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); +-} +- + static struct phy_driver at803x_driver[] = { + { + /* Qualcomm Atheros AR8035 */ +@@ -1989,34 +1123,6 @@ static struct phy_driver at803x_driver[] + .read_status = at803x_read_status, + .soft_reset = genphy_soft_reset, + .config_aneg = at803x_config_aneg, +-}, { +- /* Qualcomm QCA8081 */ +- PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), +- .name = "Qualcomm QCA8081", +- .flags = PHY_POLL_CABLE_TEST, +- .probe = at803x_probe, +- .config_intr = at803x_config_intr, +- .handle_interrupt = at803x_handle_interrupt, +- .get_tunable = at803x_get_tunable, +- .set_tunable = at803x_set_tunable, +- .set_wol = at803x_set_wol, +- .get_wol = at803x_get_wol, +- .get_features = qca808x_get_features, +- .config_aneg = qca808x_config_aneg, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_status = qca808x_read_status, +- .config_init = qca808x_config_init, +- .soft_reset = qca808x_soft_reset, +- .cable_test_start = qca808x_cable_test_start, +- .cable_test_get_status = qca808x_cable_test_get_status, +- .link_change_notify = qca808x_link_change_notify, +- .led_brightness_set = qca808x_led_brightness_set, +- .led_blink_set = qca808x_led_blink_set, +- .led_hw_is_supported = qca808x_led_hw_is_supported, +- .led_hw_control_set = qca808x_led_hw_control_set, +- .led_hw_control_get = qca808x_led_hw_control_get, +- .led_polarity_set = qca808x_led_polarity_set, + }, }; + + module_phy_driver(at803x_driver); +@@ -2028,7 +1134,6 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, + { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, +- { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { } + }; + +--- /dev/null ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -0,0 +1,934 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++ ++#include "qcom.h" ++ ++/* ADC threshold */ ++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 ++#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) ++#define QCA808X_ADC_THRESHOLD_80MV 0 ++#define QCA808X_ADC_THRESHOLD_100MV 0xf0 ++#define QCA808X_ADC_THRESHOLD_200MV 0x0f ++#define QCA808X_ADC_THRESHOLD_300MV 0xff ++ ++/* CLD control */ ++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 ++#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) ++#define QCA808X_8023AZ_AFE_EN 0x90 ++ ++/* AZ control */ ++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 ++#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 ++#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E ++#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E ++#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 ++ ++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 ++#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 ++ ++#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c ++#define QCA808X_TOP_OPTION1_DATA 0x0 ++ ++#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 ++#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 ++#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 ++#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad ++#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 ++#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 ++#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 ++#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 ++#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 ++#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 ++#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 ++#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 ++ ++/* master/slave seed config */ ++#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 ++#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) ++#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) ++#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 ++ ++/* Hibernation yields lower power consumpiton in contrast with normal operation mode. ++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. ++ */ ++#define QCA808X_DBG_AN_TEST 0xb ++#define QCA808X_HIBERNATION_EN BIT(15) ++ ++#define QCA808X_CDT_ENABLE_TEST BIT(15) ++#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) ++#define QCA808X_CDT_STATUS BIT(11) ++#define QCA808X_CDT_LENGTH_UNIT BIT(10) ++ ++#define QCA808X_MMD3_CDT_STATUS 0x8064 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 ++#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 ++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) ++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) ++ ++#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) ++#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) ++#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) ++#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) ++ ++#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) ++#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) ++#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) ++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) ++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) ++ ++#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) ++#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) ++#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) ++#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) ++ ++/* NORMAL are MDI with type set to 0 */ ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI1) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI1) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI2) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI2) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ ++ QCA808X_CDT_STATUS_STAT_MDI3) ++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ ++ QCA808X_CDT_STATUS_STAT_MDI3) ++ ++/* Added for reference of existence but should be handled by wait_for_completion already */ ++#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) ++ ++#define QCA808X_MMD7_LED_GLOBAL 0x8073 ++#define QCA808X_LED_BLINK_1 GENMASK(11, 6) ++#define QCA808X_LED_BLINK_2 GENMASK(5, 0) ++/* Values are the same for both BLINK_1 and BLINK_2 */ ++#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) ++#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) ++#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) ++#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) ++#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) ++#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) ++#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) ++#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) ++#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) ++#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) ++#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) ++#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) ++#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) ++#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) ++#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) ++#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) ++#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) ++#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) ++ ++#define QCA808X_MMD7_LED2_CTRL 0x8074 ++#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 ++#define QCA808X_MMD7_LED1_CTRL 0x8076 ++#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 ++#define QCA808X_MMD7_LED0_CTRL 0x8078 ++#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) ++ ++/* LED hw control pattern is the same for every LED */ ++#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) ++#define QCA808X_LED_SPEED2500_ON BIT(15) ++#define QCA808X_LED_SPEED2500_BLINK BIT(14) ++/* Follow blink trigger even if duplex or speed condition doesn't match */ ++#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) ++#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) ++#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) ++#define QCA808X_LED_TX_BLINK BIT(10) ++#define QCA808X_LED_RX_BLINK BIT(9) ++#define QCA808X_LED_TX_ON_10MS BIT(8) ++#define QCA808X_LED_RX_ON_10MS BIT(7) ++#define QCA808X_LED_SPEED1000_ON BIT(6) ++#define QCA808X_LED_SPEED100_ON BIT(5) ++#define QCA808X_LED_SPEED10_ON BIT(4) ++#define QCA808X_LED_COLLISION_BLINK BIT(3) ++#define QCA808X_LED_SPEED1000_BLINK BIT(2) ++#define QCA808X_LED_SPEED100_BLINK BIT(1) ++#define QCA808X_LED_SPEED10_BLINK BIT(0) ++ ++#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 ++#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) ++ ++/* LED force ctrl is the same for every LED ++ * No documentation exist for this, not even internal one ++ * with NDA as QCOM gives only info about configuring ++ * hw control pattern rules and doesn't indicate any way ++ * to force the LED to specific mode. ++ * These define comes from reverse and testing and maybe ++ * lack of some info or some info are not entirely correct. ++ * For the basic LED control and hw control these finding ++ * are enough to support LED control in all the required APIs. ++ * ++ * On doing some comparison with implementation with qca807x, ++ * it was found that it's 1:1 equal to it and confirms all the ++ * reverse done. It was also found further specification with the ++ * force mode and the blink modes. ++ */ ++#define QCA808X_LED_FORCE_EN BIT(15) ++#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) ++#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) ++#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) ++#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) ++#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) ++ ++#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a ++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for ++ * LED to active high. It's not clear what BIT 3 and BIT 4 does. ++ */ ++#define QCA808X_LED_ACTIVE_HIGH BIT(6) ++ ++/* QCA808X 1G chip type */ ++#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d ++#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) ++ ++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 ++#define QCA8081_PHY_FIFO_RSTN BIT(11) ++ ++#define QCA8081_PHY_ID 0x004dd101 ++ ++MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); ++MODULE_AUTHOR("Matus Ujhelyi"); ++MODULE_LICENSE("GPL"); ++ ++struct qca808x_priv { ++ int led_polarity_mode; ++}; ++ ++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Enable fast retrain */ ++ ret = genphy_c45_fast_retrain(phydev, true); ++ if (ret) ++ return ret; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, ++ QCA808X_TOP_OPTION1_DATA); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, ++ QCA808X_MSE_THRESHOLD_20DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, ++ QCA808X_MSE_THRESHOLD_17DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, ++ QCA808X_MSE_THRESHOLD_27DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, ++ QCA808X_MSE_THRESHOLD_28DB_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, ++ QCA808X_MMD3_DEBUG_1_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, ++ QCA808X_MMD3_DEBUG_4_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, ++ QCA808X_MMD3_DEBUG_5_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, ++ QCA808X_MMD3_DEBUG_3_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, ++ QCA808X_MMD3_DEBUG_6_VALUE); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, ++ QCA808X_MMD3_DEBUG_2_VALUE); ++ ++ return 0; ++} ++ ++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) ++{ ++ u16 seed_value; ++ ++ if (!enable) ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, ++ QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); ++ ++ seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE); ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, ++ QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, ++ FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | ++ QCA808X_MASTER_SLAVE_SEED_ENABLE); ++} ++ ++static bool qca808x_is_prefer_master(struct phy_device *phydev) ++{ ++ return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || ++ (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); ++} ++ ++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) ++{ ++ return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); ++} ++ ++static int qca808x_probe(struct phy_device *phydev) ++{ ++ struct device *dev = &phydev->mdio.dev; ++ struct qca808x_priv *priv; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ /* Init LED polarity mode to -1 */ ++ priv->led_polarity_mode = -1; ++ ++ phydev->priv = priv; ++ ++ return 0; ++} ++ ++static int qca808x_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Active adc&vga on 802.3az for the link 1000M and 100M */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, ++ QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); ++ if (ret) ++ return ret; ++ ++ /* Adjust the threshold on 802.3az for the link 1000M */ ++ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, ++ QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, ++ QCA808X_MMD3_AZ_TRAINING_VAL); ++ if (ret) ++ return ret; ++ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { ++ /* Config the fast retrain for the link 2500M */ ++ ret = qca808x_phy_fast_retrain_config(phydev); ++ if (ret) ++ return ret; ++ ++ ret = genphy_read_master_slave(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (!qca808x_is_prefer_master(phydev)) { ++ /* Enable seed and configure lower ramdom seed to make phy ++ * linked as slave mode. ++ */ ++ ret = qca808x_phy_ms_seed_enable(phydev, true); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ /* Configure adc threshold as 100mv for the link 10M */ ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, ++ QCA808X_ADC_THRESHOLD_MASK, ++ QCA808X_ADC_THRESHOLD_100MV); ++} ++ ++static int qca808x_read_status(struct phy_device *phydev) ++{ ++ struct at803x_ss_mask ss_mask = { 0 }; ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); ++ if (ret < 0) ++ return ret; ++ ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, ++ ret & MDIO_AN_10GBT_STAT_LP2_5G); ++ ++ ret = genphy_read_status(phydev); ++ if (ret) ++ return ret; ++ ++ /* qca8081 takes the different bits for speed value from at803x */ ++ ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; ++ ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); ++ ret = at803x_read_specific_status(phydev, ss_mask); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->link) { ++ if (phydev->speed == SPEED_2500) ++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ else ++ phydev->interface = PHY_INTERFACE_MODE_SGMII; ++ } else { ++ /* generate seed as a lower random value to make PHY linked as SLAVE easily, ++ * except for master/slave configuration fault detected or the master mode ++ * preferred. ++ * ++ * the reason for not putting this code into the function link_change_notify is ++ * the corner case where the link partner is also the qca8081 PHY and the seed ++ * value is configured as the same value, the link can't be up and no link change ++ * occurs. ++ */ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { ++ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || ++ qca808x_is_prefer_master(phydev)) { ++ qca808x_phy_ms_seed_enable(phydev, false); ++ } else { ++ qca808x_phy_ms_seed_enable(phydev, true); ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int qca808x_soft_reset(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_soft_reset(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) ++ ret = qca808x_phy_ms_seed_enable(phydev, true); ++ ++ return ret; ++} ++ ++static bool qca808x_cdt_fault_length_valid(int cdt_code) ++{ ++ switch (cdt_code) { ++ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static int qca808x_cable_test_result_trans(int cdt_code) ++{ ++ switch (cdt_code) { ++ case QCA808X_CDT_STATUS_STAT_NORMAL: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OK; ++ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: ++ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; ++ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: ++ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: ++ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: ++ return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; ++ case QCA808X_CDT_STATUS_STAT_FAIL: ++ default: ++ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; ++ } ++} ++ ++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, ++ int result) ++{ ++ int val; ++ u32 cdt_length_reg = 0; ++ ++ switch (pair) { ++ case ETHTOOL_A_CABLE_PAIR_A: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_B: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_C: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; ++ break; ++ case ETHTOOL_A_CABLE_PAIR_D: ++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); ++ if (val < 0) ++ return val; ++ ++ if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) ++ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); ++ else ++ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); ++ ++ return at803x_cdt_fault_length(val); ++} ++ ++static int qca808x_cable_test_start(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* perform CDT with the following configs: ++ * 1. disable hibernation. ++ * 2. force PHY working in MDI mode. ++ * 3. for PHY working in 1000BaseT. ++ * 4. configure the threshold. ++ */ ++ ++ ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); ++ if (ret < 0) ++ return ret; ++ ++ ret = at803x_config_mdix(phydev, ETH_TP_MDI); ++ if (ret < 0) ++ return ret; ++ ++ /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ ++ phydev->duplex = DUPLEX_FULL; ++ phydev->speed = SPEED_1000; ++ ret = genphy_c45_pma_setup_forced(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = genphy_setup_forced(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* configure the thresholds for open, short, pair ok test */ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); ++ ++ return 0; ++} ++ ++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, ++ u16 status) ++{ ++ int length, result; ++ u16 pair_code; ++ ++ switch (pair) { ++ case ETHTOOL_A_CABLE_PAIR_A: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_B: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_C: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); ++ break; ++ case ETHTOOL_A_CABLE_PAIR_D: ++ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ result = qca808x_cable_test_result_trans(pair_code); ++ ethnl_cable_test_result(phydev, pair, result); ++ ++ if (qca808x_cdt_fault_length_valid(pair_code)) { ++ length = qca808x_cdt_fault_length(phydev, pair, result); ++ ethnl_cable_test_fault_length(phydev, pair, length); ++ } ++ ++ return 0; ++} ++ ++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) ++{ ++ int ret, val; ++ ++ *finished = false; ++ ++ val = QCA808X_CDT_ENABLE_TEST | ++ QCA808X_CDT_LENGTH_UNIT; ++ ret = at803x_cdt_start(phydev, val); ++ if (ret) ++ return ret; ++ ++ ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); ++ if (ret) ++ return ret; ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); ++ if (val < 0) ++ return val; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); ++ if (ret) ++ return ret; ++ ++ *finished = true; ++ ++ return 0; ++} ++ ++static int qca808x_get_features(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_c45_pma_read_abilities(phydev); ++ if (ret) ++ return ret; ++ ++ /* The autoneg ability is not existed in bit3 of MMD7.1, ++ * but it is supported by qca808x PHY, so we add it here ++ * manually. ++ */ ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); ++ ++ /* As for the qca8081 1G version chip, the 2500baseT ability is also ++ * existed in the bit0 of MMD1.21, we need to remove it manually if ++ * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. ++ */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); ++ if (ret < 0) ++ return ret; ++ ++ if (QCA808X_PHY_CHIP_TYPE_1G & ret) ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); ++ ++ return 0; ++} ++ ++static int qca808x_config_aneg(struct phy_device *phydev) ++{ ++ int phy_ctrl = 0; ++ int ret; ++ ++ ret = at803x_prepare_config_aneg(phydev); ++ if (ret) ++ return ret; ++ ++ /* The reg MII_BMCR also needs to be configured for force mode, the ++ * genphy_config_aneg is also needed. ++ */ ++ if (phydev->autoneg == AUTONEG_DISABLE) ++ genphy_c45_pma_setup_forced(phydev); ++ ++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) ++ phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; ++ ++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ++ MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); ++ if (ret < 0) ++ return ret; ++ ++ return __genphy_config_aneg(phydev, ret); ++} ++ ++static void qca808x_link_change_notify(struct phy_device *phydev) ++{ ++ /* Assert interface sgmii fifo on link down, deassert it on link up, ++ * the interface device address is always phy address added by 1. ++ */ ++ mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, ++ MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, ++ QCA8081_PHY_FIFO_RSTN, ++ phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); ++} ++ ++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, ++ u16 *offload_trigger) ++{ ++ /* Parsing specific to netdev trigger */ ++ if (test_bit(TRIGGER_NETDEV_TX, &rules)) ++ *offload_trigger |= QCA808X_LED_TX_BLINK; ++ if (test_bit(TRIGGER_NETDEV_RX, &rules)) ++ *offload_trigger |= QCA808X_LED_RX_BLINK; ++ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED10_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED100_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED1000_ON; ++ if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) ++ *offload_trigger |= QCA808X_LED_SPEED2500_ON; ++ if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) ++ *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; ++ if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) ++ *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; ++ ++ if (rules && !*offload_trigger) ++ return -EOPNOTSUPP; ++ ++ /* Enable BLINK_CHECK_BYPASS by default to make the LED ++ * blink even with duplex or speed mode not enabled. ++ */ ++ *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; ++ ++ return 0; ++} ++ ++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN); ++} ++ ++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 offload_trigger = 0; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); ++} ++ ++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 reg, offload_trigger = 0; ++ int ret; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); ++ if (ret) ++ return ret; ++ ++ ret = qca808x_led_hw_control_enable(phydev, index); ++ if (ret) ++ return ret; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_PATTERN_MASK, ++ offload_trigger); ++} ++ ++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ int val; ++ ++ if (index > 2) ++ return false; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); ++ ++ return !(val & QCA808X_LED_FORCE_EN); ++} ++ ++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ u16 reg; ++ int val; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ /* Check if we have hw control enabled */ ++ if (qca808x_led_hw_control_status(phydev, index)) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); ++ if (val & QCA808X_LED_TX_BLINK) ++ set_bit(TRIGGER_NETDEV_TX, rules); ++ if (val & QCA808X_LED_RX_BLINK) ++ set_bit(TRIGGER_NETDEV_RX, rules); ++ if (val & QCA808X_LED_SPEED10_ON) ++ set_bit(TRIGGER_NETDEV_LINK_10, rules); ++ if (val & QCA808X_LED_SPEED100_ON) ++ set_bit(TRIGGER_NETDEV_LINK_100, rules); ++ if (val & QCA808X_LED_SPEED1000_ON) ++ set_bit(TRIGGER_NETDEV_LINK_1000, rules); ++ if (val & QCA808X_LED_SPEED2500_ON) ++ set_bit(TRIGGER_NETDEV_LINK_2500, rules); ++ if (val & QCA808X_LED_HALF_DUPLEX_ON) ++ set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); ++ if (val & QCA808X_LED_FULL_DUPLEX_ON) ++ set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); ++ ++ return 0; ++} ++ ++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) ++{ ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_CTRL(index); ++ ++ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_PATTERN_MASK); ++} ++ ++static int qca808x_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ u16 reg; ++ int ret; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ if (!value) { ++ ret = qca808x_led_hw_control_reset(phydev, index); ++ if (ret) ++ return ret; ++ } ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, ++ QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : ++ QCA808X_LED_FORCE_OFF); ++} ++ ++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, ++ unsigned long *delay_on, ++ unsigned long *delay_off) ++{ ++ int ret; ++ u16 reg; ++ ++ if (index > 2) ++ return -EINVAL; ++ ++ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); ++ ++ /* Set blink to 50% off, 50% on at 4Hz by default */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, ++ QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, ++ QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); ++ if (ret) ++ return ret; ++ ++ /* We use BLINK_1 for normal blinking */ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, ++ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); ++ if (ret) ++ return ret; ++ ++ /* We set blink to 4Hz, aka 250ms */ ++ *delay_on = 250 / 2; ++ *delay_off = 250 / 2; ++ ++ return 0; ++} ++ ++static int qca808x_led_polarity_set(struct phy_device *phydev, int index, ++ unsigned long modes) ++{ ++ struct qca808x_priv *priv = phydev->priv; ++ bool active_low = false; ++ u32 mode; ++ ++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { ++ switch (mode) { ++ case PHY_LED_ACTIVE_LOW: ++ active_low = true; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ /* PHY polarity is global and can't be set per LED. ++ * To detect this, check if last requested polarity mode ++ * match the new one. ++ */ ++ if (priv->led_polarity_mode >= 0 && ++ priv->led_polarity_mode != active_low) { ++ phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); ++ return -EINVAL; ++ } ++ ++ /* Save the last PHY polarity mode */ ++ priv->led_polarity_mode = active_low; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_AN, ++ QCA808X_MMD7_LED_POLARITY_CTRL, ++ QCA808X_LED_ACTIVE_HIGH, ++ active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); ++} ++ ++static struct phy_driver qca808x_driver[] = { ++{ ++ /* Qualcomm QCA8081 */ ++ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), ++ .name = "Qualcomm QCA8081", ++ .flags = PHY_POLL_CABLE_TEST, ++ .probe = qca808x_probe, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++ .set_tunable = at803x_set_tunable, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .get_features = qca808x_get_features, ++ .config_aneg = qca808x_config_aneg, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++ .config_init = qca808x_config_init, ++ .soft_reset = qca808x_soft_reset, ++ .cable_test_start = qca808x_cable_test_start, ++ .cable_test_get_status = qca808x_cable_test_get_status, ++ .link_change_notify = qca808x_link_change_notify, ++ .led_brightness_set = qca808x_led_brightness_set, ++ .led_blink_set = qca808x_led_blink_set, ++ .led_hw_is_supported = qca808x_led_hw_is_supported, ++ .led_hw_control_set = qca808x_led_hw_control_set, ++ .led_hw_control_get = qca808x_led_hw_control_get, ++ .led_polarity_set = qca808x_led_polarity_set, ++}, }; ++ ++module_phy_driver(qca808x_driver); ++ ++static struct mdio_device_id __maybe_unused qca808x_tbl[] = { ++ { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, qca808x_tbl); diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index c6301662f7..80214d1efd 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -5076,6 +5076,8 @@ CONFIG_PWRSEQ_SIMPLE=y # CONFIG_QCA7000 is not set # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set # CONFIG_QCOM_A7PLL is not set # CONFIG_QCOM_BAM_DMUX is not set # CONFIG_QCOM_EMAC is not set diff --git a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c b/target/linux/ipq40xx/files/drivers/net/phy/qcom/qca807x.c similarity index 100% rename from target/linux/ipq40xx/files/drivers/net/phy/qca807x.c rename to target/linux/ipq40xx/files/drivers/net/phy/qcom/qca807x.c diff --git a/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch index dbf87d4dde..80b066c31c 100644 --- a/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch +++ b/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch @@ -23,11 +23,11 @@ Signed-off-by: Robert Marko drivers/net/phy/Makefile | 1 + 2 files changed, 8 insertions(+) ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -366,6 +366,13 @@ config AT803X_PHY - Currently supports the AR8030, AR8031, AR8033, AR8035 and internal - QCA8337(Internal qca8k PHY) model +--- a/drivers/net/phy/qcom/Kconfig ++++ b/drivers/net/phy/qcom/Kconfig +@@ -15,6 +15,13 @@ config QCA83XX_PHY + help + Currently supports the internal QCA8337(Internal qca8k PHY) model +config QCA807X_PHY + tristate "Qualcomm QCA807x PHYs" @@ -36,16 +36,14 @@ Signed-off-by: Robert Marko + Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII + control PHY. + - config QSEMI_PHY - tristate "Quality Semiconductor PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -90,6 +90,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm - obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o - obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o + config QCA808X_PHY + tristate "Qualcomm QCA808x PHYs" + select QCOM_NET_PHYLIB +--- a/drivers/net/phy/qcom/Makefile ++++ b/drivers/net/phy/qcom/Makefile +@@ -2,4 +2,5 @@ + obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o + obj-$(CONFIG_AT803X_PHY) += at803x.o + obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o +obj-$(CONFIG_QCA807X_PHY) += qca807x.o - obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o + obj-$(CONFIG_QCA808X_PHY) += qca808x.o diff --git a/target/linux/ipq806x/config-6.1 b/target/linux/ipq806x/config-6.1 index e31e822380..e6c9b930a2 100644 --- a/target/linux/ipq806x/config-6.1 +++ b/target/linux/ipq806x/config-6.1 @@ -49,7 +49,6 @@ CONFIG_ARM_QCOM_SPM_CPUIDLE=y CONFIG_ARM_THUMB=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_MQ_PCI=y @@ -389,6 +388,7 @@ CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PRINTK_TIME=y CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QCA83XX_PHY=y # CONFIG_QCM_DISPCC_2290 is not set # CONFIG_QCM_GCC_2290 is not set # CONFIG_QCOM_A53PLL is not set diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch index 9c575d694b..7dd12ad55a 100644 --- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch +++ b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -386,6 +386,12 @@ config ROCKCHIP_PHY +@@ -381,6 +381,12 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch index f4e972f658..98f3f46f46 100644 --- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch @@ -63,7 +63,7 @@ Signed-off-by: David S. Miller depends on PTP_1588_CLOCK_OPTIONAL --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o +@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch index a3dcefd3f1..30f06d94d9 100644 --- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch @@ -29,7 +29,7 @@ Signed-off-by: Daniel Golle depends on PTP_1588_CLOCK_OPTIONAL --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell +@@ -78,6 +78,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o From 5a3f6c50ef29c8b11fe6967e65277b8331be0ff0 Mon Sep 17 00:00:00 2001 From: Chad Monroe Date: Tue, 16 Jan 2024 15:44:33 -0800 Subject: [PATCH 07/20] ucode: add libjson-c/host dependency ensure host libjson-c is built prior to ucode Signed-off-by: Chad Monroe --- package/utils/ucode/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/utils/ucode/Makefile b/package/utils/ucode/Makefile index f706ee5d20..ed5ad350b5 100644 --- a/package/utils/ucode/Makefile +++ b/package/utils/ucode/Makefile @@ -19,6 +19,7 @@ PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=ISC PKG_ABI_VERSION:=20230711 +HOST_BUILD_DEPENDS:=libjson-c/host include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/host-build.mk From 45554ffb96b2c5f621061ab72c0b5fcd1cd6369f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 10 Nov 2023 23:16:21 +0800 Subject: [PATCH 08/20] kernel: modules: gpio.mk: renamed from gpio-cascade.mk This can be used to place the gpio module, so rename it. Signed-off-by: Chukun Pan --- package/kernel/linux/modules/{gpio-cascade.mk => gpio.mk} | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename package/kernel/linux/modules/{gpio-cascade.mk => gpio.mk} (90%) diff --git a/package/kernel/linux/modules/gpio-cascade.mk b/package/kernel/linux/modules/gpio.mk similarity index 90% rename from package/kernel/linux/modules/gpio-cascade.mk rename to package/kernel/linux/modules/gpio.mk index 3a559f19ef..62d2688ee0 100644 --- a/package/kernel/linux/modules/gpio-cascade.mk +++ b/package/kernel/linux/modules/gpio.mk @@ -2,10 +2,10 @@ # See /LICENSE for more information. # -MENU_TITLE:=GPIO support +GPIO_MENU:=GPIO support define KernelPackage/gpio-cascade - SUBMENU:=$(MENU_TITLE) + SUBMENU:=$(GPIO_MENU) TITLE:=Generic GPIO cascade KCONFIG:=CONFIG_GPIO_CASCADE DEPENDS:=@GPIO_SUPPORT +kmod-mux-core From 3d24668f99759937daa624944187b36d48710667 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 19 Nov 2023 23:16:26 +0800 Subject: [PATCH 09/20] kernel: modules: move gpio modules to gpio menu Since we have the 'GPIO support' menu, it is strange to look up gpio related modules in 'Other modules' menu. So move these modules and put them in the gpio menu. Signed-off-by: Chukun Pan --- package/kernel/linux/modules/gpio.mk | 118 ++++++++++++++++++++++++++ package/kernel/linux/modules/other.mk | 116 ------------------------- 2 files changed, 118 insertions(+), 116 deletions(-) diff --git a/package/kernel/linux/modules/gpio.mk b/package/kernel/linux/modules/gpio.mk index 62d2688ee0..511cd3af8c 100644 --- a/package/kernel/linux/modules/gpio.mk +++ b/package/kernel/linux/modules/gpio.mk @@ -4,6 +4,42 @@ GPIO_MENU:=GPIO support +define KernelPackage/gpio-amd-fch + SUBMENU:=$(GPIO_MENU) + DEPENDS:=@GPIO_SUPPORT @TARGET_x86 + TITLE:=GPIO support for AMD Fusion Controller Hub (G-series SOCs) + KCONFIG:=CONFIG_GPIO_AMD_FCH + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-amd-fch.ko + AUTOLOAD:=$(call AutoLoad,25,gpio-amd-fch,1) +endef + +define KernelPackage/gpio-amd-fch/description + This option enables driver for GPIO on AMDs Fusion Controller Hub, + as found on G-series SOCs (eg. GX-412TC) +endef + +$(eval $(call KernelPackage,gpio-amd-fch)) + + +define KernelPackage/gpio-beeper + SUBMENU:=$(GPIO_MENU) + TITLE:=GPIO beeper support + DEPENDS:=+kmod-input-core + KCONFIG:= \ + CONFIG_INPUT_MISC=y \ + CONFIG_INPUT_GPIO_BEEPER + FILES:= \ + $(LINUX_DIR)/drivers/input/misc/gpio-beeper.ko + AUTOLOAD:=$(call AutoLoad,50,gpio-beeper) +endef + +define KernelPackage/gpio-beeper/description + This enables playing beeps through an GPIO-connected buzzer +endef + +$(eval $(call KernelPackage,gpio-beeper)) + + define KernelPackage/gpio-cascade SUBMENU:=$(GPIO_MENU) TITLE:=Generic GPIO cascade @@ -18,3 +54,85 @@ define KernelPackage/gpio-cascade/description endef $(eval $(call KernelPackage,gpio-cascade)) + + +define KernelPackage/gpio-f7188x + SUBMENU:=$(GPIO_MENU) + TITLE:=Fintek F718xx/F818xx GPIO Support + DEPENDS:=@GPIO_SUPPORT @TARGET_x86 + KCONFIG:=CONFIG_GPIO_F7188X + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-f7188x.ko + AUTOLOAD:=$(call AutoProbe,gpio-f7188x) +endef + +define KernelPackage/gpio-f7188x/description + Kernel module for the GPIOs found on many Fintek Super-IO chips. +endef + +$(eval $(call KernelPackage,gpio-f7188x)) + + +define KernelPackage/gpio-it87 + SUBMENU:=$(GPIO_MENU) + DEPENDS:=@GPIO_SUPPORT @TARGET_x86 + TITLE:=GPIO support for IT87xx Super I/O chips + KCONFIG:=CONFIG_GPIO_IT87 + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-it87.ko + AUTOLOAD:=$(call AutoLoad,25,gpio-it87,1) +endef + +define KernelPackage/gpio-it87/description + This driver is tested with ITE IT8728 and IT8732 Super I/O chips, and + supports the IT8761E, IT8613, IT8620E, and IT8628E Super I/O chips as + well. +endef + +$(eval $(call KernelPackage,gpio-it87)) + + +define KernelPackage/gpio-nxp-74hc164 + SUBMENU:=$(GPIO_MENU) + TITLE:=NXP 74HC164 GPIO expander support + KCONFIG:=CONFIG_GPIO_74X164 + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-74x164.ko + AUTOLOAD:=$(call AutoProbe,gpio-74x164) +endef + +define KernelPackage/gpio-nxp-74hc164/description + Kernel module for NXP 74HC164 GPIO expander +endef + +$(eval $(call KernelPackage,gpio-nxp-74hc164)) + + +define KernelPackage/gpio-pca953x + SUBMENU:=$(GPIO_MENU) + DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c + TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports + KCONFIG:=CONFIG_GPIO_PCA953X + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko + AUTOLOAD:=$(call AutoLoad,55,gpio-pca953x) +endef + +define KernelPackage/gpio-pca953x/description + Kernel module for MAX731{0,2,3,5}, PCA6107, PCA953{4-9}, PCA955{4-7}, + PCA957{4,5} and TCA64{08,16} I2C GPIO expanders +endef + +$(eval $(call KernelPackage,gpio-pca953x)) + + +define KernelPackage/gpio-pcf857x + SUBMENU:=$(GPIO_MENU) + DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core + TITLE:=PCX857x, PCA967x and MAX732X I2C GPIO expanders + KCONFIG:=CONFIG_GPIO_PCF857X + FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pcf857x.ko + AUTOLOAD:=$(call AutoLoad,55,gpio-pcf857x) +endef + +define KernelPackage/gpio-pcf857x/description + Kernel module for PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders +endef + +$(eval $(call KernelPackage,gpio-pcf857x)) diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk index face579472..4a061974c3 100644 --- a/package/kernel/linux/modules/other.mk +++ b/package/kernel/linux/modules/other.mk @@ -228,22 +228,6 @@ endef $(eval $(call KernelPackage,google-firmware)) -define KernelPackage/gpio-f7188x - SUBMENU:=$(OTHER_MENU) - TITLE:=Fintek F718xx/F818xx GPIO Support - DEPENDS:=@GPIO_SUPPORT @TARGET_x86 - KCONFIG:=CONFIG_GPIO_F7188X - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-f7188x.ko - AUTOLOAD:=$(call AutoProbe,gpio-f7188x) -endef - -define KernelPackage/gpio-f7188x/description - Kernel module for the GPIOs found on many Fintek Super-IO chips. -endef - -$(eval $(call KernelPackage,gpio-f7188x)) - - define KernelPackage/lkdtm SUBMENU:=$(OTHER_MENU) TITLE:=Linux Kernel Dump Test Tool Module @@ -312,87 +296,6 @@ endef $(eval $(call KernelPackage,pinctrl-mcp23s08-spi)) -define KernelPackage/gpio-nxp-74hc164 - SUBMENU:=$(OTHER_MENU) - TITLE:=NXP 74HC164 GPIO expander support - KCONFIG:=CONFIG_GPIO_74X164 - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-74x164.ko - AUTOLOAD:=$(call AutoProbe,gpio-74x164) -endef - -define KernelPackage/gpio-nxp-74hc164/description - Kernel module for NXP 74HC164 GPIO expander -endef - -$(eval $(call KernelPackage,gpio-nxp-74hc164)) - -define KernelPackage/gpio-pca953x - SUBMENU:=$(OTHER_MENU) - DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c - TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports - KCONFIG:=CONFIG_GPIO_PCA953X - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko - AUTOLOAD:=$(call AutoLoad,55,gpio-pca953x) -endef - -define KernelPackage/gpio-pca953x/description - Kernel module for MAX731{0,2,3,5}, PCA6107, PCA953{4-9}, PCA955{4-7}, - PCA957{4,5} and TCA64{08,16} I2C GPIO expanders -endef - -$(eval $(call KernelPackage,gpio-pca953x)) - -define KernelPackage/gpio-pcf857x - SUBMENU:=$(OTHER_MENU) - DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core - TITLE:=PCX857x, PCA967x and MAX732X I2C GPIO expanders - KCONFIG:=CONFIG_GPIO_PCF857X - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pcf857x.ko - AUTOLOAD:=$(call AutoLoad,55,gpio-pcf857x) -endef - -define KernelPackage/gpio-pcf857x/description - Kernel module for PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders -endef - -$(eval $(call KernelPackage,gpio-pcf857x)) - - -define KernelPackage/gpio-it87 - SUBMENU:=$(OTHER_MENU) - DEPENDS:=@GPIO_SUPPORT @TARGET_x86 - TITLE:=GPIO support for IT87xx Super I/O chips - KCONFIG:=CONFIG_GPIO_IT87 - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-it87.ko - AUTOLOAD:=$(call AutoLoad,25,gpio-it87,1) -endef - -define KernelPackage/gpio-it87/description - This driver is tested with ITE IT8728 and IT8732 Super I/O chips, and - supports the IT8761E, IT8613, IT8620E, and IT8628E Super I/O chips as - well. -endef - -$(eval $(call KernelPackage,gpio-it87)) - - -define KernelPackage/gpio-amd-fch - SUBMENU:=$(OTHER_MENU) - DEPENDS:=@GPIO_SUPPORT @TARGET_x86 - TITLE:=GPIO support for AMD Fusion Controller Hub (G-series SOCs) - KCONFIG:=CONFIG_GPIO_AMD_FCH - FILES:=$(LINUX_DIR)/drivers/gpio/gpio-amd-fch.ko - AUTOLOAD:=$(call AutoLoad,25,gpio-amd-fch,1) -endef - -define KernelPackage/gpio-amd-fch/description - This option enables driver for GPIO on AMDs Fusion Controller Hub, - as found on G-series SOCs (eg. GX-412TC) -endef - -$(eval $(call KernelPackage,gpio-amd-fch)) - - define KernelPackage/ppdev SUBMENU:=$(OTHER_MENU) TITLE:=Parallel port support @@ -1207,25 +1110,6 @@ endef $(eval $(call KernelPackage,thermal)) -define KernelPackage/gpio-beeper - SUBMENU:=$(OTHER_MENU) - TITLE:=GPIO beeper support - DEPENDS:=+kmod-input-core - KCONFIG:= \ - CONFIG_INPUT_MISC=y \ - CONFIG_INPUT_GPIO_BEEPER - FILES:= \ - $(LINUX_DIR)/drivers/input/misc/gpio-beeper.ko - AUTOLOAD:=$(call AutoLoad,50,gpio-beeper) -endef - -define KernelPackage/gpio-beeper/description - This enables playing beeps through an GPIO-connected buzzer -endef - -$(eval $(call KernelPackage,gpio-beeper)) - - define KernelPackage/echo SUBMENU:=$(OTHER_MENU) TITLE:=Line Echo Canceller From dbe2a0c091a51c82067cd2053f7ce5ad45694ab8 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 20 Nov 2023 23:16:16 +0800 Subject: [PATCH 10/20] kernel: move gpio packages to gpio menu Move gpio packages to the 'GPIO support' menu. Signed-off-by: Chukun Pan --- package/kernel/gpio-button-hotplug/Makefile | 2 +- package/kernel/gpio-nct5104d/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/package/kernel/gpio-button-hotplug/Makefile b/package/kernel/gpio-button-hotplug/Makefile index 7ca6195a03..04cbb69ada 100644 --- a/package/kernel/gpio-button-hotplug/Makefile +++ b/package/kernel/gpio-button-hotplug/Makefile @@ -15,7 +15,7 @@ PKG_LICENSE:=GPL-2.0 include $(INCLUDE_DIR)/package.mk define KernelPackage/gpio-button-hotplug - SUBMENU:=Other modules + SUBMENU:=GPIO support TITLE:=Simple GPIO Button Hotplug driver FILES:=$(PKG_BUILD_DIR)/gpio-button-hotplug.ko AUTOLOAD:=$(call AutoLoad,30,gpio-button-hotplug,1) diff --git a/package/kernel/gpio-nct5104d/Makefile b/package/kernel/gpio-nct5104d/Makefile index 72b1d58e62..bb6010d2d0 100644 --- a/package/kernel/gpio-nct5104d/Makefile +++ b/package/kernel/gpio-nct5104d/Makefile @@ -17,7 +17,7 @@ PKG_LICENSE:=GPL-2.0 include $(INCLUDE_DIR)/package.mk define KernelPackage/gpio-nct5104d - SUBMENU:=Other modules + SUBMENU:=GPIO support TITLE:= GPIO nct5104d support DEPENDS:= @GPIO_SUPPORT @TARGET_x86 FILES:=$(PKG_BUILD_DIR)/gpio-nct5104d.ko From 3c7ce20d5cd08b54fffd73a38900534a22d0aeca Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 11/20] ath79: add back board-2.bin to COMFAST devices The ath10k driver will load both pre-calibration data and board-2.bin if board-2.bin exists. So it's not necessary to remove it. And this change won't increase jffs2 image size. Signed-off-by: Shiji Yang --- .../generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 1acbf35947..a5d244d85b 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -185,7 +185,6 @@ case "$FIRMWARE" in ath10k_patch_mac $(mtd_get_mac_binary art 0x6) ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin ;; comfast,cf-e375ac|\ comfast,cf-e560ac|\ @@ -195,7 +194,6 @@ case "$FIRMWARE" in ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2) ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin ;; dlink,dir-842-c1|\ dlink,dir-842-c2|\ From 650d37a809bdb84a517ff0580bb2c4168e501d0d Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 12/20] ath79: convert ath10k pre-calibration data to NVMEM (built-in MAC) This patch converts ath10k pre-calibration data to NVMEM format for wave 2 devices with built-in MAC address. The "pre-calibration" NVMEM cell size is 0x2f20. Signed-off-by: Shiji Yang --- target/linux/ath79/dts/qca9531_asus_rp-ac51.dts | 11 +++++++++++ .../linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts | 11 +++++++++++ target/linux/ath79/dts/qca9563_yuncore_xd3200.dts | 7 +++++++ target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi | 6 ++++++ .../etc/hotplug.d/firmware/11-ath10k-caldata | 12 ------------ 5 files changed, 35 insertions(+), 12 deletions(-) diff --git a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts index b2777f6cc6..cdc365beb7 100644 --- a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts +++ b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts @@ -65,6 +65,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; }; &spi { @@ -109,6 +116,10 @@ macaddr_art_1002: macaddr@1002 { reg = <0x1002 0x6>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts index 2085644f76..6dfc885bc0 100644 --- a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts +++ b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts @@ -118,6 +118,10 @@ macaddr_art_0: macaddr@0 { reg = <0x0 0x6>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; @@ -183,4 +187,11 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; }; diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts index 5c87752585..d496f48263 100644 --- a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts +++ b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts @@ -30,3 +30,10 @@ }; }; }; + +&pcie { + wifi@0,0 { + /delete-property/ nvmem-cells; + /delete-property/ nvmem-cell-names; + }; +}; diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi index dff9428295..f6b68989be 100644 --- a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi +++ b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi @@ -57,6 +57,8 @@ wifi@0,0 { compatible = "pci168c,0056"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; }; }; @@ -103,6 +105,10 @@ macaddr_art_0: macaddr@0 { reg = <0x0 0x6>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; }; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index a5d244d85b..559bcd55a0 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -173,13 +173,6 @@ case "$FIRMWARE" in ;; "ath10k/pre-cal-pci-0000:00:00.0.bin") case $board in - asus,rp-ac51|\ - yuncore,a782|\ - yuncore,xd4200) - caldata_extract "art" 0x5000 0x2f20 - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; comfast,cf-e313ac) caldata_extract "art" 0x5000 0x2f20 ath10k_patch_mac $(mtd_get_mac_binary art 0x6) @@ -237,11 +230,6 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin ;; - xiaomi,aiot-ac2350) - caldata_extract "art" 0x5000 0x2f20 - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9984/hw1.0/board.bin - ;; tplink,deco-m4r-v1) caldata_extract "art" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x8) -1) From 348e0ee157637a7b6da61d56638f9e843645d673 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 13/20] ath79: convert ath10k pre-calibration data to NVMEM (binary MAC) This patch converts ath10k pre-calibration data to NVMEM format for wave 2 devices with mtd binary MAC address. The "pre-calibration" NVMEM cell size is 0x2f20. The MAC addresses are assigned via dts. Signed-off-by: Shiji Yang --- .../ath79/dts/qca9531_comfast_cf-e313ac.dts | 10 +++++ .../ath79/dts/qca9531_comfast_cf-e560ac.dts | 11 +++++ .../ath79/dts/qca9531_comfast_cf-ew72.dts | 11 +++++ .../dts/qca9531_comfast_cf-wr752ac-v1.dts | 11 +++++ .../dts/qca9561_tplink_archer-c58-v1.dts | 19 +++++++++ .../dts/qca9561_tplink_archer-c59-v1.dts | 19 +++++++++ .../dts/qca9561_tplink_archer-c59-v2.dts | 19 +++++++++ .../dts/qca9561_tplink_archer-c60-v1.dts | 19 +++++++++ .../dts/qca9561_tplink_archer-c60-v2.dts | 19 +++++++++ .../dts/qca9561_tplink_archer-c60-v3.dts | 19 +++++++++ .../ath79/dts/qca9563_comfast_cf-e375ac.dts | 11 +++++ .../dts/qca9563_tplink_archer-c6-v2-us.dts | 25 ++++++++++- .../ath79/dts/qca9563_tplink_archer-c6-v2.dts | 25 ++++++++++- .../ath79/dts/qca9563_tplink_cpe710-v1.dts | 17 ++++++++ .../ath79/dts/qca9563_tplink_deco-m4r-v1.dts | 23 ++++++++++- .../ath79/dts/qca9563_tplink_tl-wa1201-v2.dts | 23 ++++++++++- .../dts/qca9563_tplink_tl-wpa8630p-v2-int.dts | 25 ++++++++++- .../qca9563_tplink_tl-wpa8630p-v2.0-eu.dts | 25 ++++++++++- .../qca9563_tplink_tl-wpa8630p-v2.1-eu.dts | 25 ++++++++++- .../etc/hotplug.d/firmware/11-ath10k-caldata | 41 ------------------- .../etc/hotplug.d/firmware/11-ath10k-caldata | 25 ----------- 21 files changed, 342 insertions(+), 80 deletions(-) delete mode 100644 target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts index d078a9dcce..40aa19a66f 100644 --- a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts +++ b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts @@ -103,9 +103,17 @@ reg = <0x0 0x6>; }; + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + macaddr_art_1002: macaddr@1002 { reg = <0x1002 0x6>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; @@ -155,5 +163,7 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_art_6>; + nvmem-cell-names = "pre-calibration", "mac-address"; }; }; diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts index a316c48c5b..b68ef442df 100644 --- a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts +++ b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts @@ -114,6 +114,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; @@ -140,6 +144,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &usb_phy { diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts index f725ab1faa..88a3eccb2b 100644 --- a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts +++ b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts @@ -62,6 +62,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &spi { @@ -98,6 +105,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts index ba33ee9a92..6fcda9fbe3 100644 --- a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts +++ b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts @@ -62,6 +62,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &spi { @@ -98,6 +105,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts index a09e1fae6f..95af751784 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts @@ -11,6 +11,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -64,6 +73,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts index 720a2b01a9..397e81d17b 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts @@ -28,6 +28,15 @@ status = "okay"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -81,6 +90,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts index be6e6ade1c..8a93d2b3b1 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts @@ -28,6 +28,15 @@ status = "okay"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -87,6 +96,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts index eff85d6a58..9e437b6f00 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts @@ -23,6 +23,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -76,6 +85,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts index 18053d691c..e71fc9eb7a 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts @@ -23,6 +23,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -82,6 +91,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts index 068f957759..d84ba25db4 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts @@ -18,6 +18,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -77,6 +86,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts index 2f0a0992a9..15b8b81958 100644 --- a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts +++ b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts @@ -59,6 +59,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &spi { @@ -95,6 +102,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts index 6857054f1c..61c52943de 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts @@ -76,6 +76,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -106,7 +115,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -133,19 +144,29 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts index e7d19c9fbd..4a69d29b31 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts @@ -76,6 +76,15 @@ }; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -106,7 +115,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -127,19 +138,29 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts index 491ffac132..5439adaacb 100644 --- a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts +++ b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts @@ -45,6 +45,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &spi { @@ -109,6 +116,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts index 63f42eba76..989a21b1f1 100644 --- a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts +++ b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts @@ -53,6 +53,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_config_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; &mdio0 { @@ -113,7 +120,9 @@ #size-cells = <1>; macaddr_config_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -122,6 +131,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; @@ -133,7 +152,7 @@ phy-mode = "sgmii"; phy-handle = <&phy0>; - nvmem-cells = <&macaddr_config_8>; + nvmem-cells = <&macaddr_config_8 0>; nvmem-cell-names = "mac-address"; }; @@ -141,6 +160,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_config_8>; + nvmem-cells = <&macaddr_config_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts index cf13fcd6b7..0629a63955 100644 --- a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts @@ -83,6 +83,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; }; ð0 { @@ -91,7 +98,7 @@ phy-mode = "sgmii"; phy-handle = <&phy4>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; @@ -100,7 +107,7 @@ mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; @@ -134,7 +141,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -155,6 +164,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts index 8786e30965..1e62094c12 100644 --- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts +++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts @@ -53,7 +53,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -62,17 +64,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts index 3c688d67d6..5f834542f2 100644 --- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts +++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts @@ -47,7 +47,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -62,17 +64,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts index 786cd3cc03..7be23423df 100644 --- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts +++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts @@ -49,7 +49,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -58,17 +60,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; +}; + +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "pre-calibration", "mac-address"; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 559bcd55a0..6145487393 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -173,21 +173,6 @@ case "$FIRMWARE" in ;; "ath10k/pre-cal-pci-0000:00:00.0.bin") case $board in - comfast,cf-e313ac) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(mtd_get_mac_binary art 0x6) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - comfast,cf-e375ac|\ - comfast,cf-e560ac|\ - comfast,cf-ew72|\ - comfast,cf-wr752ac-v1) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; dlink,dir-842-c1|\ dlink,dir-842-c2|\ dlink,dir-842-c3) @@ -210,32 +195,6 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin ;; - tplink,archer-c58-v1|\ - tplink,archer-c59-v1|\ - tplink,archer-c59-v2|\ - tplink,archer-c60-v1|\ - tplink,archer-c60-v2|\ - tplink,archer-c60-v3|\ - tplink,archer-c6-v2|\ - tplink,archer-c6-v2-us|\ - tplink,tl-wa1201-v2) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - tplink,cpe710-v1) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(mtd_get_mac_binary info 0x8) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - tplink,deco-m4r-v1) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x8) -1) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; tplink,deco-s4-v2) caldata_extract "art" 0x5000 0x2f20 base_mac=$(mtd_get_mac_encrypted_deco $(find_mtd_part config)) diff --git a/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata deleted file mode 100644 index 8e3e142ec9..0000000000 --- a/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -[ -e /lib/firmware/$FIRMWARE ] && exit 0 - -. /lib/functions/caldata.sh - -board=$(board_name) - -case "$FIRMWARE" in -"ath10k/pre-cal-pci-0000:00:00.0.bin") - case $board in - tplink,tl-wpa8630p-v2-int|\ - tplink,tl-wpa8630p-v2.0-eu|\ - tplink,tl-wpa8630p-v2.1-eu) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - esac - ;; -*) - exit 1 - ;; -esac From 7e71eef5edbbe3670621cfdacb3731e1bd9a8ec0 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 14/20] ath79: convert ath10k pre-calibration data to NVMEM (ASCII MAC) This patch converts ath10k pre-calibration data to NVMEM format for wave 2 devices with mtd ASCII MAC address. The "pre-calibration" NVMEM cell size is 0x2f20. All unportable MAC address settings have been moved to '10_fix_wifi_mac' scripts. Signed-off-by: Shiji Yang --- .../linux/ath79/dts/qca9561_nec_wf1200cr.dts | 12 +++++++++++ .../linux/ath79/dts/qca9563_nec_wg1200cr.dts | 12 +++++++++++ .../linux/ath79/dts/qca9563_phicomm_k2t.dts | 17 +++++++++++++++ .../ath79/dts/qca9563_tplink_deco-s4-v2.dts | 17 +++++++++++++++ .../etc/hotplug.d/firmware/11-ath10k-caldata | 21 ------------------- .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 13 ++++++++++++ 6 files changed, 71 insertions(+), 21 deletions(-) diff --git a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts index 90aac30d7f..8f67299c48 100644 --- a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts +++ b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts @@ -105,6 +105,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; @@ -156,6 +166,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts index 26c1932154..22ba567694 100644 --- a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts +++ b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts @@ -120,6 +120,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; @@ -157,6 +167,8 @@ wifi@0,0 { compatible = "pci168c,0056"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts index 9dbb291295..5befbb1608 100644 --- a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts +++ b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts @@ -48,6 +48,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; }; &spi { @@ -91,6 +98,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts index e4bb88807e..9c731ad996 100644 --- a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts @@ -53,6 +53,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; }; &mdio0 { @@ -106,6 +113,16 @@ label = "art"; reg = <0x1f0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; }; partition@200000 { diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 6145487393..c5256a23bb 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -3,7 +3,6 @@ [ -e /lib/firmware/$FIRMWARE ] && exit 0 . /lib/functions/caldata.sh -. /lib/functions/k2t.sh board=$(board_name) @@ -182,26 +181,6 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin ;; - nec,wf1200cr|\ - nec,wg1200cr) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - phicomm,k2t) - caldata_extract "art" 0x5000 0x2f20 - ath10k_patch_mac $(k2t_get_mac "5g_mac") - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; - tplink,deco-s4-v2) - caldata_extract "art" 0x5000 0x2f20 - base_mac=$(mtd_get_mac_encrypted_deco $(find_mtd_part config)) - ath10k_patch_mac $(macaddr_add $base_mac 2) - ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ - /lib/firmware/ath10k/QCA9888/hw2.0/board.bin - ;; esac ;; *) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index 42b69d2ca0..d3392aa61e 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -59,13 +59,26 @@ case "$board" in [ "$PHYNBR" -eq 1 ] && \ macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress ;; + nec,wf1200cr|\ + nec,wg1200cr) + [ "$PHYNBR" -eq 0 ] && \ + mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress + ;; phicomm,k2t) + [ "$PHYNBR" -eq 0 ] && \ + k2t_get_mac "5g_mac" > /sys${DEVPATH}/macaddress # The K2T factory firmware does use LAN mac address as the 2.4G wifi mac address [ "$PHYNBR" -eq 1 ] && \ k2t_get_mac "lan_mac" > /sys${DEVPATH}/macaddress ;; siemens,ws-ap3610) mtd_get_mac_ascii cfg1 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress + ;; + tplink,deco-s4-v2) + base_mac=$(mtd_get_mac_encrypted_deco $(find_mtd_part config)) + [ "$PHYNBR" -eq 0 ] && \ + macaddr_add $base_mac 2 > /sys${DEVPATH}/macaddress + ;; trendnet,tew-823dru) # set the 2.4G interface mac address to LAN MAC From d07cec6b2bdcf6389c06a2599a5c924ee490136f Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 15/20] ath79: convert ath10k calibration data to NVMEM (built-in MAC) This patch converts ath10k calibration data to NVMEM format for wave 1 devices with built-in MAC address. The "calibration" NVMEM cell size is 0x844. Signed-off-by: Shiji Yang --- target/linux/ath79/dts/ar9342_ubnt_wa.dtsi | 11 +++++ .../ath79/dts/ar9344_devolo_dlan_wifi.dtsi | 6 +++ .../ath79/dts/qca9531_joyit_jt-or750i.dts | 11 +++++ .../ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts | 4 ++ .../ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts | 4 ++ .../linux/ath79/dts/qca9531_qxwlan_e600g.dtsi | 11 +++++ .../linux/ath79/dts/qca9531_yuncore_a770.dts | 11 +++++ .../ath79/dts/qca9556_avm_fritz-repeater.dtsi | 10 +++++ .../ath79/dts/qca9556_avm_fritz1750e.dts | 7 ++++ .../linux/ath79/dts/qca9556_avm_fritzdvbc.dts | 7 ++++ .../dts/qca9558_comfast_cf-wr650ac-v1.dts | 13 ++++++ .../dts/qca9558_comfast_cf-wr650ac-v2.dts | 15 +++++++ target/linux/ath79/dts/qca9558_sophos_ap.dtsi | 17 ++++++++ .../linux/ath79/dts/qca9558_sophos_ap15.dts | 17 ++++++++ target/linux/ath79/dts/qca955x_ubnt_xc.dtsi | 11 +++++ .../linux/ath79/dts/qca9563_asus_pl-ac56.dts | 11 +++++ .../linux/ath79/dts/qca9563_asus_rp-ac66.dts | 11 +++++ .../ath79/dts/qca9563_qxwlan_e1700ac.dtsi | 17 ++++++++ .../linux/ath79/dts/qca9563_ubnt_unifiac.dtsi | 11 +++++ .../ath79/dts/qca9563_yuncore_xd3200.dts | 4 +- .../ath79/dts/qca9563_yuncore_xd4200.dtsi | 4 ++ .../etc/hotplug.d/firmware/11-ath10k-caldata | 41 ------------------- 22 files changed, 211 insertions(+), 43 deletions(-) diff --git a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi index d85a07a8dc..779b3b681f 100644 --- a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi +++ b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi @@ -27,6 +27,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -79,6 +86,10 @@ macaddr_art_0: macaddr@0 { reg = <0x0 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi index df157f582c..fc8ac9ce8a 100644 --- a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi +++ b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi @@ -127,6 +127,10 @@ reg = <0x1002 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -161,6 +165,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts index 3b01fa9e42..f599f5b77c 100644 --- a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts +++ b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts @@ -107,6 +107,10 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -129,6 +133,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &wmac { diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts index 9b4c0a514d..d6e23bef12 100644 --- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts +++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts @@ -23,6 +23,10 @@ }; }; +&pcie0 { + /delete-node/ wifi@0,0; +}; + &usb_phy { status = "okay"; }; diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts index 7822ec664a..ff6bdd4815 100644 --- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts +++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts @@ -23,6 +23,10 @@ }; }; +&pcie0 { + /delete-node/ wifi@0,0; +}; + &usb_phy { status = "okay"; }; diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi index 04becd63c1..383b2e67c5 100644 --- a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi +++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi @@ -48,6 +48,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -90,6 +97,10 @@ reg = <0x400 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9531_yuncore_a770.dts b/target/linux/ath79/dts/qca9531_yuncore_a770.dts index fa1f7dc5fc..0385d73a7a 100644 --- a/target/linux/ath79/dts/qca9531_yuncore_a770.dts +++ b/target/linux/ath79/dts/qca9531_yuncore_a770.dts @@ -101,6 +101,10 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -123,6 +127,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &wmac { diff --git a/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi index d0c796fadb..4d2f3bb814 100644 --- a/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi +++ b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi @@ -34,6 +34,16 @@ label = "urlader"; reg = <0x0 0x20000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_urlader_198a: calibration@198a { + reg = <0x198a 0x844>; + }; + }; }; partition@20000 { diff --git a/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts index bdb983cd7c..05b76ecadb 100644 --- a/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts +++ b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts @@ -89,6 +89,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_urlader_198a>; + nvmem-cell-names = "calibration"; + }; }; &phy0 { diff --git a/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts b/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts index bf1c026d17..355f0850c4 100644 --- a/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts +++ b/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts @@ -92,6 +92,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_urlader_198a>; + nvmem-cell-names = "calibration"; + }; }; &gpio { diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts index e0471c5348..2e6f86b0b2 100644 --- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts +++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts @@ -7,6 +7,15 @@ model = "Comfast CF-WR650AC v1"; }; +&pcie0 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; +}; + &spi { status = "okay"; @@ -47,6 +56,10 @@ macaddr_art_18: macaddr@18 { reg = <0x18 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts index 9bbbf2a9b4..a4aa4118fa 100644 --- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts +++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts @@ -7,6 +7,17 @@ model = "Comfast CF-WR650AC v2"; }; +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; +}; + &spi { status = "okay"; @@ -47,6 +58,10 @@ macaddr_art_18: macaddr@18 { reg = <0x18 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi index 0cf5eb6e66..70d9e9d148 100644 --- a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi +++ b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi @@ -71,6 +71,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -101,6 +108,16 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; config: partition@60000 { diff --git a/target/linux/ath79/dts/qca9558_sophos_ap15.dts b/target/linux/ath79/dts/qca9558_sophos_ap15.dts index 490d3ae227..69a0af972e 100644 --- a/target/linux/ath79/dts/qca9558_sophos_ap15.dts +++ b/target/linux/ath79/dts/qca9558_sophos_ap15.dts @@ -39,6 +39,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -69,6 +76,16 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; config: partition@60000 { diff --git a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi index 519f831bea..7c1870d714 100644 --- a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi +++ b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi @@ -7,6 +7,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -59,6 +66,10 @@ macaddr_art_0: macaddr@0 { reg = <0x0 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts index a31f188142..4510872e27 100644 --- a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts +++ b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts @@ -59,6 +59,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -99,6 +106,10 @@ macaddr_art_1002: macaddr@1002 { reg = <0x1002 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts index c4b9f34713..71c95ad332 100644 --- a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts +++ b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts @@ -81,6 +81,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -121,6 +128,10 @@ macaddr_art_1002: macaddr@1002 { reg = <0x1002 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi index a4f7be3e1c..0861821f44 100644 --- a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi +++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi @@ -51,6 +51,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -98,6 +105,16 @@ label = "art"; reg = <0x060000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi index 60d6fbc895..48d8d9c83e 100644 --- a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi +++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi @@ -41,6 +41,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -99,6 +106,10 @@ macaddr_art_0: macaddr@0 { reg = <0x0 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts index d496f48263..fa82a6914b 100644 --- a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts +++ b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts @@ -33,7 +33,7 @@ &pcie { wifi@0,0 { - /delete-property/ nvmem-cells; - /delete-property/ nvmem-cell-names; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi index f6b68989be..2cc227a2da 100644 --- a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi +++ b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi @@ -106,6 +106,10 @@ reg = <0x0 0x6>; }; + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + precal_art_5000: pre-calibration@5000 { reg = <0x5000 0x2f20>; }; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index c5256a23bb..cc7458ae59 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -19,47 +19,6 @@ case "$FIRMWARE" in caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2) ;; - asus,pl-ac56|\ - asus,rp-ac66|\ - comfast,cf-wr650ac-v1|\ - comfast,cf-wr650ac-v2|\ - devolo,dlan-pro-1200plus-ac|\ - devolo,magic-2-wifi|\ - joyit,jt-or750i|\ - qxwlan,e1700ac-v2-8m|\ - qxwlan,e1700ac-v2-16m|\ - qxwlan,e600gac-v2-8m|\ - qxwlan,e600gac-v2-16m|\ - sophos,ap15|\ - sophos,ap55|\ - sophos,ap55c|\ - sophos,ap100|\ - sophos,ap100c|\ - ubnt,bullet-ac|\ - ubnt,uk-ultra|\ - ubnt,unifiac-lite|\ - ubnt,unifiac-lr|\ - ubnt,unifiac-mesh|\ - ubnt,unifiac-mesh-pro|\ - ubnt,lap-120|\ - ubnt,litebeam-ac-gen2|\ - ubnt,nanobeam-ac|\ - ubnt,nanobeam-ac-gen2|\ - ubnt,nanobeam-ac-xc|\ - ubnt,nanostation-ac|\ - ubnt,nanostation-ac-loco|\ - ubnt,powerbeam-5ac-500|\ - ubnt,powerbeam-5ac-gen2|\ - ubnt,rocket-5ac-lite|\ - ubnt,unifiac-pro|\ - yuncore,a770|\ - yuncore,xd3200) - caldata_extract "art" 0x5000 0x844 - ;; - avm,fritz1750e|\ - avm,fritzdvbc) - caldata_extract "urlader" 0x198a 0x844 - ;; devolo,dvl1200e|\ devolo,dvl1200i|\ devolo,dvl1750c|\ From 2f1c62e5af071c05631209867acefdc1f112ae26 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 16/20] ath79: convert ath10k calibration data to NVMEM (binary MAC) This patch converts ath10k calibration data to NVMEM format for wave 1 devices with mtd binary MAC address. The "calibration" NVMEM cell size is 0x844. The MAC addresses are assigned via dts. Signed-off-by: Shiji Yang --- .../ath79/dts/qca9531_glinet_gl-ar750.dts | 6 ++ .../ath79/dts/qca9531_glinet_gl-x750.dts | 11 +++ .../dts/qca9531_tplink_archer-d50-v1.dts | 12 +++ .../dts/qca9531_tplink_tl-wr902ac-v1.dts | 12 +++ .../dts/qca9557_araknis_an-500-ap-i-ac.dts | 11 +++ .../dts/qca9557_engenius_enstationac-v1.dts | 11 +++ .../dts/qca9558_allnet_all-wap02860ac.dts | 11 +++ .../dts/qca9558_araknis_an-700-ap-i-ac.dts | 33 +++++--- .../dts/qca9558_comfast_cf-e380ac-v2.dts | 11 +++ .../ath79/dts/qca9558_devolo_dvl1xxx.dtsi | 11 +++ .../ath79/dts/qca9558_domywifi_dw33d.dts | 10 +++ .../linux/ath79/dts/qca9558_ocedo_koala.dts | 15 ++++ .../linux/ath79/dts/qca9558_ocedo_ursus.dts | 15 ++++ .../linux/ath79/dts/qca9558_openmesh_a60.dtsi | 11 +++ .../linux/ath79/dts/qca9558_openmesh_mr.dtsi | 11 +++ .../ath79/dts/qca9558_openmesh_mr900-v1.dts | 2 + .../ath79/dts/qca9558_openmesh_mr900-v2.dts | 2 + .../ath79/dts/qca9558_openmesh_om5p-ac-v1.dts | 11 +++ .../ath79/dts/qca9558_openmesh_om5p-ac-v2.dts | 11 +++ .../ath79/dts/qca9558_tplink_archer-c5-v1.dts | 19 +++++ .../ath79/dts/qca9558_tplink_archer-d7-v1.dts | 19 +++++ .../dts/qca9558_tplink_archer-d7b-v1.dts | 19 +++++ .../ath79/dts/qca9558_tplink_re350k-v1.dts | 23 +++++- .../linux/ath79/dts/qca9558_tplink_rex5x.dtsi | 17 ++++ .../dts/qca9558_tplink_tl-wdr7500-v3.dts | 19 +++++ .../ath79/dts/qca9558_watchguard_ap300.dts | 11 +++ .../dts/qca9561_tplink_archer-c25-v1.dts | 17 ++++ .../ath79/dts/qca9563_glinet_gl-ar750s.dtsi | 15 +++- .../ath79/dts/qca9563_tplink_archer-a7-v5.dts | 25 +++++- .../ath79/dts/qca9563_tplink_archer-c2-v3.dts | 23 +++++- .../ath79/dts/qca9563_tplink_archer-c7-v4.dts | 23 +++++- .../ath79/dts/qca9563_tplink_archer-c7-v5.dts | 27 +++++- .../ath79/dts/qca9563_tplink_re450-v2.dts | 25 +++++- .../ath79/dts/qca9563_tplink_re450-v3.dts | 25 +++++- .../ath79/dts/qca9563_tplink_re455-v1.dts | 25 +++++- .../dts/qca9563_tplink_tl-wpa8630-v1.dts | 25 +++++- .../etc/hotplug.d/firmware/11-ath10k-caldata | 82 ------------------- .../etc/hotplug.d/firmware/11-ath10k-caldata | 9 -- 38 files changed, 543 insertions(+), 122 deletions(-) diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts index b81485f465..e5d7cd04c1 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts +++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts @@ -72,6 +72,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 1>; + nvmem-cell-names = "calibration", "mac-address"; }; }; @@ -123,6 +125,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts index 3f1ad22a76..0ed3f805c7 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts +++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts @@ -57,6 +57,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &usb0 { @@ -106,6 +113,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts index fb594f78c0..37353ce100 100644 --- a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts +++ b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts @@ -148,6 +148,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -181,6 +191,8 @@ wifi@0,0 { compatible = "pci168c,003c"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_romfile_f100 2>; + nvmem-cell-names = "calibration", "mac-address"; }; }; diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts index 048099e260..a31694effd 100644 --- a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts +++ b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts @@ -149,6 +149,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -181,6 +191,8 @@ wifi@0,0 { compatible = "pci168c,0050"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; }; }; diff --git a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts index 6d402df13f..941d87657f 100644 --- a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts +++ b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts @@ -70,6 +70,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -107,4 +111,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts index 154744afd5..b9338f55db 100644 --- a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts +++ b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts @@ -76,6 +76,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -124,4 +128,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts index a6197fd25a..9001e3fb86 100644 --- a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts +++ b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts @@ -94,6 +94,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -108,4 +112,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts index 81a9e6ca08..778710eb91 100644 --- a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts +++ b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts @@ -59,6 +59,22 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; @@ -94,18 +110,11 @@ &pcie0 { status = "okay"; -}; -&art { - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - compatible = "mac-base"; - reg = <0x0 0x6>; - #nvmem-cell-cells = <1>; - }; + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; }; }; diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts index 8ce173f70d..281559ac12 100644 --- a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts +++ b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts @@ -102,6 +102,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; @@ -136,6 +140,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &wdt { diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi index 9a2579dd94..9fea258970 100644 --- a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi +++ b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi @@ -38,6 +38,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -80,6 +87,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; diff --git a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts index 73f4ed0d1e..de44aec47d 100644 --- a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts +++ b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts @@ -68,6 +68,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_12>; + nvmem-cell-names = "calibration", "mac-address"; }; }; @@ -137,6 +139,14 @@ macaddr_art_c: macaddr@c { reg = <0xc 0x6>; }; + + macaddr_art_12: macaddr@12 { + reg = <0x12 0x6>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_ocedo_koala.dts b/target/linux/ath79/dts/qca9558_ocedo_koala.dts index 76305b2ece..ad5a378e93 100644 --- a/target/linux/ath79/dts/qca9558_ocedo_koala.dts +++ b/target/linux/ath79/dts/qca9558_ocedo_koala.dts @@ -57,6 +57,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_c>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -119,6 +126,14 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts index d2125c38ba..8ddeccefb7 100644 --- a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts +++ b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts @@ -28,6 +28,13 @@ &pcie1 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_c>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -91,9 +98,17 @@ reg = <0x6 0x6>; }; + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + macaddr_art_12: macaddr@12 { reg = <0x12 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi index 32a176b542..cfceb9e698 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi +++ b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi @@ -126,6 +126,10 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -193,4 +197,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi index 218d5eb944..3bb793db7f 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi +++ b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi @@ -130,6 +130,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -173,4 +177,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts b/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts index 8ef3241ee0..e10e364219 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts +++ b/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts @@ -16,6 +16,8 @@ }; &pcie0 { + /delete-node/ wifi@0,0; + wifi@0,0 { compatible = "pci168c,0033"; reg = <0x0000 0 0 0 0>; diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts index cd3baacd15..3198ad2aa9 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts +++ b/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts @@ -16,6 +16,8 @@ }; &pcie0 { + /delete-node/ wifi@0,0; + wifi@0,0 { compatible = "pci168c,0033"; reg = <0x0000 0 0 0 0>; diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts index ee4b82ee8d..d8b6b5d98f 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts +++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts @@ -145,6 +145,10 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -212,4 +216,11 @@ &pcie1 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts index d448ca4284..0d9053e43f 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts +++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts @@ -113,6 +113,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -175,6 +182,10 @@ macaddr_art_6: macaddr@6 { reg = <0x6 0x6>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts index d41b065c27..584a66ba52 100644 --- a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts +++ b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts @@ -57,6 +57,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; @@ -70,6 +80,15 @@ nvmem-cell-names = "mac-address"; }; +&pcie1 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_1fc00 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts index 5869ee16e3..20cefe0b79 100644 --- a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts +++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts @@ -11,6 +11,15 @@ }; }; +&pcie1 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_romfs_f100 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -76,6 +85,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts index 7094077bc6..3418601c41 100644 --- a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts +++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts @@ -11,6 +11,15 @@ }; }; +&pcie1 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_romfs_f100 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &spi { status = "okay"; @@ -70,6 +79,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts index 7c48326d57..5205426f8e 100644 --- a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts +++ b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts @@ -99,7 +99,7 @@ phy-handle = <&phy4>; pll-data = <0x9e000000 0x80000101 0x80001313>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; gmac-config { @@ -115,6 +115,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -159,7 +166,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -174,6 +183,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -183,6 +202,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi index f90ebfea15..e8ab6ff512 100644 --- a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi +++ b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi @@ -98,6 +98,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-2)>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &spi { @@ -159,6 +166,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts index 99a4273ad0..33697d3b83 100644 --- a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts +++ b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts @@ -57,6 +57,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; @@ -70,6 +80,15 @@ nvmem-cell-names = "mac-address"; }; +&pcie1 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_1fc00 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; diff --git a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts index 5f5ef0f968..68cd277719 100644 --- a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts +++ b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts @@ -115,6 +115,10 @@ reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; }; }; }; @@ -134,4 +138,11 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts index 6179e621bf..3e87bebd14 100644 --- a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts +++ b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts @@ -170,6 +170,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -177,6 +187,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; ð0 { diff --git a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi index 09d2f48c2a..da9e7ee867 100644 --- a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi +++ b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi @@ -102,7 +102,13 @@ #size-cells = <1>; macaddr_art_0: macaddr@0 { + compatible = "mac-base"; reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; }; }; }; @@ -133,7 +139,7 @@ status = "okay"; phy-handle = <&phy0>; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; }; @@ -161,6 +167,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 1>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &usb0 { diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts index 339891f6da..50996e06c7 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts @@ -50,7 +50,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -71,17 +73,36 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts index 9925666f82..57db3cfa9a 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts @@ -134,7 +134,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -143,6 +145,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -165,12 +177,19 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; ð0 { status = "okay"; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; phy-mode = "sgmii"; phy-handle = <&phy0>; @@ -180,6 +199,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts index ae6061c4ce..929e8dc1bb 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts @@ -145,6 +145,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &usb_phy0 { @@ -205,7 +212,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -214,6 +223,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -241,7 +260,7 @@ pll-data = <0x03000101 0x00000101 0x00001919>; phy-mode = "sgmii"; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; }; @@ -250,6 +269,6 @@ status = "okay"; mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts index 32b75cad7b..d37fc14b11 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts @@ -43,6 +43,16 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; info: partition@60000 { @@ -56,7 +66,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -81,13 +93,24 @@ }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts index 5eb1eafaf4..25a7b8229b 100644 --- a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts @@ -41,7 +41,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -56,17 +58,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts index fdd982ae2e..2572901def 100644 --- a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts +++ b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts @@ -29,7 +29,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -62,17 +64,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts index a976f4fa5a..7caa356861 100644 --- a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts +++ b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts @@ -29,7 +29,9 @@ #size-cells = <1>; macaddr_info_8: macaddr@8 { + compatible = "mac-base"; reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -62,17 +64,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_info_8>; + nvmem-cells = <&macaddr_info_8 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts index 8c6c91f107..a44caa0b6b 100644 --- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts +++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts @@ -23,7 +23,9 @@ #size-cells = <1>; macaddr_uboot_fc00: macaddr@fc00 { + compatible = "mac-base"; reg = <0xfc00 0x6>; + #nvmem-cell-cells = <1>; }; }; }; @@ -44,17 +46,36 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; ð0 { - nvmem-cells = <&macaddr_uboot_fc00>; + nvmem-cells = <&macaddr_uboot_fc00 0>; nvmem-cell-names = "mac-address"; }; +&pcie { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_fc00 1>; + nvmem-cell-names = "calibration", "mac-address"; + }; +}; + &wmac { mtd-cal-data = <&art 0x1000>; - nvmem-cells = <&macaddr_uboot_fc00>; + nvmem-cells = <&macaddr_uboot_fc00 0>; nvmem-cell-names = "mac-address"; }; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index cc7458ae59..02cc293a6e 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -9,25 +9,6 @@ board=$(board_name) case "$FIRMWARE" in "ath10k/cal-pci-0000:00:00.0.bin") case $board in - allnet,all-wap02860ac|\ - araknis,an-500-ap-i-ac|\ - araknis,an-700-ap-i-ac|\ - comfast,cf-e380ac-v2|\ - engenius,enstationac-v1|\ - glinet,gl-x750|\ - watchguard,ap300) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2) - ;; - devolo,dvl1200e|\ - devolo,dvl1200i|\ - devolo,dvl1750c|\ - devolo,dvl1750e|\ - devolo,dvl1750i|\ - devolo,dvl1750x) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) -1) - ;; engenius,ecb1200|\ engenius,ecb1750) caldata_extract "art" 0x5000 0x844 @@ -41,10 +22,6 @@ case "$FIRMWARE" in caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(mtd_get_mac_ascii cfg1 RADIOADDR0) ;; - glinet,gl-ar750) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1) - ;; iodata,wn-ac1167dgr|\ iodata,wn-ac1600dgr2|\ sitecom,wlr-7100|\ @@ -56,73 +33,14 @@ case "$FIRMWARE" in caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(mtd_get_mac_text board_data 0x880) ;; - ocedo,koala|\ - ocedo,ursus) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_binary art 0xc) - ;; - openmesh,a40|\ - openmesh,a60|\ - openmesh,mr1750-v1|\ - openmesh,mr1750-v2|\ - openmesh,om5p-ac-v2) - caldata_extract "ART" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 16) - ;; qihoo,c301) caldata_extract "radiocfg" 0x5000 0x844 ath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac) ;; - tplink,archer-a7-v5|\ - tplink,archer-c2-v3|\ - tplink,archer-c7-v4|\ - tplink,archer-c7-v5|\ - tplink,archer-c25-v1|\ - tplink,tl-wr902ac-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1) - ;; - tplink,archer-c5-v1|\ - tplink,tl-wdr7500-v3) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x1fc00) -1) - ;; - tplink,archer-d50-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfile 0xf100) 2) - ;; - tplink,archer-d7-v1|\ - tplink,archer-d7b-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfs 0xf100) 2) - ;; - tplink,re350k-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 2) - ;; - tplink,re355-v1|\ - tplink,re450-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2) - ;; - tplink,re450-v2|\ - tplink,re450-v3|\ - tplink,re455-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1) - ;; - tplink,tl-wpa8630-v1) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x0fc00) 1) - ;; esac ;; "ath10k/cal-pci-0000:01:00.0.bin") case $board in - openmesh,om5p-ac-v1) - caldata_extract "ART" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16) - ;; sitecom,wlr-8100) caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1) diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index d26625981e..c85a134b58 100644 --- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -9,15 +9,6 @@ board=$(board_name) case "$FIRMWARE" in "ath10k/cal-pci-0000:00:00.0.bin") case $board in - domywifi,dw33d) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_binary art 0x12) - ;; - glinet,gl-ar750s-nor|\ - glinet,gl-ar750s-nor-nand) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1) - ;; zyxel,emg2926-q10a|\ zyxel,nbg6716) caldata_extract "art" 0x5000 0x844 From 0db4f9785ca30f79fa1abbffb0fab5a6053f68f5 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 1 Feb 2024 19:39:51 +0800 Subject: [PATCH 17/20] ath79: convert ath10k calibration data to NVMEM (ASCII MAC) This patch converts ath10k calibration data to NVMEM format for wave 1 devices with mtd ASCII MAC address. The "calibration" NVMEM cell size is 0x844. All unportable MAC address settings have been moved to '10_fix_wifi_mac' scripts. Signed-off-by: Shiji Yang --- .../ath79/dts/ar1022_sitecom_wlr-7100.dts | 12 ++++++ target/linux/ath79/dts/ar9344_qihoo_c301.dts | 12 ++++++ .../ath79/dts/qca9531_engenius_ews511ap.dts | 17 ++++++++ .../qca9557_extreme-networks_ws-ap3805i.dts | 12 ++++++ .../ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi | 12 ++++++ .../ath79/dts/qca9557_iodata_wn-ac1600dgr.dts | 7 ++++ .../linux/ath79/dts/qca9557_zyxel_nbg6616.dts | 13 +++++- .../ath79/dts/qca9558_sitecom_wlr-8100.dts | 12 ++++++ .../linux/ath79/dts/qca9558_zyxel_nbg6716.dts | 12 ++++++ .../ath79/dts/qca955x_engenius_ecb1xxx.dtsi | 13 +++++- .../linux/ath79/dts/qca9563_nec_wg800hp.dts | 29 ++++++++++++++ .../etc/hotplug.d/firmware/11-ath10k-caldata | 40 ------------------- .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 23 ++++++++++- .../etc/hotplug.d/firmware/11-ath10k-caldata | 22 ---------- .../etc/hotplug.d/ieee80211/10-fix-wifi-mac | 6 ++- 15 files changed, 174 insertions(+), 68 deletions(-) delete mode 100644 target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata diff --git a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts index e2ccef105d..b45d6bd77f 100644 --- a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts +++ b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts @@ -93,6 +93,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; @@ -147,6 +149,16 @@ label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/ar9344_qihoo_c301.dts b/target/linux/ath79/dts/ar9344_qihoo_c301.dts index d7e2e24239..8241c21dd0 100644 --- a/target/linux/ath79/dts/ar9344_qihoo_c301.dts +++ b/target/linux/ath79/dts/ar9344_qihoo_c301.dts @@ -157,6 +157,16 @@ label = "radiocfg"; reg = <0xff0000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_radiocfg_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -200,6 +210,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_radiocfg_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts index 6fd28d5b36..07b0655e35 100644 --- a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts +++ b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts @@ -82,6 +82,13 @@ &pcie0 { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; }; &spi { @@ -112,6 +119,16 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; partition@60000 { diff --git a/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts b/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts index 4a68f53075..686a474517 100644 --- a/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts +++ b/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts @@ -78,6 +78,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; @@ -193,6 +195,16 @@ label = "art"; reg = <0x3fc0000 0x40000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; diff --git a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi index 204a63cda8..76932be64a 100644 --- a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi +++ b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi @@ -140,6 +140,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -171,6 +181,8 @@ wifi@0,0 { compatible = "pci168c,003c"; reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts b/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts index 1e7d92db3f..934422f571 100644 --- a/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts +++ b/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts @@ -22,3 +22,10 @@ debounce-interval = <60>; }; }; + +&pcie1 { + wifi@0,0 { + /delete-property/ nvmem-cells; + /delete-property/ nvmem-cell-names; + }; +}; diff --git a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts index fff23dcf2b..25b36e50be 100644 --- a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts +++ b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts @@ -86,6 +86,16 @@ label = "art"; reg = <0x040000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; partition@50000 { @@ -118,6 +128,7 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; - qca,no-eeprom; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts index 01a69fce15..ba7feeab5a 100644 --- a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts +++ b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts @@ -113,6 +113,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -128,6 +138,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts index 20230e684e..27341a88e6 100644 --- a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts +++ b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts @@ -107,6 +107,16 @@ label = "art"; reg = <0x050000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; partition@60000 { @@ -167,6 +177,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; qcom,ath10k-calibration-variant = "ZyXEL-NBG6716"; }; }; diff --git a/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi b/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi index 66f2e38853..9d591bd6b3 100644 --- a/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi +++ b/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi @@ -87,6 +87,16 @@ label = "art"; reg = <0xff0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -122,7 +132,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x0 0 0 0 0>; - qca,no-eeprom; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; }; }; diff --git a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts index 1069a63a5e..a7390573cd 100644 --- a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts +++ b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts @@ -133,12 +133,34 @@ label = "board_data"; reg = <0x7e0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_board_data_880: macaddr@880 { + compatible = "mac-base"; + reg = <0x880 0x11>; + #nvmem-cell-cells = <1>; + }; + }; }; art: partition@7f0000 { label = "art"; reg = <0x7f0000 0x010000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; }; }; }; @@ -170,6 +192,13 @@ &pcie { status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>, <&macaddr_board_data_880 0>; + nvmem-cell-names = "calibration", "mac-address"; + }; }; &wmac { diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 02cc293a6e..19b02a5905 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -7,46 +7,6 @@ board=$(board_name) case "$FIRMWARE" in -"ath10k/cal-pci-0000:00:00.0.bin") - case $board in - engenius,ecb1200|\ - engenius,ecb1750) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_ascii u-boot-env athaddr) - ;; - engenius,ews511ap) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 1) - ;; - extreme-networks,ws-ap3805i) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_ascii cfg1 RADIOADDR0) - ;; - iodata,wn-ac1167dgr|\ - iodata,wn-ac1600dgr2|\ - sitecom,wlr-7100|\ - zyxel,nbg6616) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1) - ;; - nec,wg800hp) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_text board_data 0x880) - ;; - qihoo,c301) - caldata_extract "radiocfg" 0x5000 0x844 - ath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac) - ;; - esac - ;; -"ath10k/cal-pci-0000:01:00.0.bin") - case $board in - sitecom,wlr-8100) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1) - ;; - esac - ;; "ath10k/pre-cal-pci-0000:00:00.0.bin") case $board in dlink,dir-842-c1|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index d3392aa61e..1a845a4ed7 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -41,13 +41,31 @@ case "$board" in [ "$PHYNBR" -eq 1 ] && \ mtd_get_mac_ascii bdcfg "wlanmac" > /sys${DEVPATH}/macaddress ;; + engenius,ecb1200|\ + engenius,ecb1750) + [ "$PHYNBR" -eq 0 ] && \ + mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress + ;; engenius,epg5000|\ engenius,esr1200|\ engenius,esr1750|\ engenius,esr900) macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" "$PHYNBR" > /sys${DEVPATH}/macaddress ;; - iodata,wn-ac1600dgr) + engenius,ews511ap) + [ "$PHYNBR" -eq 0 ] && \ + macaddr_add $(cat /sys/class/net/eth0/address) 1 > /sys${DEVPATH}/macaddress + ;; + extreme-networks,ws-ap3805i) + [ "$PHYNBR" -eq 0 ] && \ + mtd_get_mac_ascii cfg1 RADIOADDR0 > /sys${DEVPATH}/macaddress + ;; + iodata,wn-ac1167dgr|\ + iodata,wn-ac1600dgr|\ + iodata,wn-ac1600dgr2|\ + sitecom,wlr-7100|\ + sitecom,wlr-8100|\ + zyxel,nbg6616) # There is no eeprom data for 5 GHz wlan in "art" partition # which would allow to patch the macaddress [ "$PHYNBR" -eq 0 ] && \ @@ -60,7 +78,8 @@ case "$board" in macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress ;; nec,wf1200cr|\ - nec,wg1200cr) + nec,wg1200cr|\ + qihoo,c301) [ "$PHYNBR" -eq 0 ] && \ mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress ;; diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata deleted file mode 100644 index c85a134b58..0000000000 --- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh - -[ -e /lib/firmware/$FIRMWARE ] && exit 0 - -. /lib/functions/caldata.sh - -board=$(board_name) - -case "$FIRMWARE" in -"ath10k/cal-pci-0000:00:00.0.bin") - case $board in - zyxel,emg2926-q10a|\ - zyxel,nbg6716) - caldata_extract "art" 0x5000 0x844 - ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1) - ;; - esac - ;; -*) - exit 1 - ;; -esac diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac index 20974248c1..5a933df501 100644 --- a/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac +++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac @@ -17,8 +17,10 @@ case $board in ;; zyxel,emg2926-q10a|\ zyxel,nbg6716) - # Set mac address for 2.4g device + ethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr) + [ "$PHYNBR" -eq 0 ] && \ + macaddr_add $ethaddr 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" -eq 1 ] && \ - mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress + echo -n $ethaddr > /sys${DEVPATH}/macaddress ;; esac From e430815f5a3fede7342332c27554de62094b4e87 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 1 Feb 2024 16:26:32 +0100 Subject: [PATCH 18/20] generic: 6.1: backport PHY package MMD patch Backport PHY package MMD patch merged upstream that add support for writing MMD regs for the PHY package and support for writing to PHY package at an offset. All affected patches automatically refreshed. Signed-off-by: Christian Marangi --- ...r-type-u8-in-phy_package_shared-stru.patch | 28 ++ ...HY-package-API-to-support-multiple-g.patch | 341 ++++++++++++++++++ ...ure-__phy_write-read_mmd-to-helper-a.patch | 116 ++++++ ...pport-for-PHY-package-MMD-read-write.patch | 196 ++++++++++ ...5-net-phy-Add-a-binding-for-PHY-LEDs.patch | 10 +- ...ce-Call-into-the-PHY-driver-to-set-L.patch | 8 +- ...ce-Call-into-the-PHY-driver-to-set-L.patch | 6 +- ...fix-circular-LEDS_CLASS-dependencies.patch | 2 +- ...net-phy-Fix-reading-LED-reg-property.patch | 4 +- ...emove-LEDs-to-ensure-correct-orderin.patch | 8 +- ...ce-Call-into-the-PHY-driver-to-set-L.patch | 6 +- ...-support-for-PHY-LEDs-polarity-modes.patch | 8 +- ...detach-callback-to-struct-phy_driver.patch | 4 +- 13 files changed, 709 insertions(+), 28 deletions(-) create mode 100644 target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch create mode 100644 target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch create mode 100644 target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch create mode 100644 target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch diff --git a/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch new file mode 100644 index 0000000000..6decc3430b --- /dev/null +++ b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch @@ -0,0 +1,28 @@ +From ebb30ccbbdbd6fae5177b676da4f4ac92bb4f635 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 15 Dec 2023 14:15:31 +0100 +Subject: [PATCH 1/4] net: phy: make addr type u8 in phy_package_shared struct + +Switch addr type in phy_package_shared struct to u8. + +The value is already checked to be non negative and to be less than +PHY_MAX_ADDR, hence u8 is better suited than using int. + +Signed-off-by: Christian Marangi +Reviewed-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + include/linux/phy.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -330,7 +330,7 @@ struct mdio_bus_stats { + * phy_package_leave(). + */ + struct phy_package_shared { +- int addr; ++ u8 addr; + refcount_t refcnt; + unsigned long flags; + size_t priv_size; diff --git a/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch new file mode 100644 index 0000000000..0cf01df3d3 --- /dev/null +++ b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch @@ -0,0 +1,341 @@ +From 9eea577eb1155fe4a183bc5e7bf269b0b2e7a6ba Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 15 Dec 2023 14:15:32 +0100 +Subject: [PATCH 2/4] net: phy: extend PHY package API to support multiple + global address + +Current API for PHY package are limited to single address to configure +global settings for the PHY package. + +It was found that some PHY package (for example the qca807x, a PHY +package that is shipped with a bundle of 5 PHY) requires multiple PHY +address to configure global settings. An example scenario is a PHY that +have a dedicated PHY for PSGMII/serdes calibrarion and have a specific +PHY in the package where the global PHY mode is set and affects every +other PHY in the package. + +Change the API in the following way: +- Change phy_package_join() to take the base addr of the PHY package + instead of the global PHY addr. +- Make __/phy_package_write/read() require an additional arg that + select what global PHY address to use by passing the offset from the + base addr passed on phy_package_join(). + +Each user of this API is updated to follow this new implementation +following a pattern where an enum is defined to declare the offset of the +addr. + +We also drop the check if shared is defined as any user of the +phy_package_read/write is expected to use phy_package_join first. Misuse +of this will correctly trigger a kernel panic for NULL pointer +exception. + +Signed-off-by: Christian Marangi +Signed-off-by: David S. Miller +--- + drivers/net/phy/bcm54140.c | 16 ++++++-- + drivers/net/phy/mscc/mscc.h | 5 +++ + drivers/net/phy/mscc/mscc_main.c | 4 +- + drivers/net/phy/phy_device.c | 35 +++++++++-------- + include/linux/phy.h | 64 +++++++++++++++++++++----------- + 5 files changed, 80 insertions(+), 44 deletions(-) + +--- a/drivers/net/phy/bcm54140.c ++++ b/drivers/net/phy/bcm54140.c +@@ -128,6 +128,10 @@ + #define BCM54140_DEFAULT_DOWNSHIFT 5 + #define BCM54140_MAX_DOWNSHIFT 9 + ++enum bcm54140_global_phy { ++ BCM54140_BASE_ADDR = 0, ++}; ++ + struct bcm54140_priv { + int port; + int base_addr; +@@ -429,11 +433,13 @@ static int bcm54140_base_read_rdb(struct + int ret; + + phy_lock_mdio_bus(phydev); +- ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb); ++ ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, ++ MII_BCM54XX_RDB_ADDR, rdb); + if (ret < 0) + goto out; + +- ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA); ++ ret = __phy_package_read(phydev, BCM54140_BASE_ADDR, ++ MII_BCM54XX_RDB_DATA); + + out: + phy_unlock_mdio_bus(phydev); +@@ -446,11 +452,13 @@ static int bcm54140_base_write_rdb(struc + int ret; + + phy_lock_mdio_bus(phydev); +- ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb); ++ ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, ++ MII_BCM54XX_RDB_ADDR, rdb); + if (ret < 0) + goto out; + +- ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val); ++ ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, ++ MII_BCM54XX_RDB_DATA, val); + + out: + phy_unlock_mdio_bus(phydev); +--- a/drivers/net/phy/mscc/mscc.h ++++ b/drivers/net/phy/mscc/mscc.h +@@ -414,6 +414,11 @@ struct vsc8531_private { + * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO + * is shared. + */ ++ ++enum vsc85xx_global_phy { ++ VSC88XX_BASE_ADDR = 0, ++}; ++ + struct vsc85xx_shared_private { + struct mutex gpio_lock; + }; +--- a/drivers/net/phy/mscc/mscc_main.c ++++ b/drivers/net/phy/mscc/mscc_main.c +@@ -700,7 +700,7 @@ int phy_base_write(struct phy_device *ph + dump_stack(); + } + +- return __phy_package_write(phydev, regnum, val); ++ return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); + } + + /* phydev->bus->mdio_lock should be locked when using this function */ +@@ -711,7 +711,7 @@ int phy_base_read(struct phy_device *phy + dump_stack(); + } + +- return __phy_package_read(phydev, regnum); ++ return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); + } + + u32 vsc85xx_csr_read(struct phy_device *phydev, +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1602,20 +1602,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1 + /** + * phy_package_join - join a common PHY group + * @phydev: target phy_device struct +- * @addr: cookie and PHY address for global register access ++ * @base_addr: cookie and base PHY address of PHY package for offset ++ * calculation of global register access + * @priv_size: if non-zero allocate this amount of bytes for private data + * + * This joins a PHY group and provides a shared storage for all phydevs in + * this group. This is intended to be used for packages which contain + * more than one PHY, for example a quad PHY transceiver. + * +- * The addr parameter serves as a cookie which has to have the same value +- * for all members of one group and as a PHY address to access generic +- * registers of a PHY package. Usually, one of the PHY addresses of the +- * different PHYs in the package provides access to these global registers. ++ * The base_addr parameter serves as cookie which has to have the same values ++ * for all members of one group and as the base PHY address of the PHY package ++ * for offset calculation to access generic registers of a PHY package. ++ * Usually, one of the PHY addresses of the different PHYs in the package ++ * provides access to these global registers. + * The address which is given here, will be used in the phy_package_read() +- * and phy_package_write() convenience functions. If your PHY doesn't have +- * global registers you can just pick any of the PHY addresses. ++ * and phy_package_write() convenience functions as base and added to the ++ * passed offset in those functions. + * + * This will set the shared pointer of the phydev to the shared storage. + * If this is the first call for a this cookie the shared storage will be +@@ -1625,17 +1627,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1 + * Returns < 1 on error, 0 on success. Esp. calling phy_package_join() + * with the same cookie but a different priv_size is an error. + */ +-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size) ++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size) + { + struct mii_bus *bus = phydev->mdio.bus; + struct phy_package_shared *shared; + int ret; + +- if (addr < 0 || addr >= PHY_MAX_ADDR) ++ if (base_addr < 0 || base_addr >= PHY_MAX_ADDR) + return -EINVAL; + + mutex_lock(&bus->shared_lock); +- shared = bus->shared[addr]; ++ shared = bus->shared[base_addr]; + if (!shared) { + ret = -ENOMEM; + shared = kzalloc(sizeof(*shared), GFP_KERNEL); +@@ -1647,9 +1649,9 @@ int phy_package_join(struct phy_device * + goto err_free; + shared->priv_size = priv_size; + } +- shared->addr = addr; ++ shared->base_addr = base_addr; + refcount_set(&shared->refcnt, 1); +- bus->shared[addr] = shared; ++ bus->shared[base_addr] = shared; + } else { + ret = -EINVAL; + if (priv_size && priv_size != shared->priv_size) +@@ -1687,7 +1689,7 @@ void phy_package_leave(struct phy_device + return; + + if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) { +- bus->shared[shared->addr] = NULL; ++ bus->shared[shared->base_addr] = NULL; + mutex_unlock(&bus->shared_lock); + kfree(shared->priv); + kfree(shared); +@@ -1706,7 +1708,8 @@ static void devm_phy_package_leave(struc + * devm_phy_package_join - resource managed phy_package_join() + * @dev: device that is registering this PHY package + * @phydev: target phy_device struct +- * @addr: cookie and PHY address for global register access ++ * @base_addr: cookie and base PHY address of PHY package for offset ++ * calculation of global register access + * @priv_size: if non-zero allocate this amount of bytes for private data + * + * Managed phy_package_join(). Shared storage fetched by this function, +@@ -1714,7 +1717,7 @@ static void devm_phy_package_leave(struc + * phy_package_join() for more information. + */ + int devm_phy_package_join(struct device *dev, struct phy_device *phydev, +- int addr, size_t priv_size) ++ int base_addr, size_t priv_size) + { + struct phy_device **ptr; + int ret; +@@ -1724,7 +1727,7 @@ int devm_phy_package_join(struct device + if (!ptr) + return -ENOMEM; + +- ret = phy_package_join(phydev, addr, priv_size); ++ ret = phy_package_join(phydev, base_addr, priv_size); + + if (!ret) { + *ptr = phydev; +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -319,7 +319,8 @@ struct mdio_bus_stats { + + /** + * struct phy_package_shared - Shared information in PHY packages +- * @addr: Common PHY address used to combine PHYs in one package ++ * @base_addr: Base PHY address of PHY package used to combine PHYs ++ * in one package and for offset calculation of phy_package_read/write + * @refcnt: Number of PHYs connected to this shared data + * @flags: Initialization of PHY package + * @priv_size: Size of the shared private data @priv +@@ -330,7 +331,7 @@ struct mdio_bus_stats { + * phy_package_leave(). + */ + struct phy_package_shared { +- u8 addr; ++ u8 base_addr; + refcount_t refcnt; + unsigned long flags; + size_t priv_size; +@@ -1763,10 +1764,10 @@ int phy_ethtool_get_link_ksettings(struc + int phy_ethtool_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd); + int phy_ethtool_nway_reset(struct net_device *ndev); +-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size); ++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size); + void phy_package_leave(struct phy_device *phydev); + int devm_phy_package_join(struct device *dev, struct phy_device *phydev, +- int addr, size_t priv_size); ++ int base_addr, size_t priv_size); + + #if IS_ENABLED(CONFIG_PHYLIB) + int __init mdio_bus_init(void); +@@ -1778,46 +1779,65 @@ int phy_ethtool_get_sset_count(struct ph + int phy_ethtool_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data); + +-static inline int phy_package_read(struct phy_device *phydev, u32 regnum) ++static inline int phy_package_address(struct phy_device *phydev, ++ unsigned int addr_offset) + { + struct phy_package_shared *shared = phydev->shared; ++ u8 base_addr = shared->base_addr; + +- if (!shared) ++ if (addr_offset >= PHY_MAX_ADDR - base_addr) + return -EIO; + +- return mdiobus_read(phydev->mdio.bus, shared->addr, regnum); ++ /* we know that addr will be in the range 0..31 and thus the ++ * implicit cast to a signed int is not a problem. ++ */ ++ return base_addr + addr_offset; + } + +-static inline int __phy_package_read(struct phy_device *phydev, u32 regnum) ++static inline int phy_package_read(struct phy_device *phydev, ++ unsigned int addr_offset, u32 regnum) + { +- struct phy_package_shared *shared = phydev->shared; ++ int addr = phy_package_address(phydev, addr_offset); + +- if (!shared) +- return -EIO; ++ if (addr < 0) ++ return addr; ++ ++ return mdiobus_read(phydev->mdio.bus, addr, regnum); ++} ++ ++static inline int __phy_package_read(struct phy_device *phydev, ++ unsigned int addr_offset, u32 regnum) ++{ ++ int addr = phy_package_address(phydev, addr_offset); ++ ++ if (addr < 0) ++ return addr; + +- return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum); ++ return __mdiobus_read(phydev->mdio.bus, addr, regnum); + } + + static inline int phy_package_write(struct phy_device *phydev, +- u32 regnum, u16 val) ++ unsigned int addr_offset, u32 regnum, ++ u16 val) + { +- struct phy_package_shared *shared = phydev->shared; ++ int addr = phy_package_address(phydev, addr_offset); + +- if (!shared) +- return -EIO; ++ if (addr < 0) ++ return addr; + +- return mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val); ++ return mdiobus_write(phydev->mdio.bus, addr, regnum, val); + } + + static inline int __phy_package_write(struct phy_device *phydev, +- u32 regnum, u16 val) ++ unsigned int addr_offset, u32 regnum, ++ u16 val) + { +- struct phy_package_shared *shared = phydev->shared; ++ int addr = phy_package_address(phydev, addr_offset); + +- if (!shared) +- return -EIO; ++ if (addr < 0) ++ return addr; + +- return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val); ++ return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); + } + + static inline bool __phy_package_set_once(struct phy_device *phydev, diff --git a/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch new file mode 100644 index 0000000000..4a17d46453 --- /dev/null +++ b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch @@ -0,0 +1,116 @@ +From 028672bd1d73cf65249a420c1de75e8d2acd2f6a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 15 Dec 2023 14:15:33 +0100 +Subject: [PATCH 3/4] net: phy: restructure __phy_write/read_mmd to helper and + phydev user + +Restructure phy_write_mmd and phy_read_mmd to implement generic helper +for direct mdiobus access for mmd and use these helper for phydev user. + +This is needed in preparation of PHY package API that requires generic +access to the mdiobus and are deatched from phydev struct but instead +access them based on PHY package base_addr and offsets. + +Signed-off-by: Christian Marangi +Reviewed-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phy-core.c | 64 ++++++++++++++++++-------------------- + 1 file changed, 30 insertions(+), 34 deletions(-) + +--- a/drivers/net/phy/phy-core.c ++++ b/drivers/net/phy/phy-core.c +@@ -528,6 +528,28 @@ static void mmd_phy_indirect(struct mii_ + devad | MII_MMD_CTRL_NOINCR); + } + ++static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45, ++ int devad, u32 regnum) ++{ ++ if (is_c45) ++ return __mdiobus_c45_read(bus, phy_addr, devad, regnum); ++ ++ mmd_phy_indirect(bus, phy_addr, devad, regnum); ++ /* Read the content of the MMD's selected register */ ++ return __mdiobus_read(bus, phy_addr, MII_MMD_DATA); ++} ++ ++static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45, ++ int devad, u32 regnum, u16 val) ++{ ++ if (is_c45) ++ return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val); ++ ++ mmd_phy_indirect(bus, phy_addr, devad, regnum); ++ /* Write the data into MMD's selected register */ ++ return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); ++} ++ + /** + * __phy_read_mmd - Convenience function for reading a register + * from an MMD on a given PHY. +@@ -539,26 +561,14 @@ static void mmd_phy_indirect(struct mii_ + */ + int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) + { +- int val; +- + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + +- if (phydev->drv && phydev->drv->read_mmd) { +- val = phydev->drv->read_mmd(phydev, devad, regnum); +- } else if (phydev->is_c45) { +- val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr, +- devad, regnum); +- } else { +- struct mii_bus *bus = phydev->mdio.bus; +- int phy_addr = phydev->mdio.addr; +- +- mmd_phy_indirect(bus, phy_addr, devad, regnum); +- +- /* Read the content of the MMD's selected register */ +- val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); +- } +- return val; ++ if (phydev->drv && phydev->drv->read_mmd) ++ return phydev->drv->read_mmd(phydev, devad, regnum); ++ ++ return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, ++ phydev->is_c45, devad, regnum); + } + EXPORT_SYMBOL(__phy_read_mmd); + +@@ -595,28 +605,14 @@ EXPORT_SYMBOL(phy_read_mmd); + */ + int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) + { +- int ret; +- + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + +- if (phydev->drv && phydev->drv->write_mmd) { +- ret = phydev->drv->write_mmd(phydev, devad, regnum, val); +- } else if (phydev->is_c45) { +- ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr, +- devad, regnum, val); +- } else { +- struct mii_bus *bus = phydev->mdio.bus; +- int phy_addr = phydev->mdio.addr; ++ if (phydev->drv && phydev->drv->write_mmd) ++ return phydev->drv->write_mmd(phydev, devad, regnum, val); + +- mmd_phy_indirect(bus, phy_addr, devad, regnum); +- +- /* Write the data into MMD's selected register */ +- __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); +- +- ret = 0; +- } +- return ret; ++ return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, ++ phydev->is_c45, devad, regnum, val); + } + EXPORT_SYMBOL(__phy_write_mmd); + diff --git a/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch new file mode 100644 index 0000000000..a628a37929 --- /dev/null +++ b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch @@ -0,0 +1,196 @@ +From d63710fc0f1a501fd75a7025e3070a96ffa1645f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 15 Dec 2023 14:15:34 +0100 +Subject: [PATCH 4/4] net: phy: add support for PHY package MMD read/write + +Some PHY in PHY package may require to read/write MMD regs to correctly +configure the PHY package. + +Add support for these additional required function in both lock and no +lock variant. + +It's assumed that the entire PHY package is either C22 or C45. We use +C22 or C45 way of writing/reading to mmd regs based on the passed phydev +whether it's C22 or C45. + +Signed-off-by: Christian Marangi +Signed-off-by: David S. Miller +--- + drivers/net/phy/phy-core.c | 140 +++++++++++++++++++++++++++++++++++++ + include/linux/phy.h | 16 +++++ + 2 files changed, 156 insertions(+) + +--- a/drivers/net/phy/phy-core.c ++++ b/drivers/net/phy/phy-core.c +@@ -639,6 +639,146 @@ int phy_write_mmd(struct phy_device *phy + EXPORT_SYMBOL(phy_write_mmd); + + /** ++ * __phy_package_read_mmd - read MMD reg relative to PHY package base addr ++ * @phydev: The phy_device struct ++ * @addr_offset: The offset to be added to PHY package base_addr ++ * @devad: The MMD to read from ++ * @regnum: The register on the MMD to read ++ * ++ * Convenience helper for reading a register of an MMD on a given PHY ++ * using the PHY package base address. The base address is added to ++ * the addr_offset value. ++ * ++ * Same calling rules as for __phy_read(); ++ * ++ * NOTE: It's assumed that the entire PHY package is either C22 or C45. ++ */ ++int __phy_package_read_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum) ++{ ++ int addr = phy_package_address(phydev, addr_offset); ++ ++ if (addr < 0) ++ return addr; ++ ++ if (regnum > (u16)~0 || devad > 32) ++ return -EINVAL; ++ ++ return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, ++ regnum); ++} ++EXPORT_SYMBOL(__phy_package_read_mmd); ++ ++/** ++ * phy_package_read_mmd - read MMD reg relative to PHY package base addr ++ * @phydev: The phy_device struct ++ * @addr_offset: The offset to be added to PHY package base_addr ++ * @devad: The MMD to read from ++ * @regnum: The register on the MMD to read ++ * ++ * Convenience helper for reading a register of an MMD on a given PHY ++ * using the PHY package base address. The base address is added to ++ * the addr_offset value. ++ * ++ * Same calling rules as for phy_read(); ++ * ++ * NOTE: It's assumed that the entire PHY package is either C22 or C45. ++ */ ++int phy_package_read_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum) ++{ ++ int addr = phy_package_address(phydev, addr_offset); ++ int val; ++ ++ if (addr < 0) ++ return addr; ++ ++ if (regnum > (u16)~0 || devad > 32) ++ return -EINVAL; ++ ++ phy_lock_mdio_bus(phydev); ++ val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, ++ regnum); ++ phy_unlock_mdio_bus(phydev); ++ ++ return val; ++} ++EXPORT_SYMBOL(phy_package_read_mmd); ++ ++/** ++ * __phy_package_write_mmd - write MMD reg relative to PHY package base addr ++ * @phydev: The phy_device struct ++ * @addr_offset: The offset to be added to PHY package base_addr ++ * @devad: The MMD to write to ++ * @regnum: The register on the MMD to write ++ * @val: value to write to @regnum ++ * ++ * Convenience helper for writing a register of an MMD on a given PHY ++ * using the PHY package base address. The base address is added to ++ * the addr_offset value. ++ * ++ * Same calling rules as for __phy_write(); ++ * ++ * NOTE: It's assumed that the entire PHY package is either C22 or C45. ++ */ ++int __phy_package_write_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum, u16 val) ++{ ++ int addr = phy_package_address(phydev, addr_offset); ++ ++ if (addr < 0) ++ return addr; ++ ++ if (regnum > (u16)~0 || devad > 32) ++ return -EINVAL; ++ ++ return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, ++ regnum, val); ++} ++EXPORT_SYMBOL(__phy_package_write_mmd); ++ ++/** ++ * phy_package_write_mmd - write MMD reg relative to PHY package base addr ++ * @phydev: The phy_device struct ++ * @addr_offset: The offset to be added to PHY package base_addr ++ * @devad: The MMD to write to ++ * @regnum: The register on the MMD to write ++ * @val: value to write to @regnum ++ * ++ * Convenience helper for writing a register of an MMD on a given PHY ++ * using the PHY package base address. The base address is added to ++ * the addr_offset value. ++ * ++ * Same calling rules as for phy_write(); ++ * ++ * NOTE: It's assumed that the entire PHY package is either C22 or C45. ++ */ ++int phy_package_write_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum, u16 val) ++{ ++ int addr = phy_package_address(phydev, addr_offset); ++ int ret; ++ ++ if (addr < 0) ++ return addr; ++ ++ if (regnum > (u16)~0 || devad > 32) ++ return -EINVAL; ++ ++ phy_lock_mdio_bus(phydev); ++ ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, ++ regnum, val); ++ phy_unlock_mdio_bus(phydev); ++ ++ return ret; ++} ++EXPORT_SYMBOL(phy_package_write_mmd); ++ ++/** + * phy_modify_changed - Function for modifying a PHY register + * @phydev: the phy_device struct + * @regnum: register number to modify +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -1840,6 +1840,22 @@ static inline int __phy_package_write(st + return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); + } + ++int __phy_package_read_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum); ++ ++int phy_package_read_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum); ++ ++int __phy_package_write_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum, u16 val); ++ ++int phy_package_write_mmd(struct phy_device *phydev, ++ unsigned int addr_offset, int devad, ++ u32 regnum, u16 val); ++ + static inline bool __phy_package_set_once(struct phy_device *phydev, + unsigned int b) + { diff --git a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch index d33fc72dd1..c958362e96 100644 --- a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch +++ b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch @@ -56,7 +56,7 @@ Signed-off-by: David S. Miller mutex_init(&dev->lock); INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); -@@ -2931,6 +2934,74 @@ static bool phy_drv_supports_irq(struct +@@ -2934,6 +2937,74 @@ static bool phy_drv_supports_irq(struct return phydrv->config_intr && phydrv->handle_interrupt; } @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller /** * fwnode_mdio_find_device - Given a fwnode, find the mdio_device * @fwnode: pointer to the mdio_device's fwnode -@@ -3109,6 +3180,11 @@ static int phy_probe(struct device *dev) +@@ -3112,6 +3183,11 @@ static int phy_probe(struct device *dev) /* Set the state to READY by default */ phydev->state = PHY_READY; @@ -153,7 +153,7 @@ Signed-off-by: David S. Miller #include #include #include -@@ -602,6 +603,7 @@ struct macsec_ops; +@@ -603,6 +604,7 @@ struct macsec_ops; * @phy_num_led_triggers: Number of triggers in @phy_led_triggers * @led_link_trigger: LED trigger for link up/down * @last_triggered: last LED trigger for link speed @@ -161,7 +161,7 @@ Signed-off-by: David S. Miller * @master_slave_set: User requested master/slave configuration * @master_slave_get: Current master/slave advertisement * @master_slave_state: Current master/slave configuration -@@ -694,6 +696,7 @@ struct phy_device { +@@ -695,6 +697,7 @@ struct phy_device { struct phy_led_trigger *led_link_trigger; #endif @@ -169,7 +169,7 @@ Signed-off-by: David S. Miller /* * Interrupt number for this PHY -@@ -768,6 +771,19 @@ struct phy_tdr_config { +@@ -769,6 +772,19 @@ struct phy_tdr_config { #define PHY_PAIR_ALL -1 /** diff --git a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch index c1678ce2ea..3c2477a63a 100644 --- a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch +++ b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch @@ -20,7 +20,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2934,11 +2934,18 @@ static bool phy_drv_supports_irq(struct +@@ -2937,11 +2937,18 @@ static bool phy_drv_supports_irq(struct return phydrv->config_intr && phydrv->handle_interrupt; } @@ -41,7 +41,7 @@ Signed-off-by: David S. Miller } static int of_phy_led(struct phy_device *phydev, -@@ -2955,12 +2962,14 @@ static int of_phy_led(struct phy_device +@@ -2958,12 +2965,14 @@ static int of_phy_led(struct phy_device return -ENOMEM; cdev = &phyled->led_cdev; @@ -59,7 +59,7 @@ Signed-off-by: David S. Miller init_data.fwnode = of_fwnode_handle(led); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -774,15 +774,19 @@ struct phy_tdr_config { +@@ -775,15 +775,19 @@ struct phy_tdr_config { * struct phy_led: An LED driven by the PHY * * @list: List of LEDs @@ -79,7 +79,7 @@ Signed-off-by: David S. Miller /** * struct phy_driver - Driver structure for a particular PHY type * -@@ -997,6 +1001,15 @@ struct phy_driver { +@@ -998,6 +1002,15 @@ struct phy_driver { int (*get_sqi)(struct phy_device *dev); /** @get_sqi_max: Get the maximum signal quality indication */ int (*get_sqi_max)(struct phy_device *dev); diff --git a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch index f234b2bff1..35d83d8a6a 100644 --- a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch +++ b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2948,6 +2948,22 @@ static int phy_led_set_brightness(struct +@@ -2951,6 +2951,22 @@ static int phy_led_set_brightness(struct return err; } @@ -41,7 +41,7 @@ Signed-off-by: David S. Miller static int of_phy_led(struct phy_device *phydev, struct device_node *led) { -@@ -2970,6 +2986,8 @@ static int of_phy_led(struct phy_device +@@ -2973,6 +2989,8 @@ static int of_phy_led(struct phy_device if (phydev->drv->led_brightness_set) cdev->brightness_set_blocking = phy_led_set_brightness; @@ -52,7 +52,7 @@ Signed-off-by: David S. Miller init_data.fwnode = of_fwnode_handle(led); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -1010,6 +1010,18 @@ struct phy_driver { +@@ -1011,6 +1011,18 @@ struct phy_driver { */ int (*led_brightness_set)(struct phy_device *dev, u8 index, enum led_brightness value); diff --git a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch index 1de086417b..66dbcb8a90 100644 --- a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch +++ b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch @@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs" --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -3210,7 +3210,8 @@ static int phy_probe(struct device *dev) +@@ -3213,7 +3213,8 @@ static int phy_probe(struct device *dev) /* Get the LEDs from the device tree, and instantiate standard * LEDs for them. */ diff --git a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch index d6081d0e63..3710cfade2 100644 --- a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch +++ b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch @@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2971,6 +2971,7 @@ static int of_phy_led(struct phy_device +@@ -2974,6 +2974,7 @@ static int of_phy_led(struct phy_device struct led_init_data init_data = {}; struct led_classdev *cdev; struct phy_led *phyled; @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski int err; phyled = devm_kzalloc(dev, sizeof(*phyled), GFP_KERNEL); -@@ -2980,10 +2981,13 @@ static int of_phy_led(struct phy_device +@@ -2983,10 +2984,13 @@ static int of_phy_led(struct phy_device cdev = &phyled->led_cdev; phyled->phydev = phydev; diff --git a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch index 8f076be640..80ac785cdb 100644 --- a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch +++ b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch @@ -22,7 +22,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2964,6 +2964,15 @@ static int phy_led_blink_set(struct led_ +@@ -2967,6 +2967,15 @@ static int phy_led_blink_set(struct led_ return err; } @@ -38,7 +38,7 @@ Signed-off-by: David S. Miller static int of_phy_led(struct phy_device *phydev, struct device_node *led) { -@@ -2997,7 +3006,7 @@ static int of_phy_led(struct phy_device +@@ -3000,7 +3009,7 @@ static int of_phy_led(struct phy_device init_data.fwnode = of_fwnode_handle(led); init_data.devname_mandatory = true; @@ -47,7 +47,7 @@ Signed-off-by: David S. Miller if (err) return err; -@@ -3026,6 +3035,7 @@ static int of_phy_leds(struct phy_device +@@ -3029,6 +3038,7 @@ static int of_phy_leds(struct phy_device err = of_phy_led(phydev, led); if (err) { of_node_put(led); @@ -55,7 +55,7 @@ Signed-off-by: David S. Miller return err; } } -@@ -3231,6 +3241,9 @@ static int phy_remove(struct device *dev +@@ -3234,6 +3244,9 @@ static int phy_remove(struct device *dev cancel_delayed_work_sync(&phydev->state_queue); diff --git a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch index daa970884e..0bf1e03c49 100644 --- a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch +++ b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch @@ -23,7 +23,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2964,6 +2964,61 @@ static int phy_led_blink_set(struct led_ +@@ -2967,6 +2967,61 @@ static int phy_led_blink_set(struct led_ return err; } @@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski static void phy_leds_unregister(struct phy_device *phydev) { struct phy_led *phyled; -@@ -3001,6 +3056,19 @@ static int of_phy_led(struct phy_device +@@ -3004,6 +3059,19 @@ static int of_phy_led(struct phy_device cdev->brightness_set_blocking = phy_led_set_brightness; if (phydev->drv->led_blink_set) cdev->blink_set = phy_led_blink_set; @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski init_data.fwnode = of_fwnode_handle(led); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -1022,6 +1022,39 @@ struct phy_driver { +@@ -1023,6 +1023,39 @@ struct phy_driver { int (*led_blink_set)(struct phy_device *dev, u8 index, unsigned long *delay_on, unsigned long *delay_off); diff --git a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch index 604b3db270..97fbd2bfc5 100644 --- a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch +++ b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch @@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -3034,6 +3034,7 @@ static int of_phy_led(struct phy_device +@@ -3037,6 +3037,7 @@ static int of_phy_led(struct phy_device struct device *dev = &phydev->mdio.dev; struct led_init_data init_data = {}; struct led_classdev *cdev; @@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski struct phy_led *phyled; u32 index; int err; -@@ -3051,6 +3052,21 @@ static int of_phy_led(struct phy_device +@@ -3054,6 +3055,21 @@ static int of_phy_led(struct phy_device if (index > U8_MAX) return -EINVAL; @@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski cdev->brightness_set_blocking = phy_led_set_brightness; --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -787,6 +787,15 @@ struct phy_led { +@@ -788,6 +788,15 @@ struct phy_led { #define to_phy_led(d) container_of(d, struct phy_led, led_cdev) @@ -76,7 +76,7 @@ Signed-off-by: Jakub Kicinski /** * struct phy_driver - Driver structure for a particular PHY type * -@@ -1055,6 +1064,19 @@ struct phy_driver { +@@ -1056,6 +1065,19 @@ struct phy_driver { int (*led_hw_control_get)(struct phy_device *dev, u8 index, unsigned long *rules); diff --git a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch index aa852e7fec..b658d5205e 100644 --- a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch +++ b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -1753,6 +1753,9 @@ void phy_detach(struct phy_device *phyde +@@ -1756,6 +1756,9 @@ void phy_detach(struct phy_device *phyde struct module *ndev_owner = NULL; struct mii_bus *bus; @@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos sysfs_remove_link(&dev->dev.kobj, "phydev"); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -896,6 +896,12 @@ struct phy_driver { +@@ -897,6 +897,12 @@ struct phy_driver { /** @handle_interrupt: Override default interrupt handling */ irqreturn_t (*handle_interrupt)(struct phy_device *phydev); From 2c363a070e3a007a2f4f5e12491676cbe670fe5a Mon Sep 17 00:00:00 2001 From: John Audia Date: Fri, 26 Jan 2024 16:09:33 -0500 Subject: [PATCH 19/20] kernel: bump 6.1 to 6.1.75 Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.75 Removed upstreamed: generic/hack-6.1/321-powerpc_crtsavres_prereq.patch[1] generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch[2] Rebased: bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch[3] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.75&id=16b88e68b85d5520c28498bb847358ff6300cb90 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/fs/smb?h=v6.1.75&id=c866866c795296d3637ab0d48a3d8a3ef5d6f4a3 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.75&id=81f444f22816a82ada2cc787a2845cffc8c584a6 Build system: x86/64 Build-tested: x86/64/AMD Cezanne Run-tested: x86/64/AMD Cezanne Signed-off-by: John Audia --- include/kernel-6.1 | 4 +- ...ds-add-reset-controller-based-driver.patch | 2 +- ...835-Support-setting-reboot-partition.patch | 6 +-- ...50-bcm2835aux-defer-if-clock-is-zero.patch | 2 +- ...-Ignore-params-after-the-partition-n.patch | 2 +- ...ncel-deferred-work-if-pagelist-empty.patch | 8 ++-- ...7xx-Read-modem-line-state-at-startup.patch | 2 +- ...wc3-Set-DMA-and-coherent-masks-early.patch | 14 +++---- ...rt-for-Sercomm-MSP430-LED-controller.patch | 2 +- ...c-move-TX-timer-arm-after-DMA-enable.patch | 8 ++-- ...a-Support-HW-controlled-mode-via-pri.patch | 2 +- .../321-powerpc_crtsavres_prereq.patch | 38 ------------------- ...-only-v2-leases-handle-the-directory.patch | 32 ---------------- ...les-ignore-EOPNOTSUPP-on-flowtable-d.patch | 2 +- ...ert-PERST-for-100ms-for-power-and-cl.patch | 2 +- ...1-pcie-mediatek-gen3-PERST-for-100ms.patch | 2 +- ...ediatek-add-support-for-coherent-DMA.patch | 2 +- .../950-smartrg-i2c-led-driver.patch | 2 +- ...d-the-IEI-WT61P803-PUZZLE-LED-driver.patch | 2 +- 19 files changed, 32 insertions(+), 102 deletions(-) delete mode 100644 target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch delete mode 100644 target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 87c6bf5097..b6c55613b6 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .74 -LINUX_KERNEL_HASH-6.1.74 = b7fbd1d79faed2ce3570ef79dc1223e4e19c868b86326b14a435db56ebbb2022 +LINUX_VERSION-6.1 = .75 +LINUX_KERNEL_HASH-6.1.75 = 6cd19410330c13ec4c18fd28a83d3e40fc12a152815fb7c3e1b0764329093a56 diff --git a/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch index e9349b4f8c..0002b9b95b 100644 --- a/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch +++ b/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -873,6 +873,17 @@ source "drivers/leds/flash/Kconfig" +@@ -874,6 +874,17 @@ source "drivers/leds/flash/Kconfig" comment "RGB LED drivers" source "drivers/leds/rgb/Kconfig" diff --git a/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch b/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch index b1ba4ae6b8..1fa6d6d75a 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch @@ -36,7 +36,7 @@ Signed-off-by: Noralf Trønnes #define SECS_TO_WDOG_TICKS(x) ((x) << 16) #define WDOG_TICKS_TO_SECS(x) ((x) >> 16) -@@ -97,9 +91,24 @@ static unsigned int bcm2835_wdt_get_time +@@ -98,9 +92,24 @@ static unsigned int bcm2835_wdt_get_time return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); } @@ -63,7 +63,7 @@ Signed-off-by: Noralf Trønnes /* use a timeout of 10 ticks (~150us) */ writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG); -@@ -117,7 +126,13 @@ static int bcm2835_restart(struct watchd +@@ -118,7 +127,13 @@ static int bcm2835_restart(struct watchd { struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); @@ -78,7 +78,7 @@ Signed-off-by: Noralf Trønnes return 0; } -@@ -152,19 +167,9 @@ static struct watchdog_device bcm2835_wd +@@ -153,19 +168,9 @@ static struct watchdog_device bcm2835_wd static void bcm2835_power_off(void) { struct bcm2835_wdt *wdt = bcm2835_power_off_wdt; diff --git a/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch b/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch index 5013109566..656defb3c7 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch @@ -12,7 +12,7 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/8250/8250_bcm2835aux.c +++ b/drivers/tty/serial/8250/8250_bcm2835aux.c -@@ -180,6 +180,13 @@ static int bcm2835aux_serial_probe(struc +@@ -182,6 +182,13 @@ static int bcm2835aux_serial_probe(struc */ up.port.uartclk = uartclk * 2; diff --git a/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch b/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch index bf3ba2153e..a7614795df 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch @@ -12,7 +12,7 @@ which are only relevant to other reboot notifiers. --- a/drivers/watchdog/bcm2835_wdt.c +++ b/drivers/watchdog/bcm2835_wdt.c -@@ -126,10 +126,12 @@ static int bcm2835_restart(struct watchd +@@ -127,10 +127,12 @@ static int bcm2835_restart(struct watchd { struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); diff --git a/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch b/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch index 35441799dd..31a34fee85 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch @@ -1,4 +1,4 @@ -From a25b0ea78e73b699e89c6d5589ba43cd0a22f97e Mon Sep 17 00:00:00 2001 +From cf40d2d8c44a659d09d5c20189aab02f20263e81 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 29 Mar 2023 09:49:36 +0100 Subject: [PATCH] fbdev: Don't cancel deferred work if pagelist empty @@ -24,13 +24,13 @@ Signed-off-by: Phil Elwell --- a/drivers/video/fbdev/core/fb_defio.c +++ b/drivers/video/fbdev/core/fb_defio.c -@@ -321,7 +321,8 @@ static void fb_deferred_io_lastclose(str +@@ -317,7 +317,8 @@ static void fb_deferred_io_lastclose(str struct page *page; int i; -- cancel_delayed_work_sync(&info->deferred_work); +- flush_delayed_work(&info->deferred_work); + if (!list_empty(&info->fbdefio->pagereflist)) -+ cancel_delayed_work_sync(&info->deferred_work); ++ flush_delayed_work(&info->deferred_work); /* clear out the mapping that we setup */ for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) { diff --git a/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch b/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch index c93ebf3e7e..148134f0a2 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch @@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c -@@ -1221,6 +1221,9 @@ static int sc16is7xx_startup(struct uart +@@ -1222,6 +1222,9 @@ static int sc16is7xx_startup(struct uart SC16IS7XX_IER_MSI_BIT; sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); diff --git a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch index f6944e226f..2c09524dfd 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch @@ -212,7 +212,7 @@ Signed-off-by: Jonathan Bell }, --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c -@@ -1216,6 +1216,24 @@ static void dwc3_config_threshold(struct +@@ -1179,6 +1179,24 @@ static void dwc3_config_threshold(struct } } @@ -237,7 +237,7 @@ Signed-off-by: Jonathan Bell /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure -@@ -1308,6 +1326,8 @@ static int dwc3_core_init(struct dwc3 *d +@@ -1271,6 +1289,8 @@ static int dwc3_core_init(struct dwc3 *d dwc3_set_incr_burst_type(dwc); @@ -246,7 +246,7 @@ Signed-off-by: Jonathan Bell usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0); ret = phy_power_on(dwc->usb2_generic_phy); -@@ -1541,6 +1561,7 @@ static void dwc3_get_properties(struct d +@@ -1504,6 +1524,7 @@ static void dwc3_get_properties(struct d u8 tx_thr_num_pkt_prd = 0; u8 tx_max_burst_prd = 0; u8 tx_fifo_resize_max_num; @@ -254,7 +254,7 @@ Signed-off-by: Jonathan Bell const char *usb_psy_name; int ret; -@@ -1563,6 +1584,9 @@ static void dwc3_get_properties(struct d +@@ -1526,6 +1547,9 @@ static void dwc3_get_properties(struct d */ tx_fifo_resize_max_num = 6; @@ -264,7 +264,7 @@ Signed-off-by: Jonathan Bell dwc->maximum_speed = usb_get_maximum_speed(dev); dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); dwc->dr_mode = usb_get_dr_mode(dev); -@@ -1678,6 +1702,9 @@ static void dwc3_get_properties(struct d +@@ -1641,6 +1665,9 @@ static void dwc3_get_properties(struct d dwc->dis_split_quirk = device_property_read_bool(dev, "snps,dis-split-quirk"); @@ -274,7 +274,7 @@ Signed-off-by: Jonathan Bell dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; -@@ -1695,6 +1722,8 @@ static void dwc3_get_properties(struct d +@@ -1658,6 +1685,8 @@ static void dwc3_get_properties(struct d dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; dwc->tx_max_burst_prd = tx_max_burst_prd; @@ -283,7 +283,7 @@ Signed-off-by: Jonathan Bell dwc->imod_interval = 0; dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; -@@ -1903,6 +1932,12 @@ static int dwc3_probe(struct platform_de +@@ -1866,6 +1895,12 @@ static int dwc3_probe(struct platform_de dwc3_get_properties(dwc); diff --git a/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch b/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch index adcb01ec29..763e25ba03 100644 --- a/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch +++ b/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch @@ -17,7 +17,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -282,6 +282,15 @@ config LEDS_COBALT_RAQ +@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ help This option enables support for the Cobalt Raq series LEDs. diff --git a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch index d1e04e9069..e94a2ca819 100644 --- a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch +++ b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch @@ -42,7 +42,7 @@ Signed-off-by: Paolo Abeni __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); -@@ -5485,12 +5489,13 @@ static int stmmac_napi_poll_tx(struct na +@@ -5486,12 +5490,13 @@ static int stmmac_napi_poll_tx(struct na struct stmmac_channel *ch = container_of(napi, struct stmmac_channel, tx_napi); struct stmmac_priv *priv = ch->priv_data; @@ -57,7 +57,7 @@ Signed-off-by: Paolo Abeni work_done = min(work_done, budget); if (work_done < budget && napi_complete_done(napi, work_done)) { -@@ -5501,6 +5506,10 @@ static int stmmac_napi_poll_tx(struct na +@@ -5502,6 +5507,10 @@ static int stmmac_napi_poll_tx(struct na spin_unlock_irqrestore(&ch->lock, flags); } @@ -68,7 +68,7 @@ Signed-off-by: Paolo Abeni return work_done; } -@@ -5509,12 +5518,13 @@ static int stmmac_napi_poll_rxtx(struct +@@ -5510,12 +5519,13 @@ static int stmmac_napi_poll_rxtx(struct struct stmmac_channel *ch = container_of(napi, struct stmmac_channel, rxtx_napi); struct stmmac_priv *priv = ch->priv_data; @@ -83,7 +83,7 @@ Signed-off-by: Paolo Abeni tx_done = min(tx_done, budget); rx_done = stmmac_rx_zc(priv, budget, chan); -@@ -5539,6 +5549,10 @@ static int stmmac_napi_poll_rxtx(struct +@@ -5540,6 +5550,10 @@ static int stmmac_napi_poll_rxtx(struct spin_unlock_irqrestore(&ch->lock, flags); } diff --git a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch index f64bbc7782..00773ab0f6 100644 --- a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch +++ b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch @@ -49,7 +49,7 @@ Signed-off-by: Lee Jones --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA +@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA depends on I2C depends on MACH_ARMADA_38X || COMPILE_TEST depends on OF diff --git a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch deleted file mode 100644 index 17eba0b354..0000000000 --- a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001 -From: "Alexandros C. Couloumbis" -Date: Fri, 7 Jul 2017 17:14:51 +0200 -Subject: hack: arch: powerpc: drop register save/restore library from modules - -Upstream GCC uses a libgcc function for saving/restoring registers. This -makes the code bigger, and upstream kernels need to carry that function -for every single kernel module. Our GCC is patched to avoid those -references, so we can drop the extra bloat for modules. - -lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec -Signed-off-by: Alexandros C. Couloumbis ---- - arch/powerpc/Makefile | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/powerpc/Makefile -+++ b/arch/powerpc/Makefile -@@ -42,19 +42,6 @@ machine-$(CONFIG_PPC64) += 64 - machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le - UTS_MACHINE := $(subst $(space),,$(machine-y)) - --# XXX This needs to be before we override LD below --ifdef CONFIG_PPC32 --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --else --ifeq ($(call ld-ifversion, -ge, 22500, y),y) --# Have the linker provide sfpr if possible. --# There is a corresponding test in arch/powerpc/lib/Makefile --KBUILD_LDFLAGS_MODULE += --save-restore-funcs --else --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --endif --endif -- - ifdef CONFIG_CPU_LITTLE_ENDIAN - KBUILD_CFLAGS += -mlittle-endian - KBUILD_LDFLAGS += -EL diff --git a/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch b/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch deleted file mode 100644 index b565fbd5b9..0000000000 --- a/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 86b7307af26834415e1ba8597319a8b64846346f Mon Sep 17 00:00:00 2001 -From: Namjae Jeon -Date: Mon, 15 Jan 2024 10:24:54 +0900 -Subject: [PATCH] ksmbd: only v2 leases handle the directory - -When smb2 leases is disable, ksmbd can send oplock break notification -and cause wait oplock break ack timeout. It may appear like hang when -accessing a directory. This patch make only v2 leases handle the -directory. - -Cc: stable@vger.kernel.org -Signed-off-by: Namjae Jeon -Signed-off-by: Steve French ---- - fs/smb/server/oplock.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/fs/smb/server/oplock.c -+++ b/fs/smb/server/oplock.c -@@ -1191,6 +1191,12 @@ int smb_grant_oplock(struct ksmbd_work * - bool prev_op_has_lease; - __le32 prev_op_state = 0; - -+ /* Only v2 leases handle the directory */ -+ if (S_ISDIR(file_inode(fp->filp)->i_mode)) { -+ if (!lctx || lctx->version != 2) -+ return 0; -+ } -+ - opinfo = alloc_opinfo(work, pid, tid); - if (!opinfo) - return -ENOMEM; diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index 307ddce761..683df4df83 100644 --- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -7884,7 +7884,7 @@ static int nft_register_flowtable_net_ho +@@ -7900,7 +7900,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch index 05a6ff0fdb..983fde707f 100644 --- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch @@ -18,7 +18,7 @@ Acked-by: Pali Rohár --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c -@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru +@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru */ msleep(100); diff --git a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch index 5e343d01cc..32b4237d82 100644 --- a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch +++ b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch @@ -1,6 +1,6 @@ --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct +@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct msleep(100); /* De-assert reset signals */ diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index de64eda827..76ee2fc89a 100644 --- a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau struct mtk_pcie_port; /** -@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci +@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci struct mtk_pcie_port *port, *tmp; int err, slot; diff --git a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch index a98cca19a5..8b86c50429 100644 --- a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch +++ b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch @@ -5,7 +5,7 @@ --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -873,6 +873,16 @@ source "drivers/leds/flash/Kconfig" +@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig" comment "RGB LED drivers" source "drivers/leds/rgb/Kconfig" diff --git a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch index ec783256e3..1abb1b9416 100644 --- a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch +++ b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch @@ -30,7 +30,7 @@ Cc: Robert Marko --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -299,6 +299,14 @@ config LEDS_IPAQ_MICRO +@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO Choose this option if you want to use the notification LED on Compaq/HP iPAQ h3100 and h3600. From 99c9d8abd6779d41b763108f877c068f16b19c17 Mon Sep 17 00:00:00 2001 From: John Audia Date: Fri, 26 Jan 2024 16:55:30 -0500 Subject: [PATCH 20/20] kernel: bump 5.15 to 5.15.148 Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.148 Removed upstreamed: generic/hack-5.15/321-powerpc_crtsavres_prereq.patch[1] Manually rebased: target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch[2] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.148&id=0b11a145eb00d51f7ef18cfcae587b93f9adb1e9 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit?h=v5.15.148&id=b67064bd372300a75293efbbc70624996dccffd4 Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3 Run-tested: ramips/tplink_archer-a6-v3 Signed-off-by: John Audia --- include/kernel-5.15 | 4 +- ...ds-add-reset-controller-based-driver.patch | 2 +- ...ved-syscon_regmap_lookup_by_pdevname.patch | 2 +- ...k-gate-Add-devm_clk_hw_register_gate.patch | 4 +- ...icro-stmmac-move-queue-reset-to-dedi.patch | 10 +- ...icro-stmmac-first-disable-all-queues.patch | 4 +- ...icro-stmmac-move-dma-conf-to-dedicat.patch | 98 +++++++++---------- ...icro-stmmac-generate-stmmac-dma-conf.patch | 24 ++--- ...icro-stmmac-permit-MTU-change-with-i.patch | 4 +- ...ll-of_parse_phandle-variants-static-.patch | 8 +- ...-of_parse_phandle_with_optional_args.patch | 2 +- ...0004-of-Move-of_modalias-to-module.c.patch | 2 +- ...uest-module-helper-logic-to-module.c.patch | 2 +- ...a-Support-HW-controlled-mode-via-pri.patch | 2 +- .../321-powerpc_crtsavres_prereq.patch | 38 ------- ...les-ignore-EOPNOTSUPP-on-flowtable-d.patch | 2 +- ...ert-PERST-for-100ms-for-power-and-cl.patch | 2 +- ...ediatek-add-support-for-coherent-DMA.patch | 2 +- ...move-drivers-from-strlcpy-to-strscpy.patch | 4 +- .../950-smartrg-i2c-led-driver.patch | 2 +- ...d-the-IEI-WT61P803-PUZZLE-LED-driver.patch | 2 +- ...r-Gateworks-PLX-PEX860x-switch-with-.patch | 2 +- ...IPS-ralink-add-sdhci-for-mt7620a-SoC.patch | 2 +- 23 files changed, 93 insertions(+), 131 deletions(-) delete mode 100644 target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 5cc07434b2..d93ae194b8 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .147 -LINUX_KERNEL_HASH-5.15.147 = 56c1e65625d201db431efda7a3816e7b424071e7cb0245b2ba594d15b1fdfcd4 +LINUX_VERSION-5.15 = .148 +LINUX_KERNEL_HASH-5.15.148 = c48575c97fd9f4767cbe50a13b1b2b40ee42830aba3182fabd35a03259a6e5d8 diff --git a/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch index 9daea4c95a..bbf8d7ef8c 100644 --- a/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch +++ b/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -877,6 +877,17 @@ source "drivers/leds/blink/Kconfig" +@@ -878,6 +878,17 @@ source "drivers/leds/blink/Kconfig" comment "Flash and Torch LED drivers" source "drivers/leds/flash/Kconfig" diff --git a/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch b/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch index 5a3e6b0679..7199166377 100644 --- a/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch +++ b/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch @@ -16,7 +16,7 @@ Signed-off-by: Adrian Schmutzler --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c -@@ -205,6 +205,27 @@ struct regmap *syscon_regmap_lookup_by_c +@@ -209,6 +209,27 @@ struct regmap *syscon_regmap_lookup_by_c } EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible); diff --git a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch index 51c23b6e34..819cc292e8 100644 --- a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch +++ b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch @@ -66,7 +66,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h -@@ -490,6 +490,13 @@ struct clk_hw *__clk_hw_register_gate(st +@@ -517,6 +517,13 @@ struct clk_hw *__clk_hw_register_gate(st unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); @@ -80,7 +80,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, -@@ -544,6 +551,22 @@ struct clk *clk_register_gate(struct dev +@@ -571,6 +578,22 @@ struct clk *clk_register_gate(struct dev __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch index 3c10819b68..931c589cfa 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch @@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); stmmac_start_tx_dma(priv, chan); -@@ -3782,6 +3773,8 @@ static int stmmac_open(struct net_device +@@ -3783,6 +3774,8 @@ static int stmmac_open(struct net_device } } @@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski ret = stmmac_hw_setup(dev, true); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); -@@ -6429,6 +6422,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6430,6 +6423,7 @@ void stmmac_enable_rx_queue(struct stmma return; } @@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_rx_descriptors(priv, queue); stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -6490,6 +6484,7 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6491,6 +6485,7 @@ void stmmac_enable_tx_queue(struct stmma return; } @@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_tx_descriptors(priv, queue); stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -7414,6 +7409,25 @@ int stmmac_suspend(struct device *dev) +@@ -7415,6 +7410,25 @@ int stmmac_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(stmmac_suspend); @@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski /** * stmmac_reset_queues_param - reset queue parameters * @priv: device pointer -@@ -7424,22 +7438,11 @@ static void stmmac_reset_queues_param(st +@@ -7425,22 +7439,11 @@ static void stmmac_reset_queues_param(st u32 tx_cnt = priv->plat->tx_queues_to_use; u32 queue; diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch index 6e115834eb..8bdeef7a69 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch @@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3834,8 +3834,6 @@ static int stmmac_release(struct net_dev +@@ -3835,8 +3835,6 @@ static int stmmac_release(struct net_dev struct stmmac_priv *priv = netdev_priv(dev); u32 chan; @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski if (device_may_wakeup(priv->device)) phylink_speed_down(priv->phylink, false); /* Stop and disconnect the PHY */ -@@ -3847,6 +3845,8 @@ static int stmmac_release(struct net_dev +@@ -3848,6 +3846,8 @@ static int stmmac_release(struct net_dev for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) hrtimer_cancel(&priv->tx_queue[chan].txtimer); diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch index 99518b11a0..c59a5d1fe1 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch @@ -719,7 +719,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -3575,7 +3575,7 @@ static int stmmac_request_irq_multi_msi( +@@ -3576,7 +3576,7 @@ static int stmmac_request_irq_multi_msi( sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); ret = request_irq(priv->rx_irq[i], stmmac_msi_intr_rx, @@ -728,7 +728,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(ret < 0)) { netdev_err(priv->dev, "%s: alloc rx-%d MSI %d (error: %d)\n", -@@ -3598,7 +3598,7 @@ static int stmmac_request_irq_multi_msi( +@@ -3599,7 +3599,7 @@ static int stmmac_request_irq_multi_msi( sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); ret = request_irq(priv->tx_irq[i], stmmac_msi_intr_tx, @@ -737,7 +737,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(ret < 0)) { netdev_err(priv->dev, "%s: alloc tx-%d MSI %d (error: %d)\n", -@@ -3729,21 +3729,21 @@ static int stmmac_open(struct net_device +@@ -3730,21 +3730,21 @@ static int stmmac_open(struct net_device bfsize = 0; if (bfsize < BUF_SIZE_16KiB) @@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; /* Setup per-TXQ tbs flag before TX descriptor alloc */ -@@ -3801,7 +3801,7 @@ irq_error: +@@ -3802,7 +3802,7 @@ irq_error: phylink_stop(priv->phylink); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -3843,7 +3843,7 @@ static int stmmac_release(struct net_dev +@@ -3844,7 +3844,7 @@ static int stmmac_release(struct net_dev stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski netif_tx_disable(dev); -@@ -3907,7 +3907,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3908,7 +3908,7 @@ static bool stmmac_vlan_insert(struct st return false; stmmac_set_tx_owner(priv, p); @@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski return true; } -@@ -3925,7 +3925,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3926,7 +3926,7 @@ static bool stmmac_vlan_insert(struct st static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, int total_len, bool last_segment, u32 queue) { @@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *desc; u32 buff_size; int tmp_len; -@@ -3936,7 +3936,7 @@ static void stmmac_tso_allocator(struct +@@ -3937,7 +3937,7 @@ static void stmmac_tso_allocator(struct dma_addr_t curr_addr; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); if (tx_q->tbs & STMMAC_TBS_AVAIL) -@@ -3964,7 +3964,7 @@ static void stmmac_tso_allocator(struct +@@ -3965,7 +3965,7 @@ static void stmmac_tso_allocator(struct static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) { @@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski int desc_size; if (likely(priv->extend_desc)) -@@ -4026,7 +4026,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4027,7 +4027,7 @@ static netdev_tx_t stmmac_tso_xmit(struc dma_addr_t des; int i; @@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; /* Compute header lengths */ -@@ -4066,7 +4066,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4067,7 +4067,7 @@ static netdev_tx_t stmmac_tso_xmit(struc stmmac_set_mss(priv, mss_desc, mss); tx_q->mss = mss; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); } -@@ -4178,7 +4178,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4179,7 +4179,7 @@ static netdev_tx_t stmmac_tso_xmit(struc * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", -@@ -4266,7 +4266,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4267,7 +4267,7 @@ static netdev_tx_t stmmac_xmit(struct sk int entry, first_tx; dma_addr_t des; @@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) -@@ -4329,7 +4329,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4330,7 +4330,7 @@ static netdev_tx_t stmmac_xmit(struct sk int len = skb_frag_size(frag); bool last_segment = (i == (nfrags - 1)); @@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[entry]); if (likely(priv->extend_desc)) -@@ -4400,7 +4400,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4401,7 +4401,7 @@ static netdev_tx_t stmmac_xmit(struct sk * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; if (netif_msg_pktdata(priv)) { -@@ -4512,7 +4512,7 @@ static void stmmac_rx_vlan(struct net_de +@@ -4513,7 +4513,7 @@ static void stmmac_rx_vlan(struct net_de */ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) { @@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski int dirty = stmmac_rx_dirty(priv, queue); unsigned int entry = rx_q->dirty_rx; -@@ -4562,7 +4562,7 @@ static inline void stmmac_rx_refill(stru +@@ -4563,7 +4563,7 @@ static inline void stmmac_rx_refill(stru dma_wmb(); stmmac_set_rx_owner(priv, p, use_rx_wd); @@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski } rx_q->dirty_rx = entry; rx_q->rx_tail_addr = rx_q->dma_rx_phy + -@@ -4590,12 +4590,12 @@ static unsigned int stmmac_rx_buf1_len(s +@@ -4591,12 +4591,12 @@ static unsigned int stmmac_rx_buf1_len(s /* First descriptor, not last descriptor and not split header */ if (status & rx_not_ls) @@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski } static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, -@@ -4611,7 +4611,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4612,7 +4612,7 @@ static unsigned int stmmac_rx_buf2_len(s /* Not last descriptor */ if (status & rx_not_ls) @@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski plen = stmmac_get_rx_frame_len(priv, p, coe); -@@ -4622,7 +4622,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4623,7 +4623,7 @@ static unsigned int stmmac_rx_buf2_len(s static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, struct xdp_frame *xdpf, bool dma_map) { @@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; -@@ -4685,7 +4685,7 @@ static int stmmac_xdp_xmit_xdpf(struct s +@@ -4686,7 +4686,7 @@ static int stmmac_xdp_xmit_xdpf(struct s stmmac_enable_dma_transmission(priv, priv->ioaddr); @@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; return STMMAC_XDP_TX; -@@ -4859,7 +4859,7 @@ static void stmmac_dispatch_skb_zc(struc +@@ -4860,7 +4860,7 @@ static void stmmac_dispatch_skb_zc(struc static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) { @@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = rx_q->dirty_rx; struct dma_desc *rx_desc = NULL; bool ret = true; -@@ -4902,7 +4902,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4903,7 +4903,7 @@ static bool stmmac_rx_refill_zc(struct s dma_wmb(); stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); @@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski } if (rx_desc) { -@@ -4917,7 +4917,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4918,7 +4918,7 @@ static bool stmmac_rx_refill_zc(struct s static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) { @@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski unsigned int count = 0, error = 0, len = 0; int dirty = stmmac_rx_dirty(priv, queue); unsigned int next_entry = rx_q->cur_rx; -@@ -4939,7 +4939,7 @@ static int stmmac_rx_zc(struct stmmac_pr +@@ -4940,7 +4940,7 @@ static int stmmac_rx_zc(struct stmmac_pr desc_size = sizeof(struct dma_desc); } @@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -4986,7 +4986,7 @@ read_again: +@@ -4987,7 +4987,7 @@ read_again: /* Prefetch the next RX descriptor */ rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5107,7 +5107,7 @@ read_again: +@@ -5108,7 +5108,7 @@ read_again: */ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) { @@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned int count = 0, error = 0, len = 0; int status = 0, coe = priv->hw->rx_csum; -@@ -5120,7 +5120,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5121,7 +5121,7 @@ static int stmmac_rx(struct stmmac_priv int buf_sz; dma_dir = page_pool_get_dma_dir(rx_q->page_pool); @@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski if (netif_msg_rx_status(priv)) { void *rx_head; -@@ -5134,7 +5134,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5135,7 +5135,7 @@ static int stmmac_rx(struct stmmac_priv desc_size = sizeof(struct dma_desc); } @@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -5178,7 +5178,7 @@ read_again: +@@ -5179,7 +5179,7 @@ read_again: break; rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5312,7 +5312,7 @@ read_again: +@@ -5313,7 +5313,7 @@ read_again: buf1_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->page, buf->page_offset, buf1_len, @@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->page); -@@ -5324,7 +5324,7 @@ read_again: +@@ -5325,7 +5325,7 @@ read_again: buf2_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->sec_page, 0, buf2_len, @@ -1033,7 +1033,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->sec_page); -@@ -5767,11 +5767,13 @@ static irqreturn_t stmmac_safety_interru +@@ -5768,11 +5768,13 @@ static irqreturn_t stmmac_safety_interru static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) { struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; @@ -1048,7 +1048,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5811,10 +5813,12 @@ static irqreturn_t stmmac_msi_intr_tx(in +@@ -5812,10 +5814,12 @@ static irqreturn_t stmmac_msi_intr_tx(in static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) { struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; @@ -1062,7 +1062,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5845,10 +5849,10 @@ static void stmmac_poll_controller(struc +@@ -5846,10 +5850,10 @@ static void stmmac_poll_controller(struc if (priv->plat->multi_msi_en) { for (i = 0; i < priv->plat->rx_queues_to_use; i++) @@ -1075,7 +1075,7 @@ Signed-off-by: Jakub Kicinski } else { disable_irq(dev->irq); stmmac_interrupt(dev->irq, dev); -@@ -6029,34 +6033,34 @@ static int stmmac_rings_status_show(stru +@@ -6030,34 +6034,34 @@ static int stmmac_rings_status_show(stru return 0; for (queue = 0; queue < rx_count; queue++) { @@ -1116,7 +1116,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -6403,7 +6407,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6404,7 +6408,7 @@ void stmmac_disable_rx_queue(struct stmm void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1125,7 +1125,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; u32 buf_size; -@@ -6440,7 +6444,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6441,7 +6445,7 @@ void stmmac_enable_rx_queue(struct stmma rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1134,7 +1134,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6466,7 +6470,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6467,7 +6471,7 @@ void stmmac_disable_tx_queue(struct stmm void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1143,7 +1143,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; int ret; -@@ -6516,7 +6520,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6517,7 +6521,7 @@ void stmmac_xdp_release(struct net_devic stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1152,7 +1152,7 @@ Signed-off-by: Jakub Kicinski /* Free the IRQ lines */ stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); -@@ -6575,7 +6579,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6576,7 +6580,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA RX Channel Configuration */ for (chan = 0; chan < rx_cnt; chan++) { @@ -1161,7 +1161,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, chan); -@@ -6593,7 +6597,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6594,7 +6598,7 @@ int stmmac_xdp_open(struct net_device *d rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1170,7 +1170,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6602,7 +6606,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6603,7 +6607,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA TX Channel Configuration */ for (chan = 0; chan < tx_cnt; chan++) { @@ -1179,7 +1179,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -6635,7 +6639,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6636,7 +6640,7 @@ int stmmac_xdp_open(struct net_device *d irq_error: for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1188,7 +1188,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -6662,8 +6666,8 @@ int stmmac_xsk_wakeup(struct net_device +@@ -6663,8 +6667,8 @@ int stmmac_xsk_wakeup(struct net_device queue >= priv->plat->tx_queues_to_use) return -EINVAL; @@ -1199,7 +1199,7 @@ Signed-off-by: Jakub Kicinski ch = &priv->channel[queue]; if (!rx_q->xsk_pool && !tx_q->xsk_pool) -@@ -6923,8 +6927,8 @@ int stmmac_reinit_ringparam(struct net_d +@@ -6924,8 +6928,8 @@ int stmmac_reinit_ringparam(struct net_d if (netif_running(dev)) stmmac_release(dev); @@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski if (netif_running(dev)) ret = stmmac_open(dev); -@@ -7359,7 +7363,7 @@ int stmmac_suspend(struct device *dev) +@@ -7360,7 +7364,7 @@ int stmmac_suspend(struct device *dev) stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski if (priv->eee_enabled) { priv->tx_path_in_lpi_mode = false; -@@ -7411,7 +7415,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); +@@ -7412,7 +7416,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski rx_q->cur_rx = 0; rx_q->dirty_rx = 0; -@@ -7419,7 +7423,7 @@ static void stmmac_reset_rx_queue(struct +@@ -7420,7 +7424,7 @@ static void stmmac_reset_rx_queue(struct static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) { diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch index 7336456c0c..bdf8b8585e 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch @@ -860,7 +860,7 @@ Signed-off-by: Jakub Kicinski stmmac_reset_tx_queue(priv, chan); stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -3685,19 +3748,93 @@ static int stmmac_request_irq(struct net +@@ -3686,19 +3749,93 @@ static int stmmac_request_irq(struct net } /** @@ -957,7 +957,7 @@ Signed-off-by: Jakub Kicinski u32 chan; int ret; -@@ -3724,45 +3861,10 @@ static int stmmac_open(struct net_device +@@ -3725,45 +3862,10 @@ static int stmmac_open(struct net_device memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); priv->xstats.threshold = tc; @@ -1005,7 +1005,7 @@ Signed-off-by: Jakub Kicinski if (priv->plat->serdes_powerup) { ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); -@@ -3805,14 +3907,28 @@ irq_error: +@@ -3806,14 +3908,28 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) { set_bit(__FPE_REMOVING, &priv->fpe_task_state); -@@ -3859,7 +3975,7 @@ static int stmmac_release(struct net_dev +@@ -3860,7 +3976,7 @@ static int stmmac_release(struct net_dev stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1045,7 +1045,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6402,7 +6518,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6403,7 +6519,7 @@ void stmmac_disable_rx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_rx_dma(priv, queue); @@ -1054,7 +1054,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6413,21 +6529,21 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6414,21 +6530,21 @@ void stmmac_enable_rx_queue(struct stmma u32 buf_size; int ret; @@ -1080,7 +1080,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, rx_q->queue_index); -@@ -6465,7 +6581,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6466,7 +6582,7 @@ void stmmac_disable_tx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_tx_dma(priv, queue); @@ -1089,7 +1089,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6475,21 +6591,21 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6476,21 +6592,21 @@ void stmmac_enable_tx_queue(struct stmma unsigned long flags; int ret; @@ -1115,7 +1115,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, tx_q->queue_index); -@@ -6529,7 +6645,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6530,7 +6646,7 @@ void stmmac_xdp_release(struct net_devic stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1124,7 +1124,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6554,14 +6670,14 @@ int stmmac_xdp_open(struct net_device *d +@@ -6555,14 +6671,14 @@ int stmmac_xdp_open(struct net_device *d u32 chan; int ret; @@ -1141,7 +1141,7 @@ Signed-off-by: Jakub Kicinski if (ret < 0) { netdev_err(dev, "%s: DMA descriptors initialization failed\n", __func__); -@@ -6643,7 +6759,7 @@ irq_error: +@@ -6644,7 +6760,7 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski dma_desc_error: return ret; } -@@ -7506,7 +7622,7 @@ int stmmac_resume(struct device *dev) +@@ -7507,7 +7623,7 @@ int stmmac_resume(struct device *dev) stmmac_reset_queues_param(priv); stmmac_free_tx_skbufs(priv); diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch index 6ebb527726..2576df4522 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5624,18 +5624,15 @@ static int stmmac_change_mtu(struct net_ +@@ -5625,18 +5625,15 @@ static int stmmac_change_mtu(struct net_ { struct stmmac_priv *priv = netdev_priv(dev); int txfifosz = priv->plat->tx_fifo_size; @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); return -EINVAL; -@@ -5647,8 +5644,29 @@ static int stmmac_change_mtu(struct net_ +@@ -5648,8 +5645,29 @@ static int stmmac_change_mtu(struct net_ if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) return -EINVAL; diff --git a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch index b00cf57419..0ad89de560 100644 --- a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch +++ b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch @@ -128,7 +128,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc /** * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it -@@ -1684,47 +1612,6 @@ free: +@@ -1685,47 +1613,6 @@ free: EXPORT_SYMBOL(of_parse_phandle_with_args_map); /** @@ -200,7 +200,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc extern int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name); -@@ -864,18 +858,12 @@ static inline int of_property_read_strin +@@ -714,18 +708,12 @@ static inline int of_property_read_strin return -ENOSYS; } @@ -225,7 +225,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc { return -ENOSYS; } -@@ -889,13 +877,6 @@ static inline int of_parse_phandle_with_ +@@ -739,13 +727,6 @@ static inline int of_parse_phandle_with_ return -ENOSYS; } @@ -239,7 +239,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc static inline int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name) -@@ -1077,6 +1058,117 @@ static inline bool of_node_is_type(const +@@ -927,6 +908,117 @@ static inline bool of_node_is_type(const } /** diff --git a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch index 2b2a60e096..97f4c6981e 100644 --- a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch +++ b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch @@ -24,7 +24,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/include/linux/of.h +++ b/include/linux/of.h -@@ -1169,6 +1169,31 @@ static inline int of_parse_phandle_with_ +@@ -1019,6 +1019,31 @@ static inline int of_parse_phandle_with_ } /** diff --git a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch index a70c6f2eec..b4554b2eca 100644 --- a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch +++ b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch @@ -145,7 +145,7 @@ Signed-off-by: Greg Kroah-Hartman /* phandle iterator functions */ extern int of_phandle_iterator_init(struct of_phandle_iterator *it, const struct device_node *np, -@@ -885,6 +888,12 @@ static inline int of_count_phandle_with_ +@@ -735,6 +738,12 @@ static inline int of_count_phandle_with_ return -ENOSYS; } diff --git a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch index 06bc24ca6e..ad42039e11 100644 --- a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch +++ b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch @@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman /* phandle iterator functions */ extern int of_phandle_iterator_init(struct of_phandle_iterator *it, -@@ -893,6 +894,11 @@ static inline ssize_t of_modalias(const +@@ -743,6 +744,11 @@ static inline ssize_t of_modalias(const { return -ENODEV; } diff --git a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch index dd2b310d66..7f6bac37dd 100644 --- a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch +++ b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch @@ -48,7 +48,7 @@ Signed-off-by: Lee Jones --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA +@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA depends on I2C depends on MACH_ARMADA_38X || COMPILE_TEST depends on OF diff --git a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch deleted file mode 100644 index f1942e2037..0000000000 --- a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001 -From: "Alexandros C. Couloumbis" -Date: Fri, 7 Jul 2017 17:14:51 +0200 -Subject: hack: arch: powerpc: drop register save/restore library from modules - -Upstream GCC uses a libgcc function for saving/restoring registers. This -makes the code bigger, and upstream kernels need to carry that function -for every single kernel module. Our GCC is patched to avoid those -references, so we can drop the extra bloat for modules. - -lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec -Signed-off-by: Alexandros C. Couloumbis ---- - arch/powerpc/Makefile | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/powerpc/Makefile -+++ b/arch/powerpc/Makefile -@@ -44,19 +44,6 @@ machine-$(CONFIG_PPC64) += 64 - machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le - UTS_MACHINE := $(subst $(space),,$(machine-y)) - --# XXX This needs to be before we override LD below --ifdef CONFIG_PPC32 --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --else --ifeq ($(call ld-ifversion, -ge, 22500, y),y) --# Have the linker provide sfpr if possible. --# There is a corresponding test in arch/powerpc/lib/Makefile --KBUILD_LDFLAGS_MODULE += --save-restore-funcs --else --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --endif --endif -- - ifdef CONFIG_CPU_LITTLE_ENDIAN - KBUILD_CFLAGS += -mlittle-endian - KBUILD_LDFLAGS += -EL diff --git a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index d2ca7c7b53..892887c423 100644 --- a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -7736,7 +7736,7 @@ static int nft_register_flowtable_net_ho +@@ -7752,7 +7752,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch index ff48227210..b7311e042d 100644 --- a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch @@ -18,7 +18,7 @@ Acked-by: Pali Rohár --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c -@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru +@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index de64eda827..76ee2fc89a 100644 --- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau struct mtk_pcie_port; /** -@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci +@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci struct mtk_pcie_port *port, *tmp; int err, slot; diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch index d5c8a4e300..46e92a92f3 100644 --- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch +++ b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch @@ -458,7 +458,7 @@ Signed-off-by: Wolfram Sang adap->dev.parent = &pdev->dev; --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c -@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor +@@ -1247,7 +1247,7 @@ static int rk3x_i2c_probe(struct platfor /* use common interface to get I2C timing properties */ i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); @@ -469,7 +469,7 @@ Signed-off-by: Wolfram Sang i2c->adap.retries = 3; --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c -@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat +@@ -1078,7 +1078,7 @@ static int s3c24xx_i2c_probe(struct plat else s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); diff --git a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch index 9f7b4ef338..f8f1156e71 100644 --- a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch +++ b/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch @@ -5,7 +5,7 @@ --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -877,6 +877,16 @@ source "drivers/leds/blink/Kconfig" +@@ -878,6 +878,16 @@ source "drivers/leds/blink/Kconfig" comment "Flash and Torch LED drivers" source "drivers/leds/flash/Kconfig" diff --git a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch index a3fc731c47..8192d1998b 100644 --- a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch +++ b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch @@ -30,7 +30,7 @@ Cc: Robert Marko --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -306,6 +306,14 @@ config LEDS_IPAQ_MICRO +@@ -307,6 +307,14 @@ config LEDS_IPAQ_MICRO Choose this option if you want to use the notification LED on Compaq/HP iPAQ h3100 and h3600. diff --git a/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch b/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch index 0400d1e9dd..6dd02bed54 100644 --- a/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch +++ b/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch @@ -22,7 +22,7 @@ Signed-off-by: Tim Harvey #include #include #include -@@ -5879,3 +5880,34 @@ static void nvidia_ion_ahci_fixup(struct +@@ -5883,3 +5884,34 @@ static void nvidia_ion_ahci_fixup(struct pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); diff --git a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch index 2896002ed1..9a0dbd7bb8 100644 --- a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch @@ -25,7 +25,7 @@ Signed-off-by: John Crispin --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig -@@ -1093,3 +1093,5 @@ config MMC_OWL +@@ -1095,3 +1095,5 @@ config MMC_OWL config MMC_SDHCI_EXTERNAL_DMA bool