Hardware specification:
SoC: MediaTek MT7981B 2x A53
Flash: 64GB eMMC or 128 MB SPI-NAND
RAM: 512MB DDR3 or DDR4
Ethernet: 4x 10/100/1000 Mbps
Switch: MediaTek MT7531AE
WiFi: MediaTek MT7976C
Button: Reset, Mesh
Power: DC 12V 1A
Gain SSH access:
1. Login into web interface, and download the configuration.
2. Get the SN of the device from web interface or the label on the back of the device.
3. Calculate configuration decryption password:
Command "eval" is necessary here as the encryption implentation treats '$...' as (empty) variables.
decpwd="$(eval echo $(openssl passwd -1 -salt aV6dW8bD "your_device_sn"))"
4. Decrypt the configuration:
openssl aes-256-cbc -d -pbkdf2 -k "$decpwd" -in cfg_export_config_file.conf -out cfg_export_config_file.conf.dec
5. Enter fakeroot, decompress the configuration:
tar -zxf cfg_export_config_file.conf.dec
6. Edit 'etc/shadow', update (remove) root password: 'root::19179:0:99999:7:::'
7. Edit 'etc/rc.local', insert telnetd command before 'exit 0':
( sleep 3s; telnetd; ) &
8. Repack the configuration:
tar -zc etc/ | openssl aes-256-cbc -pbkdf2 -k "$decpwd" -out cfg_export_config_file.conf
* If you find an error about 'etc/wireless/mediatek/DBDC_card0.dat',
just ignore it.
9. Upload new configuration via web interface, now you can connect to
CMCC RAX3000Me via telnet.
(Big thanks to https://github.com/lyq1996 who reverse engineered the encryption method)
Check flash type:
If '/dev/mmcblk0' exists on the device, it's eMMC version.
If '/dev/mtd0' exists on the device, it's NAND version.
eMMC Flash instructions:
1. Connect to RAX3000Me, and backup everything, especially 'factory' part.
('data' partition can be ignored, it's useless.)
2. Write new GPT table:
dd if=immortalwrt-mediatek-filogic-cmcc_rax3000me-emmc-gpt.bin of=/dev/mmcblk0 bs=512 seek=0 count=34 conv=fsync
3. Write new BL2:
echo 0 > /sys/block/mmcblk0boot0/force_ro
dd if=immortalwrt-mediatek-filogic-cmcc_rax3000me-emmc-preloader.bin of=/dev/mmcblk0boot0 bs=512 conv=fsync
4. Write new FIP:
dd if=immortalwrt-mediatek-filogic-cmcc_rax3000me-emmc-bl31-uboot.fip of=/dev/mmcblk0 bs=512 seek=13312 conv=fsync
5. Set static IP on your PC:
IP 192.168.1.254/24, GW 192.168.1.1
6. Serve ImmortalWrt initramfs image using TFTP server.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After ImmortalWrt has booted, perform sysupgrade.
NAND Flash instructions:
1. Connect to RAX3000Me, and backup everything, especially 'Factory' part.
2. Write new BL2 and FIP:
If your device HAS USB port, run:
mtd write immortalwrt-mediatek-filogic-cmcc_rax3000me-nand-ddr3-preloader.bin BL2
mtd write immortalwrt-mediatek-filogic-cmcc_rax3000me-nand-ddr3-bl31-uboot.fip FIP
If your device DOES NOT have USB port, run:
mtd write immortalwrt-mediatek-filogic-cmcc_rax3000me-nand-ddr4-preloader.bin BL2
mtd write immortalwrt-mediatek-filogic-cmcc_rax3000me-nand-ddr4-bl31-uboot.fip FIP
4. Set static IP on your PC:
IP 192.168.1.254/24, GW 192.168.1.1
5. Serve ImmortalWrt initramfs image using TFTP server.
6. Cut off the power and re-engage, wait for TFTP recovery to complete.
7. After ImmortalWrt has booted, perform sysupgrade.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 57f31cd5b11cb7e590c330845ec74ffa2d6eb13e)
I selected one subtarget after the other and refreshed their
configuration using this command:
make kernel_oldconfig CONFIG_TARGET=subtarget
For MT7629 I had to re-add CONFIG_LEDS_SMARTRG_LED manually.
Otherwise, building MT7629 with ALL_KMODS we get prompted for
LEDS_SMARTRG_LED and this will break CI and in future buildbot
compilation. See commit 6bdea8c7bd ("mediatek: mt7629: 6.6: disable
LEDS_SMARTRG_LED by default") for more details.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Link: https://github.com/openwrt/openwrt/pull/18182
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 5013efc4f907550fadbf15e2fb1bdb2ead3325db)
Prior to commit 8a7d12d674,
cdc-ethernet USB LTE modems (e.g. Quectel EC200A) were consistently named
usb0. After 8a7d12d67, devices began renaming to eth1 due to an assumption
that local MAC addresses originate exclusively from the kernel. Some
devices provide driver-assigned local MACs, causing point-to-point
interfaces with driver-set MACs to adopt eth%d names instead of usb%d.
Restore the naming exception for point-to-point devices: interfaces
without driver MACs or with driver-provided local MACs will retain the
usb%d convention. This addresses issues reported in [1] and fixed in [2].
[1] https://lore.kernel.org/all/Z00udyMgW6XnAw6h@atmark-techno.com/
[2] https://lore.kernel.org/all/20241203130457.904325-1-asmadeus@codewreck.org/
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17757
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit ecd609f509f29ed1f75db5c7a623f359c64efb72)
kmod-mmc-mtk does not work well on this board, switch back to deprecated
kmod-sdhci-mt7620 driver for now.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Specification:
* Mediatek MT7981BA
* 256 MB SPI-NAND
* 512 MB DDR4 RAM
* MT7976CN DBDC AX Wi-Fi
* MediaTek MT7531AE (3x LAN Gigabit ports) + Internal Gbe Phy (1x WAN Gigabit port)
* 4x LED (power, internet, fn, wifi)
* 3x buttons (wps, fn, reset)
* 1x USB 3.0 port
Serial Interface:
* 3 Pins GND, RX, TX
* Settings: 115200, 8N1
Notes:
* The device supports dual boot mode
* Fn led reassigned to wlan 2.4
Flash instruction:
The only way to flash OpenWrt image is to use tftp recovery mode in U-Boot:
1. Configure PC with static IP 192.168.1.2/24 and tftp server.
2. Rename "openwrt-mediatek-filogic-keenetic_kn-3811-squashfs-factory.bin"
to "KN-3811_recovery.bin" and place it in tftp server directory.
3. Connect PC with ethernet port, press the reset button, power up
the device and keep button pressed until status led start blinking.
4. Device will download file from server, write it to flash and reboot.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17135
(cherry picked from commit d087a79b7b)
Link: https://github.com/openwrt/openwrt/pull/18055
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specification:
- MT7981 CPU using 2.4GHz and 5GHz WiFi (both AX)
- 512MB RAM
- 128MB SPI NAND
- 2 LEDs (green, orange)
- 3 buttons (fn, reset, wps)
- 2 2.5Gbit ethernet ports based on Airoha EN8811H phy
Serial Interface:
- 3 Pins GND, RX, TX
- Settings: 115200, 8N1
Notes:
- The device supports dual boot mode
Flash instruction:
The only way to flash OpenWrt image is to use tftp recovery mode in U-Boot:
1. Configure PC with static IP 192.168.1.2/24 and tftp server.
2. Rename "openwrt-mediatek-filogic-keenetic_kn-3911-squashfs-factory.bin"
to "KN-3911_recovery.bin" and place it in tftp server directory.
3. Connect PC with ethernet port, press the reset button, power up
the device and keep button pressed until status led start blinking.
4. Device will download file from server, write it to flash and reboot.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16830
(cherry picked from commit 5a4eb56a7b)
Link: https://github.com/openwrt/openwrt/pull/18055
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
cmcc_a10-ubootmod stands for custom U-Boot layout in ImmortalWrt 23.05,
add compat version to avoid bricking devices. For 24.10+ users you can
just ignore the compat warning.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 4b000293b2)
This board is also as known as SuperElectron ZN-M5 and ZN-M8. However,
for ZN-M5 and ZN-M8, there's another version uses ZX279128 as CPU
chip, which is unsupported.
You can check it in "高级设置" > "系统日志" > "内核日志" page from webUI.
Stock layout flash instructions:
Login into webUI and upload sysupgrade firmware in "系统管理" > "升级固件" page.
Remember to unselect "保留配置" ("Keep configurations") first before doing that.
OpenWrt U-Boot layout flash instructions:
1. Flash stock layout firmware first.
2. Connect to the device via SSH, and backup everything,
especially 'Factory' partition.
3. Unlock MTD partitions:
apk update && apk add kmod-mtd-rw
insmod mtd-rw i_want_a_brick=1
4. Write new BL2 and FIP:
mtd write immortalwrt-mediatek-filogic-cmcc_a10-ubootmod-preloader.bin BL2
mtd write immortalwrt-mediatek-filogic-cmcc_a10-ubootmod-bl31-uboot.fip FIP
5. Set static IP on your PC:
IP 192.168.1.254/24, GW 192.168.1.1
6. Serve ImmortalWrt initramfs image using TFTP server.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After ImmortalWrt has booted, perform sysupgrade.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 4e9240e733)
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 890293c13c)
The JG928A has an RTL8231 on the aux mdio bus. Add it to dts to expose
the GPIO pins used to control and monitor the fan speed. To enable speed
control, add the appropriate kernel driver module to DEVICE_PACKAGES.
Of note, this does not control all fans for the unit. The power supply
fans are not controlled.
Signed-off-by: Evan Jobling <evan@jobling.au>
Link: https://github.com/openwrt/openwrt/pull/17699
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit cbd1acbad3)
The old RTL8231 driver integrated the MDIO bus access with the GPIO
control ops, making this driver not very portable to newer platforms.
It depended on the SoC ID instead of the compatible to determine the
MDIO access register, further complicating portability.
A new MFD driver is now available, which offers proper pin config as
well as optional LED support, which can work on any (bitbanged) MDIO
bus. Now that all devices have been migrated, we can drop the old code.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit b410f2216c)
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 807074309d)
Update the common external GPIO DTSI file for the DGS-1210 devices to
use an MDIO device on the auxilairy MDIO bus, as the original driver was
doing behind the screen.
Switching to the new driver will allow for full pin-control and will no
longer reset pin config set by the bootloader.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 3d6a1a7874)
The DTS file for the DGS-1210-10P is slightly different from the other
DGS-1210 devices, in that it didn't specify a gpio-restart node when it
was added. The gpio-restart has been found to work on the DGS-1210-10P
as well, so switch it over to the common definitions.
This converts the last device from the product family to the common
definition for the (external) GPIOs.
Tested-by: Michel Thill <jmthill@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 7c0d1c1eb1)
The 'indirect-access-id' property on gpio0 is a remnant from the
original GPIO driver. This property has not been relevant on the SoC's
embedded GPIO controller for a long time, so just drop it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 022b7d80bf)
Change devices with RTL8231 GPIO expander definition that can easily be
translated to the new RTL8231 binding and carry over any gpio-hogs. This
will let them use the new RTL8231 MFD driver, without any functional
changes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit b7af54d5c1)
Zyxel GS1900-8 v2 devices have been produced more recently than v1
devices. As there are v1 boards with RTL8380M rev. C SoCs, it can likely
safely be assumed that all v2 devices will also have a recent SoC
revision, supporting the hardware auxiliary MDIO controller.
Make the GS1900-8 v1 use an emulated auxiliary MDIO bus, for backward
compatibility with devices containing an RTL8380M rev. A.
Since the devicetrees are otherwise identical, GS1900-8 v1 devices with
an RTL8380M rev. B or C will also be able to use the (more efficient) v2
image. This includes any currently functioning device with OpenWrt, so
include the old compatible as a supported device for the GS1900-8 v2.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 7322d3266d)
The mdio-gpio driver is required to support early revision of RTL8380M
slicon (rev A) where the auxilairy MDIO controller does not function
correctly. Add this driver to the rtl838x kernel so devices with old
SoCs are also able to function correctly.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit efffcfa436)
In order to be able to define the external GPIO controller on an
emulated MDIO bus, move the controller definition outside of the main
GS1900 include for RTL838x-based devices.
Additionally, a new DTSI is provided defining the RTL8231 on the
emulated MDIO bus.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit a6a77896f4)
Some RTL8380M-based devices have been around for a long time and use an
early A revision of the RTL8380M SoC. This revision has an issue with
the auxiliary MDIO controller, causing it to malfunction. This may lead
to device reboots when the controller is used.
Provide a bit-banged MDIO bus, which muxes the auxiliary MDIO pins to
their GPIO function. Although this will result in lower performance,
there should otherwise be no functional differences.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit d4bf16a9e1)
As the bootloader is reconfiguring the RTL8231 on these devices anyway,
no pin state can be maintained over warm reboots. This results in for
example the PoE disable pin always being asserted by the bootloader.
Define the GPIO line linked to the RTL8231's reset so the MDIO subsystem
will also reset the expander on boot and ensure the line in the correct
state.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit b2d17dbb68)
Switch the Zyxel GS1900-48 over to the new MDIO-based driver for the
RTL8231 GPIO expander.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 45aafe67f3)
Enable the RTL8231 MFD core driver, as well as the pinctrl/gpio driver
to allow RTL839x devices to use it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit fd5797b7ce)
Enable the driver for the Realtek Otto auxiliary MDIO driver so RTL839x
devices can use it. The related node is added to the base devicetree for
rtl839x-based devices, so they can enabled and use it when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit cddcc69ddf)
For RTL839x, the driver was producing frequent timeouts on bus accesses.
Increasing the timeout to the one from a recent Realtek SDK resolves
these timeouts. To minimize overhead on different SoCs, each controller
can specify their own timeout.
This also add support for the register format as used on RTL93xx.
Support is added for the RTL930x "ext gpio" controller.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 52ffef6471)
regmap_read_poll_timeout() relies on usleep_range() to time the polling
loop. With the current, rather large, scheduling interval, a short
usleep_range() may take a lot longer than expected, causing performance
issues.
Switch the driver over to using regmap_read_poll_timeout_atomic(), which
uses udelay() to time the polling loop.
For comparision, the 'ethtool -m <dev>' command is about 10 times faster
with the atomic variant.
Using 'perf -r10 ethtool -m lan25':
- Driver using regmap_read_poll_timeout():
2.0117 +- 0.0118 seconds time elapsed ( +- 0.58% )
- Driver using regmap_read_poll_timeout_atomic():
0.1674 +- 0.0250 seconds time elapsed ( +- 14.95% )
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 693c1ea81a)
Apply the equivalent of commit f64541db02 ("realtek: HPE 1920 8G PoE+
180W move fans to hwmon") to the 24-ports variants of the HPE 1920 PoE+
switches, with model numbers JG925A and JG926A.
Copy from the original commit message:
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
As the init script 03_gpio_switches does not perform any action after
removing these devices from it, the file can be dropped.
Link: https://github.com/openwrt/openwrt/pull/17598
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 0a7c8ed9d9)
Update the base DTS file for the 16 and 24 port HPE 1920 devices
(JG923A, JG924A, JG925A, JG926A), causing the new RTL8231 MFD driver to
be loaded at start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 96850585e5)
