b06f37e92d
This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: maurerr <mariusd84@gmail.com>
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* The cache manipulation routine has been taken from the U-Boot project.
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*/
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#include "cache.h"
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#include "cacheops.h"
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#include "config.h"
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#include "printf.h"
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void flush_cache(unsigned long start_addr, unsigned long size)
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{
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unsigned long lsize = CONFIG_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size + (lsize - 1)) & ~(lsize - 1);
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printf("blasting from 0x%08x to 0x%08x (0x%08x - 0x%08x)\n", start_addr, size, addr, aend);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Invalidate_I, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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