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kernel: bump 6.1 to 6.1.73

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This commit is contained in:
DHDAXCW
2024-02-19 19:04:59 +08:00
parent c656dbd449
commit 7c42d66e8a
138 changed files with 5379 additions and 14406 deletions
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4
include/kernel-6.1
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@@ -1,2 +1,2 @@
LINUX_VERSION-6.1 = .73
LINUX_KERNEL_HASH-6.1.73 = 6cad48706bf1cde342613dca2a2cd6dd4f79f88f9e4d356263564e4b2a5d7e87
LINUX_VERSION-6.1 = .78
LINUX_KERNEL_HASH-6.1.78 = 65206b969831236849c9906eba267e715734a93808e9909fd9b4f12eea10d689

4
include/kernel-6.6
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@@ -1,2 +1,2 @@
LINUX_VERSION-6.6 = .10
LINUX_KERNEL_HASH-6.6.10 = 9ee627e4c109aec7fca3eda5898e81d201af2c7eb2f7d9d7d94c1f0e1205546c
LINUX_VERSION-6.6 = .17
LINUX_KERNEL_HASH-6.6.17 = ee7650996ba75aa29fe66f309b413097f249a03e7001f2a41128c7c95205226a

91
package/boot/arm-trusted-firmware-rockchip-vendor/Makefile
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@@ -1,91 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 ImmortalWrt.org
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-rockchip-vendor
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
PKG_SOURCE_DATE:=2022-08-01
PKG_SOURCE_VERSION:=b0c100f1a260d807df450019774993c761beb79d
PKG_MIRROR_HASH:=0a6887af6edaecc0b9798612a0126c6ab470503f9b8841449e9543bd5a8a055e
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
MAKE_PATH:=$(PKG_NAME)
include $(INCLUDE_DIR)/package.mk
define Package/arm-trusted-firmware-rockchip-vendor
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:=ARM Trusted Firmware for Rockchip
endef
define Package/arm-trusted-firmware-rk3328
$(Package/arm-trusted-firmware-rockchip-vendor)
DEPENDS:=@TARGET_rockchip_armv8
VARIANT:=rk3328
endef
define Package/arm-trusted-firmware-rk3399
$(Package/arm-trusted-firmware-rockchip-vendor)
DEPENDS:=@TARGET_rockchip_armv8
VARIANT:=rk3399
endef
define Package/arm-trusted-firmware-rk3566
$(Package/arm-trusted-firmware-rockchip-vendor)
DEPENDS:=@TARGET_rockchip_armv8
VARIANT:=rk3566
endef
define Package/arm-trusted-firmware-rk3568
$(Package/arm-trusted-firmware-rockchip-vendor)
DEPENDS:=@TARGET_rockchip_armv8
VARIANT:=rk3568
endef
define Package/arm-trusted-firmware-rk3588
$(Package/arm-trusted-firmware-rockchip-vendor)
DEPENDS:=@TARGET_rockchip_armv8
VARIANT:=rk3588
endef
define Build/Configure
$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini
$(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini
$(call Build/Configure/Default)
endef
define Build/Compile
$(CURDIR)/pack-firmware.sh build $(BUILD_VARIANT) '$(PKG_BUILD_DIR)'
endef
define Build/InstallDev
$(CURDIR)/pack-firmware.sh install $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' '$(STAGING_DIR_IMAGE)'
endef
define Package/arm-trusted-firmware-rk3328/install
endef
define Package/arm-trusted-firmware-rk3399/install
endef
define Package/arm-trusted-firmware-rk3566/install
endef
define Package/arm-trusted-firmware-rk3568/install
endef
define Package/arm-trusted-firmware-rk3588/install
endef
$(eval $(call BuildPackage,arm-trusted-firmware-rk3328))
$(eval $(call BuildPackage,arm-trusted-firmware-rk3399))
$(eval $(call BuildPackage,arm-trusted-firmware-rk3566))
$(eval $(call BuildPackage,arm-trusted-firmware-rk3568))
$(eval $(call BuildPackage,arm-trusted-firmware-rk3588))

64
package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh
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@@ -1,64 +0,0 @@
#!/bin/bash
# Copyright (C) 2021 ImmortalWrt.org
ACTION="$1"
VARIANT="$2"
PKG_BUILD_DIR="$3"
STAGING_DIR_IMAGE="$4"
case "$VARIANT" in
"rk3328")
ATF="rk33/rk322xh_bl31_v1.49.elf"
DDR="rk33/rk3328_ddr_333MHz_v1.19.bin"
LOADER="rk33/rk322xh_miniloader_v2.50.bin"
;;
"rk3399")
ATF="rk33/rk3399_bl31_v1.35.elf"
DDR="rk33/rk3399_ddr_800MHz_v1.27.bin"
LOADER="rk33/rk3399_miniloader_v1.26.bin"
;;
"rk3566")
ATF="rk35/rk3568_bl31_v1.28.elf"
DDR="rk35/rk3566_ddr_1056MHz_v1.13.bin"
;;
"rk3568")
ATF="rk35/rk3568_bl31_v1.28.elf"
DDR="rk35/rk3568_ddr_1560MHz_v1.13.bin"
;;
"rk3588")
ATF="rk35/rk3588_bl31_v1.27.elf"
DDR="rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin"
;;
*)
echo -e "Not compatible with your platform: $VARIANT."
exit 1
;;
esac
set -x
if [ "$ACTION" == "build" ]; then
case "$VARIANT" in
rk33*)
"$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
"$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini"
;;
esac
elif [ "$ACTION" == "install" ]; then
mkdir -p "$STAGING_DIR_IMAGE"
cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/
case "$VARIANT" in
rk33*)
cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/
cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/
cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/
;;
rk35*)
cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/
;;
esac
else
echo -e "Unknown operation: $ACTION."
exit 1
fi
set +x

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package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3566_ddr_1056MHz_v1.13.bin
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package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf
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package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.38.elf
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package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3588_bl31_v1.27.elf
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package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin
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106
package/boot/arm-trusted-firmware-rockchip/Makefile
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@@ -1,49 +1,95 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# Copyright (C) 2021-2023 ImmortalWrt.org
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-rockchip
PKG_VERSION:=2.3
PKG_NAME:=rkbin
PKG_RELEASE:=1
PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?
PKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://gitlab.com/rk3588_linux/rk/rkbin.git
PKG_SOURCE_DATE:=2023-08-17
PKG_SOURCE_VERSION:=1a417bbf7d05c3491ee9613be12a9905fbb8ccb7
PKG_MIRROR_HASH:=8145efc2463baf4a5777f5f6ae3ecececb98f570dbdc090ad5a1412dda8b2e14
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=license.md
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
MAKE_PATH:=$(PKG_NAME)
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
include ./atf-version.mk
define Package/arm-trusted-firmware-rockchip
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:=ARM Trusted Firmware for Rockchip
DEPENDS:=@TARGET_rockchip_armv8
define Trusted-Firmware-A/Default
NAME:=Rockchip $(1) SoCs
BUILD_TARGET:=rockchip
endef
define Build/Prepare
$(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE)
define Trusted-Firmware-A/rk3328
BUILD_SUBTARGET:=armv8
ATF:=rk33/$(RK3328_ATF)
TPL:=rk33/$(RK3328_TPL)
LOADER:=rk33/$(RK3328_LOADER)
endef
define Trusted-Firmware-A/rk3399
BUILD_SUBTARGET:=armv8
ATF:=rk33/$(RK3399_ATF)
TPL:=rk33/$(RK3399_TPL)
LOADER:=rk33/$(RK3399_LOADER)
endef
define Trusted-Firmware-A/rk3566
BUILD_SUBTARGET:=armv8
ATF:=rk35/$(RK3566_ATF)
TPL:=rk35/$(RK3566_TPL)
endef
define Trusted-Firmware-A/rk3568
BUILD_SUBTARGET:=armv8
ATF:=rk35/$(RK3568_ATF)
TPL:=rk35/$(RK3568_TPL)
endef
define Trusted-Firmware-A/rk3588
BUILD_SUBTARGET:=armv8
ATF:=rk35/$(RK3588_ATF)
TPL:=rk35/$(RK3588_TPL)
endef
TFA_TARGETS:= \
rk3328 \
rk3399 \
rk3566 \
rk3568 \
rk3588
define Build/Compile
# This comment is the workaround for "extraneous 'endif'" error
ifneq ($(LOADER),)
( \
pushd $(PKG_BUILD_DIR) ; \
$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' trust.ini ; \
$(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' trust.ini ; \
./tools/mkimage -n $(BUILD_VARIANT) -T rksd -d bin/$(TPL) \
$(BUILD_VARIANT)-idbloader.bin ; \
cat bin/$(LOADER) >> $(BUILD_VARIANT)-idbloader.bin ; \
./tools/trust_merger --replace bl31.elf bin/$(ATF) trust.ini ; \
popd ; \
)
endif
endef
define Build/InstallDev
$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/
ifneq ($(LOADER),)
$(CP) $(PKG_BUILD_DIR)/tools/loaderimage $(STAGING_DIR_IMAGE)/
$(CP) $(PKG_BUILD_DIR)/$(BUILD_VARIANT)-idbloader.bin $(STAGING_DIR_IMAGE)/
$(CP) $(PKG_BUILD_DIR)/$(BUILD_VARIANT)-trust.bin $(STAGING_DIR_IMAGE)/
else
$(CP) $(PKG_BUILD_DIR)/bin/$(TPL) $(STAGING_DIR_IMAGE)/
endif
endef
define Package/arm-trusted-firmware-rockchip/install
endef
$(eval $(call BuildPackage,arm-trusted-firmware-rockchip))
$(eval $(call BuildPackage/Trusted-Firmware-A))

16
package/boot/arm-trusted-firmware-rockchip/atf-version.mk Normal file
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@@ -0,0 +1,16 @@
RK3328_ATF:=rk322xh_bl31_v1.49.elf
RK3328_TPL:=rk3328_ddr_333MHz_v1.19.bin
RK3328_LOADER:=rk322xh_miniloader_v2.50.bin
RK3399_ATF:=rk3399_bl31_v1.36.elf
RK3399_TPL:=rk3399_ddr_800MHz_v1.30.bin
RK3399_LOADER:=rk3399_miniloader_v1.30.bin
RK3566_ATF:=rk3568_bl31_v1.43.elf
RK3566_TPL:=rk3566_ddr_1056MHz_v1.18.bin
RK3568_ATF:=rk3568_bl31_v1.43.elf
RK3568_TPL:=rk3568_ddr_1560MHz_v1.18.bin
RK3588_ATF:=rk3588_bl31_v1.41.elf
RK3588_TPL:=rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.13.bin

0
package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini → package/boot/arm-trusted-firmware-rockchip/src/trust.ini
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270
package/boot/uboot-rockchip/Makefile
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@@ -5,15 +5,18 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2022.07
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e
PKG_VERSION:=2024.01
PKG_RELEASE:=1
PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
UBOOT_USE_BINMAN:=1
UBOOT_USE_INTREE_DTC:=1
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
include ../arm-trusted-firmware-rockchip/atf-version.mk
define U-Boot/Default
BUILD_TARGET:=rockchip
@@ -24,166 +27,188 @@ endef
# RK3328 boards
define U-Boot/nanopi-r2c-rk3328
define U-Boot/Default/rk3328
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328
ATF:=$(RK3328_ATF)
endef
define U-Boot/nanopi-r2c-rk3328
$(U-Boot/Default/rk3328)
NAME:=NanoPi R2C
BUILD_DEVICES:= \
friendlyarm_nanopi-r2c
DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk322xh_bl31_v1.49.elf
USE_RKBIN:=1
endef
define U-Boot/nanopi-r2s-rk3328
BUILD_SUBTARGET:=armv8
$(U-Boot/Default/rk3328)
NAME:=NanoPi R2S
BUILD_DEVICES:= \
friendlyarm_nanopi-r2s \
friendlyarm_nanopi-neo3
DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk322xh_bl31_v1.49.elf
USE_RKBIN:=1
friendlyarm_nanopi-r2s
endef
define U-Boot/doornet1-rk3328
BUILD_SUBTARGET:=armv8
$(U-Boot/Default/rk3328)
NAME:=DoorNet1
BUILD_DEVICES:= \
embedfire_doornet1
DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk322xh_bl31_v1.49.elf
USE_RKBIN:=1
endef
# RK3399 boards
define U-Boot/nanopi-r4s-rk3399
define U-Boot/Default/rk3399
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3399
ATF:=$(RK3399_ATF)
endef
define U-Boot/nanopi-r4s-rk3399
$(U-Boot/Default/rk3399)
NAME:=NanoPi R4S
BUILD_DEVICES:= \
friendlyarm_nanopi-r4s
DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rk3399
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3399_bl31_v1.35.elf
USE_RKBIN:=1
friendlyarm_nanopi-r4s \
friendlyarm_nanopi-r4s-enterprise
endef
define U-Boot/nanopi-r4se-rk3399
BUILD_SUBTARGET:=armv8
$(U-Boot/Default/rk3399)
NAME:=NanoPi R4SE
BUILD_DEVICES:= \
friendlyarm_nanopi-r4se
DEPENDS:=+PACKAGE_u-boot-nanopi-r4se-rk3399:arm-trusted-firmware-rk3399
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3399_bl31_v1.35.elf
USE_RKBIN:=1
endef
define U-Boot/doornet2-rk3399
BUILD_SUBTARGET:=armv8
$(U-Boot/Default/rk3399)
NAME:=DoorNet2
BUILD_DEVICES:= \
embedfire_doornet2
DEPENDS:=+PACKAGE_u-boot-doornet2-rk3399:arm-trusted-firmware-rk3399
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3399_bl31_v1.35.elf
endef
# RK3566 boards
define U-Boot/lubancat-1n-rk3566
define U-Boot/Default/rk3566
BUILD_SUBTARGET:=armv8
NAME:=LubanCan-1N
BUILD_DEVICES:= \
embedfire_lubancat-1n
DEPENDS:=+PACKAGE_u-boot-lubancat-1n-rk3566:arm-trusted-firmware-rk3566
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3566_ddr_1056MHz_v1.13.bin
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3566
ATF:=$(RK3566_ATF)
TPL:=$(RK3566_TPL)
endef
define U-Boot/lubancat-1-rk3566
BUILD_SUBTARGET:=armv8
NAME:=LubanCat-1
$(U-Boot/Default/rk3566)
NAME:=LubanCan-1N
BUILD_DEVICES:= \
embedfire_lubancat-1
DEPENDS:=+PACKAGE_u-boot-lubancat-1-rk3566:arm-trusted-firmware-rk3566
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3566_ddr_1056MHz_v1.13.bin
endef
define U-Boot/lubancat-1n-rk3566
$(U-Boot/Default/rk3566)
NAME:=LubanCan-1N
BUILD_DEVICES:= \
embedfire_lubancat-1n
endef
# RK3568 boards
define U-Boot/lubancat-2-rk3568
define U-Boot/Default/rk3568
BUILD_SUBTARGET:=armv8
NAME:=LubanCat-2
BUILD_DEVICES:= \
embedfire_lubancat-2
DEPENDS:=+PACKAGE_u-boot-lubancat-2-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
endef
define U-Boot/lubancat-2n-rk3568
BUILD_SUBTARGET:=armv8
NAME:=LubanCan-2N
BUILD_DEVICES:= \
embedfire_lubancat-2n
DEPENDS:=+PACKAGE_u-boot-lubancat-2n-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
endef
define U-Boot/nanopi-r5s-rk3568
BUILD_SUBTARGET:=armv8
NAME:=NanoPi R5S
BUILD_DEVICES:= \
friendlyarm_nanopi-r5s
DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568
ATF:=$(RK3568_ATF)
TPL:=$(RK3568_TPL)
endef
define U-Boot/nanopi-r5c-rk3568
BUILD_SUBTARGET:=armv8
$(U-Boot/Default/rk3568)
NAME:=NanoPi R5C
BUILD_DEVICES:= \
friendlyarm_nanopi-r5c
DEPENDS:=+PACKAGE_u-boot-nanopi-r5c-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
endef
define U-Boot/mrkaio-m68s-rk3568
BUILD_SUBTARGET:=armv8
NAME:=Mrkaio M68S
define U-Boot/nanopi-r5s-rk3568
$(U-Boot/Default/rk3568)
NAME:=NanoPi R5S
BUILD_DEVICES:= \
ezpro_mrkaio-m68s
DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
friendlyarm_nanopi-r5s
endef
define U-Boot/lubancat-2-rk3568
$(U-Boot/Default/rk3568)
NAME:=LubanCat-2
BUILD_DEVICES:= \
embedfire_lubancat-2
endef
define U-Boot/lubancat-2n-rk3568
$(U-Boot/Default/rk3568)
NAME:=LubanCat-2N
BUILD_DEVICES:= \
embedfire_lubancat-2n
endef
define U-Boot/opc-h66k-rk3568
$(U-Boot/Default/rk3568)
NAME:=OPC-H66K
BUILD_DEVICES:= \
hinlink_opc-h66k
endef
define U-Boot/opc-h68k-rk3568
BUILD_SUBTARGET:=armv8
NAME:=OPC-H68K Board
$(U-Boot/Default/rk3568)
NAME:=OPC-H68K
BUILD_DEVICES:= \
hinlink_opc-h68k
endef
define U-Boot/opc-h69k-rk3568
$(U-Boot/Default/rk3568)
NAME:=OPC-H69K
BUILD_DEVICES:= \
hinlink_opc-h66k \
hinlink_opc-h68k \
hinlink_opc-h69k
DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3568_bl31_v1.28.elf
DDR:=rk3568_ddr_1560MHz_v1.13.bin
endef
# RK3588 boards
define U-Boot/Default/rk3588
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3588
ATF:=$(RK3588_ATF)
TPL:=$(RK3588_TPL)
endef
define U-Boot/nanopc-t6-rk3588
$(U-Boot/Default/rk3588)
NAME:=NanoPC T6
BUILD_DEVICES:= \
friendlyarm_nanopc-t6
endef
define U-Boot/lubancat-5-rk3588
$(U-Boot/Default/rk3588)
NAME:=LubanCat-5
BUILD_DEVICES:= \
embedfire_lubancat-5
endef
# RK3588S boards
define U-Boot/nanopi-r6c-rk3588s
$(U-Boot/Default/rk3588)
NAME:=NanoPi R6C
BUILD_DEVICES:= \
friendlyarm_nanopi-r6c
endef
define U-Boot/nanopi-r6s-rk3588s
$(U-Boot/Default/rk3588)
NAME:=NanoPi R6S
BUILD_DEVICES:= \
friendlyarm_nanopi-r6s
endef
define U-Boot/lubancat-4-rk3588s
$(U-Boot/Default/rk3588)
NAME:=LubanCat-4
BUILD_DEVICES:= \
embedfire_lubancat-4
endef
UBOOT_TARGETS := \
@@ -194,43 +219,40 @@ UBOOT_TARGETS := \
nanopi-r4se-rk3399 \
doornet2-rk3399 \
nanopi-r5s-rk3568 \
nanopi-r5c-rk3568 \
nanopc-t6-rk3588 \
nanopi-r6s-rk3588s \
nanopi-r6c-rk3588s \
opc-h66k-rk3568 \
opc-h68k-rk3568 \
opc-h69k-rk3568 \
lubancat-1-rk3566 \
lubancat-2-rk3568 \
lubancat-1n-rk3566 \
lubancat-2n-rk3568 \
nanopi-r5c-rk3568
lubancat-4-rk3588s \
lubancat-5-rk3588
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_CUSTOMIZE_CONFIG := \
--disable SPL_FIT_SIGNATURE \
--disable TOOLS_MKEFICAPSULE \
--set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc
UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/$(ATF)
define Build/Configure
$(call Build/Configure/U-Boot)
$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
ifneq ($(DDR),)
$(CP) $(STAGING_DIR_IMAGE)/$(DDR) $(PKG_BUILD_DIR)/ram_init.bin
endif
endef
PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
BL31=$(STAGING_DIR_IMAGE)/$(ATF) \
$(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL))
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
ifneq ($(USE_RKBIN),)
$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000
$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img
else
ifneq ($(TPL),)
$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
endif
ifneq ($(OF_PRE_BUILD),)
$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/boot.scr $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-boot.scr
else
$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000
$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img
endif
endef

43
package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch
View File

@@ -1,43 +0,0 @@
From 9b92a43a4f5acf4cba14fd9d473b3120688532dc Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 19 Dec 2021 08:10:24 -0500
Subject: [PATCH 01/11] rockchip: rk3568: add boot device detection
Enable spl to detect which device it was booted from.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -23,6 +24,7 @@
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -43,6 +45,12 @@ enum {
UART2_IO_SEL_M0 = 0,
};
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
+ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
+};
+
static struct mm_region rk3568_mem_map[] = {
{
.virt = 0x0UL,

52
package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch
View File

@@ -1,52 +0,0 @@
From 09d877cf076cbb67c79054e12bbb7c63a91faa71 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 19 Dec 2021 08:11:56 -0500
Subject: [PATCH 02/11] rockchip: rk3568: enable automatic power savings
Enable automatic clock gating, solves the 7c temperature difference on
SoQuartz.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -25,6 +25,15 @@
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
+#define PMU_BASE_ADDR 0xfdd90000
+#define PMU_NOC_AUTO_CON0 (0x70)
+#define PMU_NOC_AUTO_CON1 (0x74)
+#define EDP_PHY_GRF_BASE 0xfdcb0000
+#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
+#define CPU_GRF_BASE 0xfdc30000
+#define GRF_CORE_PVTPLL_CON0 (0x10)
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -99,6 +108,20 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+ /*
+ * When perform idle operation, corresponding clock can
+ * be opened or gated automatically.
+ */
+ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+ /* Disable eDP phy by default */
+ writel(0x00070007, EDP_PHY_GRF_CON10);
+ writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+ /* Set core pvtpll ring length */
+ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
/* Set the emmc sdmmc0 to secure */
rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
| SDMMC0_HPROT_SECURE_CTRL << 4));

47
package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch
View File

@@ -1,47 +0,0 @@
From ddbcec939789d1f7264134b3628ffb649ec88168 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 19 Dec 2021 08:20:33 -0500
Subject: [PATCH 03/11] Makefile: rockchip: HACK: build rk3568 images
This is a hack to build rk3568 images.
It seems makefile can't cope with the format mkimage expects for
multiple file entries, so hack around the situation.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
Makefile | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/Makefile
+++ b/Makefile
@@ -1047,6 +1047,9 @@ quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
+cmd_mkimage_combined = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $(COMBINED_FILE):$< $@ \
+ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
+
quiet_cmd_mkfitimage = MKIMAGE $@
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) \
-f $(U_BOOT_ITS) -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@ \
@@ -1491,6 +1494,7 @@ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_
ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
# TPL + SPL
+ifneq ($(CONFIG_SYS_SOC),$(filter $(CONFIG_SYS_SOC),"rk3568" "rk3566"))
ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
@@ -1502,6 +1506,12 @@ MKIMAGEFLAGS_idbloader.img = -n $(CONFIG
idbloader.img: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
endif
+else
+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
+COMBINED_FILE = ram_init.bin
+idbloader.img: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage_combined)
+endif
ifeq ($(CONFIG_ARM64),y)
OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \

3520
package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch
View File

File diff suppressed because it is too large Load Diff

50
package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch
View File

@@ -1,50 +0,0 @@
From 01e8a38985a90043abddc5c5bcd049c74bb29a53 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 19 Dec 2021 18:52:18 -0500
Subject: [PATCH 05/11] rockchip: rk356x: HACK: fix sdmmc support
HACK: lock mmc0 to initial frequency and disable dw-mmc control of power
line.
The sdmmc on quartz64-a is powered by the sdmmc0 power line, which is
active low.
Even though it is set as a gpio, it still seems to be triggered by the
dw-mmc driver toggling the power line.
Downstream fixes this by setting this to "0" instead of "1" using
kconfigs.
Also, for some reason the controller will only operate at initial
frequencies.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 4 +++-
drivers/mmc/dw_mmc.c | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -13,8 +13,10 @@
};
&sdmmc0 {
+ max-frequency = <400000>;
+ bus-width = <4>;
u-boot,dm-spl;
- status = "okay";
+ u-boot,spl-fifo-mode;
};
&uart2 {
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -529,7 +529,8 @@ static int dwmci_init(struct mmc *mmc)
if (host->board_init)
host->board_init(host);
- dwmci_writel(host, DWMCI_PWREN, 1);
+// dwmci_writel(host, DWMCI_PWREN, 1);
+ dwmci_writel(host, DWMCI_PWREN, 0);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);

214
package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch
View File

@@ -1,214 +0,0 @@
From 9f623c0e96fc7c3b5c9b7a81f0a3017c47033ec7 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 19 Dec 2021 18:57:36 -0500
Subject: [PATCH 06/11] rockchip: rk356x: add quartz64-a board
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/Kconfig | 12 ++-
board/pine64/quartz64-a-rk3566/Kconfig | 15 ++++
board/pine64/quartz64-a-rk3566/Makefile | 4 +
.../quartz64-a-rk3566/quartz64-a-rk3566.c | 1 +
configs/quartz64-a-rk3566_defconfig | 77 +++++++++++++++++++
include/configs/quartz64-a-rk3566.h | 14 ++++
include/dt-bindings/power/rk3568-power.h | 32 ++++++++
7 files changed, 154 insertions(+), 1 deletion(-)
create mode 100644 board/pine64/quartz64-a-rk3566/Kconfig
create mode 100644 board/pine64/quartz64-a-rk3566/Makefile
create mode 100644 board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
create mode 100644 configs/quartz64-a-rk3566_defconfig
create mode 100644 include/configs/quartz64-a-rk3566.h
create mode 100644 include/dt-bindings/power/rk3568-power.h
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -1,11 +1,20 @@
if ROCKCHIP_RK3568
+choice
+ prompt "RK3568/RK3566 board select"
+
config TARGET_EVB_RK3568
bool "RK3568 evaluation board"
- select BOARD_LATE_INIT
help
RK3568 EVB is a evaluation board for Rockchp RK3568.
+config TARGET_QUARTZ64_A_RK3566
+ bool "Quartz64 Model A RK3566 development board"
+ help
+ Quartz64 Model A RK3566 is a development board from Pine64.
+
+endchoice
+
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
@@ -19,5 +28,6 @@ config SYS_MALLOC_F_LEN
default 0x2000
source "board/rockchip/evb_rk3568/Kconfig"
+source "board/pine64/quartz64-a-rk3566/Kconfig"
endif
--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QUARTZ64_A_RK3566
+
+config SYS_BOARD
+ default "quartz64-a-rk3566"
+
+config SYS_VENDOR
+ default "pine64"
+
+config SYS_CONFIG_NAME
+ default "quartz64-a-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += quartz64-a-rk3566.o
--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
@@ -0,0 +1 @@
+// SPDX-License-Identifier: GPL-2.0+
--- /dev/null
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_A_RK3566=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+++ b/include/configs/quartz64-a-rk3566.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __QUARTZ64_A_RK3566_H
+#define __QUARTZ64_A_RK3566_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
--- /dev/null
+++ b/include/dt-bindings/power/rk3568-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
+#define __DT_BINDINGS_POWER_RK3568_POWER_H__
+
+/* VD_CORE */
+#define RK3568_PD_CPU_0 0
+#define RK3568_PD_CPU_1 1
+#define RK3568_PD_CPU_2 2
+#define RK3568_PD_CPU_3 3
+#define RK3568_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RK3568_PD_PMU 5
+
+/* VD_NPU */
+#define RK3568_PD_NPU 6
+
+/* VD_GPU */
+#define RK3568_PD_GPU 7
+
+/* VD_LOGIC */
+#define RK3568_PD_VI 8
+#define RK3568_PD_VO 9
+#define RK3568_PD_RGA 10
+#define RK3568_PD_VPU 11
+#define RK3568_PD_CENTER 12
+#define RK3568_PD_RKVDEC 13
+#define RK3568_PD_RKVENC 14
+#define RK3568_PD_PIPE 15
+#define RK3568_PD_LOGIC_ALIVE 16
+
+#endif

755
package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch
View File

@@ -1,755 +0,0 @@
From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Thu, 28 May 2020 11:01:58 +0800
Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller
The v2 gpio controller add write enable bit for some register,
such as data register, data direction register and so on.
This patch support v2 gpio controller by redefine the read and
write operation functions.
Also adds support for the rk3568 pinctrl device.
Squash all fixes into this commit.
Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/include/asm/arch-rockchip/gpio.h | 36 ++
drivers/gpio/Kconfig | 13 +
drivers/gpio/rk_gpio.c | 89 ++++-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 360 ++++++++++++++++++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 11 +-
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 42 ++
7 files changed, 530 insertions(+), 22 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#ifndef CONFIG_ROCKCHIP_GPIO_V2
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -23,6 +24,41 @@ struct rockchip_gpio_regs {
u32 ls_sync;
};
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
+ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO
The GPIOs for a device are defined in the device tree with one node
for each bank.
+config ROCKCHIP_GPIO_V2
+ bool "Rockchip GPIO driver version 2.0"
+ depends on ROCKCHIP_GPIO
+ default n
+ help
+ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
+ a number of banks (different for each SoC type) each with 32 GPIOs.
+ The GPIOs for a device are defined in the device tree with one node
+ for each bank.
+
+ Support version 2.0 GPIO controller, which support write enable bits
+ for some registers, such as dr, ddr.
+
config SANDBOX_GPIO
bool "Enable sandbox GPIO driver"
depends on SANDBOX && DM && DM_GPIO
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2020 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
*/
#include <common.h>
#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/device_compat.h>
#include <syscon.h>
#include <linux/errno.h>
#include <asm/gpio.h>
@@ -17,12 +20,34 @@
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
-enum {
- ROCKCHIP_GPIOS_PER_BANK = 32,
-};
+#include "../pinctrl/rockchip/pinctrl-rockchip.h"
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+#ifdef CONFIG_ROCKCHIP_GPIO_V2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
+ ((readl(REG_H(REG)) & 0xFFFF) << 16))
+#define WRITE_REG(REG, VAL) \
+{\
+ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
+ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
+#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
+#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
+ (READ_REG(REG) & ~(MASK)) | (VAL))
+
+#else
+#define READ_REG(REG) readl(REG)
+#define WRITE_REG(REG, VAL) writel(VAL, REG)
+#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
+#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
+#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
+#endif
+
+
struct rockchip_gpio_priv {
struct rockchip_gpio_regs *regs;
struct udevice *pinctrl;
@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct rockchip_gpio_regs *regs = priv->regs;
- clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+ CLRBITS_LE32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
return 0;
}
@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
- setbits_le32(&regs->swport_ddr, mask);
+ CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
+ SETBITS_LE32(&regs->swport_ddr, mask);
return 0;
}
@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+ CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
return 0;
}
@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st
ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
if (ret)
return ret;
- is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
-
+ is_output = READ_REG(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
+
return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
#endif
}
@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
- char *end;
- int ret;
+ struct rockchip_pinctrl_priv *pctrl_priv;
+ struct rockchip_pin_bank *bank;
+ char *end = NULL;
+ static int gpio;
+ int id = -1, ret;
priv->regs = dev_read_addr_ptr(dev);
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
- if (ret)
+ if (ret) {
+ dev_err(dev, "failed to get pinctrl device %d\n", ret);
return ret;
+ }
+
+ pctrl_priv = dev_get_priv(priv->pinctrl);
+ if (!pctrl_priv) {
+ dev_err(dev, "failed to get pinctrl priv\n");
+ return -EINVAL;
+ }
- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
end = strrchr(dev->name, '@');
- priv->bank = trailing_strtoln(dev->name, end);
- priv->name[0] = 'A' + priv->bank;
- uc_priv->bank_name = priv->name;
+ if (end)
+ id = trailing_strtoln(dev->name, end);
+ else
+ dev_read_alias_seq(dev, &id);
+
+ if (id < 0)
+ id = gpio++;
+
+ if (id >= pctrl_priv->ctrl->nr_banks) {
+ dev_err(dev, "bank id invalid\n");
+ return -EINVAL;
+ }
+
+ bank = &pctrl_priv->ctrl->pin_banks[id];
+ if (bank->bank_num != id) {
+ dev_err(dev, "bank id mismatch with pinctrl\n");
+ return -EINVAL;
+ }
+
+ priv->bank = bank->bank_num;
+ uc_priv->gpio_count = bank->nr_pins;
+ uc_priv->gpio_base = bank->pin_base;
+ uc_priv->bank_name = bank->name;
return 0;
}
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
+ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
+};
+
+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = priv->regmap_pmu;
+ else
+ regmap = priv->regmap_base;
+
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3568_PULL_PMU_OFFSET 0x20
+#define RK3568_PULL_GRF_OFFSET 0x80
+#define RK3568_PULL_BITS_PER_PIN 2
+#define RK3568_PULL_PINS_PER_REG 8
+#define RK3568_PULL_BANK_STRIDE 0x10
+
+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_PULL_PMU_OFFSET;
+ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_PULL_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
+ *bit *= RK3568_PULL_BITS_PER_PIN;
+}
+
+#define RK3568_DRV_PMU_OFFSET 0x70
+#define RK3568_DRV_GRF_OFFSET 0x200
+#define RK3568_DRV_BITS_PER_PIN 8
+#define RK3568_DRV_PINS_PER_REG 2
+#define RK3568_DRV_BANK_STRIDE 0x40
+
+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_DRV_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
+ *bit *= RK3568_DRV_BITS_PER_PIN;
+}
+
+#define RK3568_SCHMITT_BITS_PER_PIN 2
+#define RK3568_SCHMITT_PINS_PER_REG 8
+#define RK3568_SCHMITT_BANK_STRIDE 0x10
+#define RK3568_SCHMITT_GRF_OFFSET 0xc0
+#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
+
+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_SCHMITT_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
+ *bit *= RK3568_SCHMITT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3568_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3568_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static int rk3568_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+ int ret = 0;
+
+ rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+
+ ret = regmap_write(regmap, reg, data);
+ if (ret)
+ return ret;
+
+ if (bank->bank_num == 1 && pin_num == 21)
+ reg = 0x0840;
+ else if (bank->bank_num == 2 && pin_num == 2)
+ reg = 0x0844;
+ else if (bank->bank_num == 2 && pin_num == 8)
+ reg = 0x0848;
+ else if (bank->bank_num == 3 && pin_num == 0)
+ reg = 0x084c;
+ else if (bank->bank_num == 3 && pin_num == 6)
+ reg = 0x0850;
+ else if (bank->bank_num == 4 && pin_num == 0)
+ reg = 0x0854;
+ else
+ return 0;
+
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
+ data |= drv;
+
+ return regmap_write(regmap, reg, data);
+}
+
+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+
+ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+static struct rockchip_pin_bank rk3568_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+};
+
+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
+ .pin_banks = rk3568_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rk3568_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
+ .set_mux = rk3568_set_mux,
+ .set_pull = rk3568_set_pull,
+ .set_drive = rk3568_set_drive,
+ .set_schmitt = rk3568_set_schmitt,
+};
+
+static const struct udevice_id rk3568_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3568-pinctrl",
+ .data = (ulong)&rk3568_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3568) = {
+ .name = "rockchip_rk3568_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3568_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st
int prop_len, param;
const u32 *data;
ofnode node;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
const struct device_node *np;
struct property *pp;
#else
@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st
node = ofnode_get_by_phandle(conf);
if (!ofnode_valid(node))
return -ENODEV;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
np = ofnode_to_np(node);
for (pp = np->properties; pp; pp = pp->next) {
prop_name = pp->name;
@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
- pmu_offs : grf_offs;
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
+ pmu_offs : grf_offs;
}
/* preset drv offset value, set new start value */
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -6,9 +6,13 @@
#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
#define __DRIVERS_PINCTRL_ROCKCHIP_H
+#include <dt-bindings/pinctrl/rockchip.h>
#include <linux/bitops.h>
#include <linux/types.h>
+#define RK_GENMASK_VAL(h, l, v) \
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
/**
* Encode variants of iomux registers into a type variable
*/
@@ -18,6 +22,8 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_8WIDTH_2BIT BIT(5)
+#define IOMUX_WRITABLE_32BIT BIT(6)
+#define IOMUX_L_SOURCE_PMU BIT(7)
/**
* Defined some common pins constants
@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type {
};
/**
+ * enum mux route register type, should be invalid/default/topgrf/pmugrf.
+ * INVALID: means do not need to set mux route
+ * DEFAULT: means same regmap as pin iomux
+ * TOPGRF: means mux route setting in topgrf
+ * PMUGRF: means mux route setting in pmugrf
+ */
+enum rockchip_pin_route_type {
+ ROUTE_TYPE_DEFAULT = 0,
+ ROUTE_TYPE_TOPGRF = 1,
+ ROUTE_TYPE_PMUGRF = 2,
+
+ ROUTE_TYPE_INVALID = -1,
+};
+
+/**
* @drv_type: drive strength variant using rockchip_perpin_drv_type
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
@@ -220,6 +241,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
+ { \
+ .bank_num = ID, \
+ .pin = PIN, \
+ .func = FUNC, \
+ .route_offset = REG, \
+ .route_val = VAL, \
+ .route_type = FLAG, \
+ }
+
+#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
+
+#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
+
+#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
+
/**
* struct rockchip_mux_recalced_data: recalculate a pin iomux data.
* @num: bank number.
@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data {
* @bank_num: bank number.
* @pin: index at register or used to calc index.
* @func: the min pin.
+ * @route_type: the register type.
* @route_offset: the max pin.
* @route_val: the register offset.
*/
@@ -248,6 +289,7 @@ struct rockchip_mux_route_data {
u8 bank_num;
u8 pin;
u8 func;
+ enum rockchip_pin_route_type route_type : 8;
u32 route_offset;
u32 route_val;
};

22
package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch
View File

@@ -1,22 +0,0 @@
From 16cc17fc2cf2f308f5ac20b829d427114c6e59fa Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Mon, 20 Dec 2021 08:50:48 -0500
Subject: [PATCH 08/11] rockchip: allow sdmmc at full speed
Adding pinctrl and gpio support fixed quartz64-a sdmmc.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -13,7 +13,6 @@
};
&sdmmc0 {
- max-frequency = <400000>;
bus-width = <4>;
u-boot,dm-spl;
u-boot,spl-fifo-mode;

25
package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch
View File

@@ -1,25 +0,0 @@
From d3b3e9c1045e9fa0aff987a036b30cf380809e35 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Mon, 20 Dec 2021 10:11:52 -0500
Subject: [PATCH 09/11] rockchip: defconfig: add gpio-v2 to quartz64
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
configs/quartz64-a-rk3566_defconfig | 2 ++
1 file changed, 2 insertions(+)
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -42,10 +42,12 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_HS200_SUPPORT=y

97
package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch
View File

@@ -1,97 +0,0 @@
From 981df845d960a9078893dad88e1dd82dfcb4a148 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Wed, 22 Dec 2021 19:40:32 -0500
Subject: [PATCH 10/11] rockchip: rk356x: enable usb2 support on quartz64-a
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 22 ++++++++++++++++++++++
configs/quartz64-a-rk3566_defconfig | 17 +++++++++++++++++
include/configs/quartz64-a-rk3566.h | 3 +++
3 files changed, 42 insertions(+)
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -12,12 +12,34 @@
};
};
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ status = "disabled";
+};
+
&sdmmc0 {
bus-width = <4>;
u-boot,dm-spl;
u-boot,spl-fifo-mode;
};
+&usb_host0_ehci {
+ vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host0_ohci {
+ vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host1_ehci {
+ vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host1_ohci {
+ vbus-supply = <&vcc5v0_usb20_host>;
+};
+
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-spl;
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -22,6 +22,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@@ -35,6 +36,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
@@ -76,4 +78,19 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_ERRNO_STR=y
--- a/include/configs/quartz64-a-rk3566.h
+++ b/include/configs/quartz64-a-rk3566.h
@@ -11,4 +11,7 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
#endif

173
package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch
View File

@@ -1,173 +0,0 @@
From ea6da572fe3cee637319f1e7e588c059622c815e Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Wed, 22 Dec 2021 19:52:38 -0500
Subject: [PATCH 11/11] rockchip: rk356x: attempt to fix ram detection
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++
arch/arm/mach-rockchip/sdram.c | 31 ++++++++++++++------------
common/board_f.c | 7 ++++++
configs/quartz64-a-rk3566_defconfig | 1 +
include/configs/rk3568_common.h | 5 +++++
5 files changed, 59 insertions(+), 14 deletions(-)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <dm.h>
+#include <fdt_support.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
@@ -135,3 +136,31 @@ int arch_cpu_init(void)
#endif
return 0;
}
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+ int areas = 1;
+ u64 start[2], size[2];
+
+ /* Reserve the io address space. */
+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) {
+ start[0] = gd->bd->bi_dram[0].start;
+ size[0] = SDRAM_LOWER_ADDR_MAX - gd->bd->bi_dram[0].start;
+
+ /* Add the upper 4GB address space */
+ start[1] = SDRAM_UPPER_ADDR_MIN;
+ size[1] = gd->ram_top - SDRAM_UPPER_ADDR_MIN;
+ areas = 2;
+
+ ret = fdt_set_usable_memory(blob, start, size, areas);
+ if (ret) {
+ printf("Cannot set usable memory\n");
+ return ret;
+ }
+ }
+
+ return 0;
+};
+#endif
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -3,6 +3,8 @@
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*/
+#define DEBUG
+
#include <common.h>
#include <dm.h>
#include <init.h>
@@ -98,8 +100,7 @@ size_t rockchip_sdram_size(phys_addr_t r
SYS_REG_COL_MASK);
cs1_col = cs0_col;
bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
- SYS_REG_VERSION_MASK) == 0x2) {
+ if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) >= 0x2) {
cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
SYS_REG_CS1_COL_MASK);
if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
@@ -136,7 +137,7 @@ size_t rockchip_sdram_size(phys_addr_t r
SYS_REG_BW_MASK));
row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
SYS_REG_ROW_3_4_MASK;
- if (dram_type == DDR4) {
+ if ((dram_type == DDR4) && (sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) != 0x3){
dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
SYS_REG_DBW_MASK;
bg = (dbw == 2) ? 2 : 1;
@@ -150,15 +151,11 @@ size_t rockchip_sdram_size(phys_addr_t r
chipsize_mb = chipsize_mb * 3 / 4;
size_mb += chipsize_mb;
if (rank > 1)
- debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
- cs1_row %d bw %d row_3_4 %d\n",
- rank, cs0_col, cs1_col, bk, cs0_row,
- cs1_row, bw, row_3_4);
+ debug("rank=%d cs0_col=%d cs1_col=%d bk=%d cs0_row=%d cs1_row=%d bg=%d bw=%d row_3_4=%d\n",
+ rank, cs0_col, cs1_col, bk, cs0_row, cs1_row, bg, bw, row_3_4);
else
- debug("rank %d cs0_col %d bk %d cs0_row %d\
- bw %d row_3_4 %d\n",
- rank, cs0_col, bk, cs0_row,
- bw, row_3_4);
+ debug("rank %d cs0_col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
+ rank, cs0_col, bk, cs0_row, bw, row_3_4);
}
/*
@@ -176,9 +173,11 @@ size_t rockchip_sdram_size(phys_addr_t r
* 2. update board_get_usable_ram_top() and dram_init_banksize()
* to reserve memory for peripheral space after previous update.
*/
+
+#ifndef __aarch64__
if (size_mb > (SDRAM_MAX_SIZE >> 20))
size_mb = (SDRAM_MAX_SIZE >> 20);
-
+#endif
return (size_t)size_mb << 20;
}
@@ -208,6 +207,10 @@ int dram_init(void)
ulong board_get_usable_ram_top(ulong total_size)
{
unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
-
- return (gd->ram_top > top) ? top : gd->ram_top;
+#ifdef SDRAM_UPPER_ADDR_MIN
+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN)
+ return gd->ram_top;
+ else
+#endif
+ return (gd->ram_top > top) ? top : gd->ram_top;
}
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -345,7 +345,14 @@ static int setup_dest_addr(void)
#endif
gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
+#ifdef SDRAM_LOWER_ADDR_MAX
+ if (gd->ram_top > SDRAM_LOWER_ADDR_MAX)
+ gd->relocaddr = SDRAM_LOWER_ADDR_MAX;
+ else
+ gd->relocaddr = gd->ram_top;
+#else
gd->relocaddr = gd->ram_top;
+#endif
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
/*
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -21,6 +21,7 @@ CONFIG_API=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
# CONFIG_SYS_DEVICE_NULLDEV is not set
# CONFIG_DISPLAY_CPUINFO is not set
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -24,6 +24,11 @@
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
+#ifdef CONFIG_OF_SYSTEM_SETUP
+#define SDRAM_LOWER_ADDR_MAX 0xf0000000
+#define SDRAM_UPPER_ADDR_MIN 0x100000000
+#endif
+
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00c00000\0" \

1060
package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch
View File

File diff suppressed because it is too large Load Diff

795
package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch
View File

@@ -1,795 +0,0 @@
From 89d609d74e4ef84e0e3d399d8763b268b60302fc Mon Sep 17 00:00:00 2001
From: Marty Jones <mj8263788@gmail.com>
Date: Sat, 28 May 2022 20:19:38 -0400
Subject: [PATCH] rockchip: rk356x: add bpi r2 pro board
Signed-off-by: Marty Jones <mj8263788@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 47 ++
arch/arm/dts/rk3568-bpi-r2-pro.dts | 532 ++++++++++++++++++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
board/rockchip/bpi-r2-pro-rk3568/Kconfig | 15 +
board/rockchip/bpi-r2-pro-rk3568/Makefile | 7 +
.../bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c | 4 +
configs/bpi-r2-pro-rk3568_defconfig | 97 ++++
include/configs/bpi-r2-pro-rk3568.h | 15 +
9 files changed, 724 insertions(+)
create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Kconfig
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Makefile
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
create mode 100644 configs/bpi-r2-pro-rk3568_defconfig
create mode 100644 include/configs/bpi-r2-pro-rk3568.h
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -164,6 +164,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
rk3566-quartz64-a.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ status = "disabled";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,dm-spl;
+ u-boot,spl-fifo-mode;
+};
+
+&usb_host0_ehci {
+ vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host0_ohci {
+ vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host1_ehci {
+ vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host1_ohci {
+ vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
+ compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blue_led_pin &green_led_pin>;
+
+ blue_led: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ green_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: vcc5v0_usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&combphy0 {
+ /* used for USB3 */
+ status = "okay";
+};
+
+&combphy1 {
+ /* used for USB3 */
+ status = "okay";
+};
+
+&combphy2 {
+ /* used for SATA */
+ status = "okay";
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x0f>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+
+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ /* pin 3 (SDA) + 4 (SCL) of header con2 */
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ leds {
+ blue_led_pin: blue-led-pin {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ green_led_pin: green-led-pin {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm8 {
+ /* fan 5v - gnd - pwm */
+ status = "okay";
+};
+
+&pwm10 {
+ /* pin 7 of header con2 */
+ status = "disabled";
+};
+
+&pwm11 {
+ /* pin 15 of header con2 */
+ status = "disabled";
+};
+
+
+&pwm13 {
+ /* pin 24 of header con2 */
+ /* shared with uart9 */
+ pinctrl-0 = <&pwm13m1_pins>;
+ status = "disabled";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart0 {
+ /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
+ status = "disabled";
+};
+
+&uart2 {
+ /* debug-uart */
+ status = "okay";
+};
+
+&uart7 {
+ /* pin 11 (TX) + 13 (RX) of header con2 */
+ pinctrl-0 = <&uart7m1_xfer>;
+ status = "disabled";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -3,6 +3,11 @@ if ROCKCHIP_RK3568
choice
prompt "RK3568/RK3566 board select"
+config TARGET_BPI_R2_PRO_RK3568
+ bool "Banana Pi R2 Pro RK3566 development board"
+ help
+ Banana Pi R2 Pro is a development board Rockchp RK3568.
+
config TARGET_EVB_RK3568
bool "RK3568 evaluation board"
help
@@ -27,6 +32,7 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x2000
+source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
source "board/rockchip/evb_rk3568/Kconfig"
source "board/pine64/quartz64-a-rk3566/Kconfig"
--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BPI_R2_PRO_RK3568
+
+config SYS_BOARD
+ default "bpi-r2-pro-rk3568"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "bpi-r2-pro-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += bpi-r2-pro-rk3568.o
--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
--- /dev/null
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_BPI_R2_PRO_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+++ b/include/configs/bpi-r2-pro-rk3568.h
@@ -0,0 +1,15 @@
+#ifndef __BPI_R2_PRO_RK3568_H
+#define __BPI_R2_PRO_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
+#endif

690
package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch
View File

@@ -1,690 +0,0 @@
From 443eb96a82563a3b38a3c9548853a5a266dfd072 Mon Sep 17 00:00:00 2001
From: Marty Jones <mj8263788@gmail.com>
Date: Sun, 29 May 2022 06:09:59 -0400
Subject: [PATCH] uboot: add Radxa ROCK 3A board
Signed-off-by: Marty Jones <mj8263788@gmail.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +
arch/arm/dts/rk3568-rock-3a.dts | 525 ++++++++++++++++++++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
board/radxa/rock-3a-rk3568/Kconfig | 15 +
board/radxa/rock-3a-rk3568/Makefile | 4 +
board/radxa/rock-3a-rk3568/rock-3a-rk3568.c | 1 +
configs/rock-3a-rk3568_defconfig | 97 ++++
include/configs/rock-3a-rk3568.h | 17 +
9 files changed, 692 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-3a-rk3568_defconfig
create mode 100644 include/configs/rock-3a-rk3568.h
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -166,7 +166,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
- rk3566-quartz64-a.dtb
+ rk3566-quartz64-a.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_hub_en>;
+ regulator-name = "vcc5v0_usb_hub";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ mic-in-differential;
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_phy_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth_phy_rst {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_user_en: led_user_en {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--- /dev/null
+++ b/configs/rock-3a-rk3568_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y

247
package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch
View File

@@ -1,247 +0,0 @@
From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001
From: Marty Jones <mj8263788@gmail.com>
Date: Tue, 31 May 2022 00:51:23 -0400
Subject: [PATCH] uboot: add NanoPi R5S board
Signed-off-by: Marty Jones <mj8263788@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 25 +++++
arch/arm/dts/rk3568-nanopi-r5s.dts | 9 ++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++
board/friendlyelec/nanopi-r5s-rk3568/Kconfig | 15 +++
board/friendlyelec/nanopi-r5s-rk3568/Makefile | 4 +
.../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c | 4 +
configs/nanopi-r5s-rk3568_defconfig | 97 +++++++++++++++++++
include/configs/nanopi-r5s-rk3568.h | 17 ++++
9 files changed, 178 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
create mode 100644 include/configs/nanopi-r5s-rk3568.h
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5s.dtb \
rk3566-quartz64-a.dtb \
rk3568-rock-3a.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,dm-spl;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3568-evb.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R5S";
+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
+};
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -13,6 +13,11 @@ config TARGET_EVB_RK3568
help
RK3568 EVB is a evaluation board for Rockchp RK3568.
+config TARGET_NANOPI_R5S_RK3568
+ bool "NanoPi R5S board"
+ help
+ NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
+
config TARGET_QUARTZ64_A_RK3566
bool "Quartz64 Model A RK3566 development board"
help
@@ -34,6 +39,7 @@ config SYS_MALLOC_F_LEN
source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
source "board/rockchip/evb_rk3568/Kconfig"
+source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
source "board/pine64/quartz64-a-rk3566/Kconfig"
endif
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NANOPI_R5S_RK3568
+
+config SYS_BOARD
+ default "nanopi-r5s-rk3568"
+
+config SYS_VENDOR
+ default "friendlyelec"
+
+config SYS_CONFIG_NAME
+ default "nanopi-r5s-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nanopi-r5s-rk3568.o
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
@@ -0,0 +1,4 @@
+ // SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ */
--- /dev/null
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_NANOPI_R5S_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+++ b/include/configs/nanopi-r5s-rk3568.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NANOPI_R5S_RK3568_H
+#define __NANOPI_R5S_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif

250
package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch
View File

@@ -1,250 +0,0 @@
From cd6a45a41fb2c19884ac87afade87b4d53601929 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Sat, 25 Jun 2022 11:02:31 -0400
Subject: [PATCH] Convert CONFIG_USB_OHCI_NEW et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
CONFIG_SYS_USB_OHCI_CPU_INIT
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_OHCI_SLOT_NAME
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
Signed-off-by: Tom Rini <trini@konsulko.com>
---
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -89,6 +89,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -93,6 +93,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -98,6 +98,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -96,6 +96,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -64,6 +64,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -80,6 +80,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -257,10 +257,17 @@ config USB_EHCI_FSL
Enables support for the on-chip EHCI controller on FSL chips.
endif # USB_EHCI_HCD
+config USB_OHCI_NEW
+ bool
+
+config SYS_USB_OHCI_CPU_INIT
+ bool
+
config USB_OHCI_HCD
bool "OHCI HCD (USB 1.1) support"
depends on DM && OF_CONTROL
select USB_HOST
+ select USB_OHCI_NEW
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
@@ -292,6 +299,19 @@ config USB_OHCI_DA8XX
endif # USB_OHCI_HCD
+config SYS_USB_OHCI_SLOT_NAME
+ string "Display name for the OHCI controller"
+ depends on USB_OHCI_NEW && !DM_USB
+
+config SYS_USB_OHCI_MAX_ROOT_PORTS
+ int "Maximal number of ports of the root hub"
+ depends on USB_OHCI_NEW
+ default 1 if ARCH_SUNXI
+
+config SYS_OHCI_SWAP_REG_ACCESS
+ bool "Perform byte swapping on OHCI controller register accesses"
+ depends on USB_OHCI_NEW
+
config USB_UHCI_HCD
bool "UHCI HCD (most Intel and VIA) support"
select USB_HOST
@@ -340,3 +360,27 @@ config USB_R8A66597_HCD
---help---
This enables support for the on-chip Renesas R8A66597 USB 2.0
controller, present in various RZ and SH SoCs.
+
+config USB_ATMEL
+ bool "AT91 OHCI USB support"
+ depends on ARCH_AT91
+ select SYS_USB_OHCI_CPU_INIT
+ select USB_OHCI_NEW
+
+choice
+ prompt "Clock for OHCI"
+ depends on USB_ATMEL
+
+config USB_ATMEL_CLK_SEL_PLLB
+ bool "PLLB"
+
+config USB_ATMEL_CLK_SEL_UPLL
+ bool "UPLL"
+
+endchoice
+
+config USB_OHCI_LPC32XX
+ bool "LPC32xx USB OHCI support"
+ depends on ARCH_LPC32XX
+ select SYS_USB_OHCI_CPU_INIT
+ select USB_OHCI_NEW
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -5,9 +5,6 @@
*/
#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-
#include <asm/arch/clk.h>
int usb_cpu_init(void)
@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void)
{
return usb_cpu_stop();
}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -14,10 +14,6 @@
#include <reset.h>
#include "ohci.h"
-#if !defined(CONFIG_USB_OHCI_NEW)
-# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
-#endif
-
struct generic_ohci {
ohci_t ohci;
struct clk *clocks; /* clock list */
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -151,7 +151,7 @@ struct ohci_hcca {
* Maximum number of root hub ports.
*/
#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
/*
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -15,7 +15,4 @@
#define SDRAM_BANK_SIZE (2UL << 30)
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
#endif
--- a/include/configs/gru.h
+++ b/include/configs/gru.h
@@ -13,7 +13,4 @@
#include <configs/rk3399_common.h>
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
#endif
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -42,8 +42,4 @@
#endif
-/* rockchip ohci host driver */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-
#endif
--- a/include/configs/rock960_rk3399.h
+++ b/include/configs/rock960_rk3399.h
@@ -14,7 +14,4 @@
#include <configs/rk3399_common.h>
#define SDRAM_BANK_SIZE (2UL << 30)
-
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
--- a/include/configs/rockpro64_rk3399.h
+++ b/include/configs/rockpro64_rk3399.h
@@ -14,7 +14,4 @@
#include <configs/rk3399_common.h>
#define SDRAM_BANK_SIZE (2UL << 30)
-
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif

57
package/boot/uboot-rockchip/patches/100-spl-Add-Kconfig-options-for-ADC.patch Normal file
View File

@@ -0,0 +1,57 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: u-boot@lists.denx.de
Cc: andre.przywara@arm.com, kever.yang@rock-chips.com,
philipp.tomsich@vrull.eu, sjg@chromium.org, jagan@edgeble.ai,
jonas@kwiboo.se, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V4 2/7] spl: Add Kconfig options for ADC
Date: Tue, 2 Jan 2024 09:46:49 -0600 [thread overview]
Message-ID: <20240102154654.191055-3-macroalpha82@gmail.com> (raw)
In-Reply-To: <20240102154654.191055-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add kconfig options to enable ADC in SPL
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
common/spl/Kconfig | 7 +++++++
drivers/Makefile | 1 +
drivers/adc/Makefile | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -579,6 +579,13 @@ config SPL_FIT_IMAGE_TINY
ensure this information is available to the next image
invoked).
+config SPL_ADC
+ bool "Support ADC drivers"
+ help
+ Enable ADC drivers in SPL. These drivers can allow the reading of
+ analog values from one or more channels. Enable this option to
+ build the drivers in drivers/adc as part of an SPL build.
+
config SPL_CACHE
bool "Support CACHE drivers"
help
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -4,7 +4,7 @@
# Przemyslaw Marczak <p.marczak@samsung.com>
#
-obj-$(CONFIG_ADC) += adc-uclass.o
+obj-$(CONFIG_$(SPL_)ADC) += adc-uclass.o
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o

122
package/boot/uboot-rockchip/patches/101-rockchip-boot_mode-Allow-rockchip_dnl_key_pressed-in-SPL.patch Normal file
View File

@@ -0,0 +1,122 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: u-boot@lists.denx.de
Cc: andre.przywara@arm.com, kever.yang@rock-chips.com,
philipp.tomsich@vrull.eu, sjg@chromium.org, jagan@edgeble.ai,
jonas@kwiboo.se, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V4 3/7] rockchip: boot_mode: Allow rockchip_dnl_key_pressed() in SPL
Date: Tue, 2 Jan 2024 09:46:50 -0600 [thread overview]
Message-ID: <20240102154654.191055-4-macroalpha82@gmail.com> (raw)
In-Reply-To: <20240102154654.191055-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Update the rockchip_dnl_key_pressed() so that it can run in
SPL. Also change the ADC channel to a define that can be
overridden by a board specific option.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/Makefile | 4 ++--
arch/arm/mach-rockchip/boot_mode.c | 11 ++++++++++-
2 files changed, 12 insertions(+), 3 deletions(-)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
-
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -38,6 +38,10 @@ void set_back_to_bootrom_dnl_flag(void)
#define KEY_DOWN_MIN_VAL 0
#define KEY_DOWN_MAX_VAL 30
+#ifndef RK_DNL_ADC_CHAN
+#define RK_DNL_ADC_CHAN 0
+#endif
+
__weak int rockchip_dnl_key_pressed(void)
{
unsigned int val;
@@ -52,7 +56,8 @@ __weak int rockchip_dnl_key_pressed(void
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
- ret = adc_channel_single_shot(dev->name, 1, &val);
+ ret = adc_channel_single_shot(dev->name,
+ RK_DNL_ADC_CHAN, &val);
break;
}
}
@@ -73,11 +78,13 @@ __weak int rockchip_dnl_key_pressed(void
void rockchip_dnl_mode_check(void)
{
+#if CONFIG_IS_ENABLED(ADC)
if (rockchip_dnl_key_pressed()) {
printf("download key pressed, entering download mode...");
set_back_to_bootrom_dnl_flag();
do_reset(NULL, 0, 0, NULL);
}
+#endif
}
int setup_boot_mode(void)
@@ -90,6 +97,7 @@ int setup_boot_mode(void)
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
/* Clear boot mode */
writel(BOOT_NORMAL, reg);
@@ -103,6 +111,7 @@ int setup_boot_mode(void)
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
+#endif
return 0;
}
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -135,3 +135,26 @@ int arch_cpu_init(void)
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+
+void __weak led_setup(void)
+{
+}
+
+void spl_board_init(void)
+{
+ led_setup();
+
+#if (CONFIG_IS_ENABLED(DM_REGULATOR))
+ /*
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
+ * BIOS_ENABLE) signal is done through a always-on regulator).
+ */
+ if (regulators_enable_boot_on(false))
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+ setup_boot_mode();
+}
+#endif

561
package/boot/uboot-rockchip/patches/102-configs-rockchip-Use-dwc3-generic-driver-on-RK3328-and.patch Normal file
View File

@@ -0,0 +1,561 @@
From a7503c6fffae2d7ec85f92b76d64f2cfd1a464c5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 12 Nov 2023 17:48:57 +0000
Subject: [PATCH] configs: rockchip: Use dwc3-generic driver on RK3328 and
RK3399
Complete the transition away from xhci-dwc3 and dwc3-of-simple drivers
and change to use the dwc3-generic driver on remaining RK3328 and RK3399
boards.
MISC, USB_DWC3 and USB_DWC3_GENERIC is enabled on boards that used to
enable USB_XHCI_DWC3. USB_XHCI_DWC3 is dropped from updated boards along
with the default y of USB_XHCI_DWC3_OF_SIMPLE.
There is no intended change in functionality with this changes, USB 3.0
is expected to continue same as before this change.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/chromebook_bob_defconfig | 2 +-
configs/chromebook_kevin_defconfig | 2 +-
configs/eaidk-610-rk3399_defconfig | 4 +++-
configs/evb-rk3399_defconfig | 1 -
configs/firefly-rk3399_defconfig | 1 -
configs/khadas-edge-captain-rk3399_defconfig | 4 +++-
configs/khadas-edge-rk3399_defconfig | 4 +++-
configs/khadas-edge-v-rk3399_defconfig | 4 +++-
configs/leez-rk3399_defconfig | 4 +++-
configs/nanopc-t4-rk3399_defconfig | 3 ++-
configs/nanopi-m4-2gb-rk3399_defconfig | 4 +++-
configs/nanopi-m4-rk3399_defconfig | 4 +++-
configs/nanopi-m4b-rk3399_defconfig | 4 +++-
configs/nanopi-neo4-rk3399_defconfig | 4 +++-
configs/nanopi-r4s-rk3399_defconfig | 3 ++-
configs/orangepi-r1-plus-lts-rk3328_defconfig | 3 ++-
configs/orangepi-r1-plus-rk3328_defconfig | 3 ++-
configs/orangepi-rk3399_defconfig | 4 +++-
configs/pinebook-pro-rk3399_defconfig | 1 -
configs/pinephone-pro-rk3399_defconfig | 1 -
configs/puma-rk3399_defconfig | 1 -
configs/roc-pc-mezzanine-rk3399_defconfig | 1 -
configs/roc-pc-rk3399_defconfig | 1 -
configs/rock-4c-plus-rk3399_defconfig | 1 -
configs/rock-4se-rk3399_defconfig | 1 -
configs/rock-pi-4-rk3399_defconfig | 1 -
configs/rock-pi-4c-rk3399_defconfig | 1 -
configs/rock-pi-n10-rk3399pro_defconfig | 1 -
configs/rock960-rk3399_defconfig | 3 ++-
configs/rockpro64-rk3399_defconfig | 1 -
drivers/usb/host/Kconfig | 1 -
31 files changed, 42 insertions(+), 31 deletions(-)
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -98,12 +98,12 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -99,12 +99,12 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,8 +57,9 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -66,7 +66,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -66,7 +66,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -61,11 +62,12 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -42,6 +42,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -60,11 +61,12 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -61,11 +62,12 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -60,10 +61,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -63,9 +63,10 @@ CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -99,7 +100,6 @@ CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
@@ -107,6 +107,7 @@ CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -99,7 +100,6 @@ CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
@@ -107,6 +107,7 @@ CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -56,9 +57,10 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -96,7 +96,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -85,7 +85,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -97,7 +97,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -81,7 +81,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -82,7 +82,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -74,7 +74,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -76,7 +76,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -77,7 +77,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -74,7 +74,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -68,7 +68,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -70,12 +71,12 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -93,7 +93,6 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -39,7 +39,6 @@ config USB_XHCI_DWC3
config USB_XHCI_DWC3_OF_SIMPLE
bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
depends on DM_USB
- default y if ARCH_ROCKCHIP
default y if DRA7XX
help
Support USB2/3 functionality in simple SoC integrations with

131
package/boot/uboot-rockchip/patches/103-rockchip-board-Remove-dwc3-usb-init-and-gadget-handler.patch Normal file
View File

@@ -0,0 +1,131 @@
From ed7a42771f3b72c2cd51942b525ea6ba8935578d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 12 Nov 2023 17:48:58 +0000
Subject: [PATCH] rockchip: board: Remove dwc3 usb init and gadget handler
functions
Remove board_usb_init() and dm_usb_gadget_handle_interrupts() functions
related to dwc3, they use e.g. a hard-coded reg address for RK3399 and
are obsolete with use of DM_USB_GADGET.
Use of DM_USB_GADGET, USB_DWC3_GENERIC and USB_DWC3_GADGET have replaced
same feature provided by the removed functions on RK3399 boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-rockchip/board.c | 30 +-----------------------
configs/nanopc-t6-rk3588_defconfig | 1 -
configs/orangepi-5-plus-rk3588_defconfig | 1 -
configs/orangepi-5-rk3588s_defconfig | 1 -
configs/rock5a-rk3588s_defconfig | 1 -
configs/rock5b-rk3588_defconfig | 1 -
7 files changed, 2 insertions(+), 34 deletions(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1974,6 +1974,7 @@ config ARCH_ROCKCHIP
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select DM_USB_GADGET if USB_DWC3_GADGET
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPI
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -208,10 +208,8 @@ void enable_caches(void)
}
#endif
-#if defined(CONFIG_USB_GADGET)
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <usb.h>
-
-#if defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <linux/usb/otg.h>
#include <usb/dwc2_udc.h>
@@ -287,32 +285,6 @@ int board_usb_cleanup(int index, enum us
}
#endif /* CONFIG_USB_GADGET_DWC2_OTG */
-#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
-#include <dwc3-uboot.h>
-
-static struct dwc3_device dwc3_device_data = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = 0xfe800000,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 0,
- .dis_u2_susphy_quirk = 1,
- .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
-};
-
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- dwc3_uboot_handle_interrupt(dev);
- return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc3_uboot_init(&dwc3_device_data);
-}
-#endif /* CONFIG_USB_DWC3_GADGET */
-
-#endif /* CONFIG_USB_GADGET */
-
#if IS_ENABLED(CONFIG_FASTBOOT)
int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -91,7 +91,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -94,7 +94,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -91,7 +91,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -75,7 +75,6 @@ CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -99,7 +99,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y

166
package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch
View File

@@ -1,166 +0,0 @@
--- a/include/image.h
+++ b/include/image.h
@@ -1020,21 +1020,6 @@ int fit_image_hash_get_value(const void
int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
-/**
- * fit_pre_load_data() - add public key to fdt blob
- *
- * Adds public key to the node pre load.
- *
- * @keydir: Directory containing keys
- * @keydest: FDT blob to write public key
- * @fit: Pointer to the FIT format image header
- *
- * returns:
- * 0, on success
- * < 0, on failure
- */
-int fit_pre_load_data(const char *keydir, void *keydest, void *fit);
-
int fit_cipher_data(const char *keydir, void *keydest, void *fit,
const char *comment, int require_keys,
const char *engine_id, const char *cmdname);
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -59,9 +59,6 @@ static int fit_add_file_data(struct imag
ret = fit_set_timestamp(ptr, 0, time);
}
- if (!ret)
- ret = fit_pre_load_data(params->keydir, dest_blob, ptr);
-
if (!ret) {
ret = fit_cipher_data(params->keydir, dest_blob, ptr,
params->comment,
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -14,11 +14,6 @@
#include <image.h>
#include <version.h>
-#include <openssl/pem.h>
-#include <openssl/evp.h>
-
-#define IMAGE_PRE_LOAD_PATH "/image/pre-load/sig"
-
/**
* fit_set_hash_value - set hash value in requested has node
* @fit: pointer to the FIT format image header
@@ -1116,115 +1111,6 @@ static int fit_config_add_verification_d
return 0;
}
-/*
- * 0) open file (open)
- * 1) read certificate (PEM_read_X509)
- * 2) get public key (X509_get_pubkey)
- * 3) provide der format (d2i_RSAPublicKey)
- */
-static int read_pub_key(const char *keydir, const void *name,
- unsigned char **pubkey, int *pubkey_len)
-{
- char path[1024];
- EVP_PKEY *key = NULL;
- X509 *cert;
- FILE *f;
- int ret;
-
- memset(path, 0, 1024);
- snprintf(path, sizeof(path), "%s/%s.crt", keydir, (char *)name);
-
- /* Open certificate file */
- f = fopen(path, "r");
- if (!f) {
- fprintf(stderr, "Couldn't open RSA certificate: '%s': %s\n",
- path, strerror(errno));
- return -EACCES;
- }
-
- /* Read the certificate */
- cert = NULL;
- if (!PEM_read_X509(f, &cert, NULL, NULL)) {
- printf("Couldn't read certificate");
- ret = -EINVAL;
- goto err_cert;
- }
-
- /* Get the public key from the certificate. */
- key = X509_get_pubkey(cert);
- if (!key) {
- printf("Couldn't read public key\n");
- ret = -EINVAL;
- goto err_pubkey;
- }
-
- /* Get DER form */
- ret = i2d_PublicKey(key, pubkey);
- if (ret < 0) {
- printf("Couldn't get DER form\n");
- ret = -EINVAL;
- goto err_pubkey;
- }
-
- *pubkey_len = ret;
- ret = 0;
-
-err_pubkey:
- X509_free(cert);
-err_cert:
- fclose(f);
- return ret;
-}
-
-int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
-{
- int pre_load_noffset;
- const void *algo_name;
- const void *key_name;
- unsigned char *pubkey = NULL;
- int ret, pubkey_len;
-
- if (!keydir || !keydest || !fit)
- return 0;
-
- /* Search node pre-load sig */
- pre_load_noffset = fdt_path_offset(keydest, IMAGE_PRE_LOAD_PATH);
- if (pre_load_noffset < 0) {
- ret = 0;
- goto out;
- }
-
- algo_name = fdt_getprop(keydest, pre_load_noffset, "algo-name", NULL);
- key_name = fdt_getprop(keydest, pre_load_noffset, "key-name", NULL);
-
- /* Check that all mandatory properties are present */
- if (!algo_name || !key_name) {
- if (!algo_name)
- printf("The property algo-name is missing in the node %s\n",
- IMAGE_PRE_LOAD_PATH);
- if (!key_name)
- printf("The property key-name is missing in the node %s\n",
- IMAGE_PRE_LOAD_PATH);
- ret = -EINVAL;
- goto out;
- }
-
- /* Read public key */
- ret = read_pub_key(keydir, key_name, &pubkey, &pubkey_len);
- if (ret < 0)
- goto out;
-
- /* Add the public key to the device tree */
- ret = fdt_setprop(keydest, pre_load_noffset, "public-key",
- pubkey, pubkey_len);
- if (ret)
- printf("Can't set public-key in node %s (ret = %d)\n",
- IMAGE_PRE_LOAD_PATH, ret);
-
- out:
- return ret;
-}
-
int fit_cipher_data(const char *keydir, void *keydest, void *fit,
const char *comment, int require_keys,
const char *engine_id, const char *cmdname)

27
package/boot/uboot-rockchip/patches/104-usb-dwc3-of-simple-Remove-Amlogic-and-Rockchip-compatible.patch Normal file
View File

@@ -0,0 +1,27 @@
From 6b211613625eb264c22bbf3a53fa8cb1014d6da3 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 9 May 2023 01:32:22 +0000
Subject: [PATCH] usb: dwc3-of-simple: Remove Amlogic and Rockchip compatible
Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.
Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/usb/host/dwc3-of-simple.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -90,8 +90,6 @@ static int dwc3_of_simple_remove(struct
}
static const struct udevice_id dwc3_of_simple_ids[] = {
- { .compatible = "amlogic,meson-gxl-dwc3" },
- { .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "ti,dwc3" },
{ }
};

125
package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch
View File

@@ -1,125 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -413,13 +413,7 @@ PERL = perl
PYTHON ?= python
PYTHON2 = python2
PYTHON3 ?= python3
-
-# The devicetree compiler and pylibfdt are automatically built unless DTC is
-# provided. If DTC is provided, it is assumed the pylibfdt is available too.
-DTC_INTREE := $(objtree)/scripts/dtc/dtc
-DTC ?= $(DTC_INTREE)
-DTC_MIN_VERSION := 010406
-
+DTC ?= $(objtree)/scripts/dtc/dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -2070,29 +2064,9 @@ endif
endif
-# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(Q)$(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -131,27 +131,6 @@ Further important build parameters are
* O=<dir> - generate all output files in directory <dir>, including .config
* V=1 - verbose build
-Devicetree compiler
-~~~~~~~~~~~~~~~~~~~
-
-Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the
-devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python
-library for accessing devicetree data. Suitable versions of these are included
-in the U-Boot tree in `scripts/dtc` and built automatically as needed.
-
-To use the system versions of these, use the DTC parameter, for example
-
-.. code-block:: bash
-
- DTC=/usr/bin/dtc make
-
-In this case, dtc and pylibfdt are not built. The build checks that the version
-of dtc is new enough. It also makes sure that pylibfdt is present, if needed
-(see `scripts_dtc` in the Makefile).
-
-Note that the :doc:`tools` are always built with the included version of libfdt
-so it is not possible to build U-Boot tools with a system libfdt, at present.
-
Other build targets
~~~~~~~~~~~~~~~~~~~
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -5,6 +5,9 @@
config SUPPORT_OF_CONTROL
bool
+config DTC
+ bool
+
config PYLIBFDT
bool
@@ -21,6 +24,7 @@ menu "Device Tree Control"
config OF_CONTROL
bool "Run-time configuration via Device Tree"
+ select DTC
select OF_LIBFDT if !OF_PLATDATA
select OF_REAL if !OF_PLATDATA
help
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -10,3 +10,4 @@ always := $(hostprogs-y)
# Let clean descend into subdirs
subdir- += basic kconfig dtc
+subdir-$(CONFIG_DTC) += dtc
--- a/scripts/dtc-version.sh
+++ b/scripts/dtc-version.sh
@@ -10,16 +10,11 @@
dtc="$*"
if [ ${#dtc} -eq 0 ]; then
- echo "Error: No dtc command specified"
+ echo "Error: No dtc command specified."
printf "Usage:\n\t$0 <dtc-command>\n"
exit 1
fi
-if ! which $dtc >/dev/null ; then
- echo "Error: Cannot find dtc: $dtc"
- exit 1
-fi
-
MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)

51
package/boot/uboot-rockchip/patches/105-bootstd-efi-Initialize-PCI-to-discover-network-controller.patch Normal file
View File

@@ -0,0 +1,51 @@
From 583d37d192d92c5e92efa68b1d97f8ecdef71c47 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 12 Nov 2023 10:57:21 +0000
Subject: [PATCH] bootstd: efi: Initialize PCI to discover network controllers
Boards like Radxa ROCK 5 Model B and NanoPi R5C require PCI to be
initialized in order to discover their onboard network controllers.
During standard boot, PCI gets initialized after faster boot media have
been evaluated. However when an EFI bootflow is run from a fast boot
media, PCI initialization may not have happended and as a result no
network device is exposed to EFI.
Fix this by initializing PCI during EFI bootflow when no ethernet device
can be found.
This allows chainloading e.g. iPXE on ROCK 5B and NanoPi R5C without
having to enable PCI_INIT_R. Enabling of PCI_INIT_R has the side affect
of slowing down booting from faster boot media, by adding ~1 second off
boot delay for each unocupied M.2 slot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
boot/bootmeth_efi.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -16,6 +16,7 @@
#include <dm.h>
#include <efi_loader.h>
#include <fs.h>
+#include <init.h>
#include <malloc.h>
#include <mapmem.h>
#include <mmc.h>
@@ -453,6 +454,14 @@ static int distro_efi_boot(struct udevic
fdt = env_get_hex("fdt_addr_r", 0);
}
+ /* init PCI first since this is often used to provide Ehternet */
+ if (IS_ENABLED(CONFIG_NETDEVICES) && IS_ENABLED(CONFIG_PCI) &&
+ !eth_get_dev()) {
+ ret = pci_init();
+ if (ret)
+ return log_msg_ret("pci", ret);
+ }
+
/*
* At some point we can add a real interface to bootefi so we can call
* this directly. For now, go through the CLI, like distro boot.

10
package/boot/uboot-rockchip/patches/106-no-kwbimage.patch
View File

@@ -1,10 +0,0 @@
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
imx8image.o \
imx8mimage.o \
- kwbimage.o \
lib/md5.o \
lpc32xximage.o \
mxsimage.o \

104
package/boot/uboot-rockchip/patches/106-rockchip-board-Add-board_rng_seed-for-all-Rockchip-device.patch Normal file
View File

@@ -0,0 +1,104 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: u-boot@lists.denx.de
Cc: andre.przywara@arm.com, kever.yang@rock-chips.com,
philipp.tomsich@vrull.eu, sjg@chromium.org, jagan@edgeble.ai,
jonas@kwiboo.se, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V4 5/7] rockchip: board: Add board_rng_seed() for all Rockchip devices
Date: Tue, 2 Jan 2024 09:46:52 -0600 [thread overview]
Message-ID: <20240102154654.191055-6-macroalpha82@gmail.com> (raw)
In-Reply-To: <20240102154654.191055-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Allow all rockchip devices to use the hardware RNG to seed Linux
RNG.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/board.c | 32 ++++++++++++++++++++++
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 29 --------------------
2 files changed, 32 insertions(+), 29 deletions(-)
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -320,3 +320,35 @@ __weak int misc_init_r(void)
return ret;
}
#endif
+
+#if IS_ENABLED(CONFIG_BOARD_RNG_SEED) && IS_ENABLED(CONFIG_RNG_ROCKCHIP)
+#include <rng.h>
+
+/* Use hardware rng to seed Linux random. */
+__weak int board_rng_seed(struct abuf *buf)
+{
+ struct udevice *dev;
+ size_t len = 0x8;
+ u64 *data;
+
+ data = malloc(len);
+ if (!data) {
+ printf("Out of memory\n");
+ return -ENOMEM;
+ }
+
+ if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+ printf("No RNG device\n");
+ return -ENODEV;
+ }
+
+ if (dm_rng_read(dev, data, len)) {
+ printf("Reading RNG failed\n");
+ return -EIO;
+ }
+
+ abuf_init_set(buf, data, len);
+
+ return 0;
+}
+#endif
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -16,7 +16,6 @@
#include <mmc.h>
#include <panel.h>
#include <pwm.h>
-#include <rng.h>
#include <stdlib.h>
#include <video_bridge.h>
@@ -117,34 +116,6 @@ void spl_board_init(void)
(GPIO0_BASE + GPIO_SWPORT_DR_H));
}
-/* Use hardware rng to seed Linux random. */
-int board_rng_seed(struct abuf *buf)
-{
- struct udevice *dev;
- size_t len = 0x8;
- u64 *data;
-
- data = malloc(len);
- if (!data) {
- printf("Out of memory\n");
- return -ENOMEM;
- }
-
- if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
- printf("No RNG device\n");
- return -ENODEV;
- }
-
- if (dm_rng_read(dev, data, len)) {
- printf("Reading RNG failed\n");
- return -EIO;
- }
-
- abuf_init_set(buf, data, len);
-
- return 0;
-}
-
/*
* Buzz the buzzer so the user knows something is going on. Make it
* optional in case PWM is disabled.

27
package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch
View File

@@ -1,27 +0,0 @@
From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001
From: Marty Jones <mj8263788@gmail.com>
Date: Sun, 17 Jan 2021 15:26:09 -0500
Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT
On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3
CONFIG_USE_PREBOOT was enabled on the RockPro64.
When the board is booting, U-Boot hangs as soon as it disables the USB
controller. This is a workaround until a final solution is deployed
upstream.
Signed-off-by: Marty Jones <mj8263788@gmail.com>
---
configs/rockpro64-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y

550
package/boot/uboot-rockchip/patches/301-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch
View File

@@ -1,550 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -123,6 +123,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-roc-cc.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3328-doornet1.dtb \
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-roc-cc.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3328-doornet1-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2021 EmbedFire <embedfire@embedfire.com>
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &emmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_pin {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
+
+&gmac2io {
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+};
+
--- /dev/null
+++ b/arch/arm/dts/rk3328-doornet1.dts
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3328.dtsi"
+
+/ {
+ model = "EmbedFire DoorNet1";
+ compatible = "embedfire,doornet1", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clk: gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&reset_button_pin>;
+ pinctrl-names = "default";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <50>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+ pinctrl-names = "default";
+
+ lan_led: led-0 {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:green:lan";
+ };
+
+ sys_led: led-1 {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:red:sys";
+ };
+
+ wan_led: led-2 {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:green:wan";
+ };
+ };
+
+ vcc_io_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&sdio_vcc_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_io_sdio";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-settling-time-us = <5000>;
+ regulator-type = "voltage";
+ startup-delay-us = <2000>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ vin-supply = <&vcc_io_33>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_sd";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io_33>;
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+ clock_in_out = "input";
+ phy-handle = <&rtl8211f>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_io_33>;
+ pinctrl-0 = <&rgmiim1_pins>;
+ pinctrl-names = "default";
+ rx_delay = <0x54>;
+ snps,aal;
+ tx_delay = <0x20>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211f: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-0 = <&pmic_int_l>;
+ pinctrl-names = "default";
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vdd_5v>;
+ vcc2-supply = <&vdd_5v>;
+ vcc3-supply = <&vdd_5v>;
+ vcc4-supply = <&vdd_5v>;
+ vcc5-supply = <&vcc_io_33>;
+ vcc6-supply = <&vdd_5v>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io_33: DCDC_REG4 {
+ regulator-name = "vcc_io_33";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ pmuio-supply = <&vcc_io_33>;
+ vccio1-supply = <&vcc_io_33>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io_sdio>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io_33>;
+ vccio6-supply = <&vcc_io_33>;
+ status = "okay";
+};
+
+&pinctrl {
+ button {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet-phy {
+ eth_phy_reset_pin: eth-phy-reset-pin {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sd {
+ sdio_vcc_pin: sdio-vcc-pin {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ pinctrl-names = "default";
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_io_sdio>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io_33>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
--- /dev/null
+++ b/configs/doornet1-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-doornet1.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-doornet1"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

174
package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch
View File

@@ -1,174 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-doornet1.dtb \
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
+ rk3328-orangepi-r1-plus.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -0,0 +1 @@
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus";
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+};
+
+&lan_led {
+ label = "orangepi-r1-plus:green:lan";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&sys_led {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ label = "orangepi-r1-plus:red:sys";
+};
+
+&sys_led_pin {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&wan_led {
+ label = "orangepi-r1-plus:green:wan";
+};
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -12,6 +12,13 @@ F: configs/nanopi-r2s-rk3328_defcon
F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
F: arch/arm/dts/rk3328-nanopi-r2s.dts
+ORANGEPI-R1-PLUS-RK3328
+M: Shenzhen Xunlong Software CO.,Limited <zhao_steven@263.net>
+S: Maintained
+F: configs/orangepi-r1-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts
+
ROC-RK3328-CC
M: Loic Devulder <ldevulder@suse.com>
M: Chen-Yu Tsai <wens@csie.org>
--- /dev/null
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

136
package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch
View File

@@ -1,136 +0,0 @@
From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001
From: baiywt <baiywt_gj@163.com>
Date: Wed, 24 Nov 2021 19:59:38 +0800
Subject: [PATCH] Add support for Orangepi R1 Plus LTS
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++
configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -127,6 +127,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
+ rk3328-orangepi-r1-plus-lts.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
--- /dev/null
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

173
package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@@ -1,173 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-doornet1.dtb \
rk3328-evb.dtb \
+ rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
rk3328-orangepi-r1-plus-lts.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2021 Tianling Shen
+ */
+
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R2C";
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+ phy-handle = <&yt8521s>;
+
+ mdio {
+ /delete-node/ ethernet-phy@1;
+
+ yt8521s: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&lan_led {
+ label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+ label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {
+ label = "nanopi-r2c:green:wan";
+};
--- /dev/null
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

113
package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@@ -1,113 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -155,6 +155,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-m4b.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-nanopi-r4s.dtb \
+ rk3399-nanopi-r4se.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
rk3399-puma-haikou.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4se.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ *
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi-r4s.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R4SE";
+ compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+&sdmmc {
+ pinctrl-0 = <&sdmmc_cd>;
+};
--- /dev/null
+++ b/configs/nanopi-r4se-rk3399_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

986
package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch
View File

@@ -1,986 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -140,6 +140,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-px5-evb.dtb \
dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ rk3399-doornet2.dtb \
rk3399-evb.dtb \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3399-doornet2-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"
+
+/{
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdhci;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
+
+&sdmmc {
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
+
--- /dev/null
+++ b/arch/arm/dts/rk3399-doornet2.dts
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3399-doornet2.dtsi"
+
+/ {
+ model = "EmbedFire DoorNet2";
+ compatible = "embedfire,doornet2", "rockchip,rk3399";
+
+ /delete-node/ display-subsystem;
+
+ gpio-leds {
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+
+ /delete-node/ status;
+
+ lan_led: led-lan {
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "green:lan";
+ };
+
+ sys_led: led-sys {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "red:sys";
+ default-state = "on";
+ };
+
+ wan_led: led-wan {
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ label = "green:wan";
+ };
+ };
+
+ gpio-keys {
+ pinctrl-0 = <&reset_button_pin>;
+
+ /delete-node/ power;
+
+ reset {
+ debounce-interval = <50>;
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "disabled";
+};
+
+&pcie0 {
+ max-link-speed = <1>;
+ num-lanes = <1>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+};
+
+&pinctrl {
+ gpio-leds {
+ /delete-node/ leds-gpio;
+
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rockchip-key {
+ /delete-node/ power-key;
+
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdhci {
+ status = "okay";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&u2phy0_host {
+ phy-supply = <&vdd_5v>;
+};
+
+&u2phy1_host {
+ status = "disabled";
+};
+
+&uart0 {
+ status = "disabled";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_sys>;
+};
+
--- /dev/null
+++ b/arch/arm/dts/rk3399-doornet2.dtsi
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <&vdd_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /*
+ * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
+ * drives the enable pin, but we can't quite model that.
+ */
+ vcca0v9_s3: vcca0v9-s3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vcca0v9_s3";
+ vin-supply = <&vcc1v8_s3>;
+ };
+
+ /* As above, actually supplied by vcc3v3_sys */
+ vcca1v8_s3: vcca1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_s3";
+ vin-supply = <&vcc1v8_s3>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+ phy-handle = <&rtl8211f>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc3v3_s3>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211f: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu_b";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ clock-output-names = "xin32k", "rtc_clko_wifi";
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_center";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_cpu_l";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_cam: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_cam";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_touch";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmupll";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_sdio";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcca3v0_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_1v5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_3v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <200000>;
+ i2c-scl-rising-time-ns = <150>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vbus_typec>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc_1v8>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pcie_phy {
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ max-link-speed = <2>;
+ num-lanes = <2>;
+ vpcie0v9-supply = <&vcca0v9_s3>;
+ vpcie1v8-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&pinctrl {
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ phy {
+ phy_intb: phy-intb {
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rstb: phy-rstb {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ power_key: power-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio {
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ /* external pullup to VCC1V8_PMUPLL */
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_reg_on_h: wifi-reg_on-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc0_det_l: sdmmc0-det-l {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin_pull_down>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_host {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_host {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
--- /dev/null
+++ b/configs/doornet2-rk3399_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_TARGET_DOORNET2_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-doornet2"
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-doornet2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+

406
package/boot/uboot-rockchip/patches/307-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch
View File

@@ -1,406 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
+ rk3568-mrkaio-m68s.dtb \
rk3568-nanopi-r5s.dtb \
rk3566-quartz64-a.dtb \
rk3568-rock-3a.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-evb.dts"
+
+/ {
+ model = "EZPRO Mrkaio M68S";
+ compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
--- /dev/null
+++ b/configs/mrkaio-m68s-rk3568_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y

415
package/boot/uboot-rockchip/patches/308-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch
View File

@@ -1,415 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
+ rk3568-opc-h68k.dtb \
rk3568-mrkaio-m68s.dtb \
rk3568-nanopi-r5s.dtb \
rk3566-quartz64-a.dtb \
--- /dev/null
+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-opc-h68k.dts
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-evb.dts"
+
+/ {
+ model = "HINLINK OPC-H68K Board";
+ compatible = "hinlink,opc-h68k", "rockchip,rk3568";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ mic-in-differential;
+ };
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
--- /dev/null
+++ b/configs/opc-h68k-rk3568_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y

696
package/boot/uboot-rockchip/patches/310-rockchip-rk3399-split-doornet2-rk3399-out-of-evb_rk.patch
View File

@@ -1,696 +0,0 @@
--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1333 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,5 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
-
--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1600 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,4 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1866 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,5 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
-
--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
@@ -5,6 +5,8 @@
*/
&dmc {
+ lpddr3-2GB-1600 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x1
0xa
@@ -1537,4 +1539,5 @@
0x01010000
0x00000000
>;
+ };
};
--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
@@ -4,6 +4,8 @@
*/
&dmc {
+ lpddr3-4GB-1600 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1536,4 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
@@ -4,6 +4,8 @@
*/
&dmc {
+ lpddr3-samsung-4GB-1866 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1543,4 +1545,5 @@
0x01010000 /* DENALI_PHY_957_DATA */
0x00000000 /* DENALI_PHY_958_DATA */
>;
+ };
};
--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -6,6 +6,8 @@
*/
&dmc {
+ lpddr4-100 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1538,4 +1540,5 @@
0x01010000
0x00000000
>;
+ };
};
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -120,6 +120,21 @@ config TARGET_ROC_PC_RK3399
* wide voltage input(5V-15V), dual cell battery
* Wifi/BT accessible via expansion board M.2
+config TARGET_DOORNET2_RK3399
+ bool "EmbedFire DoorNet2 board"
+ help
+ DoorNet2 is SBC produced by EmbedFire. Key features:
+
+ * Rockchip RK3399
+ * 1-4GB DDR3 or LPDDR4
+ * SD card slot and 8-32GB eMMC
+ * Gigabit ethernet
+ * PCIe
+ * USB 3.0, 2.0
+ * USB Type C power
+ * GPIO expansion ports
+ * USB 2.0 Wifi module
+
endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -165,6 +180,7 @@ config SYS_BOOTCOUNT_ADDR
endif # BOOTCOUNT_LIMIT
+source "board/embedfire/doornet2/Kconfig"
source "board/firefly/roc-pc-rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/pinebook-pro-rk3399/Kconfig"
--- /dev/null
+++ b/board/embedfire/doornet2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DOORNET2_RK3399
+
+config SYS_BOARD
+ default "doornet2"
+
+config SYS_VENDOR
+ default "embedfire"
+
+config SYS_CONFIG_NAME
+ default "doornet2"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
--- /dev/null
+++ b/board/embedfire/doornet2/MAINTAINERS
@@ -0,0 +1,5 @@
+DoorNet2 Series
+M: embedfire <support@embedfire.com>
+S: Maintained
+F: board/embedfire/doornet2/
+F: include/configs/doornet2.h
--- /dev/null
+++ b/board/embedfire/doornet2/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += doornet2.o hwrev.o
+
--- /dev/null
+++ b/board/embedfire/doornet2/doornet2.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <hash.h>
+#include <linux/bitops.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <u-boot/sha256.h>
+#include "hwrev.h"
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /* BT565 and AUDIO is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1));
+}
+
+static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr)
+{
+ struct udevice *i2c_dev;
+ int ret;
+
+ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */
+ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev);
+ if (!ret)
+ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6);
+
+ return ret;
+}
+
+static void setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+ int from_eeprom = 0;
+ int lockdown = 0;
+
+#ifndef CONFIG_ENV_IS_NOWHERE
+ lockdown = env_get_yesno("lockdown") == 1;
+#endif
+ if (lockdown && env_get("ethaddr"))
+ return;
+
+ ret = mac_read_from_generic_eeprom(mac_addr);
+ if (!ret && is_valid_ethaddr(mac_addr)) {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ from_eeprom = 1;
+ }
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+
+ if (from_eeprom) {
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ } else {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ if (lockdown && env_get("eth1addr"))
+ return;
+
+ /* Ugly, copy another 4 bytes to generate a similar address */
+ memcpy(mac_addr + 2, hash + 8, 4);
+ if (!memcmp(hash + 2, hash + 8, 4))
+ mac_addr[5] ^= 0xff;
+
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ }
+#endif
+
+ return;
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ setup_macaddr();
+ bd_hwrev_init();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial_string;
+ u64 serial = 0;
+
+ serial_string = env_get("serial#");
+
+ if (serial_string)
+ serial = simple_strtoull(serial_string, NULL, 16);
+
+ serialnr->high = (u32)(serial >> 32);
+ serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
+
--- /dev/null
+++ b/board/embedfire/doornet2/hwrev.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch-rockchip/gpio.h>
+
+/*
+ * ID info:
+ * ID : Volts : ADC value : Bucket
+ * == ===== ========= ===========
+ * 0 : 0.102V: 58 : 0 - 81
+ * 1 : 0.211V: 120 : 82 - 150
+ * 2 : 0.319V: 181 : 151 - 211
+ * 3 : 0.427V: 242 : 212 - 274
+ * 4 : 0.542V: 307 : 275 - 342
+ * 5 : 0.666V: 378 : 343 - 411
+ * 6 : 0.781V: 444 : 412 - 477
+ * 7 : 0.900V: 511 : 478 - 545
+ * 8 : 1.023V: 581 : 546 - 613
+ * 9 : 1.137V: 646 : 614 - 675
+ * 10 : 1.240V: 704 : 676 - 733
+ * 11 : 1.343V: 763 : 734 - 795
+ * 12 : 1.457V: 828 : 796 - 861
+ * 13 : 1.576V: 895 : 862 - 925
+ * 14 : 1.684V: 956 : 926 - 989
+ * 15 : 1.800V: 1023 : 990 - 1023
+ */
+static const int id_readings[] = {
+ 81, 150, 211, 274, 342, 411, 477, 545,
+ 613, 675, 733, 795, 861, 925, 989, 1023
+};
+
+static int cached_board_id = -1;
+
+#define SARADC_BASE 0xFF100000
+#define SARADC_DATA (SARADC_BASE + 0)
+#define SARADC_CTRL (SARADC_BASE + 8)
+
+static u32 get_saradc_value(int chn)
+{
+ int timeout = 0;
+ u32 adc_value = 0;
+
+ writel(0, SARADC_CTRL);
+ udelay(2);
+
+ writel(0x28 | chn, SARADC_CTRL);
+ udelay(50);
+
+ timeout = 0;
+ do {
+ if (readl(SARADC_CTRL) & 0x40) {
+ adc_value = readl(SARADC_DATA) & 0x3FF;
+ goto stop_adc;
+ }
+
+ udelay(10);
+ } while (timeout++ < 100);
+
+stop_adc:
+ writel(0, SARADC_CTRL);
+
+ return adc_value;
+}
+
+static uint32_t get_adc_index(int chn)
+{
+ int i;
+ int adc_reading;
+
+ if (cached_board_id != -1)
+ return cached_board_id;
+
+ adc_reading = get_saradc_value(chn);
+ for (i = 0; i < ARRAY_SIZE(id_readings); i++) {
+ if (adc_reading <= id_readings[i]) {
+ debug("ADC reading %d, ID %d\n", adc_reading, i);
+ cached_board_id = i;
+ return i;
+ }
+ }
+
+ /* should die for impossible value */
+ return 0;
+}
+
+/*
+ * Extended by ADC_IN4
+ * 0x06 - SOC-RK3399
+ * 0x09 - DoorNet2 DDR3
+ * 0x0a - DoorNet2 LPDDR4
+ */
+static int pcb_rev = -1;
+
+void bd_hwrev_init(void)
+{
+#define GPIO4_BASE 0xff790000
+ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+ struct udevice *dev;
+
+ if (uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(clk_rk3399), &dev))
+ return;
+#endif
+
+ if (pcb_rev >= 0)
+ return;
+
+ /* D1, D0: input mode */
+ clrbits_le32(&regs->swport_ddr, (0x3 << 24));
+ pcb_rev = (readl(&regs->ext_port) >> 24) & 0x3;
+
+ if (pcb_rev == 0x3) {
+ /* Revision group A: 0x04 ~ 0x13 */
+ pcb_rev = 0x4 + get_adc_index(4);
+
+ } else if (pcb_rev == 0x1) {
+ int idx = get_adc_index(4);
+
+ /* Revision group B: 0x21 ~ 0x2f */
+ if (idx > 0) {
+ pcb_rev = 0x20 + idx;
+ }
+ }
+}
+
+#ifdef CONFIG_SPL_BUILD
+static struct board_ddrtype {
+ int rev;
+ const char *type;
+} ddrtypes[] = {
+ { 0x00, "lpddr3-samsung-4GB-1866" },
+ { 0x01, "lpddr3-samsung-4GB-1866" },
+ { 0x04, "ddr3-1866" },
+ { 0x06, "ddr3-1866" },
+ { 0x07, "lpddr4-100" },
+ { 0x09, "ddr3-1866" },
+ { 0x0a, "lpddr4-100" },
+ { 0x21, "lpddr4-100" },
+ { 0x22, "ddr3-1866" },
+};
+
+const char *rk3399_get_ddrtype(void) {
+ int i;
+
+ bd_hwrev_init();
+ printf("Board: rev%02x\n", pcb_rev);
+
+ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) {
+ if (ddrtypes[i].rev == pcb_rev)
+ return ddrtypes[i].type;
+ }
+
+ /* fallback to first subnode (ie, first included dtsi) */
+ return NULL;
+}
+#endif
+
+/* To override __weak symbols */
+u32 get_board_rev(void)
+{
+ return pcb_rev;
+}
+
+
--- /dev/null
+++ b/board/embedfire/doornet2/hwrev.h
@@ -0,0 +1,25 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can access it online at
+ * http://www.gnu.org/licenses/gpl-2.0.html.
+ */
+
+#ifndef __BD_HW_REV_H__
+#define __BD_HW_REV_H__
+
+extern void bd_hwrev_config_gpio(void);
+extern void bd_hwrev_init(void);
+extern u32 get_board_rev(void);
+
+#endif /* __BD_HW_REV_H__ */
+
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1372,6 +1372,8 @@ static void rkclk_init(struct rockchip_c
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
+
+ rk3399_saradc_set_clk(cru, 1000000);
}
static int rk3399_clk_probe(struct udevice *dev)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399
rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
}
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
struct rk3399_sdram_params *params)
{
@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info
clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
}
-#else
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
#include "sdram-rk3399-lpddr4-400.inc"
#include "sdram-rk3399-lpddr4-800.inc"
@@ -3011,22 +3010,43 @@ static int sdram_init(struct dram_info *
return 0;
}
+__weak const char *rk3399_get_ddrtype(void)
+{
+ return NULL;
+}
+
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
+ ofnode node = { .np = NULL };
+ const char *name;
int ret;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
- ret = dev_read_u32_array(dev, "rockchip,sdram-params",
- (u32 *)&plat->sdram_params,
- sizeof(plat->sdram_params) / sizeof(u32));
+ name = rk3399_get_ddrtype();
+ if (name)
+ node = dev_read_subnode(dev, name);
+ if (!ofnode_valid(node)) {
+ debug("Failed to read subnode %s\n", name);
+ node = dev_read_first_subnode(dev);
+ }
+
+ /* fallback to current node */
+ if (!ofnode_valid(node))
+ node = dev_ofnode(dev);
+
+ ret = ofnode_read_u32_array(node, "rockchip,sdram-params",
+ (u32 *)&plat->sdram_params,
+ sizeof(plat->sdram_params) / sizeof(u32));
+
if (ret) {
printf("%s: Cannot read rockchip,sdram-params %d\n",
__func__, ret);
return ret;
}
+
ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
if (ret)
printf("%s: regmap failed %d\n", __func__, ret);
@@ -3051,18 +3071,21 @@ static int conv_of_plat(struct udevice *
#endif
static const struct sdram_rk3399_ops rk3399_ops = {
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
+
.data_training_first = data_training_first,
.set_rate_index = switch_to_phy_index1,
.modify_param = modify_param,
.get_phy_index_params = get_phy_index_params,
-#else
+};
+
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+static const struct sdram_rk3399_ops lpddr4_ops = {
.data_training_first = lpddr4_mr_detect,
.set_rate_index = lpddr4_set_rate,
.modify_param = lpddr4_modify_param,
- .get_phy_index_params = lpddr4_get_phy_index_params,
-#endif
+ .get_phy_index_params = lpddr4_get_phy_index_params,
};
+#endif
static int rk3399_dmc_init(struct udevice *dev)
{
@@ -3081,7 +3104,17 @@ static int rk3399_dmc_init(struct udevic
return ret;
#endif
- priv->ops = &rk3399_ops;
+ if (params->base.dramtype == LPDDR4) {
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+ priv->ops = &lpddr4_ops;
+#else
+ printf("LPDDR4 support is disable\n");
+ return -EINVAL;
+#endif
+ } else {
+ priv->ops = &rk3399_ops;
+ }
+
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
--- /dev/null
+++ b/include/configs/doornet2.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_DOORNET2_H__
+#define __CONFIG_DOORNET2_H__
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+#endif
+

599
package/boot/uboot-rockchip/patches/311-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat1N.patch
View File

@@ -1,599 +0,0 @@
--- /dev/null
+++ b/arch/arm/dts/rk3566-lubancat-1n-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,dm-spl;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3566-lubancat-1n.dts
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "EmbedFire LubanCat-1N";
+ compatible = "embedfire,lubancat-1n", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ sys_led: sys-led {
+ label = "sys_led";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
+ };
+
+ dc_5v: dc-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_5v>;
+ };
+
+ pcie_3v3: pcie2-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 100ms, 100ms */
+ snps,reset-delays-us = <0 75000 100000>;
+
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2_level3
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk_level2
+ &gmac1m1_rgmii_bus_level3>;
+
+ tx_delay = <0x24>;
+ rx_delay = <0x08>;
+
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pmu_io_domains {
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&sdhci {
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ bus-width = <8>;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ supports-emmc;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ sys_led_pin: sys-status-led-pin {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
--- /dev/null
+++ b/configs/lubancat-1n-rk3566_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-lubancat-1n"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lubancat-1n.dtb"
+
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y

222
package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R5C-board.patch
View File

@@ -1,222 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-opc-h68k.dtb \
rk3568-mrkaio-m68s.dtb \
rk3568-nanopi-r5s.dtb \
+ rk3568-nanopi-r5c.dtb \
rk3566-quartz64-a.dtb \
rk3568-rock-3a.dtb
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ u-boot,dm-spl;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3568-evb.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R5C";
+ compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568";
+};
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -18,6 +18,11 @@ config TARGET_NANOPI_R5S_RK3568
help
NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
+config TARGET_NANOPI_R5C_RK3568
+ bool "NanoPi R5C board"
+ help
+ NanoPi R5C FriendlyElec is a board for Rockchp RK3568.
+
config TARGET_QUARTZ64_A_RK3566
bool "Quartz64 Model A RK3566 development board"
help
@@ -40,6 +45,7 @@ config SYS_MALLOC_F_LEN
source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
source "board/rockchip/evb_rk3568/Kconfig"
source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
+source "board/friendlyelec/nanopi-r5c-rk3568/Kconfig"
source "board/pine64/quartz64-a-rk3566/Kconfig"
endif
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NANOPI_R5C_RK3568
+
+config SYS_BOARD
+ default "nanopi-r5c-rk3568"
+
+config SYS_VENDOR
+ default "friendlyelec"
+
+config SYS_CONFIG_NAME
+ default "nanopi-r5c-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nanopi-r5c-rk3568.o
--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/nanopi-r5c-rk3568.c
@@ -0,0 +1,4 @@
+ // SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ */
--- /dev/null
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_NANOPI_R5C_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+++ b/include/configs/nanopi-r5c-rk3568.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NANOPI_R5C_RK3568_H
+#define __NANOPI_R5C_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif

23
package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch Normal file
View File

@@ -0,0 +1,23 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -157,6 +158,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-m4b.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-nanopi-r4s.dtb \
+ rk3399-nanopi-r4se.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
rk3399-pinephone-pro.dtb \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
@@ -197,7 +203,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
- rk3588-rock-5b.dtb
+ rk3588-rock-5b.dtb \
+ rk3588s-nanopi-r6c.dtb \
+ rk3588s-nanopi-r6s.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \

17
package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se-u-boot.dtsi Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3399-nanopi-r4s-u-boot.dtsi"
/ {
smbios {
smbios {
system {
product = "NanoPi R4SE";
};
baseboard {
product = "NanoPi R4SE";
};
};
};
};

17
package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT)
/dts-v1/;
#include "rk3399-nanopi-r4s.dts"
/ {
model = "FriendlyElec NanoPi R4SE";
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
};
&emmc_phy {
status = "okay";
};
&sdhci {
status = "okay";
};

21
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h66k-u-boot.dtsi Normal file
View File

@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdhci;
};
};
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

17
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h66k.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
*/
/dts-v1/;
#include "rk3568-opc-h66k.dtsi"
/ {
model = "Hinlink OPC-H66K";
compatible = "hinlink,opc-h66k", "rockchip,rk3568";
};
&vcc3v3_pcie {
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
};

619
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h66k.dtsi Normal file
View File

@@ -0,0 +1,619 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
led-boot = &power_led;
led-failsafe = &power_led;
led-running = &power_led;
led-upgrade = &power_led;
};
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&reset_button_pin>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <50>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_lan_pin>, <&led_power_pin>, <&led_wan_pin>;
led-lan {
label = "amber:lan";
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
};
power_led: led-power {
label = "green:power";
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
};
led-wan {
label = "blue:wan";
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
};
};
pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 100 150 200 255>;
#cooling-cells = <2>;
pwms = <&pwm0 0 50000 0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-name = "vcc12v_dcin";
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_sys";
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_usb";
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_usb_host";
vin-supply = <&vcc5v0_usb>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pcie";
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_logic";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_npu";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c5 {
status = "okay";
};
&i2s0_8ch {
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie3x2 {
num-lanes = <1>;
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
leds {
led_lan_pin: led-lan-pin {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_power_pin: led-power-pin {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_wan_pin: led-wan-pin {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rockchip-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0-usb-host-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sata0 {
status = "okay";
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

3
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi Normal file
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@@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-opc-h66k-u-boot.dtsi"

78
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h68k.dts Normal file
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@@ -0,0 +1,78 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
*/
/dts-v1/;
#include "rk3568-opc-h66k.dtsi"
/ {
model = "Hinlink OPC-H68K";
compatible = "hinlink,opc-h68k", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&vcc3v3_pcie {
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
};

3
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h69k-u-boot.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-opc-h66k-u-boot.dtsi"

74
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-opc-h69k.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2023 AmadeusGhost <amadeus@jmu.edu.cn>
*/
/dts-v1/;
#include "rk3568-opc-h66k.dtsi"
/ {
model = "HINLINK OPC-H69K Board";
compatible = "hinlink,opc-h69k", "rockchip,rk3568";
aliases {
ethernet0 = &gmac1;
};
vcc5v0_ahci: vcc5v0-ahci-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_pwr_en>;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_ahci";
vin-supply = <&vcc5v0_sys>;
};
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&pinctrl {
sata {
sata_pwr_en: sata-pwr-en {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sata0 {
target-supply = <&vcc5v0_ahci>;
};
&vcc3v3_pcie {
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
};

3
package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3588s-nanopi-r6s-u-boot.dtsi"

19
package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6c.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "rk3588s-nanopi-r6s.dts"
/ {
model = "FriendlyElec NanoPi R6C";
compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588";
gpio-leds {
led-lan1 {
label = "green:lan";
};
led-lan2 {
label = "green:user";
};
};
};

22
package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
#include "rk3588s-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
&rng {
status = "okay";
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
};

702
target/linux/rockchip/files-6.6/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts → package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6s.dts
View File

@@ -1,18 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588s.dtsi"
/ {
model = "RK3588 OPi 5 Plus";
compatible = "rockchip,rk3588-orangepi-5-plus", "rockchip,rk3588";
model = "FriendlyElec NanoPi R6S";
compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc;
mmc1 = &sdhci;
serial2 = &uart2;
@@ -22,42 +31,43 @@
stdout-path = "serial2:1500000n8";
};
gpio_leds: leds {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&reset_button_pin>;
button-reset {
debounce-interval = <50>;
gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 =<&leds_rgb>;
status = "okay";
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
blue_led@1 {
gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
label = "blue_led";
linux,default-trigger = "heartbeat";
linux,default-trigger-delay-ms = <0>;
led-lan1 {
label = "green:lan1";
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
};
green_led@2 {
gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
label = "green_led";
linux,default-trigger = "heartbeat";
linux,default-trigger-delay-ms = <0>;
led-lan2 {
label = "green:lan2";
gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 70 75 80 100>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm3 0 50000 0>;
#cooling-cells = <2>;
};
power_led: led-power {
label = "red:power";
gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
led-wan {
label = "green:wan";
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
};
};
vcc5v0_sys: vcc5v0-sys-regulator {
@@ -67,7 +77,38 @@
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_host_20: vcc5v0-host-20-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
};
vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
@@ -80,35 +121,18 @@
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
regulator-name = "vcc_3v3_sd_s0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
enable-active-high;
gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc_3v3_s3>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
enable-active-low;
};
vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usbdcin>;
pinctrl-0 = <&vcc3v3_sd_en>;
};
vbus5v0_typec: vbus5v0-typec-regulator {
@@ -117,99 +141,10 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
};
pcie20_avdd0v85: pcie20-avdd0v85-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd0v85";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&vdd_0v85_s0>;
};
pcie20_avdd1v8: pcie20-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
pcie30_avdd0v75: pcie30-avdd0v75-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v75";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
vin-supply = <&avdd_0v75_s0>;
};
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie2x1l0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <50000>;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie_eth";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
enable-active-low;
gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
startup-delay-us = <50000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
pinctrl-0 = <&vbus5v0_typec_en>;
};
};
@@ -217,20 +152,16 @@
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_b1 {
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
};
@@ -240,29 +171,23 @@
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-rxid";
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x42>;
/* rx_delay = <0x4f>; */
status = "okay";
};
&i2c0 {
@@ -305,153 +230,90 @@
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m2_xfer>;
status = "okay";
vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_npu_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
status = "okay";
usbc0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
status = "okay";
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_hs: endpoint {
remote-endpoint = <&usb_host0_xhci_drd_sw>;
};
};
port@1 {
reg = <1>;
usbc0_ss: endpoint {
remote-endpoint = <&usbdp_phy0_typec_ss>;
};
};
port@2 {
reg = <2>;
usbc0_sbu: endpoint {
remote-endpoint = <&usbdp_phy0_typec_sbu>;
};
};
};
};
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&pcie2x1l1 {
reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
es8388: audio-codec@11 {
compatible = "everest,es8388";
reg = <0x11>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
#sound-dai-cells = <0>;
};
};
&i2s0_8ch {
pinctrl-0 = <&i2s0_lrck
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
&pcie2x1l2 {
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
};
&pinctrl {
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
gpio-leds {
lan1_led_pin: lan1-led-pin {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
lan2_led_pin: lan2-led-pin {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
power_led_pin: power-led-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
wan_led_pin: wan-led-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwr: sdmmc_pwr {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
vcc3v3_sd_en: vcc3v3-sd-en {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-func {
leds_rgb: leds-rgb {
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
usb {
vbus5v0_typec_en: vbus5v0-typec-en {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_host20_en: vcc5v0-host20-en {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2m2_pins>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pwm3m1_pins>;
status = "okay";
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
@@ -459,36 +321,30 @@
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdmmc {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
max-frequency = <150000000>;
no-sdio;
no-mmc;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&spi0 {
assigned-clocks = <&cru CLK_SPI0>;
assigned-clock-rates = <200000000>;
num-cs = <2>;
status = "disabled";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
@@ -497,7 +353,7 @@
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
rk806single: rk806single@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
@@ -506,8 +362,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@@ -533,9 +388,49 @@
function = "pin_fun0";
};
rk806_dvs1_slp: dvs1-slp-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun1";
};
rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun2";
};
rk806_dvs1_rst: dvs1-rst-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun3";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fudr_moden0";
function = "pin_fun0";
};
rk806_dvs2_slp: dvs2-slp-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun1";
};
rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun2";
};
rk806_dvs2_rst: dvs2-rst-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun3";
};
rk806_dvs2_dvs: dvs2-dvs-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun4";
};
rk806_dvs2_gpio: dvs2-gpio-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun5";
};
rk806_dvs3_null: dvs3-null-pins {
@@ -543,6 +438,31 @@
function = "pin_fun0";
};
rk806_dvs3_slp: dvs3-slp-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun1";
};
rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun2";
};
rk806_dvs3_rst: dvs3-rst-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun3";
};
rk806_dvs3_dvs: dvs3-dvs-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun4";
};
rk806_dvs3_gpio: dvs3-gpio-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun5";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
@@ -564,7 +484,6 @@
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -813,71 +732,12 @@
};
};
&spi4 {
assigned-clocks = <&cru CLK_SPI4>;
assigned-clock-rates = <200000000>;
num-cs = <2>;
status = "disabled";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&uart9 {
pinctrl-names = "default";
pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
status = "okay";
};
&tsadc {
status = "okay";
};
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
rockchip,skip-scan-in-resume;
status = "okay";
};
&pcie2x1l1 {
reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
rockchip,init-delay-ms = <100>;
status = "okay";
};
&pcie2x1l2 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
rockchip,typec-vbus-det;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
@@ -886,7 +746,7 @@
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
@@ -894,55 +754,6 @@
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usbdp_phy0 {
orientation-switch;
mode-switch;
status = "okay";
sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_typec_ss: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_ss>;
};
usbdp_phy0_typec_sbu: endpoint@1 {
reg = <1>;
remote-endpoint = <&usbc0_sbu>;
};
};
};
&usbdp_phy0_dp {
status = "okay";
};
&usbdp_phy0_u3 {
status = "okay";
};
&usbdp_phy1 {
rockchip,dp-lane-mux = <2 3>;
status = "okay";
};
&usbdp_phy1_dp {
status = "okay";
};
&usbdp_phy1_u3 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
@@ -950,34 +761,3 @@
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
usb-role-switch;
dr_mode = "otg";
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usb_host0_xhci_drd_sw: endpoint {
remote-endpoint = <&usbc0_hs>;
};
};
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&wdt {
status = "okay";
};

114
package/boot/uboot-rockchip/src/configs/doornet1-rk3328_defconfig Normal file
View File

@@ -0,0 +1,114 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

82
package/boot/uboot-rockchip/src/configs/doornet2-rk3399_defconfig Normal file
View File

@@ -0,0 +1,82 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

52
package/boot/uboot-rockchip/src/configs/lubancat-1-rk3566_defconfig
View File

@@ -1,83 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-lubancat-1n"
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_API=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lubancat-1n.dtb"
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

85
package/boot/uboot-rockchip/src/configs/lubancat-1n-rk3566_defconfig Normal file
View File

@@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

46
package/boot/uboot-rockchip/src/configs/lubancat-2-rk3568_defconfig
View File

@@ -1,39 +1,51 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -46,14 +58,28 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

46
package/boot/uboot-rockchip/src/configs/lubancat-2n-rk3568_defconfig
View File

@@ -1,39 +1,51 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -46,14 +58,28 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

71
package/boot/uboot-rockchip/src/configs/lubancat-4-rk3588s_defconfig Normal file
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@@ -0,0 +1,71 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

71
package/boot/uboot-rockchip/src/configs/lubancat-5-rk3588_defconfig Normal file
View File

@@ -0,0 +1,71 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

82
package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig Normal file
View File

@@ -0,0 +1,82 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

71
package/boot/uboot-rockchip/src/configs/nanopi-r6c-rk3588s_defconfig Normal file
View File

@@ -0,0 +1,71 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-r6c"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

71
package/boot/uboot-rockchip/src/configs/nanopi-r6s-rk3588s_defconfig Normal file
View File

@@ -0,0 +1,71 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-r6s"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

85
package/boot/uboot-rockchip/src/configs/opc-h66k-rk3568_defconfig Normal file
View File

@@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h66k"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h66k.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

85
package/boot/uboot-rockchip/src/configs/opc-h68k-rk3568_defconfig Normal file
View File

@@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

85
package/boot/uboot-rockchip/src/configs/opc-h69k-rk3568_defconfig Normal file
View File

@@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h69k"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h69k.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

14
target/linux/generic/backport-6.1/101-net-Remove-the-obsolte-u64_stats_fetch_-_irq-users-d.patch
View File

@@ -157,7 +157,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
stats->tx_dropped = tx_drops;
--- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
@@ -957,7 +957,7 @@ unsigned int aq_ring_fill_stats_data(str
@@ -941,7 +941,7 @@ unsigned int aq_ring_fill_stats_data(str
/* This data should mimic aq_ethtool_queue_rx_stat_names structure */
do {
count = 0;
@@ -166,7 +166,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
data[count] = self->stats.rx.packets;
data[++count] = self->stats.rx.jumbo_packets;
data[++count] = self->stats.rx.lro_packets;
@@ -974,15 +974,15 @@ unsigned int aq_ring_fill_stats_data(str
@@ -958,15 +958,15 @@ unsigned int aq_ring_fill_stats_data(str
data[++count] = self->stats.rx.xdp_tx;
data[++count] = self->stats.rx.xdp_invalid;
data[++count] = self->stats.rx.xdp_redirect;
@@ -960,7 +960,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -9051,10 +9051,10 @@ static void ixgbe_get_ring_stats64(struc
@@ -9047,10 +9047,10 @@ static void ixgbe_get_ring_stats64(struc
if (ring) {
do {
@@ -973,7 +973,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
stats->tx_packets += packets;
stats->tx_bytes += bytes;
}
@@ -9074,10 +9074,10 @@ static void ixgbe_get_stats64(struct net
@@ -9070,10 +9070,10 @@ static void ixgbe_get_stats64(struct net
if (ring) {
do {
@@ -1094,7 +1094,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
es->refill_error += refill_error;
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -2008,7 +2008,7 @@ mvpp2_get_xdp_stats(struct mvpp2_port *p
@@ -2033,7 +2033,7 @@ mvpp2_get_xdp_stats(struct mvpp2_port *p
cpu_stats = per_cpu_ptr(port->stats, cpu);
do {
@@ -1103,7 +1103,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
xdp_redirect = cpu_stats->xdp_redirect;
xdp_pass = cpu_stats->xdp_pass;
xdp_drop = cpu_stats->xdp_drop;
@@ -2016,7 +2016,7 @@ mvpp2_get_xdp_stats(struct mvpp2_port *p
@@ -2041,7 +2041,7 @@ mvpp2_get_xdp_stats(struct mvpp2_port *p
xdp_xmit_err = cpu_stats->xdp_xmit_err;
xdp_tx = cpu_stats->xdp_tx;
xdp_tx_err = cpu_stats->xdp_tx_err;
@@ -1112,7 +1112,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
xdp_stats->xdp_redirect += xdp_redirect;
xdp_stats->xdp_pass += xdp_pass;
@@ -5115,12 +5115,12 @@ mvpp2_get_stats64(struct net_device *dev
@@ -5140,12 +5140,12 @@ mvpp2_get_stats64(struct net_device *dev
cpu_stats = per_cpu_ptr(port->stats, cpu);
do {

2
target/linux/generic/backport-6.1/102-drivers-net-convert-to-boolean-for-the-mac_managed_p.patch
View File

@@ -14,7 +14,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -2234,7 +2234,7 @@ static int fec_enet_mii_probe(struct net
@@ -2236,7 +2236,7 @@ static int fec_enet_mii_probe(struct net
fep->link = 0;
fep->full_duplex = 0;

2
target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
View File

@@ -148,7 +148,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* of_find_node_by_phandle - Find a node given a phandle
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -2326,8 +2326,8 @@ of_register_spi_device(struct spi_contro
@@ -2330,8 +2330,8 @@ of_register_spi_device(struct spi_contro
}
/* Select device driver */

703
target/linux/generic/config-6.6
View File

File diff suppressed because it is too large Load Diff

69
target/linux/generic/files/block/partitions/fit.c
View File

@@ -88,11 +88,17 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
const u32 *image_offset_be, *image_len_be, *image_pos_be;
int ret = 1, node, images, config;
const char *image_name, *image_type, *image_description, *config_default,
*config_description, *config_loadables;
*config_description, *config_loadables, *bootconf_c;
int image_name_len, image_type_len, image_description_len, config_default_len,
config_description_len, config_loadables_len;
config_description_len, config_loadables_len, bootconf_len;
sector_t start_sect, nr_sects;
size_t label_min;
struct device_node *np = NULL;
char *bootconf = NULL, *bootconf_term;
const char *loadable;
const char *select_rootfs = NULL;
bool found;
int loadables_rem_len, loadable_len;
if (fit_start_sector % (1<<(PAGE_SHIFT - SECTOR_SHIFT)))
return -ERANGE;
@@ -118,7 +124,6 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
dsectors = (dsectors>sectors)?sectors:dsectors;
dsize = dsectors << SECTOR_SHIFT;
size = fdt_totalsize(init_fit);
/* silently skip non-external-data legacy FIT images */
@@ -138,6 +143,19 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
if (!fit)
return -ENOMEM;
np = of_find_node_by_path("/chosen");
if (np) {
bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
if (bootconf_c && bootconf_len)
bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
}
if (bootconf) {
bootconf_term = strchr(bootconf, '#');
if (bootconf_term)
*bootconf_term = '\0';
}
config = fdt_path_offset(fit, FIT_CONFS_PATH);
if (config < 0) {
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_CONFS_PATH, images);
@@ -147,15 +165,15 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
config_default = fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
if (!config_default) {
if (!config_default && !bootconf) {
printk(KERN_ERR "FIT: Cannot find default configuration\n");
ret = -ENOENT;
goto ret_out;
}
node = fdt_subnode_offset(fit, config, config_default);
node = fdt_subnode_offset(fit, config, bootconf?:config_default);
if (node < 0) {
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", config_default, node);
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", bootconf?:config_default, node);
ret = -ENOENT;
goto ret_out;
}
@@ -163,9 +181,16 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
config_description = fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP, &config_loadables_len);
printk(KERN_DEBUG "FIT: Default configuration: \"%s\"%s%s%s\n", config_default,
printk(KERN_DEBUG "FIT: %s configuration: \"%s\"%s%s%s\n",
bootconf?"Selected":"Default", bootconf?:config_default,
config_description?" (":"", config_description?:"", config_description?")":"");
if (!config_loadables || !config_loadables_len) {
printk(KERN_ERR "FIT: No loadables configured in \"%s\"\n", bootconf?:config_default);
ret = -ENOENT;
goto ret_out;
}
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
@@ -202,6 +227,22 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
if (strcmp(image_type, FIT_FILESYSTEM_PROP))
continue;
/* check if sub-image is part of configured loadables */
found = false;
loadable = config_loadables;
loadables_rem_len = config_loadables_len;
while (loadables_rem_len > 1) {
loadable_len = strnlen(loadable, loadables_rem_len - 1) + 1;
loadables_rem_len -= loadable_len;
if (!strncmp(image_name, loadable, loadable_len)) {
found = true;
break;
}
loadable += loadable_len;
}
if (!found)
continue;
if (image_pos & ((1 << PAGE_SHIFT)-1)) {
printk(KERN_ERR "FIT: image %s start not aligned to page boundaries, skipping\n", image_name);
continue;
@@ -222,7 +263,8 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
}
put_partition(state, ++(*slot), fit_start_sector + start_sect, nr_sects);
state->parts[*slot].flags = 0;
state->parts[*slot].flags = ADDPART_FLAG_READONLY;
state->parts[*slot].has_info = true;
info = &state->parts[*slot].info;
label_min = min_t(int, sizeof(info->volname) - 1, image_name_len);
@@ -232,14 +274,16 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
snprintf(tmp, sizeof(tmp), "(%s)", info->volname);
strlcat(state->pp_buf, tmp, PAGE_SIZE);
state->parts[*slot].has_info = true;
if (config_loadables && !strcmp(image_name, config_loadables)) {
printk(KERN_DEBUG "FIT: selecting configured loadable \"%s\" to be root filesystem\n", image_name);
/* Mark first loadable listed to be mounted as rootfs */
if (!strcmp(image_name, config_loadables)) {
select_rootfs = image_name;
state->parts[*slot].flags |= ADDPART_FLAG_ROOTDEV;
}
}
if (select_rootfs)
printk(KERN_DEBUG "FIT: selecting configured loadable \"%s\" to be root filesystem\n", select_rootfs);
if (add_remain && (imgmaxsect + MIN_FREE_SECT) < dsectors) {
put_partition(state, ++(*slot), fit_start_sector + imgmaxsect, dsectors - imgmaxsect);
state->parts[*slot].flags = 0;
@@ -249,6 +293,7 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
strlcat(state->pp_buf, tmp, PAGE_SIZE);
}
ret_out:
kfree(bootconf);
kfree(fit);
return ret;
}

533
target/linux/generic/files/drivers/bcma/fallback-sprom.c Normal file
View File

@@ -0,0 +1,533 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* BCMA Fallback SPROM Driver
*
* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>
*/
#include <linux/bcma/bcma.h>
#include <linux/etherdevice.h>
#include <linux/firmware.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
#define BCMA_FBS_MAX_SIZE 468
/* SPROM Extraction */
#define SPOFF(offset) ((offset) / sizeof(u16))
#define SPEX(_outvar, _offset, _mask, _shift) \
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
#define SPEX32(_outvar, _offset, _mask, _shift) \
out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
in[SPOFF(_offset)]) & (_mask)) >> (_shift))
#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
do { \
SPEX(_field[0], _offset + 0, _mask, _shift); \
SPEX(_field[1], _offset + 2, _mask, _shift); \
SPEX(_field[2], _offset + 4, _mask, _shift); \
SPEX(_field[3], _offset + 6, _mask, _shift); \
SPEX(_field[4], _offset + 8, _mask, _shift); \
SPEX(_field[5], _offset + 10, _mask, _shift); \
SPEX(_field[6], _offset + 12, _mask, _shift); \
SPEX(_field[7], _offset + 14, _mask, _shift); \
} while (0)
struct bcma_fbs {
struct device *dev;
struct list_head list;
struct ssb_sprom sprom;
u32 pci_bus;
u32 pci_dev;
bool devid_override;
};
static DEFINE_SPINLOCK(bcma_fbs_lock);
static struct list_head bcma_fbs_list = LIST_HEAD_INIT(bcma_fbs_list);
int bcma_get_fallback_sprom(struct bcma_bus *bus, struct ssb_sprom *out)
{
struct bcma_fbs *pos;
u32 pci_bus, pci_dev;
if (bus->hosttype != BCMA_HOSTTYPE_PCI)
return -ENOENT;
pci_bus = bus->host_pci->bus->number;
pci_dev = PCI_SLOT(bus->host_pci->devfn);
list_for_each_entry(pos, &bcma_fbs_list, list) {
if (pos->pci_bus != pci_bus ||
pos->pci_dev != pci_dev)
continue;
if (pos->devid_override)
bus->host_pci->device = pos->sprom.dev_id;
memcpy(out, &pos->sprom, sizeof(struct ssb_sprom));
dev_info(pos->dev, "requested by [%x:%x]",
pos->pci_bus, pos->pci_dev);
return 0;
}
pr_err("unable to fill SPROM for [%x:%x]\n", pci_bus, pci_dev);
return -EINVAL;
}
static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
{
u16 v;
u8 gain;
v = in[SPOFF(offset)];
gain = (v & mask) >> shift;
if (gain == 0xFF) {
gain = 8; /* If unset use 2dBm */
} else {
/* Q5.2 Fractional part is stored in 0xC0 */
gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
}
return (s8)gain;
}
static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
{
static const u16 pwr_info_offset[] = {
SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
};
u16 o;
int i;
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
ARRAY_SIZE(out->core_pwr_info));
SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
SSB_SPROM4_TXPID2G0_SHIFT);
SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
SSB_SPROM4_TXPID2G1_SHIFT);
SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
SSB_SPROM4_TXPID2G2_SHIFT);
SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
SSB_SPROM4_TXPID2G3_SHIFT);
SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
SSB_SPROM4_TXPID5GL0_SHIFT);
SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
SSB_SPROM4_TXPID5GL1_SHIFT);
SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
SSB_SPROM4_TXPID5GL2_SHIFT);
SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
SSB_SPROM4_TXPID5GL3_SHIFT);
SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
SSB_SPROM4_TXPID5G0_SHIFT);
SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
SSB_SPROM4_TXPID5G1_SHIFT);
SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
SSB_SPROM4_TXPID5G2_SHIFT);
SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
SSB_SPROM4_TXPID5G3_SHIFT);
SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
SSB_SPROM4_TXPID5GH0_SHIFT);
SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
SSB_SPROM4_TXPID5GH1_SHIFT);
SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
SSB_SPROM4_TXPID5GH2_SHIFT);
SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
SSB_SPROM4_TXPID5GH3_SHIFT);
SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
/* Extract core's power info */
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
o = pwr_info_offset[i];
SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_MAXP, 0);
SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GH_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
}
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
SSB_SROM8_FEM_ANTSWLUT_SHIFT);
SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
SSB_SROM8_FEM_ANTSWLUT_SHIFT);
SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
SSB_SPROM8_ANTAVAIL_A_SHIFT);
SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
SSB_SPROM8_ANTAVAIL_BG_SHIFT);
SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
SSB_SPROM8_ITSSI_BG_SHIFT);
SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
SSB_SPROM8_ITSSI_A_SHIFT);
SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
SSB_SPROM8_MAXP_AL_SHIFT);
SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
SSB_SPROM8_GPIOA_P1_SHIFT);
SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
SSB_SPROM8_GPIOB_P3_SHIFT);
SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
SSB_SPROM8_TRI5G_SHIFT);
SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
SSB_SPROM8_TRI5GH_SHIFT);
SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
SSB_SPROM8_RXPO2G_SHIFT);
SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
SSB_SPROM8_RXPO5G_SHIFT);
SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
SSB_SPROM8_RSSISMC2G_SHIFT);
SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
SSB_SPROM8_RSSISAV2G_SHIFT);
SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
SSB_SPROM8_BXA2G_SHIFT);
SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
SSB_SPROM8_RSSISMC5G_SHIFT);
SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
SSB_SPROM8_RSSISAV5G_SHIFT);
SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
SSB_SPROM8_BXA5G_SHIFT);
SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
/* Extract the antenna gain values. */
out->antenna_gain.a0 = sprom_extract_antgain(in,
SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN0,
SSB_SPROM8_AGAIN0_SHIFT);
out->antenna_gain.a1 = sprom_extract_antgain(in,
SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN1,
SSB_SPROM8_AGAIN1_SHIFT);
out->antenna_gain.a2 = sprom_extract_antgain(in,
SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN2,
SSB_SPROM8_AGAIN2_SHIFT);
out->antenna_gain.a3 = sprom_extract_antgain(in,
SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN3,
SSB_SPROM8_AGAIN3_SHIFT);
SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
SSB_SPROM8_LEDDC_ON_SHIFT);
SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
SSB_SPROM8_LEDDC_OFF_SHIFT);
SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
SSB_SPROM8_TXRXC_SWITCH_SHIFT);
SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
SSB_SPROM8_THERMAL_TRESH_SHIFT);
SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
SSB_SPROM8_THERMAL_OFFSET_SHIFT);
SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
SSB_SPROM8_TEMPDELTA_PHYCAL,
SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
SSB_SPROM8_TEMPDELTA_HYSTERESIS,
SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
}
static int sprom_extract(struct bcma_fbs *priv, const u16 *in, u16 size)
{
struct ssb_sprom *out = &priv->sprom;
memset(out, 0, sizeof(*out));
out->revision = in[size - 1] & 0x00FF;
if (out->revision < 8 || out->revision > 11) {
dev_warn(priv->dev,
"Unsupported SPROM revision %d detected."
" Will extract v8\n",
out->revision);
out->revision = 8;
}
sprom_extract_r8(out, in);
return 0;
}
static void bcma_fbs_fixup(struct bcma_fbs *priv, u16 *sprom)
{
struct device_node *node = priv->dev->of_node;
u32 fixups, off, val;
int i = 0;
if (!of_get_property(node, "brcm,sprom-fixups", &fixups))
return;
fixups /= sizeof(u32);
dev_info(priv->dev, "patching SPROM with %u fixups...\n", fixups >> 1);
while (i < fixups) {
if (of_property_read_u32_index(node, "brcm,sprom-fixups",
i++, &off)) {
dev_err(priv->dev, "error reading fixup[%u] offset\n",
i - 1);
return;
}
if (of_property_read_u32_index(node, "brcm,sprom-fixups",
i++, &val)) {
dev_err(priv->dev, "error reading fixup[%u] value\n",
i - 1);
return;
}
dev_dbg(priv->dev, "fixup[%d]=0x%04x\n", off, val);
sprom[off] = val;
}
}
static bool sprom_override_devid(struct bcma_fbs *priv, struct ssb_sprom *out,
const u16 *in)
{
SPEX(dev_id, 0x0060, 0xFFFF, 0);
return !!out->dev_id;
}
static void bcma_fbs_set(struct bcma_fbs *priv, struct device_node *node)
{
struct ssb_sprom *sprom = &priv->sprom;
const struct firmware *fw;
const char *sprom_name;
int err;
if (of_property_read_string(node, "brcm,sprom", &sprom_name))
sprom_name = NULL;
if (sprom_name) {
err = request_firmware_direct(&fw, sprom_name, priv->dev);
if (err)
dev_err(priv->dev, "%s load error\n", sprom_name);
} else {
err = -ENOENT;
}
if (err) {
sprom->revision = 0x02;
sprom->board_rev = 0x0017;
sprom->country_code = 0x00;
sprom->ant_available_bg = 0x03;
sprom->pa0b0 = 0x15ae;
sprom->pa0b1 = 0xfa85;
sprom->pa0b2 = 0xfe8d;
sprom->pa1b0 = 0xffff;
sprom->pa1b1 = 0xffff;
sprom->pa1b2 = 0xffff;
sprom->gpio0 = 0xff;
sprom->gpio1 = 0xff;
sprom->gpio2 = 0xff;
sprom->gpio3 = 0xff;
sprom->maxpwr_bg = 0x4c;
sprom->itssi_bg = 0x00;
sprom->boardflags_lo = 0x2848;
sprom->boardflags_hi = 0x0000;
priv->devid_override = false;
dev_warn(priv->dev, "using basic SPROM\n");
} else {
size_t size = min(fw->size, (size_t) BCMA_FBS_MAX_SIZE);
u16 tmp_sprom[BCMA_FBS_MAX_SIZE >> 1];
u32 i, j;
for (i = 0, j = 0; i < size; i += 2, j++)
tmp_sprom[j] = (fw->data[i] << 8) | fw->data[i + 1];
release_firmware(fw);
bcma_fbs_fixup(priv, tmp_sprom);
sprom_extract(priv, tmp_sprom, size >> 1);
priv->devid_override = sprom_override_devid(priv, sprom,
tmp_sprom);
}
}
static int bcma_fbs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct bcma_fbs *priv;
unsigned long flags;
u8 mac[ETH_ALEN];
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
bcma_fbs_set(priv, node);
of_property_read_u32(node, "pci-bus", &priv->pci_bus);
of_property_read_u32(node, "pci-dev", &priv->pci_dev);
of_get_mac_address(node, mac);
if (is_valid_ether_addr(mac)) {
dev_info(dev, "mtd mac %pM\n", mac);
} else {
eth_random_addr(mac);
dev_info(dev, "random mac %pM\n", mac);
}
memcpy(priv->sprom.il0mac, mac, ETH_ALEN);
memcpy(priv->sprom.et0mac, mac, ETH_ALEN);
memcpy(priv->sprom.et1mac, mac, ETH_ALEN);
memcpy(priv->sprom.et2mac, mac, ETH_ALEN);
spin_lock_irqsave(&bcma_fbs_lock, flags);
list_add(&priv->list, &bcma_fbs_list);
spin_unlock_irqrestore(&bcma_fbs_lock, flags);
dev_info(dev, "registered SPROM for [%x:%x]\n",
priv->pci_bus, priv->pci_dev);
return 0;
}
static const struct of_device_id bcma_fbs_of_match[] = {
{ .compatible = "brcm,bcma-sprom", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, bcma_fbs_of_match);
static struct platform_driver bcma_fbs_driver = {
.probe = bcma_fbs_probe,
.driver = {
.name = "bcma-sprom",
.of_match_table = bcma_fbs_of_match,
},
};
int __init bcma_fbs_register(void)
{
return platform_driver_register(&bcma_fbs_driver);
}

744
target/linux/generic/files/drivers/ssb/fallback-sprom.c Normal file
View File

@@ -0,0 +1,744 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SSB Fallback SPROM Driver
*
* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>
*/
#include <linux/etherdevice.h>
#include <linux/firmware.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
#include <linux/ssb/ssb.h>
#define SSB_FBS_MAX_SIZE 440
/* Get the word-offset for a SSB_SPROM_XXX define. */
#define SPOFF(offset) ((offset) / sizeof(u16))
/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
#define SPEX16(_outvar, _offset, _mask, _shift) \
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
#define SPEX32(_outvar, _offset, _mask, _shift) \
out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
in[SPOFF(_offset)]) & (_mask)) >> (_shift))
#define SPEX(_outvar, _offset, _mask, _shift) \
SPEX16(_outvar, _offset, _mask, _shift)
#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
do { \
SPEX(_field[0], _offset + 0, _mask, _shift); \
SPEX(_field[1], _offset + 2, _mask, _shift); \
SPEX(_field[2], _offset + 4, _mask, _shift); \
SPEX(_field[3], _offset + 6, _mask, _shift); \
SPEX(_field[4], _offset + 8, _mask, _shift); \
SPEX(_field[5], _offset + 10, _mask, _shift); \
SPEX(_field[6], _offset + 12, _mask, _shift); \
SPEX(_field[7], _offset + 14, _mask, _shift); \
} while (0)
struct ssb_fbs {
struct device *dev;
struct list_head list;
struct ssb_sprom sprom;
u32 pci_bus;
u32 pci_dev;
bool devid_override;
};
static DEFINE_SPINLOCK(ssb_fbs_lock);
static struct list_head ssb_fbs_list = LIST_HEAD_INIT(ssb_fbs_list);
int ssb_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
{
struct ssb_fbs *pos;
u32 pci_bus, pci_dev;
if (bus->bustype != SSB_BUSTYPE_PCI)
return -ENOENT;
pci_bus = bus->host_pci->bus->number;
pci_dev = PCI_SLOT(bus->host_pci->devfn);
list_for_each_entry(pos, &ssb_fbs_list, list) {
if (pos->pci_bus != pci_bus ||
pos->pci_dev != pci_dev)
continue;
if (pos->devid_override)
bus->host_pci->device = pos->sprom.dev_id;
memcpy(out, &pos->sprom, sizeof(struct ssb_sprom));
dev_info(pos->dev, "requested by [%x:%x]",
pos->pci_bus, pos->pci_dev);
return 0;
}
pr_err("unable to fill SPROM for [%x:%x]\n", pci_bus, pci_dev);
return -EINVAL;
}
static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
u16 mask, u16 shift)
{
u16 v;
u8 gain;
v = in[SPOFF(offset)];
gain = (v & mask) >> shift;
if (gain == 0xFF)
gain = 2; /* If unset use 2dBm */
if (sprom_revision == 1) {
/* Convert to Q5.2 */
gain <<= 2;
} else {
/* Q5.2 Fractional part is stored in 0xC0 */
gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
}
return (s8)gain;
}
static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
{
SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
SSB_SPROM2_MAXP_A_LO_SHIFT);
}
static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
{
SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
SSB_SPROM1_ETHPHY_ET1A_SHIFT);
SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
if (out->revision == 1)
SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
SSB_SPROM1_BINF_CCODE_SHIFT);
SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
SSB_SPROM1_BINF_ANTA_SHIFT);
SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
SSB_SPROM1_BINF_ANTBG_SHIFT);
SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
SSB_SPROM1_GPIOA_P1_SHIFT);
SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
SSB_SPROM1_GPIOB_P3_SHIFT);
SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
SSB_SPROM1_MAXPWR_A_SHIFT);
SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
SSB_SPROM1_ITSSI_A_SHIFT);
SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
/* Extract the antenna gain values. */
out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
SSB_SPROM1_AGAIN,
SSB_SPROM1_AGAIN_BG,
SSB_SPROM1_AGAIN_BG_SHIFT);
out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
SSB_SPROM1_AGAIN,
SSB_SPROM1_AGAIN_A,
SSB_SPROM1_AGAIN_A_SHIFT);
if (out->revision >= 2)
sprom_extract_r23(out, in);
}
/* Revs 4 5 and 8 have partially shared layout */
static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
{
SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
}
static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
{
static const u16 pwr_info_offset[] = {
SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
};
int i;
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
ARRAY_SIZE(out->core_pwr_info));
SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
SSB_SPROM4_ETHPHY_ET1A_SHIFT);
SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
if (out->revision == 4) {
SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
} else {
SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
}
SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
SSB_SPROM4_ANTAVAIL_A_SHIFT);
SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
SSB_SPROM4_ANTAVAIL_BG_SHIFT);
SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
SSB_SPROM4_ITSSI_BG_SHIFT);
SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
SSB_SPROM4_ITSSI_A_SHIFT);
if (out->revision == 4) {
SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
SSB_SPROM4_GPIOA_P1_SHIFT);
SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
SSB_SPROM4_GPIOB_P3_SHIFT);
} else {
SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
SSB_SPROM5_GPIOA_P1_SHIFT);
SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
SSB_SPROM5_GPIOB_P3_SHIFT);
}
/* Extract the antenna gain values. */
out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
SSB_SPROM4_AGAIN01,
SSB_SPROM4_AGAIN0,
SSB_SPROM4_AGAIN0_SHIFT);
out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
SSB_SPROM4_AGAIN01,
SSB_SPROM4_AGAIN1,
SSB_SPROM4_AGAIN1_SHIFT);
out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
SSB_SPROM4_AGAIN23,
SSB_SPROM4_AGAIN2,
SSB_SPROM4_AGAIN2_SHIFT);
out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
SSB_SPROM4_AGAIN23,
SSB_SPROM4_AGAIN3,
SSB_SPROM4_AGAIN3_SHIFT);
/* Extract cores power info info */
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
u16 o = pwr_info_offset[i];
SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
SSB_SPROM4_2G_MAXP, 0);
SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
SSB_SPROM4_5G_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
SSB_SPROM4_5GH_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
}
sprom_extract_r458(out, in);
/* TODO - get remaining rev 4 stuff needed */
}
static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
{
int i;
u16 o;
static const u16 pwr_info_offset[] = {
SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
};
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
ARRAY_SIZE(out->core_pwr_info));
SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
SSB_SPROM8_ANTAVAIL_A_SHIFT);
SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
SSB_SPROM8_ANTAVAIL_BG_SHIFT);
SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
SSB_SPROM8_ITSSI_BG_SHIFT);
SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
SSB_SPROM8_ITSSI_A_SHIFT);
SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
SSB_SPROM8_MAXP_AL_SHIFT);
SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
SSB_SPROM8_GPIOA_P1_SHIFT);
SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
SSB_SPROM8_GPIOB_P3_SHIFT);
SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
SSB_SPROM8_TRI5G_SHIFT);
SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
SSB_SPROM8_TRI5GH_SHIFT);
SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
SSB_SPROM8_RXPO5G_SHIFT);
SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
SSB_SPROM8_RSSISMC2G_SHIFT);
SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
SSB_SPROM8_RSSISAV2G_SHIFT);
SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
SSB_SPROM8_BXA2G_SHIFT);
SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
SSB_SPROM8_RSSISMC5G_SHIFT);
SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
SSB_SPROM8_RSSISAV5G_SHIFT);
SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
SSB_SPROM8_BXA5G_SHIFT);
SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
/* Extract the antenna gain values. */
out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN0,
SSB_SPROM8_AGAIN0_SHIFT);
out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN1,
SSB_SPROM8_AGAIN1_SHIFT);
out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN2,
SSB_SPROM8_AGAIN2_SHIFT);
out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN3,
SSB_SPROM8_AGAIN3_SHIFT);
/* Extract cores power info info */
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
o = pwr_info_offset[i];
SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_MAXP, 0);
SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GH_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
}
/* Extract FEM info */
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
SSB_SPROM8_LEDDC_ON_SHIFT);
SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
SSB_SPROM8_LEDDC_OFF_SHIFT);
SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
SSB_SPROM8_TXRXC_SWITCH_SHIFT);
SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
SSB_SPROM8_THERMAL_TRESH_SHIFT);
SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
SSB_SPROM8_THERMAL_OFFSET_SHIFT);
SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
SSB_SPROM8_TEMPDELTA_PHYCAL,
SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
SSB_SPROM8_TEMPDELTA_HYSTERESIS,
SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
sprom_extract_r458(out, in);
/* TODO - get remaining rev 8 stuff needed */
}
static int sprom_extract(struct ssb_fbs *priv, const u16 *in, u16 size)
{
struct ssb_sprom *out = &priv->sprom;
memset(out, 0, sizeof(*out));
out->revision = in[size - 1] & 0x00FF;
switch (out->revision) {
case 1:
case 2:
case 3:
sprom_extract_r123(out, in);
break;
case 4:
case 5:
sprom_extract_r45(out, in);
break;
case 8:
sprom_extract_r8(out, in);
break;
default:
dev_warn(priv->dev,
"Unsupported SPROM revision %d detected."
" Will extract v1\n",
out->revision);
out->revision = 1;
sprom_extract_r123(out, in);
}
if (out->boardflags_lo == 0xFFFF)
out->boardflags_lo = 0; /* per specs */
if (out->boardflags_hi == 0xFFFF)
out->boardflags_hi = 0; /* per specs */
return 0;
}
static void ssb_fbs_fixup(struct ssb_fbs *priv, u16 *sprom)
{
struct device_node *node = priv->dev->of_node;
u32 fixups, off, val;
int i = 0;
if (!of_get_property(node, "brcm,sprom-fixups", &fixups))
return;
fixups /= sizeof(u32);
dev_info(priv->dev, "patching SPROM with %u fixups...\n", fixups >> 1);
while (i < fixups) {
if (of_property_read_u32_index(node, "brcm,sprom-fixups",
i++, &off)) {
dev_err(priv->dev, "error reading fixup[%u] offset\n",
i - 1);
return;
}
if (of_property_read_u32_index(node, "brcm,sprom-fixups",
i++, &val)) {
dev_err(priv->dev, "error reading fixup[%u] value\n",
i - 1);
return;
}
dev_dbg(priv->dev, "fixup[%d]=0x%04x\n", off, val);
sprom[off] = val;
}
}
static bool sprom_override_devid(struct ssb_fbs *priv, struct ssb_sprom *out,
const u16 *in)
{
SPEX(dev_id, SSB_SPROM1_PID, 0xFFFF, 0);
return !!out->dev_id;
}
static int ssb_fbs_set(struct ssb_fbs *priv, struct device_node *node)
{
struct ssb_sprom *sprom = &priv->sprom;
const struct firmware *fw;
const char *sprom_name;
int err;
if (of_property_read_string(node, "brcm,sprom", &sprom_name))
sprom_name = NULL;
if (sprom_name) {
err = request_firmware_direct(&fw, sprom_name, priv->dev);
if (err)
dev_err(priv->dev, "%s load error\n", sprom_name);
} else {
err = -ENOENT;
}
if (err) {
sprom->revision = 0x02;
sprom->board_rev = 0x0017;
sprom->country_code = 0x00;
sprom->ant_available_bg = 0x03;
sprom->pa0b0 = 0x15ae;
sprom->pa0b1 = 0xfa85;
sprom->pa0b2 = 0xfe8d;
sprom->pa1b0 = 0xffff;
sprom->pa1b1 = 0xffff;
sprom->pa1b2 = 0xffff;
sprom->gpio0 = 0xff;
sprom->gpio1 = 0xff;
sprom->gpio2 = 0xff;
sprom->gpio3 = 0xff;
sprom->maxpwr_bg = 0x4c;
sprom->itssi_bg = 0x00;
sprom->boardflags_lo = 0x2848;
sprom->boardflags_hi = 0x0000;
priv->devid_override = false;
dev_warn(priv->dev, "using basic SPROM\n");
} else {
size_t size = min(fw->size, (size_t) SSB_FBS_MAX_SIZE);
u16 tmp_sprom[SSB_FBS_MAX_SIZE >> 1];
u32 i, j;
for (i = 0, j = 0; i < size; i += 2, j++)
tmp_sprom[j] = (fw->data[i] << 8) | fw->data[i + 1];
release_firmware(fw);
ssb_fbs_fixup(priv, tmp_sprom);
sprom_extract(priv, tmp_sprom, size >> 1);
priv->devid_override = sprom_override_devid(priv, sprom,
tmp_sprom);
}
return 0;
}
static int ssb_fbs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct ssb_fbs *priv;
unsigned long flags;
u8 mac[ETH_ALEN];
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
ssb_fbs_set(priv, node);
of_property_read_u32(node, "pci-bus", &priv->pci_bus);
of_property_read_u32(node, "pci-dev", &priv->pci_dev);
of_get_mac_address(node, mac);
if (is_valid_ether_addr(mac)) {
dev_info(dev, "mtd mac %pM\n", mac);
} else {
eth_random_addr(mac);
dev_info(dev, "random mac %pM\n", mac);
}
memcpy(priv->sprom.il0mac, mac, ETH_ALEN);
memcpy(priv->sprom.et0mac, mac, ETH_ALEN);
memcpy(priv->sprom.et1mac, mac, ETH_ALEN);
memcpy(priv->sprom.et2mac, mac, ETH_ALEN);
spin_lock_irqsave(&ssb_fbs_lock, flags);
list_add(&priv->list, &ssb_fbs_list);
spin_unlock_irqrestore(&ssb_fbs_lock, flags);
dev_info(dev, "registered SPROM for [%x:%x]\n",
priv->pci_bus, priv->pci_dev);
return 0;
}
static const struct of_device_id ssb_fbs_of_match[] = {
{ .compatible = "brcm,ssb-sprom", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ssb_fbs_of_match);
static struct platform_driver ssb_fbs_driver = {
.probe = ssb_fbs_probe,
.driver = {
.name = "ssb-sprom",
.of_match_table = ssb_fbs_of_match,
},
};
int __init ssb_fbs_register(void)
{
return platform_driver_register(&ssb_fbs_driver);
}

38
target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
View File

@@ -1,38 +0,0 @@
From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
From: "Alexandros C. Couloumbis" <alex@ozo.com>
Date: Fri, 7 Jul 2017 17:14:51 +0200
Subject: hack: arch: powerpc: drop register save/restore library from modules
Upstream GCC uses a libgcc function for saving/restoring registers. This
makes the code bigger, and upstream kernels need to carry that function
for every single kernel module. Our GCC is patched to avoid those
references, so we can drop the extra bloat for modules.
lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
---
arch/powerpc/Makefile | 1 -
1 file changed, 1 deletion(-)
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -42,19 +42,6 @@ machine-$(CONFIG_PPC64) += 64
machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
UTS_MACHINE := $(subst $(space),,$(machine-y))
-# XXX This needs to be before we override LD below
-ifdef CONFIG_PPC32
-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
-else
-ifeq ($(call ld-ifversion, -ge, 22500, y),y)
-# Have the linker provide sfpr if possible.
-# There is a corresponding test in arch/powerpc/lib/Makefile
-KBUILD_LDFLAGS_MODULE += --save-restore-funcs
-else
-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
-endif
-endif
-
ifdef CONFIG_CPU_LITTLE_ENDIAN
KBUILD_CFLAGS += -mlittle-endian
KBUILD_LDFLAGS += -EL

2
target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
View File

@@ -105,7 +105,7 @@ Subject: [PATCH] kernel: add block fit partition parser
/* everything is up and running, commence */
err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
if (err)
@@ -585,6 +597,11 @@ static bool blk_add_partition(struct gen
@@ -590,6 +602,11 @@ static bool blk_add_partition(struct gen
(state->parts[p].flags & ADDPART_FLAG_RAID))
md_autodetect_dev(part->bd_dev);

8
target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
View File

@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
obj-$(CONFIG_PROC_FS) += net-procfs.o
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -114,6 +114,7 @@
@@ -115,6 +115,7 @@
#include <linux/memcontrol.h>
#include <linux/prefetch.h>
#include <linux/compat.h>
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#include <linux/uaccess.h>
@@ -145,6 +146,7 @@
@@ -146,6 +147,7 @@
static DEFINE_MUTEX(proto_list_mutex);
static LIST_HEAD(proto_list);
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static void sock_def_write_space_wfree(struct sock *sk);
static void sock_def_write_space(struct sock *sk);
@@ -584,6 +586,18 @@ discard_and_relse:
@@ -585,6 +587,18 @@ discard_and_relse:
}
EXPORT_SYMBOL(__sk_receive_skb);
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
u32));
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
@@ -2187,9 +2201,11 @@ static void __sk_free(struct sock *sk)
@@ -2188,9 +2202,11 @@ static void __sk_free(struct sock *sk)
if (likely(sk->sk_net_refcnt))
sock_inuse_add(sock_net(sk), -1);

2
target/linux/generic/hack-6.1/902-debloat_proc.patch
View File

@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -4113,6 +4113,8 @@ static __net_initdata struct pernet_oper
@@ -4114,6 +4114,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

2
target/linux/generic/hack-6.6/410-block-fit-partition-parser.patch
View File

@@ -86,7 +86,7 @@
/* everything is up and running, commence */
err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
if (err)
@@ -579,6 +591,11 @@ static bool blk_add_partition(struct gen
@@ -584,6 +596,11 @@ static bool blk_add_partition(struct gen
(state->parts[p].flags & ADDPART_FLAG_RAID))
md_autodetect_dev(part->bd_dev);

2
target/linux/generic/hack-6.6/661-use_fq_codel_by_default.patch
View File

@@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -589,12 +589,13 @@ extern struct Qdisc_ops noop_qdisc_ops;
@@ -593,12 +593,13 @@ extern struct Qdisc_ops noop_qdisc_ops;
extern struct Qdisc_ops pfifo_fast_ops;
extern struct Qdisc_ops mq_qdisc_ops;
extern struct Qdisc_ops noqueue_qdisc_ops;

2
target/linux/generic/hack-6.6/902-debloat_proc.patch
View File

@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -4116,6 +4116,8 @@ static __net_initdata struct pernet_oper
@@ -4125,6 +4125,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

2
target/linux/generic/hack-6.6/952-add-net-conntrack-events-support-multiple-registrant.patch
View File

@@ -94,7 +94,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
#ifdef CONFIG_NF_CONNTRACK_EVENTS
--- a/include/net/netns/conntrack.h
+++ b/include/net/netns/conntrack.h
@@ -104,6 +104,9 @@ struct netns_ct {
@@ -105,6 +105,9 @@ struct netns_ct {
u8 sysctl_checksum;
struct ip_conntrack_stat __percpu *stat;

10
target/linux/generic/hack-6.6/999-revert-6.5-deprecated-API.patch
View File

@@ -44,7 +44,7 @@
#endif /* _LINUX_U64_STATS_SYNC_H */
--- a/drivers/thermal/thermal_core.c
+++ b/drivers/thermal/thermal_core.c
@@ -1270,7 +1270,7 @@ thermal_zone_device_register_with_trips(
@@ -1273,7 +1273,7 @@ thermal_zone_device_register_with_trips(
return ERR_PTR(-EINVAL);
}
@@ -53,7 +53,7 @@
return ERR_PTR(-EINVAL);
if (!thermal_class)
@@ -1393,6 +1393,17 @@ free_tz:
@@ -1395,6 +1395,17 @@ free_tz:
}
EXPORT_SYMBOL_GPL(thermal_zone_device_register_with_trips);
@@ -73,7 +73,7 @@
void *devdata,
--- a/drivers/thermal/thermal_trip.c
+++ b/drivers/thermal/thermal_trip.c
@@ -116,11 +116,29 @@ void __thermal_zone_set_trips(struct the
@@ -113,11 +113,29 @@ void __thermal_zone_set_trips(struct the
int __thermal_zone_get_trip(struct thermal_zone_device *tz, int trip_id,
struct thermal_trip *trip)
{
@@ -120,7 +120,7 @@
int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
int (*get_crit_temp) (struct thermal_zone_device *, int *);
int (*set_emul_temp) (struct thermal_zone_device *, int);
@@ -300,6 +304,14 @@ int thermal_acpi_critical_trip_temp(stru
@@ -302,6 +306,14 @@ int thermal_acpi_critical_trip_temp(stru
#endif
#ifdef CONFIG_THERMAL
@@ -135,7 +135,7 @@
struct thermal_zone_device *thermal_zone_device_register_with_trips(
const char *type,
struct thermal_trip *trips,
@@ -356,6 +368,15 @@ int thermal_zone_device_enable(struct th
@@ -358,6 +370,15 @@ int thermal_zone_device_enable(struct th
int thermal_zone_device_disable(struct thermal_zone_device *tz);
void thermal_zone_device_critical(struct thermal_zone_device *tz);
#else

6
target/linux/generic/pending-6.1/613-netfilter_optional_tcp_window_check.patch
View File

@@ -9,7 +9,7 @@ Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
--- a/net/netfilter/nf_conntrack_proto_tcp.c
+++ b/net/netfilter/nf_conntrack_proto_tcp.c
@@ -513,11 +513,15 @@ tcp_in_window(struct nf_conn *ct, enum i
@@ -515,11 +515,15 @@ tcp_in_window(struct nf_conn *ct, enum i
struct ip_ct_tcp *state = &ct->proto.tcp;
struct ip_ct_tcp_state *sender = &state->seen[dir];
struct ip_ct_tcp_state *receiver = &state->seen[!dir];
@@ -25,7 +25,7 @@ Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
/*
* Get the required data from the packet.
*/
@@ -1257,7 +1261,7 @@ int nf_conntrack_tcp_packet(struct nf_co
@@ -1259,7 +1263,7 @@ int nf_conntrack_tcp_packet(struct nf_co
IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED &&
timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK])
timeout = timeouts[TCP_CONNTRACK_UNACK];
@@ -34,7 +34,7 @@ Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS])
timeout = timeouts[TCP_CONNTRACK_RETRANS];
else
@@ -1573,6 +1577,9 @@ void nf_conntrack_tcp_init_net(struct ne
@@ -1575,6 +1579,9 @@ void nf_conntrack_tcp_init_net(struct ne
*/
tn->tcp_be_liberal = 0;

28
target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
View File

@@ -275,8 +275,8 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,
const struct tnl_ptk_info *tpi,
struct metadata_dst *tun_dst,
@@ -840,6 +966,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
skb_reset_network_header(skb);
@@ -855,6 +981,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
memset(skb->cb, 0, sizeof(struct inet6_skb_parm));
+ if (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&
@@ -303,7 +303,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);
err = dscp_ecn_decapsulate(tunnel, ipv6h, skb);
@@ -987,6 +1134,7 @@ static void init_tel_txopt(struct ipv6_t
@@ -1002,6 +1149,7 @@ static void init_tel_txopt(struct ipv6_t
opt->ops.opt_nflen = 8;
}
@@ -311,7 +311,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
/**
* ip6_tnl_addr_conflict - compare packet addresses to tunnel's own
* @t: the outgoing tunnel device
@@ -1278,6 +1426,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
@@ -1293,6 +1441,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
u8 protocol)
{
struct ip6_tnl *t = netdev_priv(dev);
@@ -319,7 +319,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
struct ipv6hdr *ipv6h;
const struct iphdr *iph;
int encap_limit = -1;
@@ -1377,6 +1526,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
@@ -1392,6 +1541,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);
dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);
@@ -338,7 +338,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))
return -1;
@@ -1530,6 +1691,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
@@ -1545,6 +1706,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
t->parms.link = p->link;
t->parms.proto = p->proto;
t->parms.fwmark = p->fwmark;
@@ -353,7 +353,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
dst_cache_reset(&t->dst_cache);
ip6_tnl_link_config(t);
}
@@ -1564,6 +1733,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
@@ -1579,6 +1748,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
p->flowinfo = u->flowinfo;
p->link = u->link;
p->proto = u->proto;
@@ -361,7 +361,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
memcpy(p->name, u->name, sizeof(u->name));
}
@@ -1950,6 +2120,15 @@ static int ip6_tnl_validate(struct nlatt
@@ -1965,6 +2135,15 @@ static int ip6_tnl_validate(struct nlatt
return 0;
}
@@ -377,7 +377,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
static void ip6_tnl_netlink_parms(struct nlattr *data[],
struct __ip6_tnl_parm *parms)
{
@@ -1987,6 +2166,46 @@ static void ip6_tnl_netlink_parms(struct
@@ -2002,6 +2181,46 @@ static void ip6_tnl_netlink_parms(struct
if (data[IFLA_IPTUN_FWMARK])
parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);
@@ -424,7 +424,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
}
static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev,
@@ -2070,6 +2289,12 @@ static void ip6_tnl_dellink(struct net_d
@@ -2085,6 +2304,12 @@ static void ip6_tnl_dellink(struct net_d
static size_t ip6_tnl_get_size(const struct net_device *dev)
{
@@ -437,7 +437,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
return
/* IFLA_IPTUN_LINK */
nla_total_size(4) +
@@ -2099,6 +2324,24 @@ static size_t ip6_tnl_get_size(const str
@@ -2114,6 +2339,24 @@ static size_t ip6_tnl_get_size(const str
nla_total_size(0) +
/* IFLA_IPTUN_FWMARK */
nla_total_size(4) +
@@ -462,7 +462,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
0;
}
@@ -2106,6 +2349,9 @@ static int ip6_tnl_fill_info(struct sk_b
@@ -2121,6 +2364,9 @@ static int ip6_tnl_fill_info(struct sk_b
{
struct ip6_tnl *tunnel = netdev_priv(dev);
struct __ip6_tnl_parm *parm = &tunnel->parms;
@@ -472,7 +472,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
@@ -2115,9 +2361,27 @@ static int ip6_tnl_fill_info(struct sk_b
@@ -2130,9 +2376,27 @@ static int ip6_tnl_fill_info(struct sk_b
nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||
@@ -501,7 +501,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
@@ -2157,6 +2421,7 @@ static const struct nla_policy ip6_tnl_p
@@ -2172,6 +2436,7 @@ static const struct nla_policy ip6_tnl_p
[IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 },
[IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG },
[IFLA_IPTUN_FWMARK] = { .type = NLA_U32 },

2
target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
View File

@@ -59,7 +59,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
}
--- a/net/netfilter/nft_flow_offload.c
+++ b/net/netfilter/nft_flow_offload.c
@@ -470,47 +470,14 @@ static struct nft_expr_type nft_flow_off
@@ -475,47 +475,14 @@ static struct nft_expr_type nft_flow_off
.owner = THIS_MODULE,
};

2
target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
View File

@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#ifdef CONFIG_RPS
remsd = oldsd->rps_ipi_list;
oldsd->rps_ipi_list = NULL;
@@ -11502,6 +11576,7 @@ static int __init net_dev_init(void)
@@ -11511,6 +11585,7 @@ static int __init net_dev_init(void)
INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
spin_lock_init(&sd->defer_lock);

2
target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
View File

@@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c
@@ -900,6 +900,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
@@ -905,6 +905,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
switch (event) {
case MHI_EE_SBL:
st = DEV_ST_TRANSITION_SBL;

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