rockchip: introduce vendor USB3 inno driver
Reference: faa767a9d0
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
@@ -429,6 +429,7 @@ CONFIG_PHY_ROCKCHIP_DP=y
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK
|
||||
|
||||
maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3328-u3phy
|
||||
|
||||
reg:
|
||||
- description: the base address of the USB 3.0 PHY
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: linestate
|
||||
description: host/otg linestate interrupt
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: u3phy-otg
|
||||
description: USB 3.0 PHY UTMI
|
||||
- const: u3phy-pipe
|
||||
description: USB 3.0 PHY Pipe
|
||||
|
||||
resets:
|
||||
maxItems: 6
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: u3phy-u2-por
|
||||
description: USB 2.0 logic of USB 3.0 PHY
|
||||
- const: u3phy-u3-por
|
||||
description: USB 3.0 logic of USB 3.0 PHY
|
||||
- const: u3phy-pipe-mac
|
||||
description: USB 3.0 PHY pipe MAC
|
||||
- const: u3phy-utmi-mac
|
||||
description: USB 3.0 PHY utmi MAC
|
||||
- const: u3phy-utmi-apb
|
||||
description: USB 3.0 PHY utmi apb
|
||||
- const: u3phy-pipe-apb
|
||||
description: USB 3.0 PHY pipe apb
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
|
||||
rockchip,u3phygrf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
type: array
|
||||
- description: phandle to the syscon managing the
|
||||
"USB 3.0 PHY general register files".
|
||||
|
||||
vbus-drv-gpios:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
type: array
|
||||
- description: phandle for gpio vbus supply
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- "#phy-cells"
|
||||
- rockchip,u3phygrf
|
||||
|
||||
patternProperties:
|
||||
"^u3phy_utmi@[0-9a-f]+$":
|
||||
type: object
|
||||
|
||||
properties:
|
||||
- description: USB 2.0 utmi phy.
|
||||
|
||||
rockchip,odt-val-tuning:
|
||||
type: boolean
|
||||
- description: specify 45ohm ODT tuning value.
|
||||
|
||||
"phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
|
||||
patternProperties:
|
||||
"^u3phy_pipe@[0-9a-f]+$":
|
||||
type: object
|
||||
|
||||
properties:
|
||||
- description: USB 3.0 pipe phy.
|
||||
|
||||
rockchip,refclk-25m-quirk :
|
||||
|
||||
- description: phy reference clock changed to 25m quirk.
|
||||
|
||||
"phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
|
||||
examples:
|
||||
|
||||
usb3phy_grf: syscon@ff460000 {
|
||||
compatible = "rockchip,usb3phy-grf", "syscon";
|
||||
reg = <0x0 0xff460000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
u3phy: usb3-phy@ff470000 {
|
||||
compatible = "rockchip,rk3328-u3phy";
|
||||
reg = <0x0 0xff470000 0x0 0x0>;
|
||||
rockchip,u3phygrf = <&usb3phy_grf>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "linestate";
|
||||
clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
|
||||
clock-names = "u3phy-otg", "u3phy-pipe";
|
||||
resets = <&cru SRST_USB3PHY_U2>,
|
||||
<&cru SRST_USB3PHY_U3>,
|
||||
<&cru SRST_USB3PHY_PIPE>,
|
||||
<&cru SRST_USB3OTG_UTMI>,
|
||||
<&cru SRST_USB3PHY_OTG_P>,
|
||||
<&cru SRST_USB3PHY_PIPE_P>;
|
||||
reset-names = "u3phy-u2-por", "u3phy-u3-por",
|
||||
"u3phy-pipe-mac", "u3phy-utmi-mac",
|
||||
"u3phy-utmi-apb", "u3phy-pipe-apb";
|
||||
vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
u3phy_utmi: utmi@ff470000 {
|
||||
reg = <0x0 0xff470000 0x0 0x8000>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
u3phy_pipe: pipe@ff478000 {
|
||||
reg = <0x0 0xff478000 0x0 0x8000>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,52 @@
|
||||
From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 17:24:30 +0800
|
||||
Subject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 8 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++
|
||||
3 files changed, 1184 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -35,6 +35,15 @@ config PHY_ROCKCHIP_INNO_USB2
|
||||
help
|
||||
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
|
||||
|
||||
+config PHY_ROCKCHIP_INNO_USB3
|
||||
+ tristate "Rockchip INNO USB 3.0 PHY Driver"
|
||||
+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
|
||||
+ depends on USB_SUPPORT
|
||||
+ select GENERIC_PHY
|
||||
+ select USB_PHY
|
||||
+ help
|
||||
+ Support for Rockchip USB 3.0 PHY with Innosilicon IP block.
|
||||
+
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-ro
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
|
||||
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
|
||||
@@ -33,6 +33,8 @@ Required Properties:
|
||||
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
|
||||
- compatible: USBGRF should be one of the following
|
||||
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
|
||||
+- compatible: USB3PHYGRF should be one of the following:
|
||||
+ - "rockchip,u3phy-grf", "syscon"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
Reference in New Issue
Block a user