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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-06-15 00:50:26 +08:00
parent bb536758ea 4a281a7789
commit 114d6f0b26
37 changed files with 2004 additions and 3 deletions
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4
config/Config-kernel.in
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@@ -363,7 +363,7 @@ config KERNEL_DEBUG_INFO
config KERNEL_DEBUG_INFO_BTF
bool "Enable additional BTF type information"
default y if TARGET_armsr || TARGET_bcm27xx || TARGET_ipq807x || TARGET_mediatek_filogic || TARGET_mvebu_cortexa53 || TARGET_mvebu_cortexa72 || TARGET_rockchip || TARGET_sunxi || TARGET_x86
default y if TARGET_armsr || TARGET_bcm27xx || TARGET_ipq807x || TARGET_mediatek_filogic || TARGET_mvebu_cortexa53 || TARGET_mvebu_cortexa72 || TARGET_rockchip || TARGET_sifiveu || TARGET_sunxi || TARGET_x86
depends on !HOST_OS_MACOS
depends on KERNEL_DEBUG_INFO && !KERNEL_DEBUG_INFO_REDUCED
select DWARVES
@@ -387,7 +387,7 @@ config KERNEL_MODULE_ALLOW_BTF_MISMATCH
config KERNEL_DEBUG_INFO_REDUCED
bool "Reduce debugging information"
default y if !(TARGET_armsr || TARGET_bcm27xx || TARGET_ipq807x || TARGET_mediatek_filogic || TARGET_mvebu_cortexa53 || TARGET_mvebu_cortexa72 || TARGET_rockchip || TARGET_sunxi || TARGET_x86)
default y if !(TARGET_armsr || TARGET_bcm27xx || TARGET_ipq807x || TARGET_mediatek_filogic || TARGET_mvebu_cortexa53 || TARGET_mvebu_cortexa72 || TARGET_rockchip || TARGET_sifiveu || TARGET_sunxi || TARGET_x86)
depends on KERNEL_DEBUG_INFO
help
If you say Y here gcc is instructed to generate less debugging

2
include/kernel.mk
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@@ -90,6 +90,8 @@ else ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el ))
LINUX_KARCH := mips
else ifneq (,$(findstring $(ARCH) , powerpc64 ))
LINUX_KARCH := powerpc
else ifneq (,$(findstring $(ARCH) , riscv64 ))
LINUX_KARCH := riscv
else ifneq (,$(findstring $(ARCH) , sh2 sh3 sh4 ))
LINUX_KARCH := sh
else ifneq (,$(findstring $(ARCH) , i386 x86_64 ))

30
include/site/riscv64 Normal file
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@@ -0,0 +1,30 @@
#!/bin/sh
. $TOPDIR/include/site/linux
ac_cv_c_littleendian=${ac_cv_c_littleendian=yes}
ac_cv_c_bigendian=${ac_cv_c_bigendian=no}
ac_cv_sizeof___int64=8
ac_cv_sizeof_char=1
ac_cv_sizeof_int=4
ac_cv_sizeof_int16_t=2
ac_cv_sizeof_int32_t=4
ac_cv_sizeof_int64_t=8
ac_cv_sizeof_long_int=8
ac_cv_sizeof_long_long=8
ac_cv_sizeof_long=8
ac_cv_sizeof_off_t=8
ac_cv_sizeof_short_int=2
ac_cv_sizeof_short=2
ac_cv_sizeof_size_t=8
ac_cv_sizeof_ssize_t=8
ac_cv_sizeof_u_int16_t=2
ac_cv_sizeof_u_int32_t=4
ac_cv_sizeof_u_int64_t=8
ac_cv_sizeof_uint16_t=2
ac_cv_sizeof_uint32_t=4
ac_cv_sizeof_uint64_t=8
ac_cv_sizeof_unsigned_int=4
ac_cv_sizeof_unsigned_long=8
ac_cv_sizeof_unsigned_long_long=8
ac_cv_sizeof_unsigned_short=2
ac_cv_sizeof_void_p=8

4
include/target.mk
View File

@@ -273,6 +273,10 @@ ifeq ($(DUMP),1)
CPU_CFLAGS_arc700 = -mcpu=arc700
CPU_CFLAGS_archs = -mcpu=archs
endif
ifeq ($(ARCH),riscv64)
CPU_TYPE ?= riscv64
CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc
endif
ifneq ($(CPU_TYPE),)
ifndef CPU_CFLAGS_$(CPU_TYPE)
$(warning CPU_TYPE "$(CPU_TYPE)" doesn't correspond to a known type)

63
package/boot/opensbi/Makefile Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
include $(TOPDIR)/rules.mk
PKG_NAME:=opensbi
PKG_RELEASE:=1.2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/riscv/opensbi
PKG_SOURCE_DATE:=2022-12-24
PKG_SOURCE_VERSION:=6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf8
PKG_MIRROR_HASH:=edcdd99da6c62975171981c0aa2b73a27091067da11ccd49816b5ad27d000858
PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_TARGETS:=bin
PKG_FLAGS:=nonshared
PKG_LICENSE:=BSD-2-Clause
PKG_LICENSE_FILES:=COPYING.BSD
PKG_BUILD_PARALLEL:=1
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
include $(INCLUDE_DIR)/package.mk
define Package/opensbi
SECTION:=boot
CATEGORY:=Boot Loaders
DEPENDS:=@TARGET_sifiveu
URL:=https://github.com/riscv/opensbi/blob/master/README.md
VARIANT:=$(subst _,/,$(subst opensbi_,,$(1)))
TITLE:=OpenSBI generic
OPENSBI_IMAGE:=
PLAT:=
endef
define Package/opensbi_generic
$(Package/opensbi)
TITLE:=OpenSBI generic
OPENSBI_IMAGE:=fw_dynamic.bin
PLAT:=generic
endef
export GCC_HONOUR_COPTS=s
MAKE_VARS = \
CROSS_COMPILE="$(TARGET_CROSS)"
define Build/Compile
$(eval $(Package/opensbi_$(BUILD_VARIANT))) \
+$(MAKE_VARS) $(MAKE) -C $(PKG_BUILD_DIR) \
PLATFORM=$(PLAT)
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/build/platform/$(PLAT)/firmware/fw_dynamic.bin $(STAGING_DIR_IMAGE)/fw_dynamic-${BUILD_VARIANT}.bin
endef
$(eval $(call BuildPackage,opensbi_generic))

63
package/boot/uboot-sifiveu/Makefile Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_RELEASE:=1
PKG_VERSION:=2022.10
PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=sifiveu
BUILD_DEVICES=$(1)
UBOOT_IMAGE:=u-boot.itb
DTS_DIR:=arch/riscv/dts
UENV:=default
DEFAULT:=y
endef
define U-Boot/sifive_unleashed
NAME:=SiFive Unleashed
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=hifive-unleashed-a00.dtb
BUILD_DEVICES:=sifive_unleashed
endef
define U-Boot/sifive_unmatched
NAME:=SiFive Unmatched
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=hifive-unmatched-a00.dtb
BUILD_DEVICES:=sifive_unmatched
endef
UBOOT_TARGETS := \
sifive_unleashed \
sifive_unmatched
UBOOT_MAKE_FLAGS += \
OPENSBI=$(STAGING_DIR_IMAGE)/fw_dynamic-${OPENSBI}.bin
define Build/Configure
$(call Build/Configure/U-Boot)
sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/spl/u-boot-spl.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)-spl
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS)
mkimage -C none -A arm -T script -d uEnv-$(UENV).txt \
$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
endef
$(eval $(call BuildPackage/U-Boot))

104
package/boot/uboot-sifiveu/patches/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch Normal file
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@@ -0,0 +1,104 @@
From 725595e667cc4423347c255da8ca4c5b3aa0980a Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Mon, 15 Nov 2021 03:31:04 -0800
Subject: [PATCH 2/8] board: sifive: spl: Initialized the PWM setting in the
SPL stage
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
---
board/sifive/unmatched/Makefile | 1 +
board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++
board/sifive/unmatched/spl.c | 2 ++
3 files changed, 60 insertions(+)
create mode 100644 board/sifive/unmatched/pwm.c
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index 1345330089..5df01982e9 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -9,3 +9,4 @@ obj-y += spl.o
else
obj-y += unmatched.o
endif
+obj-y += pwm.o
diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
new file mode 100644
index 0000000000..e1cc02310a
--- /dev/null
+++ b/board/sifive/unmatched/pwm.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, SiFive Inc
+ *
+ * Authors:
+ * Vincent Chen <vincent.chen@sifive.com>
+ * David Abdurachmanov <david.abdurachmanov@sifive.com>
+ */
+
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+ unsigned int cfg; /* PWM configuration register */
+ unsigned int pad0; /* Reserved */
+ unsigned int cnt; /* PWM count register */
+ unsigned int pad1; /* Reserved */
+ unsigned int pwms; /* Scaled PWM count register */
+ unsigned int pad2; /* Reserved */
+ unsigned int pad3; /* Reserved */
+ unsigned int pad4; /* Reserved */
+ unsigned int cmp0; /* PWM 0 compare register */
+ unsigned int cmp1; /* PWM 1 compare register */
+ unsigned int cmp2; /* PWM 2 compare register */
+ unsigned int cmp3; /* PWM 3 compare register */
+};
+
+#define PWM0_BASE 0x10020000
+#define PWM1_BASE 0x10021000
+#define PWM_CFG_INIT 0x1000
+#define PWM_CMP_ENABLE_VAL 0x0
+#define PWM_CMP_DISABLE_VAL 0xffff
+
+void pwm_device_init(void)
+{
+ struct pwm_sifive_regs *pwm0, *pwm1;
+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+ /* Set the 3-color PWM LEDs to yellow in SPL */
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
+ so here sets the initial value of PWM_COMP0 as DISABLE */
+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+ else
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 7c0beedc08..f3a661a81e 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -90,6 +90,8 @@ int spl_board_init_f(void)
goto end;
}
+ pwm_device_init();
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
--
2.27.0

68
package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch Normal file
View File

@@ -0,0 +1,68 @@
From 7ead6d662a2f9d8498af6650ea38418c64b52048 Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Mon, 24 Jan 2022 02:42:02 -0800
Subject: [PATCH 3/8] board: sifive: Set LED's color to purple in the U-boot
stage
Set LED's color to purple in the U-boot stage. Because there are still
some functions to be executed before board_early_init_f(), it means
the LED's is not changed to purple instantly when entering the U-boot
stage.
---
board/sifive/unmatched/pwm.c | 7 +++++++
board/sifive/unmatched/unmatched.c | 6 ++++++
configs/sifive_unmatched_defconfig | 1 +
3 files changed, 14 insertions(+)
diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
index e1cc02310a..bd67672c22 100644
--- a/board/sifive/unmatched/pwm.c
+++ b/board/sifive/unmatched/pwm.c
@@ -36,6 +36,7 @@ void pwm_device_init(void)
struct pwm_sifive_regs *pwm0, *pwm1;
pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+#ifdef CONFIG_SPL_BUILD
writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
/* Set the 3-color PWM LEDs to yellow in SPL */
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
@@ -54,4 +55,10 @@ void pwm_device_init(void)
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+#else
+ /* Set the 3-color PWM LEDs to purple in U-boot */
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp3);
+#endif
}
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 6295deeae2..30c082d001 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -22,6 +22,12 @@ void *board_fdt_blob_setup(int *err)
return (ulong *)&_end;
}
+int board_early_init_f(void)
+{
+ pwm_device_init();
+ return 0;
+}
+
int board_init(void)
{
/* enable all cache ways */
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index d400ed0b23..0758f8e90f 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -51,3 +51,4 @@ CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_BOARD_EARLY_INIT_F=y
--
2.27.0

30
package/boot/uboot-sifiveu/patches/0004-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch Normal file
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@@ -0,0 +1,30 @@
From 6ef7023c0dcfde320015ab19e0e0d423921be77d Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Mon, 15 Nov 2021 03:39:07 -0800
Subject: [PATCH 1/2] board: sifive: Set LED's color to blue before jumping to
Linux
The LED's color wil be changed from purple to blue before executing
the sysboot command. Because the sysboot command includes the image loading
from the boot partition, It means the LED's color is blue when executing
"Retrieving file: /Image.gz".
---
include/configs/sifive-unmatched.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -49,7 +49,12 @@
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- BOOTENV
+ "setled_blue=mw.l 0x10020024 0x0000ffff; mw.l 0x10020028 0x0000ffff; mw.l 0x1002002c 0x0\0" \
+ BOOTENV \
+ "boot_extlinux=" \
+ "run setled_blue; " \
+ "sysboot ${devtype} ${devnum}:${distro_bootpart} any " \
+ "${scriptaddr} ${prefix}${boot_syslinux_conf};\0"
#define CONFIG_SYS_EEPROM_BUS_NUM 0

111
package/boot/uboot-sifiveu/patches/0005-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch Normal file
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@@ -0,0 +1,111 @@
From 07f84ed283b913cbdf87181ae2ed65467d923df5 Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Mon, 24 Jan 2022 02:57:40 -0800
Subject: [PATCH 2/2] board: sifive: spl: Set remote thermal of TMP451 to 85
deg C for the unmatched board
For TMP451 on the unmatched board, the default value of the remote
thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
---
board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++
drivers/misc/Kconfig | 10 ++++++++++
include/configs/sifive-unmatched.h | 4 ++++
scripts/config_whitelist.txt | 1 +
4 files changed, 44 insertions(+)
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,6 +10,8 @@
#include <spl.h>
#include <misc.h>
#include <log.h>
+#include <config.h>
+#include <i2c.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
@@ -26,6 +28,27 @@
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19
+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55
+
+static inline int init_tmp451_remote_therm_limit(void)
+{
+ struct udevice *dev;
+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
+ CONFIG_SYS_I2C_TMP451_ADDR,
+ CONFIG_SYS_I2C_TMP451_ADDR_LEN,
+ &dev);
+
+ if (!ret)
+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
+ &r_therm_limit,
+ sizeof(unsigned char));
+ return ret;
+}
+
static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
{
int ret;
@@ -92,6 +115,12 @@ int spl_board_init_f(void)
pwm_device_init();
+ ret = init_tmp451_remote_therm_limit();
+ if (ret) {
+ debug("TMP451 remote THERM limit init failed: %d\n", ret);
+ goto end;
+ }
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -536,8 +536,18 @@ config SYS_I2C_EEPROM_ADDR
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
default 0
+config SYS_I2C_TMP451_ADDR
+ hex "Chip address of the TMP451 device"
+ default 0
+
if I2C_EEPROM
+config SYS_I2C_TMP451_ADDR_LEN
+ int "Length in bytes of the TMP451 memory array address"
+ default 1
+ help
+ Note: This is NOT the chip address length!
+
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0x0
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -15,6 +15,10 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+#define CONFIG_SYS_TMP451_BUS_NUM 0
+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
+
/* Environment options */
#define BOOT_TARGET_DEVICES(func) \
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1268,6 +1268,7 @@ CONFIG_SYS_TIMER_BASE
CONFIG_SYS_TIMER_COUNTER
CONFIG_SYS_TIMER_COUNTS_DOWN
CONFIG_SYS_TIMER_RATE
+CONFIG_SYS_TMP451_BUS_NUM
CONFIG_SYS_TMPVIRT
CONFIG_SYS_TSEC1_OFFSET
CONFIG_SYS_TX_ETH_BUFFER

36
package/boot/uboot-sifiveu/patches/0008-riscv-dts-Add-few-PMU-events.patch Normal file
View File

@@ -0,0 +1,36 @@
From c29e4d84cfa17ab96eff2a9044f486ba3c8b5c43 Mon Sep 17 00:00:00 2001
From: Atish Patra <atish.patra@wdc.com>
Date: Mon, 25 Oct 2021 11:35:41 -0700
Subject: [PATCH] riscv: dts: Add few PMU events
fu740 has 2 HPM counters and many HPM events defined in the fu740 manual[1].
This patch adds some of these events and their mapping as per the
OpenSBI PMU DT binding for now.
[1]https://sifive.cdn.prismic.io/sifive/de1491e5-077c-461d-9605-e8a0ce57337d_fu740-c000-manual-v1p3.pdf
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/dts/fu740-c000.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -140,6 +140,17 @@
#size-cells = <2>;
compatible = "simple-bus";
ranges;
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,raw-event-to-mhpmcounters = <0x00000000 0x200 0x18
+ 0x00000000 0x400 0x18
+ 0x00000000 0x800 0x18>;
+ riscv,event-to-mhpmcounters = <0x05 0x06 0x18
+ 0x10009 0x10009 0x18>;
+ riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000
+ 0x06 0x00000000 0x4001
+ 0x10008 0x00000000 0x102>;
+ };
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
#address-cells = <0>;

50
package/boot/uboot-sifiveu/patches/0009-riscv-Fix-build-against-binutils.patch Normal file
View File

@@ -0,0 +1,50 @@
commit 1dde977518f13824b847e23275001191139bc384
Author: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Date: Mon Oct 3 18:07:54 2022 +0200
riscv: Fix build against binutils 2.38
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b80eb8d86..53d1194ffb 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
CMODEL = medany
endif
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)

35
package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch Normal file
View File

@@ -0,0 +1,35 @@
From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Wed, 19 Jul 2017 22:23:15 +0200
Subject: mkimage: check environment for dtc binary location
Currently mkimage assumes the dtc binary is in the path and fails
otherwise. This patch makes it check the DTC environment variable first
for the dtc binary and then fall back to the default path. This makes
it possible to call the u-boot build with make DTC=... and build a fit
image with the dtc binary not being the the default path.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Simon Glass <sjg@chromium.org>
---
tools/fit_image.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {
+ const char* dtc = getenv("DTC");
+
+ if (!dtc)
+ dtc = MKIMAGE_DTC;
+
/* dtc -I dts -O dtb -p 500 -o tmpfile datafile */
snprintf(cmd, sizeof(cmd), "%s %s -o \"%s\" \"%s\"",
- MKIMAGE_DTC, params->dtc, tmpfile, params->datafile);
+ dtc, params->dtc, tmpfile, params->datafile);
debug("Trying to execute \"%s\"\n", cmd);
} else {
snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",

10
package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch Normal file
View File

@@ -0,0 +1,10 @@
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
imx8image.o \
imx8mimage.o \
- kwbimage.o \
lib/md5.o \
lpc32xximage.o \
mxsimage.o \

24
package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch Normal file
View File

@@ -0,0 +1,24 @@
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
* 2) get public key (X509_get_pubkey)
* 3) provide der format (d2i_RSAPublicKey)
*/
+#ifdef CONFIG_TOOLS_LIBCRYPTO
static int read_pub_key(const char *keydir, const void *name,
unsigned char **pubkey, int *pubkey_len)
{
@@ -1178,6 +1179,13 @@ err_cert:
fclose(f);
return ret;
}
+#else
+static int read_pub_key(const char *keydir, const void *name,
+ unsigned char **pubkey, int *pubkey_len)
+{
+ return -ENOSYS;
+}
+#endif
int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
{

30
package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch Normal file
View File

@@ -0,0 +1,30 @@
--- a/Makefile
+++ b/Makefile
@@ -2028,26 +2028,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@

5
package/boot/uboot-sifiveu/uEnv-default.txt Normal file
View File

@@ -0,0 +1,5 @@
setenv loadkernel fatload mmc 0:3 \$kernel_addr_r Image
setenv loaddtb fatload mmc 0:3 \$fdt_addr_r dtb
setenv bootargs console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p4 rootwait
setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
run uenvcmd

6
package/libs/openssl/patches/110-openwrt_targets.patch
View File

@@ -9,7 +9,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
--- /dev/null
+++ b/Configurations/25-openwrt.conf
@@ -0,0 +1,52 @@
@@ -0,0 +1,56 @@
+## Openwrt "CONFIG_ARCH" matching targets.
+
+# The targets need to end in '-openwrt' for the AFALG patch to work
@@ -53,6 +53,10 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
+ inherit_from => [ "linux-ppc64", "openwrt" ],
+ perlasm_scheme => "linux64v2",
+ },
+ "linux-riscv64-openwrt" => {
+ inherit_from => [ "linux-generic64", "openwrt" ],
+ perlasm_scheme => "linux64",
+ },
+ "linux-x86_64-openwrt" => {
+ inherit_from => [ "linux-x86_64", "openwrt" ],
+ },

5
target/Config.in
View File

@@ -184,6 +184,10 @@ config powerpc64
select ARCH_64BIT
bool
config riscv64
select ARCH_64BIT
bool
config sh3
bool
@@ -223,6 +227,7 @@ config ARCH
default "mips64el" if mips64el
default "powerpc" if powerpc
default "powerpc64" if powerpc64
default "riscv64" if riscv64
default "sh3" if sh3
default "sh3eb" if sh3eb
default "sh4" if sh4

23
target/linux/sifiveu/Makefile Normal file
View File

@@ -0,0 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 Toco Technologies <info@toco.ae>
#
include $(TOPDIR)/rules.mk
ARCH:=riscv64
BOARD:=sifiveu
BOARDNAME:=SiFive U-based RISC-V boards
FEATURES:=ext4
KERNELNAME:=Image dtbs
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
include $(INCLUDE_DIR)/target.mk
define Target/Description
Build firmware images for the SiFive U-based boards
(HiFive boards)
endef
$(eval $(call BuildTarget))

21
target/linux/sifiveu/base-files/etc/board.d/01_leds Normal file
View File

@@ -0,0 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
sifive,hifive-unleashed-a00)
ucidef_set_led_netdev "lan" "LAN" "green:d3" "eth0"
;;
sifive,hifive-unmatched-a00)
ucidef_set_led_netdev "lan" "LAN" "green:d2" "eth0"
;;
esac
board_config_flush
exit 0

18
target/linux/sifiveu/base-files/etc/board.d/02_network Normal file
View File

@@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
*)
ucidef_set_interface_lan 'eth0'
;;
esac
board_config_flush
exit 0

4
target/linux/sifiveu/base-files/etc/inittab Normal file
View File

@@ -0,0 +1,4 @@
::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K shutdown
ttySIF0::askfirst:/usr/libexec/login.sh
tty1::askfirst:/usr/libexec/login.sh

19
target/linux/sifiveu/base-files/lib/preinit/79_move_config Normal file
View File

@@ -0,0 +1,19 @@
# Copyright (C) 2012-2015 OpenWrt.org
move_config() {
local partdev
. /lib/upgrade/common.sh
if export_bootdevice && export_partdevice partdev 3; then
if mount -t vfat -o rw,noatime "/dev/$partdev" /mnt; then
if [ -f "/mnt/$BACKUP_FILE" ]; then
mv -f "/mnt/$BACKUP_FILE" /
fi
umount /mnt
fi
fi
}
boot_hook_add preinit_mount_root move_config

86
target/linux/sifiveu/base-files/lib/upgrade/platform.sh Normal file
View File

@@ -0,0 +1,86 @@
platform_check_image() {
local diskdev partdev diff
export_bootdevice && export_partdevice diskdev 0 || {
echo "Unable to determine upgrade device"
return 1
}
get_partitions "/dev/$diskdev" bootdisk
#extract the boot sector from the image
get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null
get_partitions /tmp/image.bs image
#compare tables
diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
if [ -n "$diff" ]; then
echo "Partition layout has changed. Full image will be written."
ask_bool 0 "Abort" && exit 1
return 0
fi
}
platform_copy_config() {
local partdev
if export_partdevice partdev 3; then
mount -t vfat -o rw,noatime "/dev/$partdev" /mnt
cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
umount /mnt
fi
}
platform_do_upgrade() {
local diskdev partdev diff
export_bootdevice && export_partdevice diskdev 0 || {
echo "Unable to determine upgrade device"
return 1
}
sync
if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
get_partitions "/dev/$diskdev" bootdisk
#extract the boot sector from the image
get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b
get_partitions /tmp/image.bs image
#compare tables
diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
else
diff=1
fi
if [ -n "$diff" ]; then
get_image "$@" | dd of="/dev/$diskdev" bs=4096 conv=fsync
# Separate removal and addtion is necessary; otherwise, partition 1
# will be missing if it overlaps with the old partition 2
partx -d - "/dev/$diskdev"
partx -a - "/dev/$diskdev"
return 0
fi
#iterate over each partition from the image and write it to the boot disk
while read part start size; do
if export_partdevice partdev $part; then
echo "Writing image to /dev/$partdev..."
get_image "$@" | dd of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
else
echo "Unable to find partition $part device, skipped."
fi
done < /tmp/partmap.image
#copy partition uuid
echo "Writing new UUID to /dev/$diskdev..."
get_image "$@" | dd of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
}

363
target/linux/sifiveu/config-5.15 Normal file
View File

@@ -0,0 +1,363 @@
CONFIG_64BIT=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
# CONFIG_ARCH_RV32I is not set
CONFIG_ARCH_RV64I=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_ATA=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_CAVIUM_PTP=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
CONFIG_CLK_SIFIVE=y
CONFIG_CLK_SIFIVE_PRCI=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CLZ_TAB=y
CONFIG_CMODEL_MEDANY=y
# CONFIG_CMODEL_MEDLOW is not set
CONFIG_COMMON_CLK=y
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_COMPAT_BRK=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_COREDUMP=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC7=y
CONFIG_CRC_ITU_T=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC=y
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SIFIVE=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI=y
CONFIG_EFIVAR_FS=m
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_STUB=y
# CONFIG_EFI_TEST is not set
CONFIG_ELF_CORE=y
CONFIG_ERRATA_SIFIVE=y
CONFIG_ERRATA_SIFIVE_CIP_1200=y
CONFIG_ERRATA_SIFIVE_CIP_453=y
CONFIG_EXT4_FS=y
CONFIG_FAILOVER=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y
CONFIG_FONT_SUPPORT=y
CONFIG_FPU=y
CONFIG_FRAME_POINTER=y
CONFIG_FRAME_WARN=2048
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_SIFIVE=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HID=y
CONFIG_HID_GENERIC=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_HOTPLUG_PCI_SHPC=y
CONFIG_HVC_DRIVER=y
CONFIG_HVC_RISCV_SBI=y
CONFIG_HW_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_OCORES=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KEYS=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LIBFDT=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_MACB=y
# CONFIG_MACB_PCI is not set
CONFIG_MACB_USE_HWSTAMP=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MICROSEMI_PHY=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SPI=y
CONFIG_MMIOWB=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MODULE_SECTIONS=y
CONFIG_MPILIB=y
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NR_CPUS=8
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OID_REGISTRY=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xffffffe000000000
CONFIG_PAGE_REPORTING=y
CONFIG_PA_BITS=56
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DPC=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_FU740=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_XILINX=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_SW_SWITCHTEC=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHYS_RAM_BASE_FIXED is not set
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_SIFIVE=y
CONFIG_PWM_SYSFS=y
CONFIG_RATIONAL=y
CONFIG_RCU_TRACE=y
CONFIG_RD_GZIP=y
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_MMIO=y
# CONFIG_RESET_ATTACK_MITIGATION is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SIMPLE=y
CONFIG_RFS_ACCEL=y
CONFIG_RISCV=y
CONFIG_RISCV_ERRATA_ALTERNATIVE=y
CONFIG_RISCV_INTC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_SBI=y
CONFIG_RISCV_SBI_V01=y
CONFIG_RISCV_TIMER=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_EFI is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_DEBUG=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SG_POOL=y
CONFIG_SIFIVE_L2=y
CONFIG_SIFIVE_PLIC=y
CONFIG_SLUB_DEBUG=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
CONFIG_SOC_SIFIVE=y
# CONFIG_SOC_VIRT is not set
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_SIFIVE=y
CONFIG_SRCU=y
CONFIG_STACKTRACE=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_CLOCK=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_TUNE_GENERIC=y
CONFIG_UCS2_STRING=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_HID=y
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PLATFORM is not set
CONFIG_VA_BITS=39
CONFIG_VFAT_FS=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_VMAP_STACK=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y

1
target/linux/sifiveu/generic/target.mk Normal file
View File

@@ -0,0 +1 @@
BOARDNAME:=Generic

5
target/linux/sifiveu/image/Config.in Normal file
View File

@@ -0,0 +1,5 @@
config SIFIVEU_SD_BOOT_PARTSIZE
int "Boot (SD Card) filesystem partition size (in MB)"
depends on TARGET_sifiveu
default 32

56
target/linux/sifiveu/image/Makefile Normal file
View File

@@ -0,0 +1,56 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 Toco Technologies <info@toco.ae>
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
FAT32_BLOCK_SIZE=1024
FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SIFIVEU_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))
KERNEL_LOADADDR:=0x80200000
define Build/riscv-sdcard
rm -f $@.boot #$(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img
mkfs.fat $@.boot -C $(FAT32_BLOCKS)
mcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-boot.scr ::boot.scr
mcopy -i $@.boot $(DTS_DIR)/$(DEVICE_DTS).dtb ::dtb
mcopy -i $@.boot $(IMAGE_KERNEL) ::Image
./gen_sifiveu_sdcard_img.sh \
$@ \
$@.boot \
$(IMAGE_ROOTFS) \
$(CONFIG_SIFIVEU_SD_BOOT_PARTSIZE) \
$(CONFIG_TARGET_ROOTFS_PARTSIZE) \
$(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.itb \
$(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.itb-spl
endef
define Device/Default
PROFILES := Default
KERNEL_NAME := Image
KERNEL := kernel-bin | libdeflate-gzip
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := riscv-sdcard | append-metadata | gzip
endef
define Device/sifive_unleashed
DEVICE_VENDOR := SiFive
DEVICE_MODEL := Unleashed (FU540)
DEVICE_DTS := sifive/hifive-unleashed-a00
UBOOT := sifive_unleashed
endef
TARGET_DEVICES += sifive_unleashed
define Device/sifive_unmatched
DEVICE_VENDOR := SiFive
DEVICE_MODEL := Unmatched (FU740)
DEVICE_DTS := sifive/hifive-unmatched-a00
DEVICE_PACKAGES += kmod-eeprom-at24 kmod-hwmon-lm90
UBOOT := sifive_unmatched
endef
TARGET_DEVICES += sifive_unmatched
$(eval $(call BuildImage))

28
target/linux/sifiveu/image/gen_sifiveu_sdcard_img.sh Executable file
View File

@@ -0,0 +1,28 @@
#!/usr/bin/env bash
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
set -ex
[ $# -eq 7 ] || {
echo "SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size> <u-boot ITB image> <u-boot SPL>"
exit 1
}
OUTPUT="$1"
BOOTFS="$2"
ROOTFS="$3"
BOOTFSSIZE="$4"
ROOTFSSIZE="$5"
UBOOT="$6"
UBOOT_SPL="$7"
set $(ptgen -o $OUTPUT -v -g -T sifiveu_spl -N loader1 -p 1024 -T sifiveu_uboot -N loader2 -p 4096 -t ef -N boot -p ${BOOTFSSIZE}M -N rootfs -p ${ROOTFSSIZE}M)
ROOTFSOFFSET=$(($7 / 512))
dd bs=512 if="$UBOOT_SPL" of="$OUTPUT" seek=34 conv=notrunc
dd bs=512 if="$UBOOT" of="$OUTPUT" seek=2082 conv=notrunc
dd bs=512 if="$BOOTFS" of="$OUTPUT" seek=10274 conv=notrunc
dd bs=512 if="$ROOTFS" of="$OUTPUT" seek=${ROOTFSOFFSET} conv=notrunc

49
target/linux/sifiveu/patches-5.15/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch Normal file
View File

@@ -0,0 +1,49 @@
From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Wed, 17 Feb 2021 06:06:14 -0800
Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
sifive,u74-mc
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -39,7 +39,7 @@
};
};
cpu1: cpu@1 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -63,7 +63,7 @@
};
};
cpu2: cpu@2 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -87,7 +87,7 @@
};
};
cpu3: cpu@3 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -111,7 +111,7 @@
};
};
cpu4: cpu@4 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;

104
target/linux/sifiveu/patches-5.15/0002-riscv-sifive-unmatched-update-regulators-values.patch Normal file
View File

@@ -0,0 +1,104 @@
From 657819ff477dd73cd71075609698aa57ba098d8c Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Wed, 15 Sep 2021 07:10:02 -0700
Subject: [PATCH 2/7] riscv: sifive: unmatched: update regulators values
These are the regulators values from the schematics for Rev3{A,B} boards.
Note this is not fully correct as bcore1/bcore2 and bmem/bio are merged, but
it's only supported in v5.15 kernel. See:
541ee8f640327f951e7039278057827322231ab0 ("regulator: da9063: Add support for
full-current mode.")
This will be changed for v5.15 kernel based on the patch above.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 32 +++++++++++-----------
1 file changed, 16 insertions(+), 16 deletions(-)
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -73,16 +73,16 @@
regulators {
vdd_bcore1: bcore1 {
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>;
regulator-max-microamp = <5000000>;
regulator-always-on;
};
vdd_bcore2: bcore2 {
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>;
regulator-max-microamp = <5000000>;
regulator-always-on;
@@ -137,48 +137,48 @@
};
vdd_ldo3: ldo3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo4: ldo4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo5: ldo5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-min-microamp = <100000>;
regulator-max-microamp = <100000>;
regulator-always-on;
};
vdd_ldo6: ldo6 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo7: ldo7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo8: ldo8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on;

69
target/linux/sifiveu/patches-5.15/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch Normal file
View File

@@ -0,0 +1,69 @@
From 2c2d8ac8c124a2938c9326c14b2dffd46d76b4a8 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 02:15:37 -0700
Subject: [PATCH 3/7] riscv: sifive: unmatched: define PWM LEDs
Add D2 (RGB) and D12 (green) LEDs for SiFive Unmatched board.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -4,6 +4,8 @@
#include "fu740-c000.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ 1000000
@@ -31,6 +33,45 @@
soc {
};
+ pwmleds {
+ compatible = "pwm-leds";
+ green-d12 {
+ label = "green:d12";
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
+ active-low = <1>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+
+ green-d2 {
+ label = "green:d2";
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
+ active-low = <1>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+
+ red-d2 {
+ label = "red:d2";
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
+ active-low = <1>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+
+ blue-d2 {
+ label = "blue:d2";
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
+ active-low = <1>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+ };
+
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";

26
target/linux/sifiveu/patches-5.15/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch Normal file
View File

@@ -0,0 +1,26 @@
From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 02:18:30 -0700
Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
Add gpio-poweroff node to allow powering off the system.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -85,6 +85,11 @@
clock-frequency = <RTCCLK_FREQ>;
clock-output-names = "rtcclk";
};
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {

116
target/linux/sifiveu/patches-5.15/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch Normal file
View File

@@ -0,0 +1,116 @@
From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Fri, 14 May 2021 05:27:51 -0700
Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/Kconfig | 8 +++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
3 files changed, 47 insertions(+)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -565,6 +565,14 @@ config BUILTIN_DTB
depends on OF
default y if XIP_KERNEL
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+source "drivers/cpufreq/Kconfig"
+
+endmenu
+
menu "Power management options"
source "kernel/power/Kconfig"
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -54,6 +55,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -78,6 +80,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -102,6 +105,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -126,6 +130,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -84,6 +84,40 @@
label = "d4";
};
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp-999999999 {
+ opp-hz = /bits/ 64 <999999999>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu1 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu2 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu3 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu4 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
};
&uart0 {

301
target/linux/sifiveu/patches-5.15/0006-riscv-sbi-srst-support.patch Normal file
View File

@@ -0,0 +1,301 @@
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From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v7 1/1] RISC-V: Use SBI SRST extension when available
Date: Wed, 9 Jun 2021 17:43:22 +0530
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The SBI SRST extension provides a standard way to poweroff and
reboot the system irrespective to whether Linux RISC-V S-mode
is running natively (HS-mode) or inside Guest/VM (VS-mode).
The SBI SRST extension is available in the SBI v0.3 specification.
(Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1)
This patch extends Linux RISC-V SBI implementation to detect
and use SBI SRST extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++
arch/riscv/kernel/sbi.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -27,6 +27,7 @@ enum sbi_ext_id {
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@@ -70,6 +71,21 @@ enum sbi_hsm_hart_status {
SBI_HSM_HART_STATUS_STOP_PENDING,
};
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
@@ -148,6 +164,14 @@ static inline unsigned long sbi_minor_ve
return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
}
+/* Make SBI version */
+static inline unsigned long sbi_mk_version(unsigned long major,
+ unsigned long minor)
+{
+ return ((major & SBI_SPEC_VERSION_MAJOR_MASK) <<
+ SBI_SPEC_VERSION_MAJOR_SHIFT) | minor;
+}
+
int sbi_err_map_linux_errno(int err);
#else /* CONFIG_RISCV_SBI */
static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; }
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -7,6 +7,7 @@
#include <linux/init.h>
#include <linux/pm.h>
+#include <linux/reboot.h>
#include <asm/sbi.h>
#include <asm/smp.h>
@@ -501,6 +502,32 @@ int sbi_remote_hfence_vvma_asid(const un
}
EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
+static void sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+ pr_warn("%s: type=0x%lx reason=0x%lx failed\n",
+ __func__, type, reason);
+}
+
+static int sbi_srst_reboot(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ sbi_srst_reset((mode == REBOOT_WARM || mode == REBOOT_SOFT) ?
+ SBI_SRST_RESET_TYPE_WARM_REBOOT :
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_REASON_NONE);
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block sbi_srst_reboot_nb;
+
+static void sbi_srst_power_off(void)
+{
+ sbi_srst_reset(SBI_SRST_RESET_TYPE_SHUTDOWN,
+ SBI_SRST_RESET_REASON_NONE);
+}
+
/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
@@ -608,6 +635,14 @@ void __init sbi_init(void)
} else {
__sbi_rfence = __sbi_rfence_v01;
}
+ if ((sbi_spec_version >= sbi_mk_version(0, 3)) &&
+ (sbi_probe_extension(SBI_EXT_SRST) > 0)) {
+ pr_info("SBI SRST extension detected\n");
+ pm_power_off = sbi_srst_power_off;
+ sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot;
+ sbi_srst_reboot_nb.priority = 192;
+ register_restart_handler(&sbi_srst_reboot_nb);
+ }
} else {
__sbi_set_timer = __sbi_set_timer_v01;
__sbi_send_ipi = __sbi_send_ipi_v01;

38
tools/firmware-utils/patches/001-add-sifiveu-guid-types.patch Normal file
View File

@@ -0,0 +1,38 @@
diff -ruN firmware-utils-2022-02-28-002cfaf0.old/src/ptgen.c firmware-utils-2022-02-28-002cfaf0/src/ptgen.c
--- firmware-utils-2022-02-28-002cfaf0.old/src/ptgen.c 2022-04-23 19:02:07.307896842 +0200
+++ firmware-utils-2022-02-28-002cfaf0/src/ptgen.c 2022-04-22 18:48:54.477970950 +0200
@@ -82,6 +82,14 @@
GUID_INIT( 0x0fc63daf, 0x8483, 0x4772, \
0x8e, 0x79, 0x3d, 0x69, 0xd8, 0x47, 0x7d, 0xe4)
+#define GUID_PARTITION_SIFIVE_SPL \
+ GUID_INIT( 0x5b193300, 0xfc78, 0x40cd, \
+ 0x80, 0x02, 0xe8, 0x6c, 0x45, 0x58, 0x0b, 0x47)
+
+#define GUID_PARTITION_SIFIVE_UBOOT \
+ GUID_INIT( 0x2e54b353, 0x1271, 0x4842, \
+ 0x80, 0x6f, 0xe4, 0x36, 0xd6, 0xaf, 0x69, 0x85)
+
#define GPT_HEADER_SIZE 92
#define GPT_ENTRY_SIZE 128
#define GPT_ENTRY_MAX 128
@@ -276,6 +284,19 @@
(1ULL << 56); /* success=1 */
return true;
}
+
+ if (!strcmp(type, "sifiveu_spl")) {
+ part->has_guid = true;
+ part->guid = GUID_PARTITION_SIFIVE_SPL;
+ return true;
+ }
+
+ if (!strcmp(type, "sifiveu_uboot")) {
+ part->has_guid = true;
+ part->guid = GUID_PARTITION_SIFIVE_UBOOT;
+ return true;
+ }
+
return false;
}