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rockchip: re-order eth ports for fastrhino r68s

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eth0 <-> eth1
eth2 <-> eth3

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 77763dd129)
This commit is contained in:
Tianling Shen
2023-08-20 17:31:25 +08:00
parent 0b0f0a5973
commit 1238dd540c
4 changed files with 76 additions and 4 deletions
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6
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@@ -28,15 +28,13 @@ rockchip_setup_interfaces()
friendlyarm,nanopi-r5s)
ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0'
;;
hinlink,opc-h68k)
hinlink,opc-h68k|\
lunzn,fastrhino-r68s)
ucidef_set_interfaces_lan_wan 'eth0 eth1 eth2' 'eth3'
;;
hinlink,opc-h69k)
ucidef_set_interfaces_lan_wan 'eth0 eth1' 'eth2'
;;
lunzn,fastrhino-r68s)
ucidef_set_interfaces_lan_wan 'eth0 eth1 eth3' 'eth2'
;;
*)
ucidef_set_interface_lan 'eth0'
;;

15
target/linux/rockchip/armv8/base-files/etc/board.d/05_compat-version Normal file
View File

@@ -0,0 +1,15 @@
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board="$(board_name)"
board_config_update
case "$board" in
lunzn,fastrhino-r68s)
ucidef_set_compat_version "1.1"
;;
esac
board_config_flush
exit 0

6
target/linux/rockchip/image/armv8.mk
View File

@@ -5,6 +5,11 @@
# FIT will be loaded at 0x02080000. Leave 16M for that, align it to 2M and load the kernel after it.
KERNEL_LOADADDR := 0x03200000
define Device/IfnameMigration
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Network interface names have been changed
endef
define Device/ezpro_mrkaio-m68s
DEVICE_VENDOR := EZPRO
DEVICE_MODEL := Mrkaio M68S
@@ -171,6 +176,7 @@ endef
TARGET_DEVICES += lunzn_fastrhino-r66s
define Device/lunzn_fastrhino-r68s
$(Device/IfnameMigration)
DEVICE_VENDOR := Lunzn
DEVICE_MODEL := FastRhino R68S
SOC := rk3568

53
target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-eth.patch
View File

@@ -86,3 +86,56 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -31,6 +31,7 @@
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+ label = "eth0";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -53,6 +54,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+ label = "eth1";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -88,6 +90,34 @@
};
};
+&pcie3x1 {
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+ label = "eth3";
+ };
+ };
+};
+
+&pcie3x2 {
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+ label = "eth2";
+ };
+ };
+};
+
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {