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rockchip: backport latest rk3588 clk updates

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2024-10-18 19:21:16 +08:00
parent e8c765190d
commit 16c3248384
6 changed files with 92 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
target/linux/rockchip/patches-6.6/030-09-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch Normal file
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@@ -0,0 +1,51 @@
From e781bffc296766b55dbd048890d558655031e8d1 Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Wed, 28 Aug 2024 15:42:52 +0000
Subject: [PATCH] clk: rockchip: Add new pll type pll_rk3588_ddr
That PLL type is similar to the other rk3588 pll types but the actual
rate is twice the configured rate.
Therefore, the returned calculated rate must be multiplied by two.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-pll.c | 6 +++++-
drivers/clk/rockchip/clk.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll
}
rate64 = rate64 >> cur.s;
- return (unsigned long)rate64;
+ if (pll->type == pll_rk3588_ddr)
+ return (unsigned long)rate64 * 2;
+ else
+ return (unsigned long)rate64;
}
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(st
break;
case pll_rk3588:
case pll_rk3588_core:
+ case pll_rk3588_ddr:
if (!pll->rate_table)
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -287,6 +287,7 @@ enum rockchip_pll_type {
pll_rk3399,
pll_rk3588,
pll_rk3588_core,
+ pll_rk3588_ddr,
};
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \

24
target/linux/rockchip/patches-6.6/111-01-clk-rockchip-rk3588-drop-unused-code.patch → target/linux/rockchip/patches-6.6/030-10-v6.12-clk-rockchip-rk3588-drop-unused-code.patch
View File

@@ -1,23 +1,7 @@
From 2e7b3daa8cb1ebd17e6a7f417ef5e6553203035c Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org
Cc: Elaine Zhang <zhangqing@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
huangtao@rock-chips.com, andy.yan@rock-chips.com,
Michal Tomek <mtdev79b@gmail.com>, Ilya K <me@0upti.me>,
Chad LeClair <leclair@gmail.com>,
devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v9 1/7] clk: rockchip: rk3588: drop unused code
Date: Mon, 25 Mar 2024 20:33:32 +0100 [thread overview]
Message-ID: <20240325193609.237182-2-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
Date: Mon, 25 Mar 2024 20:33:32 +0100
Subject: [PATCH] clk: rockchip: rk3588: drop unused code
All clocks are registered early using CLK_OF_DECLARE(), which marks
the DT node as processed. For the processed DT node the probe routine
@@ -27,6 +11,8 @@ DT node as processed. But then the probe routine would re-register
all the clocks by calling rk3588_clk_init() again.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-rk3588.c | 40 -------------------------------
1 file changed, 40 deletions(-)

29
target/linux/rockchip/patches-6.6/030-11-v6.13-clk-rockchip-fix-finding-of-maximum-clock-ID.patch Normal file
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@@ -0,0 +1,29 @@
From ad1081a0da2744141d12e94ff816ac91feb871ca Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 12 Sep 2024 13:32:05 +0000
Subject: [PATCH] clk: rockchip: fix finding of maximum clock ID
If an ID of a branch's child is greater than current maximum, we should
set new maximum to the child's ID, instead of its parent's.
Fixes: 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20240912133204.29089-2-ziyao@disroot.org
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/rockchip/clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -439,7 +439,7 @@ unsigned long rockchip_clk_find_max_clk_
if (list->id > max)
max = list->id;
if (list->child && list->child->id > max)
- max = list->id;
+ max = list->child->id;
}
return max;

2
target/linux/rockchip/patches-6.6/111-04-clk-rockchip-expose-rockchip_clk_set_lookup.patch
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@@ -83,7 +83,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -969,6 +969,18 @@ struct rockchip_clk_branch {
@@ -970,6 +970,18 @@ struct rockchip_clk_branch {
#define SGRF_GATE(_id, cname, pname) \
FACTOR(_id, cname, pname, 0, 1, 1)

10
target/linux/rockchip/patches-6.6/111-06-clk-rockchip-implement-linked-gate-clock-support.patch
View File

@@ -178,7 +178,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
const char *name, const char *const *parent_names,
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -517,6 +517,7 @@ enum rockchip_clk_branch_type {
@@ -518,6 +518,7 @@ enum rockchip_clk_branch_type {
branch_divider,
branch_fraction_divider,
branch_gate,
@@ -186,7 +186,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
branch_mmc,
branch_inverter,
branch_factor,
@@ -544,6 +545,7 @@ struct rockchip_clk_branch {
@@ -545,6 +546,7 @@ struct rockchip_clk_branch {
int gate_offset;
u8 gate_shift;
u8 gate_flags;
@@ -194,7 +194,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
struct rockchip_clk_branch *child;
};
@@ -842,6 +844,20 @@ struct rockchip_clk_branch {
@@ -843,6 +845,20 @@ struct rockchip_clk_branch {
.gate_flags = gf, \
}
@@ -215,7 +215,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
#define MMC(_id, cname, pname, offset, shift) \
{ \
.id = _id, \
@@ -981,6 +997,11 @@ static inline void rockchip_clk_set_look
@@ -982,6 +998,11 @@ static inline void rockchip_clk_set_look
ctx->clk_data.clks[id] = clk;
}
@@ -227,7 +227,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
void __iomem *base, unsigned long nr_clks);
void rockchip_clk_of_add_provider(struct device_node *np,
@@ -990,6 +1011,10 @@ unsigned long rockchip_clk_find_max_clk_
@@ -991,6 +1012,10 @@ unsigned long rockchip_clk_find_max_clk_
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
struct rockchip_clk_branch *list,
unsigned int nr_clk);

2
target/linux/rockchip/patches-6.6/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
View File

@@ -180,7 +180,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -486,7 +486,8 @@ struct clk *rockchip_clk_register_mmc(co
@@ -487,7 +487,8 @@ struct clk *rockchip_clk_register_mmc(co
* DDRCLK flags, including method of setting the rate
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
*/