Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2024-03-04 14:44:14 +08:00
23 changed files with 1560 additions and 293 deletions

View File

@@ -117,6 +117,8 @@ endif
$(curdir)/flags-install:= -j1
$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR)
$(eval $(call stampfile,$(curdir),package,prereq,.config))
$(eval $(call stampfile,$(curdir),package,cleanup,$(TMP_DIR)/.build))
$(eval $(call stampfile,$(curdir),package,compile,$(TMP_DIR)/.build))

View File

@@ -29,6 +29,7 @@ define KernelPackage/ltq-vmmc
DEPENDS:=@(TARGET_lantiq_xway||TARGET_lantiq_xrx200) +kmod-ltq-tapi
FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.ko
AUTOLOAD:=$(call AutoProbe,drv_vmmc)
USERID:=:vmmc=386
endef
define KernelPackage/ltq-vmmc/description

View File

@@ -8,6 +8,7 @@ start() {
for i in 10 11 12 13 14 15 16 17 18; do
if ! [ -e /dev/vmmc$i ]; then
mknod -m 664 /dev/vmmc$i c 122 $i
chown root:vmmc /dev/vmmc$i
fi
done
}

View File

@@ -19,6 +19,8 @@ $(curdir)/builddirs-install:=\
$(curdir)/sdk/install:=$(curdir)/linux/install
$(curdir)/imagebuilder/install:=$(curdir)/linux/install
$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR)
$(eval $(call stampfile,$(curdir),target,prereq,.config))
$(eval $(call stampfile,$(curdir),target,compile,$(TMP_DIR)/.build))
$(eval $(call stampfile,$(curdir),target,install,$(TMP_DIR)/.build))

View File

@@ -0,0 +1,46 @@
From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 03:19:49 +0000
Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
working
To: Felix Fietkau <nbd@nbd.name>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Daniel Golle <daniel@makrotopia.org>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Set DMA coherent mask to 32-bit which makes PPE offloading engine start
working on BPi-R4 which got 4 GiB of RAM.
Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
Suggested-by: Elad Yifee <eladwf@users.github.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4830,7 +4830,10 @@ static int mtk_probe(struct platform_dev
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
+ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
+ if (!err)
+ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
if (err) {
dev_err(&pdev->dev, "Wrong DMA config\n");
return -EINVAL;

View File

@@ -0,0 +1,45 @@
From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 04:17:11 +0000
Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
To: Arınç ÜNAL <arinc.unal@arinc9.com>,
Daniel Golle <daniel@makrotopia.org>,
DENG Qingfang <dqfext@gmail.com>,
Sean Wang <sean.wang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Setup PMCR port register for actual speed and duplex on internally
connected PHYs of the MT7988 built-in switch. This fixes links with
speeds other than 1000M.
Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/dsa/mt7530.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s
/* MT753x MAC works in 1G full duplex mode for all up-clocked
* variants.
*/
- if (interface == PHY_INTERFACE_MODE_INTERNAL ||
- interface == PHY_INTERFACE_MODE_TRGMII ||
+ if (interface == PHY_INTERFACE_MODE_TRGMII ||
(phy_interface_mode_is_8023z(interface))) {
speed = SPEED_1000;
duplex = DUPLEX_FULL;

View File

@@ -1,108 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
#include "mt7622-buffalo-wsr.dtsi"
/ {
model = "Buffalo WSR-2533DHP2";
compatible = "buffalo,wsr-2533dhp2", "mediatek,mt7622";
aliases {
serial0 = &uart0;
led-boot = &power_green;
led-failsafe = &power_amber;
led-running = &power_green;
led-upgrade = &power_green;
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
label-mac-device = &gmac0;
};
memory {
reg = <0 0x40000000 0 0x0F000000>;
};
leds {
compatible = "gpio-leds";
wireless_amber {
label = "amber:wireless";
gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
};
power_amber: power_amber {
label = "amber:power";
gpios = <&pio 3 GPIO_ACTIVE_LOW>;
};
power_green: power_green {
label = "green:power";
gpios = <&pio 4 GPIO_ACTIVE_LOW>;
default-state = "on";
};
wireless_green {
label = "green:wireless";
gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
};
internet {
label = "green:internet";
gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
};
router {
label = "green:router";
gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
poll-interval = <100>;
reset {
label = "reset";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
/* GPIO 1 and 16 are a tri-state switch button with
* ROUTER / AP / WB.
*/
router {
label = "router";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
bridge {
label = "wb";
gpios = <&pio 16 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
/* GPIO 18 is a switch button with AUTO / MANUAL. */
manual {
label = "manual";
gpios = <&pio 18 GPIO_ACTIVE_LOW>;
linux,code = <BTN_2>;
linux,input-type = <EV_SW>;
};
wps {
label = "wps";
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
rtkgsw: rtkgsw@0 {
compatible = "mediatek,rtk-gsw";
mediatek,ethsys = <&ethsys>;
@@ -111,41 +23,7 @@
};
};
&cpu0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&cpu1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&slot0 {
status = "okay";
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x5000>;
ieee80211-freq-limit = <5000000 6000000>;
};
};
&pio {
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
/* Parallel nand is shared pin with eMMC */
parallel_nand_pins: parallel-nand-pins {
mux {
@@ -164,75 +42,11 @@
bias-pull-up;
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm7_pins: pwm1-2-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&bch {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-connection-type = "2500base-x";
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
mac-address-increment = <(-1)>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
&gmac0 {
nvmem-cells = <&macaddr_factory_4 (-1)>;
nvmem-cell-names = "mac-address";
};
&nandc {
@@ -273,9 +87,22 @@
};
factory: partition@1c0000 {
compatible = "nvmem-cells";
label = "factory";
reg = <0x1c0000 0x40000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@200000 {
@@ -304,47 +131,3 @@
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};
&rtc {
status = "disabled";
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
};

View File

@@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7622-buffalo-wsr.dtsi"
/ {
model = "Buffalo WSR-3200AX4S";
compatible = "buffalo,wsr-3200ax4s", "mediatek,mt7622";
memory {
reg = <0 0x40000000 0 0x1f000000>;
};
};
&pio {
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
conf-cmd-dat {
pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI",
"SPI_MISO", "SPI_CS";
input-enable;
drive-strength = <16>;
bias-pull-up;
};
conf-clk {
pins = "SPI_CLK";
drive-strength = <16>;
bias-pull-down;
};
};
};
&mdio {
switch@1f {
compatible = "mediatek,mt7531";
reg = <0x1f>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-connection-type = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
&snfi {
pinctrl-names = "default";
pinctrl-0 = <&serial_nand_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <104000000>;
nand-ecc-engine = <&snfi>;
mediatek,bmt-v2;
mediatek,bmt-table-size = <0x1000>;
/*
* - Preloader - (kernel (6MiB, in firmware))
* - Kernel2 - WTB
*/
mediatek,bmt-remap-range = <0x0 0x8c0000>,
<0x1ac0000 0x5200000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Preloader";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "ATF";
reg = <0x80000 0x40000>;
read-only;
};
partition@c0000 {
label = "u-boot";
reg = <0xc0000 0x80000>;
read-only;
};
partition@140000 {
label = "u-boot-env";
reg = <0x140000 0x80000>;
read-only;
};
factory: partition@1c0000 {
label = "factory";
reg = <0x1c0000 0x100000>;
read-only;
};
partition@2c0000 {
compatible = "brcm,trx";
brcm,trx-magic = <0x33504844>;
label = "firmware";
reg = <0x2c0000 0x1800000>;
};
partition@1ac0000 {
label = "Kernel2";
reg = <0x1ac0000 0x1800000>;
};
partition@32c0000 {
label = "glbcfg";
reg = <0x32c0000 0x200000>;
read-only;
};
partition@34c0000 {
label = "board_data";
reg = <0x34c0000 0x200000>;
read-only;
};
partition@36c0000 {
label = "WTB";
reg = <0x36c0000 0x3600000>;
read-only;
};
};
};
};

View File

@@ -0,0 +1,236 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
/ {
aliases {
serial0 = &uart0;
led-boot = &power_green;
led-failsafe = &power_amber;
led-running = &power_green;
led-upgrade = &power_green;
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
};
leds {
compatible = "gpio-leds";
led-0 {
label = "amber:wireless";
gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_WLAN;
};
power_amber: led-1 {
label = "amber:power";
gpios = <&pio 3 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_POWER;
};
power_green: led-2 {
label = "green:power";
gpios = <&pio 4 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
};
led-3 {
label = "green:wireless";
gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
};
led-4 {
label = "green:internet";
gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
};
led-5 {
label = "green:router";
gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
};
};
keys {
compatible = "gpio-keys";
key-reset {
label = "reset";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
/* GPIO 1 and 16 are a tri-state switch button with
* ROUTER / AP / WB.
*/
key-router {
label = "router";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
key-bridge {
label = "wb";
gpios = <&pio 16 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
/* GPIO 18 is a switch button with AUTO / MANUAL. */
key-manual {
label = "manual";
gpios = <&pio 18 GPIO_ACTIVE_LOW>;
linux,code = <BTN_2>;
linux,input-type = <EV_SW>;
};
key-wps {
label = "wps";
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&cpu0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&cpu1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&slot0 {
status = "okay";
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x5000>;
ieee80211-freq-limit = <5000000 6000000>;
};
};
&pio {
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-connection-type = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&bch {
status = "okay";
};
&pwm {
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};
&rtc {
status = "disabled";
};

View File

@@ -0,0 +1,399 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7622.dtsi"
#include "mt6380.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "D-Link EAGLE PRO AI M32 A1";
compatible = "dlink,eagle-pro-ai-m32-a1", "mediatek,mt7622";
aliases {
led-boot = &status_orange;
led-failsafe = &status_red;
led-running = &status_white;
led-upgrade = &status_red;
serial0 = &uart0;
label-mac-device = &gmac0;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
};
cpus {
cpu@0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
cpu@1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
};
gpio-keys {
compatible = "gpio-keys";
reset {
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
};
wps {
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
status_white: status_white {
label = "white:status";
gpios = <&pio 85 GPIO_ACTIVE_LOW>;
};
status_orange: status_orange {
label = "orange:status";
gpios = <&pio 20 GPIO_ACTIVE_LOW>;
default-state = "on";
};
status_red: status_red {
label = "red:status";
gpios = <&pio 17 GPIO_ACTIVE_LOW>;
};
};
memory {
reg = <0 0x40000000 0 0x40000000>;
};
};
&bch {
status = "okay";
};
&btif {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
nvmem-cells = <&macaddr_odm_83>;
nvmem-cell-names = "mac-address";
phy-mode = "2500base-x";
reg = <0>;
fixed-link {
full-duplex;
pause;
speed = <2500>;
};
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
wan: port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&pio {
epa_elna_pins: epa-elna-pins {
mux {
function = "antsel";
groups = "antsel0", "antsel1", "antsel2", "antsel3",
"antsel4", "antsel5", "antsel6", "antsel7",
"antsel8", "antsel9", "antsel12", "antsel13",
"antsel14", "antsel15", "antsel16", "antsel17";
};
};
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx";
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&rtc {
status = "disabled";
};
&sata {
status = "disabled";
};
&sata_phy {
status = "disabled";
};
&slot0 {
wmac1: mt7915@0,0 {
reg = <0x0000 0 0 0 0>;
ieee80211-freq-limit = <5000000 6000000>;
mediatek,mtd-eeprom = <&factory 0x05000>;
};
};
&snfi {
pinctrl-names = "default";
pinctrl-0 = <&serial_nand_pins>;
status = "okay";
snand: flash@0 {
compatible = "spi-nand";
mediatek,bmt-table-size = <0x1000>;
mediatek,bmt-v2;
nand-ecc-engine = <&snfi>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Preloader";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "ATF";
reg = <0x00080000 0x00040000>;
read-only;
};
partition@C0000 {
label = "Bootloader";
reg = <0x000C0000 0x00080000>;
read-only;
};
partition@140000 {
label = "BootConfig";
reg = <0x00140000 0x00040000>;
read-only;
};
odm: partition@180000 {
compatible = "nvmem-cells";
label = "Odm";
reg = <0x00180000 0x00040000>;
read-only;
macaddr_odm_83: macaddr@83 {
reg = <0x83 0x6>;
};
};
config1: partition@1C0000 {
compatible = "nvmem-cells";
label = "Config1";
reg = <0x001C0000 0x00080000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
};
partition@240000 {
label = "Config2";
reg = <0x00240000 0x00080000>;
read-only;
};
partition@2C0000 {
label = "Kernel1";
reg = <0x002C0000 0x02D00000>;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x00800000>;
};
partition@800000 {
label = "ubi";
reg = <0x00800000 0x02500000>;
};
};
partition@2FC0000 {
label = "Kernel2";
reg = <0x02FC0000 0x02D00000>;
read-only;
};
factory: partition@5CC0000 {
label = "Factory";
reg = <0x05CC0000 0x00100000>;
read-only;
};
partition@5DC0000 {
label = "Mydlink";
reg = <0x05DC0000 0x00200000>;
read-only;
};
partition@5FC0000 {
label = "Storage";
reg = <0x05FC0000 0x00300000>;
read-only;
};
};
};
};
&ssusb {
status = "disabled";
};
&u3phy {
status = "disabled";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&epa_elna_pins>;
mediatek,mtd-eeprom = <&factory 0x0000>;
status = "okay";
};

View File

@@ -0,0 +1,188 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "mt7629.dtsi"
/ {
model = "TP-Link EAP225 v5";
compatible = "tplink,eap225-v5", "mediatek,mt7629";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_amber;
led-running = &led_status_green;
led-upgrade = &led_status_amber;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-override = "console=ttyS0,115200n8";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&pio 21 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_green: status_green {
label = "green:status";
gpios = <&pio 55 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_status_amber: status_amber {
label = "amber:status";
gpios = <&pio 56 GPIO_ACTIVE_HIGH>;
};
};
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
pinctrl-1 = <&ephy_leds_pins>;
status = "okay";
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&phy0>;
nvmem-cells = <&macaddr_factory_8>;
nvmem-cell-names = "mac-address";
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Bootloader";
reg = <0x0 0x00080000>;
read-only;
};
partition@80000 {
label = "Partition";
reg = <0x00080000 0x00010000>;
read-only;
};
partition@90000 {
label = "Factory";
reg = <0x00090000 0x00010000>;
compatible = "nvmem-cells";
read-only;
macaddr_factory_8: macaddr@8 {
reg = <0x8 0x6>;
};
};
partition@A0000 {
label = "Radio";
reg = <0x000A0000 0x00010000>;
read-only;
};
partition@B0000 {
label = "Extra";
reg = <0x000B0000 0x00010000>;
read-only;
};
/* Vendor layout: kernel (0x000C0000 0x001A0000) - rootfs (0x00260000 0x00BE0000) */
/* OpenWrt flash layout: combine kernel and rootfs from OEM layout */
partition@C0000 {
label = "firmware";
reg = <0x000C0000 0x00D80000>;
};
partition@E40000 {
label = "Config";
reg = <0x00E40000 0x0001B0000>;
read-only;
};
};
};
};
&pio {
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio";
};
};
ephy_leds_pins: ephy-leds-pins {
mux {
function = "led";
groups = "ephy_leds";
};
};
qspi_pins: qspi-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_txd_rxd" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};

View File

@@ -55,8 +55,8 @@
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
cooling-levels = <0 128 192 255>;
/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
cooling-levels = <0 63 95 127 159 191 223 255>;
#cooling-cells = <2>;
status = "disabled";
};
@@ -67,55 +67,67 @@
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
cpu_trip_active_highest: active-highest {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
type = "active";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
temperature = <60000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
temperature = <50000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <60000>;
temperature = <45000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_lowest: active-lowest {
temperature = <40000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
cpu-active-highest {
/* active: set fan to cooling level 7 */
cooling-device = <&fan 7 7>;
trip = <&cpu_trip_active_highest>;
};
cpu-active-high {
/* active: set fan to cooling level 3 */
cooling-device = <&fan 3 3>;
/* active: set fan to cooling level 5 */
cooling-device = <&fan 5 5>;
trip = <&cpu_trip_active_high>;
};
cpu-active-med {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
/* active: set fan to cooling level 3 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_med>;
};
cpu-active-low {
/* passive: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_low>;
};
cpu-active-lowest {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_lowest>;
};
};
};
};

View File

@@ -94,6 +94,10 @@ mediatek_setup_interfaces()
xiaomi,redmi-router-ax6000-ubootmod)
ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan
;;
zyxel,ex5601-t0-stock|\
zyxel,ex5601-t0-ubootmod)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
;;
*)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan
;;

View File

@@ -6,19 +6,24 @@ define Image/Prepare
echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark
endef
define Build/buffalo-kernel-trx
define Build/buffalo-trx
$(eval magic=$(word 1,$(1)))
$(eval dummy=$(word 2,$(1)))
$(eval kern_bin=$(if $(1),$(IMAGE_KERNEL),$@))
$(eval rtfs_bin=$(word 2,$(1)))
$(eval apnd_bin=$(word 3,$(1)))
$(eval kern_size=$(if $(KERNEL_SIZE),$(KERNEL_SIZE),0x400000))
$(if $(dummy),touch $(dummy))
$(if $(rtfs_bin),touch $(rtfs_bin))
$(STAGING_DIR_HOST)/bin/otrx create $@.new \
$(if $(magic),-M $(magic),) \
-f $@ \
$(if $(dummy),\
-f $(kern_bin) \
$(if $(rtfs_bin),\
-a 0x20000 \
-b $$(( $(subst k, * 1024,$(kern_size)) )) \
-f $(dummy),)
-f $(rtfs_bin),) \
$(if $(apnd_bin),\
-A $(apnd_bin) \
-a 0x20000)
mv $@.new $@
endef
@@ -30,6 +35,25 @@ define Build/bl31-uboot
cat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.fip >> $@
endef
# Append header to a D-Link M32 Kernel 1 partition
define Build/m32-recovery-header-kernel1
echo -en "DLK6E6010001\x00\x00\xCF\x33" > "$@.header"
echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x8D\x57\x30\x0B" >> "$@.header"
# Byte 0-3: Erase Start 0x002C0000
# Byte 4-7: Erase Length 0x02D00000
# Byte 8-11: Data offset: 0x002C0000
# Byte 12-15: Data Length: 0x02D00000
echo -en "\x00\x00\x2C\x00\x00\x00\xD0\x02\x00\x00\x2C\x00\x00\x00\xD0\x02" >> "$@.header"
# Only zeros
echo -en "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" >> "$@.header"
# Note: The last 2 bytes of the following line are the checksum of the header
# If any data in the header will be changed, the checksum must be re-calculated
echo -en "\x42\x48\x02\x00\x00\x00\x08\x00\x00\x00\x00\x00\x60\x6E\x68\x61" >> "$@.header"
cat "$@.header" "$@" > "$@.new"
mv "$@.new" "$@"
rm "$@.header"
endef
define Build/mt7622-gpt
cp $@ $@.tmp 2>/dev/null || true
ptgen -g -o $@.tmp -a 1 -l 1024 \
@@ -51,19 +75,6 @@ define Build/mt7622-gpt
rm $@.tmp
endef
define Build/trx-nand
# kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even
# if it grows up between releases
# root: UBI with one extra block containing UBI mark to trigger erasing
# rest of partition
$(STAGING_DIR_HOST)/bin/otrx create $@.new \
-M 0x32504844 \
-f $(IMAGE_KERNEL) -a 0x20000 -b 0x400000 \
-f $@ \
-A $(KDIR)/ubi_mark -a 0x20000
mv $@.new $@
endef
define Device/bananapi_bpi-r64
DEVICE_VENDOR := Bananapi
DEVICE_MODEL := BPi-R64
@@ -122,18 +133,70 @@ define Device/buffalo_wsr-2533dhp2
IMAGES += factory.bin factory-uboot.bin
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \
buffalo-kernel-trx
IMAGE/factory.bin := append-ubi | trx-nand | \
buffalo-trx
IMAGE/factory.bin := append-ubi | \
buffalo-trx 0x32504844 $$$$@ $(KDIR)/ubi_mark | \
buffalo-enc WSR-2533DHP2 $$(BUFFALO_TAG_VERSION) -l | \
buffalo-tag-dhp WSR-2533DHP2 JP JP | buffalo-enc-tag -l | buffalo-dhp-image
IMAGE/factory-uboot.bin := append-ubi | trx-nand
IMAGE/sysupgrade.bin := append-kernel | \
buffalo-kernel-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \
IMAGE/factory-uboot.bin := append-ubi | \
buffalo-trx 0x32504844 $$$$@ $(KDIR)/ubi_mark
IMAGE/sysupgrade.bin := \
buffalo-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \
sysupgrade-tar kernel=$$$$@ | append-metadata
DEVICE_PACKAGES := kmod-mt7615-firmware swconfig
endef
TARGET_DEVICES += buffalo_wsr-2533dhp2
define Device/buffalo_wsr-3200ax4s
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WSR-3200AX4S
DEVICE_DTS := mt7622-buffalo-wsr-3200ax4s
IMAGE_SIZE := 24576k
BUFFALO_TRX_MAGIC := 0x33504844
DEVICE_PACKAGES := kmod-mt7915-firmware
DEVICE_DTS_DIR := ../dts
KERNEL_SIZE := 6144k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5
BUFFALO_TAG_PLATFORM := MTK
BUFFALO_TAG_VERSION := 9.99
BUFFALO_TAG_MINOR := 9.99
IMAGES += factory.bin factory-uboot.bin
KERNEL_INITRAMFS = kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \
buffalo-trx
IMAGE/factory.bin = append-ubi | \
buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark | \
buffalo-enc $$(DEVICE_MODEL) $$(BUFFALO_TAG_VERSION) -l | \
buffalo-tag-dhp $$(DEVICE_MODEL) JP JP | buffalo-enc-tag -l | buffalo-dhp-image
IMAGE/factory-uboot.bin := append-ubi | \
buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark
IMAGE/sysupgrade.bin := \
buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $(KDIR)/tmp/$$(DEVICE_NAME).null | \
sysupgrade-tar kernel=$$$$@ | append-metadata
endef
TARGET_DEVICES += buffalo_wsr-3200ax4s
define Device/dlink_eagle-pro-ai-m32-a1
IMAGE_SIZE := 46080k
DEVICE_VENDOR := D-Link
DEVICE_MODEL := EAGLE PRO AI M32
DEVICE_VARIANT := A1
DEVICE_DTS := mt7622-dlink-eagle-pro-ai-m32-a1
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7915-firmware
KERNEL_SIZE := 8192k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5
IMAGES += tftp.bin recovery.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
IMAGE/tftp.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | check-size
IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | m32-recovery-header-kernel1
endef
TARGET_DEVICES += dlink_eagle-pro-ai-m32-a1
define Device/elecom_wrc-2533gent
DEVICE_VENDOR := Elecom
DEVICE_MODEL := WRC-2533GENT

View File

@@ -48,3 +48,12 @@ define Device/netgear_ex6250-v2
pad-rootfs | check-size | netgear-encrypted-factory
endef
TARGET_DEVICES += netgear_ex6250-v2
define Device/tplink_eap225-v5
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := EAP225
DEVICE_VARIANT := v5
DEVICE_DTS := mt7629-tplink_eap225-v5
DEVICE_DTS_DIR := ../dts
endef
TARGET_DEVICES += tplink_eap225-v5

View File

@@ -9,6 +9,7 @@ mediatek_setup_interfaces()
case $board in
bananapi,bpi-r64|\
buffalo,wsr-3200ax4s|\
elecom,wrc-x3200gst3|\
linksys,e8450|\
linksys,e8450-ubi|\
@@ -23,6 +24,9 @@ mediatek_setup_interfaces()
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6@eth0"
;;
dlink,eagle-pro-ai-m32-a1)
ucidef_set_interfaces_lan_wan "lan1 lan2" wan
;;
ubnt,unifi-6-lr*)
ucidef_set_interface_lan "eth0"
;;
@@ -55,6 +59,15 @@ mediatek_setup_macs()
local label_mac=""
case $board in
buffalo,wsr-3200ax4s)
lan_mac=$(mtd_get_mac_ascii board_data "mac")
wan_mac=$lan_mac
label_mac=$lan_mac
;;
dlink,eagle-pro-ai-m32-a1)
wan_mac=$(get_mac_label)
lan_mac=$(macaddr_add $(get_mac_label) 1)
;;
reyee,ax3200-e5|\
ruijie,rg-ew3200gx-pro)
lan_mac=$(macaddr_add $(get_mac_label) 1)

View File

@@ -13,6 +13,15 @@ case "$board" in
bananapi,bpi-r64)
[ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress
;;
buffalo,wsr-3200ax4s)
basemac=$(mtd_get_mac_ascii board_data "mac")
[ "$PHYNBR" = "0" ] && macaddr_add $basemac 1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $basemac 8 > /sys${DEVPATH}/macaddress
;;
dlink,eagle-pro-ai-m32-a1)
[ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $(cat /sys/class/net/eth0/address) 3 > /sys${DEVPATH}/macaddress
;;
reyee,ax3200-e5|\
ruijie,rg-ew3200gx-pro)
[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress

View File

@@ -7,4 +7,8 @@ buffalo,wsr-2533dhp2)
mtd -M 0x44485032 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0
exit 1
;;
buffalo,wsr-3200ax4s)
mtd -M 0x44485033 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0
exit 1
;;
esac

View File

@@ -21,7 +21,8 @@ platform_do_upgrade() {
;;
esac
;;
buffalo,wsr-2533dhp2)
buffalo,wsr-2533dhp2|\
buffalo,wsr-3200ax4s)
local magic="$(get_magic_long "$1")"
# use "mtd write" if the magic is "DHP2 (0x44485032)"
@@ -33,6 +34,7 @@ platform_do_upgrade() {
nand_do_upgrade "$1"
fi
;;
dlink,eagle-pro-ai-m32-a1|\
elecom,wrc-x3200gst3|\
mediatek,mt7622-rfb1-ubi|\
netgear,wax206|\
@@ -67,9 +69,11 @@ platform_check_image() {
[ "$#" -gt 1 ] && return 1
case "$board" in
buffalo,wsr-2533dhp2)
buffalo,wsr-2533dhp2|\
buffalo,wsr-3200ax4s)
buffalo_check_image "$board" "$magic" "$1" || return 1
;;
dlink,eagle-pro-ai-m32-a1|\
elecom,wrc-x3200gst3|\
mediatek,mt7622-rfb1-ubi|\
netgear,wax206|\

View File

@@ -16,7 +16,8 @@ mediatek_setup_interfaces()
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:lan" "6@eth0"
;;
netgear,ex6250-v2)
netgear,ex6250-v2|\
tplink,eap225-v5)
ucidef_set_interface_lan "eth0"
;;
esac

View File

@@ -0,0 +1,270 @@
From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 02:27:04 +0000
Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
To: Daniel Golle <daniel@makrotopia.org>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Sync initialization and calibration routines with MediaTek's reference
driver. Improves compliance and resolves link stability issues with
CH340 IoT devices connected to MT798x built-in PHYs.
Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
1 file changed, 81 insertions(+), 66 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -479,7 +479,7 @@ static int tx_r50_fill_result(struct phy
u16 reg, val;
if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
- bias = -2;
+ bias = -1;
val = clamp_val(bias + tx_r50_cal_val, 0, 63);
@@ -695,6 +695,11 @@ restore:
static void mt798x_phy_common_finetune(struct phy_device *phydev)
{
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+ __phy_write(phydev, 0x11, 0xc71);
+ __phy_write(phydev, 0x12, 0xc);
+ __phy_write(phydev, 0x10, 0x8fae);
+
/* EnabRandUpdTrig = 1 */
__phy_write(phydev, 0x11, 0x2f00);
__phy_write(phydev, 0x12, 0xe);
@@ -705,15 +710,56 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x83aa);
- /* TrFreeze = 0 */
+ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
+ __phy_write(phydev, 0x11, 0x240);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x9680);
+
+ /* TrFreeze = 0 (mt7988 default) */
__phy_write(phydev, 0x11, 0x0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9686);
+ /* SSTrKp100 = 5 */
+ /* SSTrKf100 = 6 */
+ /* SSTrKp1000Mas = 5 */
+ /* SSTrKf1000Mas = 6 */
/* SSTrKp1000Slv = 5 */
+ /* SSTrKf1000Slv = 6 */
__phy_write(phydev, 0x11, 0xbaef);
__phy_write(phydev, 0x12, 0x2e);
__phy_write(phydev, 0x10, 0x968c);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+}
+
+static void mt7981_phy_finetune(struct phy_device *phydev)
+{
+ u16 val[8] = { 0x01ce, 0x01c1,
+ 0x020f, 0x0202,
+ 0x03d0, 0x03c0,
+ 0x0013, 0x0005 };
+ int i, k;
+
+ /* 100M eye finetune:
+ * Keep middle level of TX MLT3 shapper as default.
+ * Only change TX MLT3 overshoot level here.
+ */
+ for (k = 0, i = 1; i < 12; i++) {
+ if (i % 3 == 0)
+ continue;
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+ }
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* ResetSyncOffset = 6 */
+ __phy_write(phydev, 0x11, 0x600);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate = 1 */
+ __phy_write(phydev, 0x11, 0x4c2a);
+ __phy_write(phydev, 0x12, 0x3e);
+ __phy_write(phydev, 0x10, 0x8fa4);
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
@@ -728,7 +774,7 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x10, 0x8ec0);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
@@ -761,48 +807,6 @@ static void mt798x_phy_common_finetune(s
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
}
-static void mt7981_phy_finetune(struct phy_device *phydev)
-{
- u16 val[8] = { 0x01ce, 0x01c1,
- 0x020f, 0x0202,
- 0x03d0, 0x03c0,
- 0x0013, 0x0005 };
- int i, k;
-
- /* 100M eye finetune:
- * Keep middle level of TX MLT3 shapper as default.
- * Only change TX MLT3 overshoot level here.
- */
- for (k = 0, i = 1; i < 12; i++) {
- if (i % 3 == 0)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
- }
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
-
- /* FfeUpdGainForce = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
static void mt7988_phy_finetune(struct phy_device *phydev)
{
u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
@@ -817,17 +821,7 @@ static void mt7988_phy_finetune(struct p
/* TCT finetune */
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
- __phy_write(phydev, 0x11, 0x671);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
/* ResetSyncOffset = 5 */
__phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
@@ -835,13 +829,27 @@ static void mt7988_phy_finetune(struct p
/* VgaDecRate is 1 at default on mt7988 */
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
+ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
+ */
+ __phy_write(phydev, 0x11, 0xb90a);
+ __phy_write(phydev, 0x12, 0x6f);
+ __phy_write(phydev, 0x10, 0x8f82);
+
+ /* RemAckCntLimitCtrl = 1 */
+ __phy_write(phydev, 0x11, 0xfbba);
+ __phy_write(phydev, 0x12, 0xc3);
+ __phy_write(phydev, 0x10, 0x87f8);
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
- /* TxClkOffset = 2 */
- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
+
+ /* rg_tr_lpf_cnt_val = 1023 */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
}
static void mt798x_phy_eee(struct phy_device *phydev)
@@ -874,11 +882,11 @@ static void mt798x_phy_eee(struct phy_de
MTK_PHY_LPI_SLV_SEND_TX_EN,
FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
- MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
- MTK_PHY_LPI_TXPCS_LOC_RCV,
- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
+ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+ MTK_PHY_LPI_TXPCS_LOC_RCV);
+ /* This also fixes some IoT issues, such as CH340 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
@@ -912,7 +920,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9690);
- /* REG_EEE_st2TrKf1000 = 3 */
+ /* REG_EEE_st2TrKf1000 = 2 */
__phy_write(phydev, 0x11, 0x114f);
__phy_write(phydev, 0x12, 0x2);
__phy_write(phydev, 0x10, 0x969a);
@@ -937,7 +945,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96b8);
- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
__phy_write(phydev, 0x11, 0x1463);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96ca);
@@ -1198,6 +1206,13 @@ static int mt7988_phy_probe(struct phy_d
mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
+ /* Disable TX power saving at probing to:
+ * 1. Meet common mode compliance test criteria
+ * 2. Make sure that TX-VCM calibration works fine
+ */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+
return mt798x_phy_calibration(phydev);
}

View File

@@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) {
@@ -5163,11 +5163,15 @@ static const struct mtk_soc_data mt2701_
@@ -5166,11 +5166,15 @@ static const struct mtk_soc_data mt2701_
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.version = 1,
@@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
@@ -5183,11 +5187,15 @@ static const struct mtk_soc_data mt7621_
@@ -5186,11 +5190,15 @@ static const struct mtk_soc_data mt7621_
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
@@ -5205,11 +5213,15 @@ static const struct mtk_soc_data mt7622_
@@ -5208,11 +5216,15 @@ static const struct mtk_soc_data mt7622_
.hash_offset = 2,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
@@ -5226,11 +5238,15 @@ static const struct mtk_soc_data mt7623_
@@ -5229,11 +5241,15 @@ static const struct mtk_soc_data mt7623_
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true,
@@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
@@ -5245,11 +5261,15 @@ static const struct mtk_soc_data mt7629_
@@ -5248,11 +5264,15 @@ static const struct mtk_soc_data mt7629_
.required_pctl = false,
.has_accounting = true,
.version = 1,
@@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
@@ -5267,11 +5287,15 @@ static const struct mtk_soc_data mt7981_
@@ -5270,11 +5290,15 @@ static const struct mtk_soc_data mt7981_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
@@ -5289,11 +5313,15 @@ static const struct mtk_soc_data mt7986_
@@ -5292,11 +5316,15 @@ static const struct mtk_soc_data mt7986_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
@@ -5311,11 +5339,15 @@ static const struct mtk_soc_data mt7988_
@@ -5314,11 +5342,15 @@ static const struct mtk_soc_data mt7988_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
@@ -5328,11 +5360,15 @@ static const struct mtk_soc_data rt5350_
@@ -5331,11 +5363,15 @@ static const struct mtk_soc_data rt5350_
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
.version = 1,

View File

@@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
/* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
@@ -5293,11 +5293,11 @@ static const struct mtk_soc_data mt7981_
@@ -5296,11 +5296,11 @@ static const struct mtk_soc_data mt7981_
.dma_len_offset = 8,
},
.rx = {
@@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
},
};
@@ -5319,11 +5319,11 @@ static const struct mtk_soc_data mt7986_
@@ -5322,11 +5322,11 @@ static const struct mtk_soc_data mt7986_
.dma_len_offset = 8,
},
.rx = {