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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-06-10 17:10:59 +08:00
parent 57f5d4ef59 e827f8f702
commit 42b2588152
54 changed files with 2266 additions and 1705 deletions
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2
include/image-commands.mk
View File

@@ -307,7 +307,7 @@ define Build/fit
$(if $(DEVICE_FDT_NUM),-n $(DEVICE_FDT_NUM)) \
$(if $(DEVICE_DTS_DELIMITER),-l $(DEVICE_DTS_DELIMITER)) \
$(if $(DEVICE_DTS_LOADADDR),-s $(DEVICE_DTS_LOADADDR)) \
$(if $(DEVICE_DTS_OVERLAY),$(foreach dtso,$(DEVICE_DTS_OVERLAY), -O $(dtso):$(KERNEL_BUILD_DIR)/image-$(dtso).dtb)) \
$(if $(DEVICE_DTS_OVERLAY),$(foreach dtso,$(DEVICE_DTS_OVERLAY), -O $(dtso):$(KERNEL_BUILD_DIR)/image-$(dtso).dtbo)) \
-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),"config-1") \
-A $(LINUX_KARCH) -v $(LINUX_VERSION)
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage $(if $(findstring external,$(word 3,$(1))),\

44
include/image.mk
View File

@@ -146,7 +146,7 @@ endif
# Disable noisy checks by default as in upstream
DTC_FLAGS += \
DTC_WARN_FLAGS := \
-Wno-unit_address_vs_reg \
-Wno-simple_bus_reg \
-Wno-unit_address_format \
@@ -159,6 +159,9 @@ DTC_FLAGS += \
-Wno-graph_port \
-Wno-unique_unit_address
DTC_FLAGS += $(DTC_WARN_FLAGS)
DTCO_FLAGS += $(DTC_WARN_FLAGS)
define Image/pad-to
dd if=$(1) of=$(1).new bs=$(2) conv=sync
mv $(1).new $(1)
@@ -174,7 +177,7 @@ endef
# $(2) target dtb file
# $(3) extra CPP flags
# $(4) extra DTC flags
define Image/BuildDTB
define Image/BuildDTB/sub
$(TARGET_CROSS)cpp -nostdinc -x assembler-with-cpp \
$(DTS_CPPFLAGS) \
-I$(DTS_DIR) \
@@ -183,12 +186,20 @@ define Image/BuildDTB
-undef -D__DTS__ $(3) \
-o $(2).tmp $(1)
$(LINUX_DIR)/scripts/dtc/dtc -O dtb \
-i$(dir $(1)) $(DTC_FLAGS) $(4) \
-i$(dir $(1)) $(4) \
$(if $(CONFIG_HAS_DT_OVERLAY_SUPPORT),-@) \
-o $(2) $(2).tmp
$(RM) $(2).tmp
endef
define Image/BuildDTB
$(call Image/BuildDTB/sub,$(1),$(2),$(3),$(DTC_FLAGS) $(DEVICE_DTC_FLAGS) $(4))
endef
define Image/BuildDTBO
$(call Image/BuildDTB/sub,$(1),$(2),$(3),$(DTCO_FLAGS) $(DEVICE_DTCO_FLAGS) $(4))
endef
define Image/mkfs/jffs2/sub-raw
$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
$(2) \
@@ -400,6 +411,8 @@ define Device/Init
DEVICE_DTS_LOADADDR :=
DEVICE_DTS_OVERLAY :=
DEVICE_FDT_NUM :=
DEVICE_DTC_FLAGS :=
DEVICE_DTCO_FLAGS :=
SOC :=
BOARD_NAME :=
@@ -422,9 +435,9 @@ endef
DEFAULT_DEVICE_VARS := \
DEVICE_NAME KERNEL KERNEL_INITRAMFS KERNEL_INITRAMFS_IMAGE KERNEL_SIZE \
CMDLINE UBOOTENV_IN_UBI KERNEL_IN_UBI BLOCKSIZE PAGESIZE SUBPAGESIZE \
VID_HDR_OFFSET UBINIZE_OPTS UBINIZE_PARTS MKUBIFS_OPTS DEVICE_DTS \
DEVICE_DTS_CONFIG DEVICE_DTS_DELIMITER DEVICE_DTS_DIR DEVICE_DTS_OVERLAY \
DEVICE_DTS_LOADADDR \
VID_HDR_OFFSET UBINIZE_OPTS UBINIZE_PARTS MKUBIFS_OPTS DEVICE_DTC_FLAGS \
DEVICE_DTCO_FLAGS DEVICE_DTS DEVICE_DTS_CONFIG DEVICE_DTS_DELIMITER \
DEVICE_DTS_DIR DEVICE_DTS_OVERLAY DEVICE_DTS_LOADADDR \
DEVICE_FDT_NUM DEVICE_IMG_PREFIX SOC BOARD_NAME UIMAGE_MAGIC UIMAGE_NAME \
UIMAGE_TIME SUPPORTED_DEVICES IMAGE_METADATA KERNEL_ENTRY KERNEL_LOADADDR \
UBOOT_PATH IMAGE_SIZE \
@@ -554,16 +567,33 @@ define Device/Build/dtb
image_prepare: $(KDIR)/image-$(1).dtb
endif
endef
define Device/Build/dtbo
ifndef BUILD_DTSO_$(1)
BUILD_DTSO_$(1) := 1
$(KDIR)/image-$(1).dtbo: FORCE
$(call Image/BuildDTBO,$(strip $(2))/$(strip $(3)).dtso,$$@)
image_prepare: $(KDIR)/image-$(1).dtbo
endif
endef
endif
define Device/Build/kernel
$$(eval $$(foreach dts,$$(DEVICE_DTS) $$(DEVICE_DTS_OVERLAY), \
$$(eval $$(foreach dts,$$(DEVICE_DTS), \
$$(call Device/Build/dtb,$$(notdir $$(dts)), \
$$(if $$(DEVICE_DTS_DIR),$$(DEVICE_DTS_DIR),$$(DTS_DIR)), \
$$(dts) \
) \
))
$$(eval $$(foreach dtso,$$(DEVICE_DTS_OVERLAY), \
$$(call Device/Build/dtbo,$$(notdir $$(dtso)), \
$$(if $$(DEVICE_DTS_DIR),$$(DEVICE_DTS_DIR),$$(DTS_DIR)), \
$$(dtso) \
) \
))
$(KDIR)/$$(KERNEL_NAME):: image_prepare
$$(_TARGET): $$(if $$(KERNEL_INSTALL),$(BIN_DIR)/$$(KERNEL_IMAGE))

1
package/base-files/files/etc/sysctl.d/10-default.conf
View File

@@ -9,6 +9,7 @@ fs.protected_hardlinks=1
fs.protected_symlinks=1
net.core.bpf_jit_enable=1
net.core.bpf_jit_kallsyms=1
net.ipv4.conf.default.arp_ignore=1
net.ipv4.conf.all.arp_ignore=1

18
package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
View File

@@ -173,9 +173,9 @@
+loadaddr=0x48000000
+bootargs=root=/dev/mmcblk1p65
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
+bootconf=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata
+bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata
+bootdelay=0
+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb
+bootfile_emmcbl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-preloader.bin
@@ -412,9 +412,9 @@
+loadaddr=0x48000000
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
+bootargs=root=/dev/mmcblk0p65
+bootconf=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata
+bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata
+bootdelay=0
+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb
+bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb
@@ -619,9 +619,9 @@
+loadaddr=0x48000000
+bootargs=root=/dev/ubiblock0_2p1
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
+bootconf=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata
+bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata
+bootdelay=0
+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb
+bootfile_fip=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-bl31-uboot.fip

42
package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
View File

@@ -1118,7 +1118,7 @@
+
--- /dev/null
+++ b/bananapi_bpi-r3_sdmmc_env
@@ -0,0 +1,75 @@
@@ -0,0 +1,80 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
@@ -1126,6 +1126,11 @@
+bootargs=root=/dev/mmcblk0p65
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
+bootconf=config-mt7986a-bananapi-bpi-r3
+bootconf_base=config-mt7986a-bananapi-bpi-r3
+bootconf_nor=mt7986a-bananapi-bpi-r3-nor
+bootconf_nand=mt7986a-bananapi-bpi-r3-nand
+bootconf_sd=mt7986a-bananapi-bpi-r3-sd
+bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb
+bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb
@@ -1146,7 +1151,7 @@
+bootmenu_7=Install bootloader, recovery and production to NAND.=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return
+bootmenu_8=Reboot.=reset
+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
+boot_update_conf=if nand info ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-snand ; else if sf probe ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-nor ; else setenv bootconf config-mt7986a-bananapi-bpi-r3 ; fi ; fi
+boot_update_conf=if nand info ; then setenv bootconf $bootconf_base#$bootconf_sd#$bootconf_nand ; else if sf probe ; then setenv bootconf $bootconf_base#$bootconf_sd#$bootconf_nor ; else setenv bootconf $bootconf_base#$bootconf_sd ; fi ; fi
+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
+boot_production=led $bootled_pwr on ; run boot_update_conf ; run sdmmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
@@ -1196,14 +1201,19 @@
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_nor_env
@@ -0,0 +1,55 @@
@@ -0,0 +1,60 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
+bootargs=root=/dev/mtdblock0p1
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi
+bootconf=config-mt7986a-bananapi-bpi-r3-emmc-nor
+bootconf=config-mt7986a-bananapi-bpi-r3
+bootconf_base=config-mt7986a-bananapi-bpi-r3
+bootconf_nor=mt7986a-bananapi-bpi-r3-nor
+bootconf_nand=mt7986a-bananapi-bpi-r3-nand
+bootconf_sd=mt7986a-bananapi-bpi-r3-sd
+bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb
+bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-nor-preloader.bin
@@ -1238,7 +1248,7 @@
+boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
+boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
+boot_update_conf=if mmc partconf 0 ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-nor ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-nor ; fi
+boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_sd ; fi
+boot_nor=run boot_production ; run boot_recovery
+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
+boot_write_preloader=mtd erase bl2 && mtd write bl2 $loadaddr
@@ -1254,13 +1264,18 @@
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_snand_env
@@ -0,0 +1,69 @@
@@ -0,0 +1,74 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
+bootargs=root=/dev/ubiblock0_2p1
+bootconf=config-mt7986a-bananapi-bpi-r3-snand
+bootconf=config-mt7986a-bananapi-bpi-r3
+bootconf_base=config-mt7986a-bananapi-bpi-r3
+bootconf_nor=mt7986a-bananapi-bpi-r3-nor
+bootconf_nand=mt7986a-bananapi-bpi-r3-nand
+bootconf_sd=mt7986a-bananapi-bpi-r3-sd
+bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb
@@ -1296,7 +1311,7 @@
+boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
+boot_update_conf=if mmc partconf 0 ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-snand ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-snand ; fi
+boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_sd ; fi
+part_default=production
+part_recovery=recovery
+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
@@ -1326,14 +1341,19 @@
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_emmc_env
@@ -0,0 +1,56 @@
@@ -0,0 +1,61 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
+bootargs=root=/dev/mmcblk0p65
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
+bootconf=config-mt7986a-bananapi-bpi-r3-emmc
+bootconf=config-mt7986a-bananapi-bpi-r3
+bootconf_base=config-mt7986a-bananapi-bpi-r3
+bootconf_nor=mt7986a-bananapi-bpi-r3-nor
+bootconf_nand=mt7986a-bananapi-bpi-r3-nand
+bootconf_sd=mt7986a-bananapi-bpi-r3-sd
+bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb
+bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-emmc-preloader.bin
@@ -1367,7 +1387,7 @@
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
+boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_update_conf=if nand info ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-snand ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-nor ; fi
+boot_update_conf=if nand info ; then setenv bootconf $bootconf_base#$bootconf_emmc#$bootconf_nand ; else setenv bootconf $bootconf_base#$bootconf_emmc#$bootconf_nor ; fi
+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
+part_default=production

63
package/devel/kselftests-bpf/Makefile Normal file
View File

@@ -0,0 +1,63 @@
#
# Copyright (C) 2021 Tony Ambardar <itugrok@yahoo.com>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=kselftests-bpf
PKG_VERSION:=$(LINUX_VERSION)
PKG_RELEASE:=1
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
PKG_BUILD_FLAGS:=gc-sections lto
PKG_BUILD_PARALLEL:=1
PKG_FLAGS:=nonshared
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/nls.mk
define Package/kselftests-bpf
SECTION:=devel
CATEGORY:=Development
DEPENDS:= +libelf +zlib +libpthread +librt @!IN_SDK \
@KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS
TITLE:=Linux Kernel Selftests (BPF)
URL:=http://www.kernel.org
endef
define Package/kselftests-bpf/description
kselftests-bpf is the Linux kernel BPF test suite
endef
TEST_TARGET = test_verifier
MAKE_PATH:=tools/testing/selftests/bpf
MAKE_VARS = \
ARCH="$(LINUX_KARCH)" \
CROSS_COMPILE="$(TARGET_CROSS)" \
SAN_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \
LDLIBS="$(TARGET_LDFLAGS)" \
TOOLCHAIN_INCLUDE="$(TOOLCHAIN_DIR)/include" \
VMLINUX_BTF="$(LINUX_DIR)/vmlinux"
MAKE_FLAGS = \
$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \
O=$(PKG_BUILD_DIR)
define Build/Compile
+$(MAKE_VARS) \
$(MAKE) $(PKG_JOBS) -C $(LINUX_DIR)/$(MAKE_PATH) \
$(MAKE_FLAGS) $(TEST_TARGET) ;
endef
define Package/kselftests-bpf/install
$(INSTALL_DIR) $(1)/usr/bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(TEST_TARGET) $(1)/usr/bin/
endef
$(eval $(call BuildPackage,kselftests-bpf))

4
package/devel/valgrind/Makefile
View File

@@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=valgrind
PKG_VERSION:=3.20.0
PKG_VERSION:=3.21.0
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://sourceware.org/pub/valgrind/
PKG_HASH:=8536c031dbe078d342f121fa881a9ecd205cb5a78e639005ad570011bdb9f3c6
PKG_HASH:=10ce1618bb3e33fad16eb79552b0a3e1211762448a0d7fce11c8a6243b9ac971
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0+

30
package/devel/valgrind/patches/010-mips-Fix-new-syscall-numbers.patch
View File

@@ -1,11 +1,11 @@
From 86ab9452bd10f08dbfa22d94e1155838f6f9f2e0 Mon Sep 17 00:00:00 2001
From 82e935c564699456a766044faa39367b47cce793 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sun, 31 Oct 2021 23:11:11 +0100
Subject: [PATCH] mips: Fix new syscall numbers
The MIPS32 and MIPS64 O32 ABI are adding 4000 to all syscall numbers.
The MIPS64 N64 ABI adds 5000 to each syscall and the MIPS64 N32 ABI adds
6000 to each syscall number. We can not sue the shared file for MIPS and
6000 to each syscall number. We can not use the shared file for MIPS and
have to define this for each sycall separately.
Without this change valgrind is not able to detect new syscalls like
@@ -13,10 +13,10 @@ clock_gettime64 correctly.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
include/pub_tool_vkiscnums_asm.h | 3 ---
include/vki/vki-scnums-mips32-linux.h | 36 +++++++++++++++++++++++++++
include/vki/vki-scnums-mips64-linux.h | 32 ++++++++++++++++++++++++
3 files changed, 68 insertions(+), 3 deletions(-)
include/pub_tool_vkiscnums_asm.h | 3 --
include/vki/vki-scnums-mips32-linux.h | 40 +++++++++++++++++++++++++++
include/vki/vki-scnums-mips64-linux.h | 40 +++++++++++++++++++++++++++
3 files changed, 80 insertions(+), 3 deletions(-)
--- a/include/pub_tool_vkiscnums_asm.h
+++ b/include/pub_tool_vkiscnums_asm.h
@@ -38,7 +38,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
#elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd)
--- a/include/vki/vki-scnums-mips32-linux.h
+++ b/include/vki/vki-scnums-mips32-linux.h
@@ -401,6 +401,42 @@
@@ -401,6 +401,46 @@
#define __NR_pkey_free (__NR_Linux + 365)
#define __NR_statx (__NR_Linux + 366)
@@ -73,17 +73,21 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+#define __NR_fsmount (__NR_Linux + 432)
+#define __NR_fspick (__NR_Linux + 433)
+
+#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
+#define __NR_close_range (__NR_Linux + 436)
+#define __NR_openat2 (__NR_Linux + 437)
+
+#define __NR_faccessat2 (__NR_Linux + 439)
+
+#define __NR_epoll_pwait2 (__NR_Linux + 441)
+
/*
* Offset of the last Linux o32 flavoured syscall
*/
--- a/include/vki/vki-scnums-mips64-linux.h
+++ b/include/vki/vki-scnums-mips64-linux.h
@@ -363,6 +363,22 @@
@@ -363,6 +363,26 @@
#define __NR_pkey_free (__NR_Linux + 325)
#define __NR_statx (__NR_Linux + 326)
@@ -98,15 +102,19 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+#define __NR_fsmount (__NR_Linux + 432)
+#define __NR_fspick (__NR_Linux + 433)
+
+#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
+#define __NR_close_range (__NR_Linux + 436)
+#define __NR_openat2 (__NR_Linux + 437)
+
+#define __NR_faccessat2 (__NR_Linux + 439)
+
+#define __NR_epoll_pwait2 (__NR_Linux + 441)
+
#elif defined(VGABI_N32)
/*
@@ -702,6 +718,22 @@
@@ -702,6 +722,26 @@
#define __NR_pkey_free (__NR_Linux + 329)
#define __NR_statx (__NR_Linux + 330)
@@ -121,10 +129,14 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+#define __NR_fsmount (__NR_Linux + 432)
+#define __NR_fspick (__NR_Linux + 433)
+
+#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
+#define __NR_close_range (__NR_Linux + 436)
+#define __NR_openat2 (__NR_Linux + 437)
+
+#define __NR_faccessat2 (__NR_Linux + 439)
+
+#define __NR_epoll_pwait2 (__NR_Linux + 441)
+
#else
#error unknown mips64 abi

2
package/devel/valgrind/patches/100-fix_configure_check.patch
View File

@@ -1,6 +1,6 @@
--- a/configure.ac
+++ b/configure.ac
@@ -368,7 +368,7 @@ case "${host_os}" in
@@ -364,7 +364,7 @@ case "${host_os}" in
# Ok, this is linux. Check the kernel version
AC_MSG_CHECKING([for the kernel version])

2
package/devel/valgrind/patches/130-fix_arm_arch_detection.patch
View File

@@ -6,7 +6,7 @@ Last-Update: 2013-11-30
--- a/configure.ac
+++ b/configure.ac
@@ -275,7 +275,7 @@ case "${host_cpu}" in
@@ -271,7 +271,7 @@ case "${host_cpu}" in
ARCH_MAX="s390x"
;;

9
scripts/mkits.sh
View File

@@ -191,13 +191,10 @@ OVCONFIGS=""
"
OVCONFIGS="$OVCONFIGS
config-$ovname {
description = \"OpenWrt ${DEVICE} with $ovname\";
kernel = \"kernel${REFERENCE_CHAR}1\";
fdt = \"fdt${REFERENCE_CHAR}$FDTNUM\", \"$ovnode\";
${LOADABLES:+loadables = ${LOADABLES};}
$ovname {
description = \"OpenWrt ${DEVICE} overlay $ovname\";
fdt = \"$ovnode\";
${COMPATIBLE_PROP}
${INITRD_PROP}
};
"
done

123
target/linux/generic/backport-5.15/060-v5.18-01-bpf-selftests-Add-helpers-to-directly-use-the-capget.patch Normal file
View File

@@ -0,0 +1,123 @@
From 5287acc6f097c0c18e54401b611a877a3083b68c Mon Sep 17 00:00:00 2001
From: Martin KaFai Lau <kafai@fb.com>
Date: Wed, 16 Mar 2022 10:38:23 -0700
Subject: [PATCH 1/3] bpf: selftests: Add helpers to directly use the capget
and capset syscall
After upgrading to the newer libcap (>= 2.60),
the libcap commit aca076443591 ("Make cap_t operations thread safe.")
added a "__u8 mutex;" to the "struct _cap_struct". It caused a few byte
shift that breaks the assumption made in the "struct libcap" definition
in test_verifier.c.
The bpf selftest usage only needs to enable and disable the effective
caps of the running task. It is easier to directly syscall the
capget and capset instead. It can also remove the libcap
library dependency.
The cap_helpers.{c,h} is added. One __u64 is used for all CAP_*
bits instead of two __u32.
Signed-off-by: Martin KaFai Lau <kafai@fb.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/bpf/20220316173823.2036955-1-kafai@fb.com
---
tools/testing/selftests/bpf/cap_helpers.c | 67 +++++++++++++++++++++++
tools/testing/selftests/bpf/cap_helpers.h | 19 +++++++
2 files changed, 86 insertions(+)
create mode 100644 tools/testing/selftests/bpf/cap_helpers.c
create mode 100644 tools/testing/selftests/bpf/cap_helpers.h
--- /dev/null
+++ b/tools/testing/selftests/bpf/cap_helpers.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "cap_helpers.h"
+
+/* Avoid including <sys/capability.h> from the libcap-devel package,
+ * so directly declare them here and use them from glibc.
+ */
+int capget(cap_user_header_t header, cap_user_data_t data);
+int capset(cap_user_header_t header, const cap_user_data_t data);
+
+int cap_enable_effective(__u64 caps, __u64 *old_caps)
+{
+ struct __user_cap_data_struct data[_LINUX_CAPABILITY_U32S_3];
+ struct __user_cap_header_struct hdr = {
+ .version = _LINUX_CAPABILITY_VERSION_3,
+ };
+ __u32 cap0 = caps;
+ __u32 cap1 = caps >> 32;
+ int err;
+
+ err = capget(&hdr, data);
+ if (err)
+ return err;
+
+ if (old_caps)
+ *old_caps = (__u64)(data[1].effective) << 32 | data[0].effective;
+
+ if ((data[0].effective & cap0) == cap0 &&
+ (data[1].effective & cap1) == cap1)
+ return 0;
+
+ data[0].effective |= cap0;
+ data[1].effective |= cap1;
+ err = capset(&hdr, data);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int cap_disable_effective(__u64 caps, __u64 *old_caps)
+{
+ struct __user_cap_data_struct data[_LINUX_CAPABILITY_U32S_3];
+ struct __user_cap_header_struct hdr = {
+ .version = _LINUX_CAPABILITY_VERSION_3,
+ };
+ __u32 cap0 = caps;
+ __u32 cap1 = caps >> 32;
+ int err;
+
+ err = capget(&hdr, data);
+ if (err)
+ return err;
+
+ if (old_caps)
+ *old_caps = (__u64)(data[1].effective) << 32 | data[0].effective;
+
+ if (!(data[0].effective & cap0) && !(data[1].effective & cap1))
+ return 0;
+
+ data[0].effective &= ~cap0;
+ data[1].effective &= ~cap1;
+ err = capset(&hdr, data);
+ if (err)
+ return err;
+
+ return 0;
+}
--- /dev/null
+++ b/tools/testing/selftests/bpf/cap_helpers.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CAP_HELPERS_H
+#define __CAP_HELPERS_H
+
+#include <linux/types.h>
+#include <linux/capability.h>
+
+#ifndef CAP_PERFMON
+#define CAP_PERFMON 38
+#endif
+
+#ifndef CAP_BPF
+#define CAP_BPF 39
+#endif
+
+int cap_enable_effective(__u64 caps, __u64 *old_caps);
+int cap_disable_effective(__u64 caps, __u64 *old_caps);
+
+#endif

188
target/linux/generic/backport-5.15/060-v5.18-02-bpf-selftests-Remove-libcap-usage-from-test_verifier.patch Normal file
View File

@@ -0,0 +1,188 @@
From 847a6b7ee906be874f0cae279c8de902a7d3f092 Mon Sep 17 00:00:00 2001
From: Martin KaFai Lau <kafai@fb.com>
Date: Wed, 16 Mar 2022 10:38:29 -0700
Subject: [PATCH 2/3] bpf: selftests: Remove libcap usage from test_verifier
This patch removes the libcap usage from test_verifier.
The cap_*_effective() helpers added in the earlier patch are
used instead.
Signed-off-by: Martin KaFai Lau <kafai@fb.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/bpf/20220316173829.2038682-1-kafai@fb.com
---
tools/testing/selftests/bpf/Makefile | 31 +++++---
tools/testing/selftests/bpf/test_verifier.c | 88 ++++++---------------
2 files changed, 46 insertions(+), 73 deletions(-)
--- a/tools/testing/selftests/bpf/Makefile
+++ b/tools/testing/selftests/bpf/Makefile
@@ -189,16 +189,27 @@ TEST_GEN_PROGS_EXTENDED += $(DEFAULT_BPF
$(TEST_GEN_PROGS) $(TEST_GEN_PROGS_EXTENDED): $(OUTPUT)/test_stub.o $(BPFOBJ)
-$(OUTPUT)/test_dev_cgroup: cgroup_helpers.c
-$(OUTPUT)/test_skb_cgroup_id_user: cgroup_helpers.c
-$(OUTPUT)/test_sock: cgroup_helpers.c
-$(OUTPUT)/test_sock_addr: cgroup_helpers.c
-$(OUTPUT)/test_sockmap: cgroup_helpers.c
-$(OUTPUT)/test_tcpnotify_user: cgroup_helpers.c trace_helpers.c
-$(OUTPUT)/get_cgroup_id_user: cgroup_helpers.c
-$(OUTPUT)/test_cgroup_storage: cgroup_helpers.c
-$(OUTPUT)/test_sock_fields: cgroup_helpers.c
-$(OUTPUT)/test_sysctl: cgroup_helpers.c
+CGROUP_HELPERS := $(OUTPUT)/cgroup_helpers.o
+TESTING_HELPERS := $(OUTPUT)/testing_helpers.o
+TRACE_HELPERS := $(OUTPUT)/trace_helpers.o
+CAP_HELPERS := $(OUTPUT)/cap_helpers.o
+
+$(OUTPUT)/test_dev_cgroup: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_skb_cgroup_id_user: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_sock: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_sock_addr: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_sockmap: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_tcpnotify_user: $(CGROUP_HELPERS) $(TESTING_HELPERS) $(TRACE_HELPERS)
+$(OUTPUT)/get_cgroup_id_user: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_cgroup_storage: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_sock_fields: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_sysctl: $(CGROUP_HELPERS) $(TESTING_HELPERS)
+$(OUTPUT)/test_tag: $(TESTING_HELPERS)
+$(OUTPUT)/test_lirc_mode2_user: $(TESTING_HELPERS)
+$(OUTPUT)/xdping: $(TESTING_HELPERS)
+$(OUTPUT)/flow_dissector_load: $(TESTING_HELPERS)
+$(OUTPUT)/test_maps: $(TESTING_HELPERS)
+$(OUTPUT)/test_verifier: $(TESTING_HELPERS) $(CAP_HELPERS)
BPFTOOL ?= $(DEFAULT_BPFTOOL)
$(DEFAULT_BPFTOOL): $(wildcard $(BPFTOOLDIR)/*.[ch] $(BPFTOOLDIR)/Makefile) \
--- a/tools/testing/selftests/bpf/test_verifier.c
+++ b/tools/testing/selftests/bpf/test_verifier.c
@@ -22,8 +22,6 @@
#include <limits.h>
#include <assert.h>
-#include <sys/capability.h>
-
#include <linux/unistd.h>
#include <linux/filter.h>
#include <linux/bpf_perf_event.h>
@@ -43,6 +41,7 @@
# endif
#endif
#include "bpf_rlimit.h"
+#include "cap_helpers.h"
#include "bpf_rand.h"
#include "bpf_util.h"
#include "test_btf.h"
@@ -59,6 +58,10 @@
#define F_NEEDS_EFFICIENT_UNALIGNED_ACCESS (1 << 0)
#define F_LOAD_WITH_STRICT_ALIGNMENT (1 << 1)
+/* need CAP_BPF, CAP_NET_ADMIN, CAP_PERFMON to load progs */
+#define ADMIN_CAPS (1ULL << CAP_NET_ADMIN | \
+ 1ULL << CAP_PERFMON | \
+ 1ULL << CAP_BPF)
#define UNPRIV_SYSCTL "kernel/unprivileged_bpf_disabled"
static bool unpriv_disabled = false;
static int skips;
@@ -940,47 +943,19 @@ struct libcap {
static int set_admin(bool admin)
{
- cap_t caps;
- /* need CAP_BPF, CAP_NET_ADMIN, CAP_PERFMON to load progs */
- const cap_value_t cap_net_admin = CAP_NET_ADMIN;
- const cap_value_t cap_sys_admin = CAP_SYS_ADMIN;
- struct libcap *cap;
- int ret = -1;
-
- caps = cap_get_proc();
- if (!caps) {
- perror("cap_get_proc");
- return -1;
- }
- cap = (struct libcap *)caps;
- if (cap_set_flag(caps, CAP_EFFECTIVE, 1, &cap_sys_admin, CAP_CLEAR)) {
- perror("cap_set_flag clear admin");
- goto out;
- }
- if (cap_set_flag(caps, CAP_EFFECTIVE, 1, &cap_net_admin,
- admin ? CAP_SET : CAP_CLEAR)) {
- perror("cap_set_flag set_or_clear net");
- goto out;
- }
- /* libcap is likely old and simply ignores CAP_BPF and CAP_PERFMON,
- * so update effective bits manually
- */
+ int err;
+
if (admin) {
- cap->data[1].effective |= 1 << (38 /* CAP_PERFMON */ - 32);
- cap->data[1].effective |= 1 << (39 /* CAP_BPF */ - 32);
+ err = cap_enable_effective(ADMIN_CAPS, NULL);
+ if (err)
+ perror("cap_enable_effective(ADMIN_CAPS)");
} else {
- cap->data[1].effective &= ~(1 << (38 - 32));
- cap->data[1].effective &= ~(1 << (39 - 32));
+ err = cap_disable_effective(ADMIN_CAPS, NULL);
+ if (err)
+ perror("cap_disable_effective(ADMIN_CAPS)");
}
- if (cap_set_proc(caps)) {
- perror("cap_set_proc");
- goto out;
- }
- ret = 0;
-out:
- if (cap_free(caps))
- perror("cap_free");
- return ret;
+
+ return err;
}
static int do_prog_test_run(int fd_prog, bool unpriv, uint32_t expected_val,
@@ -1246,31 +1221,18 @@ fail_log:
static bool is_admin(void)
{
- cap_flag_value_t net_priv = CAP_CLEAR;
- bool perfmon_priv = false;
- bool bpf_priv = false;
- struct libcap *cap;
- cap_t caps;
-
-#ifdef CAP_IS_SUPPORTED
- if (!CAP_IS_SUPPORTED(CAP_SETFCAP)) {
- perror("cap_get_flag");
- return false;
- }
-#endif
- caps = cap_get_proc();
- if (!caps) {
- perror("cap_get_proc");
+ __u64 caps;
+
+ /* The test checks for finer cap as CAP_NET_ADMIN,
+ * CAP_PERFMON, and CAP_BPF instead of CAP_SYS_ADMIN.
+ * Thus, disable CAP_SYS_ADMIN at the beginning.
+ */
+ if (cap_disable_effective(1ULL << CAP_SYS_ADMIN, &caps)) {
+ perror("cap_disable_effective(CAP_SYS_ADMIN)");
return false;
}
- cap = (struct libcap *)caps;
- bpf_priv = cap->data[1].effective & (1 << (39/* CAP_BPF */ - 32));
- perfmon_priv = cap->data[1].effective & (1 << (38/* CAP_PERFMON */ - 32));
- if (cap_get_flag(caps, CAP_NET_ADMIN, CAP_EFFECTIVE, &net_priv))
- perror("cap_get_flag NET");
- if (cap_free(caps))
- perror("cap_free");
- return bpf_priv && perfmon_priv && net_priv == CAP_SET;
+
+ return (caps & ADMIN_CAPS) == ADMIN_CAPS;
}
static void get_unpriv_disabled()

122
target/linux/generic/backport-5.15/060-v5.18-03-bpf-selftests-Remove-libcap-usage-from-test_progs.patch Normal file
View File

@@ -0,0 +1,122 @@
From 1ac00fea13c576e2b13dabf9a72ad3034e3bb804 Mon Sep 17 00:00:00 2001
From: Martin KaFai Lau <kafai@fb.com>
Date: Wed, 16 Mar 2022 10:38:35 -0700
Subject: [PATCH 3/3] bpf: selftests: Remove libcap usage from test_progs
This patch removes the libcap usage from test_progs.
bind_perm.c is the only user. cap_*_effective() helpers added in the
earlier patch are directly used instead.
No other selftest binary is using libcap, so '-lcap' is also removed
from the Makefile.
Signed-off-by: Martin KaFai Lau <kafai@fb.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Reviewed-by: Stanislav Fomichev <sdf@google.com>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/bpf/20220316173835.2039334-1-kafai@fb.com
---
tools/testing/selftests/bpf/Makefile | 5 ++-
.../selftests/bpf/prog_tests/bind_perm.c | 44 ++++---------------
2 files changed, 11 insertions(+), 38 deletions(-)
--- a/tools/testing/selftests/bpf/Makefile
+++ b/tools/testing/selftests/bpf/Makefile
@@ -26,7 +26,7 @@ CFLAGS += -g -O0 -rdynamic -Wall $(GENFL
-I$(TOOLSINCDIR) -I$(APIDIR) -I$(OUTPUT) \
-Dbpf_prog_load=bpf_prog_test_load \
-Dbpf_load_program=bpf_test_load_program
-LDLIBS += -lcap -lelf -lz -lrt -lpthread
+LDLIBS += -lelf -lz -lrt -lpthread
# Silence some warnings when compiled with clang
ifneq ($(LLVM),)
@@ -471,7 +471,8 @@ TRUNNER_TESTS_DIR := prog_tests
TRUNNER_BPF_PROGS_DIR := progs
TRUNNER_EXTRA_SOURCES := test_progs.c cgroup_helpers.c trace_helpers.c \
network_helpers.c testing_helpers.c \
- btf_helpers.c flow_dissector_load.h
+ btf_helpers.c flow_dissector_load.h \
+ cap_helpers.c
TRUNNER_EXTRA_FILES := $(OUTPUT)/urandom_read $(OUTPUT)/bpf_testmod.ko \
ima_setup.sh \
$(wildcard progs/btf_dump_test_case_*.c)
--- a/tools/testing/selftests/bpf/prog_tests/bind_perm.c
+++ b/tools/testing/selftests/bpf/prog_tests/bind_perm.c
@@ -4,9 +4,9 @@
#include <stdlib.h>
#include <sys/types.h>
#include <sys/socket.h>
-#include <sys/capability.h>
#include "test_progs.h"
+#include "cap_helpers.h"
#include "bind_perm.skel.h"
static int duration;
@@ -49,41 +49,11 @@ close_socket:
close(fd);
}
-bool cap_net_bind_service(cap_flag_value_t flag)
-{
- const cap_value_t cap_net_bind_service = CAP_NET_BIND_SERVICE;
- cap_flag_value_t original_value;
- bool was_effective = false;
- cap_t caps;
-
- caps = cap_get_proc();
- if (CHECK(!caps, "cap_get_proc", "errno %d", errno))
- goto free_caps;
-
- if (CHECK(cap_get_flag(caps, CAP_NET_BIND_SERVICE, CAP_EFFECTIVE,
- &original_value),
- "cap_get_flag", "errno %d", errno))
- goto free_caps;
-
- was_effective = (original_value == CAP_SET);
-
- if (CHECK(cap_set_flag(caps, CAP_EFFECTIVE, 1, &cap_net_bind_service,
- flag),
- "cap_set_flag", "errno %d", errno))
- goto free_caps;
-
- if (CHECK(cap_set_proc(caps), "cap_set_proc", "errno %d", errno))
- goto free_caps;
-
-free_caps:
- CHECK(cap_free(caps), "cap_free", "errno %d", errno);
- return was_effective;
-}
-
void test_bind_perm(void)
{
- bool cap_was_effective;
+ const __u64 net_bind_svc_cap = 1ULL << CAP_NET_BIND_SERVICE;
struct bind_perm *skel;
+ __u64 old_caps = 0;
int cgroup_fd;
if (create_netns())
@@ -105,7 +75,8 @@ void test_bind_perm(void)
if (!ASSERT_OK_PTR(skel, "bind_v6_prog"))
goto close_skeleton;
- cap_was_effective = cap_net_bind_service(CAP_CLEAR);
+ ASSERT_OK(cap_disable_effective(net_bind_svc_cap, &old_caps),
+ "cap_disable_effective");
try_bind(AF_INET, 110, EACCES);
try_bind(AF_INET6, 110, EACCES);
@@ -113,8 +84,9 @@ void test_bind_perm(void)
try_bind(AF_INET, 111, 0);
try_bind(AF_INET6, 111, 0);
- if (cap_was_effective)
- cap_net_bind_service(CAP_SET);
+ if (old_caps & net_bind_svc_cap)
+ ASSERT_OK(cap_enable_effective(net_bind_svc_cap, NULL),
+ "cap_enable_effective");
close_skeleton:
bind_perm__destroy(skel);

22
target/linux/generic/files/block/partitions/fit.c
View File

@@ -84,13 +84,13 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
const u32 *image_offset_be, *image_len_be, *image_pos_be;
int ret = 1, node, images, config;
const char *image_name, *image_type, *image_description, *config_default,
*config_description, *config_loadables;
*config_description, *config_loadables, *bootconf_c;
int image_name_len, image_type_len, image_description_len, config_default_len,
config_description_len, config_loadables_len;
config_description_len, config_loadables_len, bootconf_len;
sector_t start_sect, nr_sects;
size_t label_min;
struct device_node *np = NULL;
const char *bootconf;
char *bootconf = NULL, *bootconf_term;
const char *loadable;
const char *select_rootfs = NULL;
bool found;
@@ -143,10 +143,17 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
return -ENOMEM;
np = of_find_node_by_path("/chosen");
if (np)
bootconf = of_get_property(np, "u-boot,bootconf", NULL);
else
bootconf = NULL;
if (np) {
bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
if (bootconf_c && bootconf_len)
bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
}
if (bootconf) {
bootconf_term = strchr(bootconf, '#');
if (bootconf_term)
*bootconf_term = '\0';
}
config = fdt_path_offset(fit, FIT_CONFS_PATH);
if (config < 0) {
@@ -285,6 +292,7 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
strlcat(state->pp_buf, tmp, PAGE_SIZE);
}
ret_out:
kfree(bootconf);
kfree(fit);
return ret;
}

14
target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts
View File

@@ -89,6 +89,10 @@
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
@@ -330,13 +334,21 @@
};
};
&wmac {
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};

80
target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts
View File

@@ -1,80 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
/delete-property/ cap-sd-highspeed;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
};
fragment@1 {
target-path = "/soc/spi@1100a000";
__overlay__ {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "reserved2";
reg = <0x80000 0x80000>;
};
partition@100000 {
label = "fip";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "recovery";
reg = <0x180000 0xa80000>;
};
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
compatible = "denx,fit";
};
};
};
};
};
};

71
target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-snand.dts
View File

@@ -1,71 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
/delete-property/ cap-sd-highspeed;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
};
fragment@1 {
target-path = "/soc/spi@1100a000";
__overlay__ {
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "reserved";
reg = <0x80000 0x300000>;
};
partition@380000 {
label = "fip";
reg = <0x380000 0x200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x7a80000>;
};
};
};
};
};
};

585
target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts
View File

@@ -1,585 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3";
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
led-boot = &led_status_green;
led-failsafe = &led_status_green;
led-running = &led_status_green;
led-upgrade = &led_status_blue;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
keys {
compatible = "gpio-keys";
/*
* RST button is also PCIe-CLKREQ signal, use WPS button as reset
* instead as RST button doesn't make sense and cannot be used.
*
* intended buttons:
factory {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
* actual setup:
*/
wps {
label = "wps";
linux,code = <KEY_RESTART>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_status_green: green {
label = "green:status";
gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_status_blue: blue {
label = "blue:status";
gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
};
};
/* SFP1 cage (WAN) */
i2c_sfp1: i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
/* SFP2 cage (LAN) */
i2c_sfp2: i2c-gpio-1 {
compatible = "i2c-gpio";
sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
sfp = <&sfp1>;
managed = "in-band-status";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port5: port@5 {
reg = <5>;
label = "sfp2";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&crypto {
status = "okay";
};
&mmc0 {
//sdcard
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&wmac {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
};
&pio {
/* don't mess around with GPIO 419, 450, 451, 498, 510 in sysfs system will freeze. */
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_pereset"; //"pcie_wake" is unused
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
i2c0_pins: i2c0-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&fan {
pwms = <&pwm 0 10000 0>;
cooling-levels = <255 96 52 0>;
status = "okay";
};
&wmac {
mediatek,eeprom-data = <0x86790900 0xc4326 0x60000000 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000000
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x800 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x24649090 0x280000 0x5100000 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x21e00 0x21e0002 0x1e00021e 0x22800 0x2280002 0x28000228 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x8080 0x8080fdf7
0x903150d 0x80808080 0x80808080 0x5050d0d 0x1313c6c6 0xc3c3c200 0xc200c2 0x8182
0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
0xc2000081 0x82858587 0x87c2c200 0x818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0xc3
0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
0x222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
0xeeeeeecc 0xccccdddd 0xdddddddd 0x4a5662 0x4a 0x56620000 0x4a5662 0x4a
0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00 0xf0f0cc00
0x00 0xaaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00 0xaaaa 0xaa000000 0xbbbbbbbb
0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
0x00 0x00 0x00 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00 0xeeee 0xeeffffff 0xcccccccc
0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x01 0x6000100 0x1050002 0xff0300
0xf900fe03 0x00 0x00 0x9b 0x6e370000 0x00 0xfc0009 0xa00fe00
0x60700fe 0x70800 0x5000b0a 0x00 0x00 0xe2 0x96460000 0x00
0x400f7 0xf8000300 0xfcfe0003 0xfbfc00 0xee00e3f2 0x00 0x00 0x11
0xbb550000 0x00 0x600f6 0xfc000300 0xfbfe0004 0xfafe00 0xf600ecf2 0x00
0x00 0x1f 0xbf580000 0x00 0x600f5 0xf6000400 0xf8f90004 0xf7f800
0xf700f0f4 0x00 0x00 0x24 0xbe570000 0x00 0x800f8 0xfe000600
0xf8fd0007 0xf9fe00 0xf500f0f4 0x00 0x00 0x2d 0xd6610000 0x00
0x400f7 0xfc000500 0xf7fc0005 0xf7fc00 0xf900f5f8 0x00 0x00 0x26
0xd96e0000 0x00 0x400f7 0xf9000600 0xf5f70005 0xf5f800 0xf900f4f7 0x00
0x00 0x1b 0xce690000 0x00 0x300f8 0xf8000600 0xf6f60004 0xf6f700
0xf900f4f7 0x00 0x00 0x18 0xd8720000 0x00 0x00 0x2404002
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
0x3fc140c1 0x41c040c0 0x00 0x00 0x41c741c7 0xc1c7c1c7 0x00 0x00
0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
0xa0ce00 0x00 0xb6840000 0x00 0x00 0x00 0x18181818 0x18181818
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x4b5763 0x4b 0x57630000 0x4b5763 0x4b 0x57630000 0x88888888 0x8474759
0x69780849 0x49596d7a 0x849495a 0x6d790848 0x48596c78 0x8484858 0x6a780848 0x48586a78
0x8484858 0x6c78084a 0x4a5b6d79 0x8474759 0x697a0848 0x48596b79 0x8484859 0x6c7a0848
0x48586c79 0x8484857 0x68770848 0x48576877 0x8484857 0x6a77084a 0x4a5a6a77 0x8464659
0x69790848 0x48586b79 0x8484858 0x6c7a0848 0x48596c79 0x8484857 0x68770848 0x48576877
0x8494958 0x6d7a084b 0x4b5c6c77 0x847475a 0x6a7b0849 0x495a6e7c 0x849495a 0x6e7c0849
0x495b6e7c 0x8494959 0x6a7a0849 0x49596a7a 0x84a4a5a 0x6f7d084b 0x4b5c6e7b 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x85848484
0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
0xc0c08282 0x83848686 0x88880000 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x1111 0x00
0x8080f703 0x10808080 0x80050d13 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0xa4 0xce000000 0xb684 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
};

14
target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi
View File

@@ -83,6 +83,10 @@
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
@@ -231,6 +235,10 @@
status = "okay";
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
@@ -239,7 +247,11 @@
status = "okay";
};
&wmac {
&watchdog {
status = "okay";
};
&wifi {
mediatek,mtd-eeprom = <&factory 0x0>;
nvmem-cells = <&macaddr_config_1c>;
nvmem-cell-names = "mac-address";

2
target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts
View File

@@ -73,7 +73,7 @@
};
};
&wmac {
&wifi {
pinctrl-names = "dbdc";
pinctrl-0 = <&wf_dbdc_pins>;
};

2
target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts
View File

@@ -58,7 +58,7 @@
};
};
&wmac {
&wifi {
pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>;
};

2
target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts
View File

@@ -73,7 +73,7 @@
};
};
&wmac {
&wifi {
pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>;
};

18
target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi
View File

@@ -42,6 +42,10 @@
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
@@ -246,7 +250,19 @@
};
};
&wmac {
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>;

1128
target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts
View File

File diff suppressed because it is too large Load Diff

4
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi
View File

@@ -327,7 +327,7 @@
<&infracfg CLK_INFRA_AP_DMA_CK>,
<&infracfg CLK_INFRA_I2C_MCK_CK>,
<&infracfg CLK_INFRA_I2C_PCK_CK>;
clock-names = "main", "dma", "mck", "pck";
clock-names = "main", "dma", "arb", "pmic";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -755,7 +755,7 @@
wifi: wifi@18000000 {
compatible = "mediatek,mt7981-wmac";
resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
pinctrl-0 = <&wifi_dbdc_pins>;
pinctrl-names = "dbdc";

29
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso Normal file
View File

@@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
};
};

8
target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-snand.dts → target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
View File

@@ -1,4 +1,8 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Authors: Daniel Golle <daniel@makrotopia.org>
* Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
@@ -9,7 +13,9 @@
fragment@0 {
target-path = "/soc/spi@1100a000";
__overlay__ {
nand-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
spi_nand: spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;

7
target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-nor.dts → target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
View File

@@ -1,4 +1,8 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Authors: Daniel Golle <daniel@makrotopia.org>
* Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
@@ -9,6 +13,8 @@
fragment@0 {
target-path = "/soc/spi@1100a000";
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
@@ -49,7 +55,6 @@
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
compatible = "denx,fit";
};
};
};

23
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
status = "okay";
};
};
};

499
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts Normal file
View File

@@ -0,0 +1,499 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Authors: Sam.Shih <sam.shih@mediatek.com>
* Frank Wunderlich <frank-w@public-files.de>
* Daniel Golle <daniel@makrotopia.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3";
chassis-type = "embedded";
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
chosen {
stdout-path = "serial0:115200n8";
};
dcin: regulator-12vd {
compatible = "regulator-fixed";
regulator-name = "12vd";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
cooling-levels = <255 96 0>;
pwms = <&pwm 0 10000 0>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
reset-key {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps-key {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
/* i2c of the left SFP cage (wan) */
i2c_sfp1: i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
/* i2c of the right SFP cage (lan) */
i2c_sfp2: i2c-gpio-1 {
compatible = "i2c-gpio";
sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
leds {
compatible = "gpio-leds";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
blue_led: led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3.3vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
/* left SFP cage (wan) */
sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
};
/* right SFP cage (lan) */
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
};
};
&cpu_thermal {
cooling-maps {
cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
cpu-active-low {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
cpu-passive {
/* passive: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
};
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
sfp = <&sfp1>;
managed = "in-band-status";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
switch: switch@31 {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
i2c_pins: i2c-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_0";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1_rx_tx";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_0_rx_tx";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
status = "okay";
};
&ssusb {
status = "okay";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port5: port@5 {
reg = <5>;
label = "lan4";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
led {
led-active-low;
};
};

2
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
View File

@@ -47,6 +47,6 @@
};
};
&wmac {
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

2
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
View File

@@ -46,6 +46,6 @@
};
};
&wmac {
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

2
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
View File

@@ -78,7 +78,7 @@
};
};
&wmac {
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;

303
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -4,19 +4,19 @@
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7986a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
clk40m: oscillator@0 {
clk40m: oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@@ -60,22 +60,14 @@
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 64 KiB reserved for ramoops/pstore */
ramoops@42ff0000 {
compatible = "ramoops";
reg = <0 0x42ff0000 0 0x10000>;
record-size = <0x1000>;
};
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
@@ -126,6 +118,7 @@
reg = <0 0x15194000 0 0x1000>;
no-map;
};
};
timer {
@@ -162,6 +155,12 @@
#clock-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
@@ -169,11 +168,17 @@
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt",
"mediatek,mt6589-wdt";
compatible = "mediatek,mt7986-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
status = "disabled";
};
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7986-apmixedsys";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@1001f000 {
@@ -197,12 +202,6 @@
#interrupt-cells = <2>;
};
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7986-apmixedsys";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
@@ -217,12 +216,13 @@
#clock-cells = <1>;
};
trng: trng@1020f000 {
compatible = "mediatek,mt7986-rng";
trng: rng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg CLK_INFRA_TRNG_CK>;
clock-names = "rng";
status = "okay";
status = "disabled";
};
crypto: crypto@10320000 {
@@ -237,7 +237,7 @@
clock-names = "infra_eip97_ck";
assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
status = "okay";
status = "disabled";
};
pwm: pwm@10048000 {
@@ -246,7 +246,7 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_PWM_HCK>,
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>;
@@ -311,6 +311,8 @@
spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
@@ -323,6 +325,8 @@
spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
@@ -334,12 +338,12 @@
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7986-auxadc",
"mediatek,mt7622-auxadc";
compatible = "mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
ssusb: usb@11200000 {
@@ -350,15 +354,15 @@
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
<&topckgen CLK_TOP_U2U3_XHCI_SEL>,
<&infracfg CLK_INFRA_IUSB_CK>,
<&infracfg CLK_INFRA_IUSB_133_CK>,
<&infracfg CLK_INFRA_IUSB_66M_CK>;
<&infracfg CLK_INFRA_IUSB_66M_CK>,
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
clock-names = "sys_ck",
"xhci_ck",
"ref_ck",
"mcu_ck",
"dma_ck";
"dma_ck",
"xhci_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
@@ -370,15 +374,13 @@
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_MSDC_CK>,
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
<&infracfg CLK_INFRA_MSDC_66M_CK>,
<&infracfg CLK_INFRA_MSDC_133M_CK>;
clock-names = "source", "hclk", "axi_cg", "ahb_cg";
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&topckgen CLK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
<&infracfg CLK_INFRA_MSDC_CK>,
<&infracfg CLK_INFRA_MSDC_133M_CK>,
<&infracfg CLK_INFRA_MSDC_66M_CK>;
clock-names = "source", "hclk", "source_cg", "bus_clk",
"sys_cg";
status = "disabled";
};
@@ -388,8 +390,9 @@
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
<&infracfg CLK_INFRA_ADC_26M_CK>,
<&infracfg CLK_INFRA_ADC_FRC_CK>;
clock-names = "therm", "auxadc", "adc_32k";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
@@ -408,11 +411,11 @@
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x00 0x20000000 0x00
0x20000000 0x00 0x10000000>;
clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
status = "disabled";
phys = <&pcie_port PHY_TYPE_PCIE>;
@@ -433,7 +436,7 @@
pcie_phy: t-phy@11c00000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v4";
"mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -444,30 +447,11 @@
clocks = <&clk40m>;
clock-names = "ref";
#phy-cells = <1>;
auto_load_valid;
auto_load_valid_ln1;
nvmem-cells = <&pcie_intr_ln0>,
<&pcie_rx_imp_ln0>,
<&pcie_tx_imp_ln0>,
<&pcie_auto_load_valid_ln0>,
<&pcie_intr_ln1>,
<&pcie_rx_imp_ln1>,
<&pcie_tx_imp_ln1>,
<&pcie_auto_load_valid_ln1>;
nvmem-cell-names = "intr",
"rx_imp",
"tx_imp",
"auto_load_valid",
"intr_ln1",
"rx_imp_ln1",
"tx_imp_ln1",
"auto_load_valid_ln1";
};
};
efuse: efuse@11d00000 {
compatible = "mediatek,mt7986-efuse",
"mediatek,efuse";
compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
reg = <0 0x11d00000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -475,149 +459,50 @@
thermal_calibration: calib@274 {
reg = <0x274 0xc>;
};
comb_auto_load_valid: usb3-alv-imp@8da {
reg = <0x8da 1>;
bits = <0 1>;
};
comb_rx_imp_p0: usb3-rx-imp@8d8 {
reg = <0x8d8 1>;
bits = <0 5>;
};
comb_tx_imp_p0: usb3-tx-imp@8d8 {
reg = <0x8d8 2>;
bits = <5 5>;
};
comb_intr_p0: usb3-intr@8d9 {
reg = <0x8d9 1>;
bits = <2 6>;
};
u2_auto_load_valid_p0: usb2-alv-p0@8e0 {
reg = <0x8e0 1>;
bits = <0 1>;
};
u2_intr_p0: usb2-intr-p0@8e0 {
reg = <0x8e0 1>;
bits = <1 5>;
};
u2_auto_load_valid_p1: usb2-alv-p1@8e0 {
reg = <0x8e0 2>;
bits = <6 1>;
};
u2_intr_p1: usb2-intr-p1@8e0 {
reg = <0x8e0 2>;
bits = <7 5>;
};
pcie_rx_imp_ln0: pcie-rx-imp@8d0 {
reg = <0x8d0 1>;
bits = <0 5>;
};
pcie_tx_imp_ln0: pcie-tx-imp@8d0 {
reg = <0x8d0 2>;
bits = <5 5>;
};
pcie_intr_ln0: pcie-intr@8d1 {
reg = <0x8d1 1>;
bits = <2 6>;
};
pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 {
reg = <0x8d4 1>;
bits = <0 1>;
};
pcie_rx_imp_ln1: pcie-rx-imp@8d2 {
reg = <0x8d2 1>;
bits = <0 5>;
};
pcie_tx_imp_ln1: pcie-tx-imp@8d2 {
reg = <0x8d2 2>;
bits = <5 5>;
};
pcie_intr_ln1: pcie-intr@8d3 {
reg = <0x8d3 1>;
bits = <2 6>;
};
pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 {
reg = <0x8d4 1>;
bits = <1 1>;
};
};
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e10000 0x1700>;
status = "disabled";
u2port0: usb-phy@11e10000 {
reg = <0 0x11e10000 0 0x700>;
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
nvmem-cell-names = "intr", "auto_load_valid";
};
u3port0: usb-phy@11e10700 {
reg = <0 0x11e10700 0 0x900>;
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&comb_intr_p0>,
<&comb_rx_imp_p0>,
<&comb_tx_imp_p0>,
<&comb_auto_load_valid>;
nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
};
u2port1: usb-phy@11e11000 {
reg = <0 0x11e11000 0 0x700>;
u2port1: usb-phy@1000 {
reg = <0x1000 0x700>;
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
nvmem-cell-names = "intr", "auto_load_valid";
};
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7986-ethsys_ck",
compatible = "mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
wed0: wed@15010000 {
compatible = "mediatek,mt7986-wed",
"syscon";
@@ -700,95 +585,49 @@
status = "disabled";
};
consys: consys@10000000 {
compatible = "mediatek,mt7986-consys";
reg = <0 0x10000000 0 0x8600000>;
memory-region = <&wmcpu_emi>;
};
wmac: wmac@18000000 {
compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
wifi: wifi@18000000 {
compatible = "mediatek,mt7986-wmac";
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wmcpu_emi>;
status = "disabled";
};
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
cooling-levels = <0 86 172 255>;
#cooling-cells = <2>;
status = "disabled";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
cpu_trip_active_low: active-low {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <60000>;
cpu_trip_passive: passive {
temperature = <40000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
cpu-active-high {
/* active: set fan to cooling level 3 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
cpu-active-med {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
cpu-active-low {
/* passive: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
};
};

2
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
View File

@@ -56,7 +56,7 @@
status = "okay";
};
&wmac {
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;

3
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
View File

@@ -5,6 +5,9 @@
*/
#include "mt7986a.dtsi"
/ {
compatible = "mediatek,mt7986b";
};
&pio {
compatible = "mediatek,mt7986b-pinctrl";

2
target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c
View File

@@ -129,4 +129,4 @@ static void __init mtk_ethsys_init(struct device_node *node)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);
CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);

59
target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h
View File

@@ -1,10 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2021 MediaTek Inc. */
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_MT7986
#define _DT_BINDINGS_RESET_MT7986
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
#define MT7986_TOPRGU_CONSYS_RST 23
#define MT7986_TOPRGU_SW_RST_NUM 32
/* INFRACFG resets */
#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
#define MT7986_INFRACFG_SSUSB_SW_RST 7
#define MT7986_INFRACFG_EIP97_SW_RST 8
#define MT7986_INFRACFG_AUDIO_SW_RST 13
#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
#endif /* _DT_BINDINGS_RESET_MT7986 */
#define MT7986_INFRACFG_TRNG_SW_RST 17
#define MT7986_INFRACFG_AP_DMA_SW_RST 32
#define MT7986_INFRACFG_I2C_SW_RST 33
#define MT7986_INFRACFG_NFI_SW_RST 34
#define MT7986_INFRACFG_SPI0_SW_RST 35
#define MT7986_INFRACFG_SPI1_SW_RST 36
#define MT7986_INFRACFG_UART0_SW_RST 37
#define MT7986_INFRACFG_UART1_SW_RST 38
#define MT7986_INFRACFG_UART2_SW_RST 39
#define MT7986_INFRACFG_AUXADC_SW_RST 43
#define MT7986_INFRACFG_APXGPT_SW_RST 66
#define MT7986_INFRACFG_PWM_SW_RST 68
#define MT7986_INFRACFG_SW_RST_NUM 69
/* TOPRGU resets */
#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
#define MT7986_TOPRGU_SGMII0_SW_RST 1
#define MT7986_TOPRGU_SGMII1_SW_RST 2
#define MT7986_TOPRGU_INFRA_SW_RST 3
#define MT7986_TOPRGU_U2PHY_SW_RST 5
#define MT7986_TOPRGU_PCIE_SW_RST 6
#define MT7986_TOPRGU_SSUSB_SW_RST 7
#define MT7986_TOPRGU_ETHDMA_SW_RST 20
#define MT7986_TOPRGU_CONSYS_SW_RST 23
#define MT7986_TOPRGU_SW_RST_NUM 24
/* ETHSYS Subsystem resets */
#define MT7986_ETHSYS_FE_SW_RST 6
#define MT7986_ETHSYS_PMTR_SW_RST 8
#define MT7986_ETHSYS_GMAC_SW_RST 23
#define MT7986_ETHSYS_PPE0_SW_RST 30
#define MT7986_ETHSYS_PPE1_SW_RST 31
#define MT7986_ETHSYS_SW_RST_NUM 32
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */

15
target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version Normal file
View File

@@ -0,0 +1,15 @@
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
bananapi,bpi-r3)
ucidef_set_compat_version "1.1"
;;
esac
board_config_flush
exit 0

10
target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version Normal file
View File

@@ -0,0 +1,10 @@
. /lib/functions.sh
case "$(board_name)" in
bananapi,bpi-r3)
uci set system.@system[0].compat_version="1.1"
uci commit system
;;
esac
exit 0

10
target/linux/mediatek/image/filogic.mk
View File

@@ -96,8 +96,8 @@ define Device/bananapi_bpi-r3
DEVICE_MODEL := BPi-R3
DEVICE_DTS := mt7986a-bananapi-bpi-r3
DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3
DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-emmc-nor mt7986a-bananapi-bpi-r3-emmc-snand mt7986a-bananapi-bpi-r3-snand
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-emmc mt7986a-bananapi-bpi-r3-nand mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-sd
DEVICE_DTS_DIR := $(DTS_DIR)/
DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
IMAGES := sysupgrade.itb
KERNEL_LOADADDR := 0x44000000
@@ -135,7 +135,9 @@ define Device/bananapi_bpi-r3
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
DTC_FLAGS += -@ --space 32768
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
endef
TARGET_DEVICES += bananapi_bpi-r3
@@ -214,7 +216,6 @@ define Device/mediatek_mt7986a-rfb-nand
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
KERNEL_INITRAMFS = kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
DTC_FLAGS += -@ --space 32768
endef
TARGET_DEVICES += mediatek_mt7986a-rfb-nand
@@ -433,6 +434,5 @@ define Device/zyxel_ex5601-t0-stock
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
KERNEL_INITRAMFS = kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
DTC_FLAGS += -@ --space 32768
endef
TARGET_DEVICES += zyxel_ex5601-t0-stock

3
target/linux/mediatek/image/mt7622.mk
View File

@@ -70,6 +70,7 @@ define Device/bananapi_bpi-r64
DEVICE_DTS := mt7622-bananapi-bpi-r64
DEVICE_DTS_OVERLAY := mt7622-bananapi-bpi-r64-pcie1 mt7622-bananapi-bpi-r64-sata
DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck
DEVICE_DTC_FLAGS := --pad 4096
ARTIFACTS := emmc-preloader.bin emmc-bl31-uboot.fip sdcard.img.gz snand-preloader.bin snand-bl31-uboot.fip
IMAGES := sysupgrade.itb
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
@@ -96,6 +97,8 @@ define Device/bananapi_bpi-r64
KERNEL := kernel-bin | gzip
KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
endef
TARGET_DEVICES += bananapi_bpi-r64

15
target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version Normal file
View File

@@ -0,0 +1,15 @@
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
bananapi,bpi-r64)
ucidef_set_compat_version "1.1"
;;
esac
board_config_flush
exit 0

10
target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version Normal file
View File

@@ -0,0 +1,10 @@
. /lib/functions.sh
case "$(board_name)" in
bananapi,bpi-r64)
uci set system.@system[0].compat_version="1.1"
uci commit system
;;
esac
exit 0

17
target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch Normal file
View File

@@ -0,0 +1,17 @@
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -68,6 +68,14 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ record-size = <0x1000>;
+ };
+
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;

196
target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch Normal file
View File

@@ -0,0 +1,196 @@
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -23,6 +23,10 @@
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
+ led-boot = &green_led;
+ led-failsafe = &green_led;
+ led-running = &green_led;
+ led-upgrade = &blue_led;
};
chosen {
@@ -417,27 +421,27 @@
port@1 {
reg = <1>;
- label = "lan0";
+ label = "lan1";
};
port@2 {
reg = <2>;
- label = "lan1";
+ label = "lan2";
};
port@3 {
reg = <3>;
- label = "lan2";
+ label = "lan3";
};
port@4 {
reg = <4>;
- label = "lan3";
+ label = "lan4";
};
port5: port@5 {
reg = <5>;
- label = "lan4";
+ label = "sfp2";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
@@ -488,9 +492,137 @@
&wifi {
status = "okay";
- pinctrl-names = "default", "dbdc";
+ pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
+
+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
led {
led-active-low;
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
@@ -55,6 +55,7 @@
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
+ compatible = "denx,fit";
};
};
};

53
target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch Normal file
View File

@@ -0,0 +1,53 @@
From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 26 May 2023 10:31:40 +0100
Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623
The MT6380 regulator typically used together with MT7622 does not
support the current maximum processor and SRAM voltage in the cpufreq
driver (1360000uV).
For MT7622 limit processor and SRAM supply voltages to 1350000uV to
avoid having the tracking algorithm request unsupported voltages from
the regulator.
On MT7623 there is no separate SRAM supply and the maximum voltage used
is 1300000uV. Create dedicated platform data for MT7623 to cover that
case as well.
Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623")
Suggested-by: Jia-wei Chang <Jia-wei.Chang@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform
static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
.min_volt_shift = 100000,
.max_volt_shift = 200000,
- .proc_max_volt = 1360000,
+ .proc_max_volt = 1350000,
.sram_min_volt = 0,
- .sram_max_volt = 1360000,
+ .sram_max_volt = 1350000,
+ .ccifreq_supported = false,
+};
+
+static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1300000,
.ccifreq_supported = false,
};
@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },

29
target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch
View File

@@ -1,29 +0,0 @@
From 20aad28ba5d62f1618408c264384d0b2ad7417db Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Mon, 22 May 2023 23:25:48 +0100
Subject: [PATCH] cpufreq: mediatek: don't request unsupported voltage
PMICs on MT7622 and MT7623 boards only support up to 1350000uV despite
the SoC's processor and SRAM voltage can be up to 1360000uV. As a
work-around specify max. processor and SRAM voltage as 1350000uV to
avoid requesting an unsupported voltage from the regulator.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/cpufreq/mediatek-cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -696,9 +696,9 @@ static const struct mtk_cpufreq_platform
static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
.min_volt_shift = 100000,
.max_volt_shift = 200000,
- .proc_max_volt = 1360000,
+ .proc_max_volt = 1350000,
.sram_min_volt = 0,
- .sram_max_volt = 1360000,
+ .sram_max_volt = 1350000,
.ccifreq_supported = false,
};

55
target/linux/mediatek/patches-5.15/855-pending-i2c-mt65xx-add-additional-clocks.patch
View File

@@ -1,55 +0,0 @@
From 94bf61df9201195d6d8ce82e299fb231b31fbaae Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 26 May 2023 10:29:45 +0100
Subject: [PATCH] i2c: mt65xx: add additional clocks
On MT7981 additional clocks are required when accessing I2C registers.
Add MCK and PCK optional clocks to i2c-mt65xx driver so we don't have
to always have them enabled, but really only if I2C is used.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/i2c/busses/i2c-mt65xx.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -93,6 +93,8 @@
* @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
* @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
* @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
+ * @I2C_MT65XX_CLK_MCK: MCK clock for i2c
+ * @I2C_MT65XX_CLK_PCK: PCK clock for i2c
* @I2C_MT65XX_CLK_MAX: Number of supported clocks
*/
enum i2c_mt65xx_clks {
@@ -100,11 +102,13 @@ enum i2c_mt65xx_clks {
I2C_MT65XX_CLK_DMA,
I2C_MT65XX_CLK_PMIC,
I2C_MT65XX_CLK_ARB,
+ I2C_MT65XX_CLK_MCK,
+ I2C_MT65XX_CLK_PCK,
I2C_MT65XX_CLK_MAX
};
static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
- "main", "dma", "pmic", "arb"
+ "main", "dma", "pmic", "arb", "mck", "pck"
};
enum DMA_REGS_OFFSET {
@@ -1444,6 +1448,14 @@ static int mtk_i2c_probe(struct platform
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
+ i2c->clocks[I2C_MT65XX_CLK_MCK].clk = devm_clk_get_optional(&pdev->dev, "mck");
+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MCK].clk))
+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MCK].clk);
+
+ i2c->clocks[I2C_MT65XX_CLK_PCK].clk = devm_clk_get_optional(&pdev->dev, "pck");
+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PCK].clk))
+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PCK].clk);
+
if (i2c->have_pmic) {
i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {

4
target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
View File

@@ -10,7 +10,7 @@
gpios = <90 GPIO_ACTIVE_HIGH>;
output-high;
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
@@ -44,7 +44,7 @@
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+

9
target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
View File

@@ -11,7 +11,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -121,11 +121,6 @@
@@ -121,12 +121,6 @@
reg = <0 0x151f8000 0 0x2000>;
no-map;
};
@@ -20,10 +20,11 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
- reg = <0 0x15194000 0 0x1000>;
- no-map;
- };
-
};
timer {
@@ -625,10 +620,11 @@
@@ -518,10 +512,11 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
@@ -37,7 +38,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
wed1: wed@15011000 {
@@ -638,10 +634,11 @@
@@ -531,10 +526,11 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
@@ -51,7 +52,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
wo_ccif0: syscon@151a5000 {
@@ -658,6 +655,11 @@
@@ -551,6 +547,11 @@
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};

6
target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
View File

@@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
wo_data: wo-data@4fd80000 {
reg = <0 0x4fd80000 0 0x240000>;
no-map;
@@ -619,11 +609,10 @@
@@ -511,11 +501,10 @@
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
@@ -49,7 +49,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
@@ -633,11 +622,10 @@
@@ -525,11 +514,10 @@
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
@@ -64,7 +64,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
@@ -655,6 +643,16 @@
@@ -547,6 +535,16 @@
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};

6
target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
View File

@@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
timer {
@@ -609,10 +599,11 @@
@@ -501,10 +491,11 @@
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
@@ -48,7 +48,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
@@ -622,10 +613,11 @@
@@ -514,10 +505,11 @@
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
@@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
@@ -653,6 +645,16 @@
@@ -545,6 +537,16 @@
reg = <0 0x151f0000 0 0x8000>;
};