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mediatek: add custom u-boot layout for livinet zr-3020

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 9cbdf85e50)
This commit is contained in:
Tianling Shen
2023-06-25 21:05:55 +08:00
parent d4da1b05fc
commit 4cea01e4a3
9 changed files with 371 additions and 330 deletions
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1
package/boot/uboot-envtools/files/mediatek_filogic
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@@ -38,6 +38,7 @@ bananapi,bpi-r3)
esac
;;
livinet,zr-3020|\
livinet,zr-3020-ubootmod|\
qihoo,360t7-ubootmod)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" "1"
;;

16
target/linux/mediatek/dts/mt7981b-livinet-zr-3020-ubootmod.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7981b-livinet-zr-3020.dtsi"
/ {
model = "Livinet ZR-3020 (custom U-Boot layout)";
compatible = "livinet,zr-3020-ubootmod", "mediatek,mt7981";
}
&partitions {
partition@580000 {
label = "ubi";
reg = <0x580000 0x6000000>;
};
};

328
target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dts
View File

@@ -1,331 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "mt7981.dtsi"
#include "mt7981b-livinet-zr-3020.dtsi"
/ {
model = "Livinet ZR-3020";
compatible = "livinet,zr-3020", "mediatek,mt7981";
}
aliases {
led-boot = &boot_led;
led-failsafe = &boot_led;
led-running = &running_led;
led-upgrade = &upgrade_led;
serial0 = &uart0;
&partitions {
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
label = "red:d8";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led-1 {
label = "blue:internet";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
running_led: led-2 {
label = "blue:running";
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
upgrade_led: led-3 {
label = "green:upgrade";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
boot_led: led-4 {
label = "red:boot";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
led-6 {
label = "blue:d7";
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
};
led-7 {
label = "blue:wlan2g";
gpios = <&pio 34 GPIO_ACTIVE_LOW>;
};
led-8 {
label = "blue:wlan5g";
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
};
partition@4580000 {
label = "firmware_backup";
reg = <0x4580000 0x2000000>;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cells = <&macaddr_config_50707>;
nvmem-cell-names = "mac-address-ascii";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
&mdio_bus {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x100000 0x80000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
partition@4580000 {
label = "firmware_backup";
reg = <0x4580000 0x2000000>;
};
partition@6580000 {
label = "zrsave";
reg = <0x6580000 0x100000>;
};
partition@6680000 {
label = "config2";
reg = <0x6680000 0x100000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_5068a: macaddr@5068a {
reg = <0x5068a 0x11>;
};
macaddr_config_50707: macaddr@50707 {
reg = <0x50707 0x11>;
};
macaddr_config_50787: macaddr@50787 {
reg = <0x50787 0x11>;
};
};
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
nvmem-cells = <&macaddr_config_50787>;
nvmem-cell-names = "mac-address-ascii";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&pio {
i2c_pins: i2c-pins-g0 {
mux {
function = "i2c";
groups = "i2c0_0";
};
};
pcm_pins: pcm-pins-g0 {
mux {
function = "pcm";
groups = "pcm";
};
};
pwm0_pin: pwm0-pin-g0 {
mux {
function = "pwm";
groups = "pwm0_0";
};
};
pwm1_pin: pwm1-pin-g0 {
mux {
function = "pwm";
groups = "pwm1_0";
};
};
pwm2_pin: pwm2-pin {
mux {
function = "pwm";
groups = "pwm2";
};
};
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
uart1_pins: uart1-pins-g1 {
mux {
function = "uart";
groups = "uart1_1";
};
};
uart2_pins: uart2-pins-g1 {
mux {
function = "uart";
groups = "uart2_1";
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
nvmem-cells = <&macaddr_config_5068a>;
nvmem-cell-names = "mac-address-ascii";
};

318
target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dtsi Normal file
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@@ -0,0 +1,318 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "mt7981.dtsi"
/ {
aliases {
led-boot = &boot_led;
led-failsafe = &boot_led;
led-running = &running_led;
led-upgrade = &upgrade_led;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
label = "red:d8";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led-1 {
label = "blue:internet";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
running_led: led-2 {
label = "blue:running";
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
upgrade_led: led-3 {
label = "green:upgrade";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
boot_led: led-4 {
label = "red:boot";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
led-6 {
label = "blue:d7";
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
};
led-7 {
label = "blue:wlan2g";
gpios = <&pio 34 GPIO_ACTIVE_LOW>;
};
led-8 {
label = "blue:wlan5g";
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cells = <&macaddr_config_50707>;
nvmem-cell-names = "mac-address-ascii";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
&mdio_bus {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x100000 0x80000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>;
};
partition@6580000 {
label = "zrsave";
reg = <0x6580000 0x100000>;
};
partition@6680000 {
label = "config2";
reg = <0x6680000 0x100000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_config_5068a: macaddr@5068a {
reg = <0x5068a 0x11>;
};
macaddr_config_50707: macaddr@50707 {
reg = <0x50707 0x11>;
};
macaddr_config_50787: macaddr@50787 {
reg = <0x50787 0x11>;
};
};
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
nvmem-cells = <&macaddr_config_50787>;
nvmem-cell-names = "mac-address-ascii";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&pio {
i2c_pins: i2c-pins-g0 {
mux {
function = "i2c";
groups = "i2c0_0";
};
};
pcm_pins: pcm-pins-g0 {
mux {
function = "pcm";
groups = "pcm";
};
};
pwm0_pin: pwm0-pin-g0 {
mux {
function = "pwm";
groups = "pwm0_0";
};
};
pwm1_pin: pwm1-pin-g0 {
mux {
function = "pwm";
groups = "pwm1_0";
};
};
pwm2_pin: pwm2-pin {
mux {
function = "pwm";
groups = "pwm2";
};
};
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
uart1_pins: uart1-pins-g1 {
mux {
function = "uart";
groups = "uart1_1";
};
};
uart2_pins: uart2-pins-g1 {
mux {
function = "uart";
groups = "uart2_1";
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
nvmem-cells = <&macaddr_config_5068a>;
nvmem-cell-names = "mac-address-ascii";
};

2
target/linux/mediatek/dts/mt7981b-qihoo-360t7-ubootmod.dts
View File

@@ -7,7 +7,7 @@
#include "mt7981.dtsi"
/ {
model = "Qihoo 360T7 (modified U-Boot layout)";
model = "Qihoo 360T7 (custom U-Boot layout)";
compatible = "qihoo,360t7-ubootmod", "mediatek,mt7981";

3
target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
View File

@@ -9,7 +9,8 @@ case $board in
cudy,wr3000-v1)
ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan"
;;
livinet,zr-3020)
livinet,zr-3020|\
livinet,zr-3020-ubootmod)
ucidef_set_led_netdev "internet" "INTERNET" "blue:internet" "wan"
ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"
ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0"

1
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View File

@@ -16,6 +16,7 @@ mediatek_setup_interfaces()
;;
cudy,wr3000-v1|\
livinet,zr-3020|\
livinet,zr-3020-ubootmod|\
qihoo,360t7|\
qihoo,360t7-ubootmod)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"

3
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View File

@@ -32,7 +32,8 @@ case "$board" in
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
;;
livinet,zr-3020)
livinet,zr-3020|\
livinet,zr-3020-ubootmod)
addr=$(mtd_get_mac_ascii config2 wifi5gmac)
[ "$PHYNBR" = "1" ] && echo $macaddr > /sys${DEVPATH}/macaddress
;;

29
target/linux/mediatek/image/filogic.mk
View File

@@ -176,16 +176,13 @@ define Device/glinet_gl-mt3000
endef
TARGET_DEVICES += glinet_gl-mt3000
define Device/livinet_zr-3020
define Device/livinet_zr-3020-common
DEVICE_VENDOR := Livinet
DEVICE_MODEL := ZR-3020
DEVICE_DTS := mt7981b-livinet-zr-3020
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
@@ -195,8 +192,24 @@ define Device/livinet_zr-3020
KERNEL_INITRAMFS = kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
endef
define Device/livinet_zr-3020
DEVICE_MODEL := ZR-3020 (stock layout)
DEVICE_DTS := mt7981b-livinet-zr-3020
SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-gsw-rfb
IMAGE_SIZE := 65536k
$(call Device/livinet_zr-3020-common)
endef
TARGET_DEVICES += livinet_zr-3020
define Device/livinet_zr-3020-ubootmod
DEVICE_MODEL := ZR-3020 (custom U-Boot layout)
DEVICE_DTS := mt7981b-livinet-zr-3020-ubootmod
IMAGE_SIZE := 98304k
$(call Device/livinet_zr-3020-common)
endef
TARGET_DEVICES += livinet_zr-3020-ubootmod
define Device/mediatek_mt7986a-rfb-nand
DEVICE_VENDOR := MediaTek
DEVICE_MODEL := MT7986 rfba AP (NAND)
@@ -281,7 +294,7 @@ TARGET_DEVICES += qihoo_360t7
define Device/qihoo_360t7-ubootmod
DEVICE_VENDOR := Qihoo
DEVICE_MODEL := 360T7 (modified U-Boot layout)
DEVICE_MODEL := 360T7 (custom U-Boot layout)
DEVICE_DTS := mt7981b-qihoo-360t7-ubootmod
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
@@ -347,10 +360,10 @@ TARGET_DEVICES += tplink_tl-xdr6088
define Device/xiaomi_redmi-router-ax6000
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := Redmi Router AX6000 (modified U-Boot layout)
DEVICE_MODEL := Redmi Router AX6000 (custom U-Boot layout)
DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-leds-ws2812b
DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
KERNEL_LOADADDR := 0x48000000
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
@@ -407,7 +420,7 @@ TARGET_DEVICES += xiaomi_redmi-router-ax6000-ubootmod
define Device/zyxel_ex5601-t0-stock
DEVICE_VENDOR := Zyxel
DEVICE_MODEL := EX5601-T0 (stock layout)
DEVICE_MODEL := EX5601-T0 (stock layout)
DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware