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rockchip: refresh rk3588 patchset

Browse Source 
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-07-12 17:20:57 +08:00
parent dec8c4080e
commit 5acf2d56af
30 changed files with 586 additions and 291 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
target/linux/rockchip/patches-6.1/117-01-clk-composite-Fix-handling-of-high-clock-rates.patch → target/linux/rockchip/patches-6.1/030-11-v6.4-clk-composite-Fix-handling-of-high-clock-rates.patch
View File

@@ -1,6 +1,6 @@
From 3ef7ead7ba37665e0b197f6ae5c2e1f4e043f334 Mon Sep 17 00:00:00 2001
From d54fb4b25a0261bf2f2bb7093fdf11a36718bf25 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:28:17 +0200
Date: Fri, 26 May 2023 19:10:56 +0200
Subject: [PATCH] clk: composite: Fix handling of high clock rates
ULONG_MAX is used by a few drivers to figure out the highest available
@@ -34,6 +34,9 @@ Cc: stable@vger.kernel.org
Fixes: 49502408007b ("mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip")
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230526171057.66876-2-sebastian.reichel@collabora.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/clk-composite.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

0
target/linux/rockchip/patches-6.1/034-v6.4-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch → target/linux/rockchip/patches-6.1/034-01-v6.4-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch
View File

20
target/linux/rockchip/patches-6.1/112-01-phy-phy-rockchip-inno-usb2-add-rk3588-support.patch → target/linux/rockchip/patches-6.1/034-02-v6.6-phy-phy-rockchip-inno-usb2-add-rk3588-support.patch
View File

@@ -1,25 +1,15 @@
From 52b99b871eb79637342660b46c900642483d4412 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com, William Wu <william.wu@rock-chips.com>
Subject: [PATCH v3 2/7] phy: phy-rockchip-inno-usb2: add rk3588 support
Date: Mon, 22 May 2023 19:03:19 +0200 [thread overview]
Message-ID: <20230522170324.61349-3-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:19 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3588 support
Add basic support for the USB2 PHY found in the Rockchip RK3588.
Co-developed-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-3-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 226 ++++++++++++++++--
1 file changed, 211 insertions(+), 15 deletions(-)

20
target/linux/rockchip/patches-6.1/112-02-phy-phy-rockchip-inno-usb2-add-reset-support.patch → target/linux/rockchip/patches-6.1/034-03-v6.6-phy-phy-rockchip-inno-usb2-add-reset-support.patch
View File

@@ -1,24 +1,14 @@
From 44d88aa9ae81c79ccc47ba4ef85aeda968bc4a50 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v3 3/7] phy: phy-rockchip-inno-usb2: add reset support
Date: Mon, 22 May 2023 19:03:20 +0200 [thread overview]
Message-ID: <20230522170324.61349-4-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:20 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add reset support
Add reset handling support, which is needed for proper
operation with RK3588.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-4-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)

20
target/linux/rockchip/patches-6.1/112-03-phy-phy-rockchip-inno-usb2-add-rk3588-phy-tuning-support.patch → target/linux/rockchip/patches-6.1/034-04-v6.6-phy-phy-rockchip-inno-usb2-add-rk3588-phy-tuning-support.patch
View File

@@ -1,19 +1,7 @@
From 7d508a92e4588a59b909e235667d515051dd5955 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v3 4/7] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning support
Date: Mon, 22 May 2023 19:03:21 +0200 [thread overview]
Message-ID: <20230522170324.61349-5-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:21 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning support
On RK3588 some registers need to be tweaked to support waking up from
suspend when a USB device is plugged into a port from a suspended PHY.
@@ -24,6 +12,8 @@ Apart from that it optimizes settings to avoid devices toggling
between fullspeed and highspeed mode.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-5-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)

20
target/linux/rockchip/patches-6.1/112-04-phy-phy-rockchip-inno-usb2-simplify-phy-clock-handling.patch → target/linux/rockchip/patches-6.1/034-05-v6.6-phy-phy-rockchip-inno-usb2-simplify-phy-clock-handling.patch
View File

@@ -1,25 +1,15 @@
From f4ca578b9803601074ab0d9e366b5fcda504e5a6 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v3 5/7] phy: phy-rockchip-inno-usb2: simplify phy clock handling
Date: Mon, 22 May 2023 19:03:22 +0200 [thread overview]
Message-ID: <20230522170324.61349-6-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:22 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: simplify phy clock handling
Simplify phyclk handling by using devm_clk_get_optional_enabled to
acquire and enable the optional clock. This also fixes a resource
leak in driver remove path and adds proper error handling.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-6-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)

20
target/linux/rockchip/patches-6.1/112-05-phy-phy-rockchip-inno-usb2-simplify-getting-match-data.patch → target/linux/rockchip/patches-6.1/034-06-v6.6-phy-phy-rockchip-inno-usb2-simplify-getting-match-data.patch
View File

@@ -1,24 +1,14 @@
From 2e5ead8478e8e4a7b3d63a2001c2f0022b2f5e1b Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v3 6/7] phy: phy-rockchip-inno-usb2: simplify getting match data
Date: Mon, 22 May 2023 19:03:23 +0200 [thread overview]
Message-ID: <20230522170324.61349-7-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:23 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: simplify getting match data
Simplify the code by directly getting the match data via
device_get_match_data() instead of open coding its functionality.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-7-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)

20
target/linux/rockchip/patches-6.1/112-06-phy-phy-rockchip-inno-usb2-improve-error-message.patch → target/linux/rockchip/patches-6.1/034-07-v6.6-phy-phy-rockchip-inno-usb2-improve-error-message.patch
View File

@@ -1,25 +1,15 @@
From e7254a4a7c444fa194440fa8dc73c7728e927162 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v3 7/7] phy: phy-rockchip-inno-usb2: improve error message
Date: Mon, 22 May 2023 19:03:24 +0200 [thread overview]
Message-ID: <20230522170324.61349-8-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522170324.61349-1-sebastian.reichel@collabora.com>
Date: Mon, 22 May 2023 19:03:24 +0200
Subject: [PATCH] phy: phy-rockchip-inno-usb2: improve error message
Printing the OF node is not useful, since we get the same information
from the device context. Instead print the reg address, that could
not be found.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230522170324.61349-8-sebastian.reichel@collabora.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

6
target/linux/rockchip/patches-6.1/111-usb-host-ohci-platform-increase-max-clock-number-to-4.patch → target/linux/rockchip/patches-6.1/039-v6.5-usb-host-ohci-platform-increase-max-clock-number-to-4.patch
View File

@@ -1,12 +1,14 @@
From eb587e7611e9c61f5a8af5d9bfc4f994e9e1fda2 Mon Sep 17 00:00:00 2001
From fba985aaf46391066773f3bf3a08fb6e75b37673 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 29 Mar 2023 18:54:49 +0200
Date: Mon, 22 May 2023 18:29:37 +0200
Subject: [PATCH] usb: host: ohci-platform: increase max clock number to 4
Rockchip RK3588 OHCI requires 4 clocks to be enabled.
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230522162937.53190-4-sebastian.reichel@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/host/ohci-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

31
target/linux/rockchip/patches-6.1/113-01-arm64-dts-rockchip-rk3588-add-combo-PHYs.patch → target/linux/rockchip/patches-6.1/050-17-v6.6-arm64-dts-rockchip-add-combo-PHYs-to-rk3588.patch
View File

@@ -1,25 +1,14 @@
From 6ebd55b3bba383e0523b0c014f17c97f3ce80708 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Serge Semin <fancer.lancer@gmail.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-ide@vger.kernel.org, linux-phy@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 5/6] arm64: dts: rockchip: rk3588: add combo PHYs
Date: Mon, 22 May 2023 19:34:22 +0200 [thread overview]
Message-ID: <20230522173423.64691-6-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522173423.64691-1-sebastian.reichel@collabora.com>
Date: Mon, 12 Jun 2023 19:13:36 +0200
Subject: [PATCH] arm64: dts: rockchip: add combo PHYs to rk3588
Add all 3 combo PHYs that can be found in RK3588.
They are used for SATA, PCIe or USB3.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230612171337.74576-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++
@@ -47,12 +36,12 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ combphy1_ps: phy@fee10000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee10000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
@@ -62,7 +51,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
};
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -944,6 +944,16 @@
@@ -398,6 +398,16 @@
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
@@ -79,19 +68,19 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2480,6 +2490,38 @@
@@ -1934,6 +1944,38 @@
#dma-cells = <1>;
};
+ combphy0_ps: phy@fee00000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee00000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
@@ -102,12 +91,12 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ combphy2_psu: phy@fee20000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee20000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;

33
target/linux/rockchip/patches-6.1/114-02-arm64-dts-rockchip-rk3588-add-SATA-support.patch → target/linux/rockchip/patches-6.1/050-18-v6.6-arm64-dts-rockchip-add-SATA-support-to-rk3588.patch
View File

@@ -1,24 +1,13 @@
From 34d6c15d8e86256ef2456c604b1c8d8242720871 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Serge Semin <fancer.lancer@gmail.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-ide@vger.kernel.org, linux-phy@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 6/6] arm64: dts: rockchip: rk3588: add SATA support
Date: Mon, 22 May 2023 19:34:23 +0200 [thread overview]
Message-ID: <20230522173423.64691-7-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20230522173423.64691-1-sebastian.reichel@collabora.com>
Date: Mon, 12 Jun 2023 19:13:37 +0200
Subject: [PATCH] arm64: dts: rockchip: add SATA support to rk3588
Add all three SATA IP blocks to the RK3588 DT.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230612171337.74576-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++
@@ -33,11 +22,11 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ sata1: sata@fe220000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe220000 0 0x1000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
@@ -58,27 +47,27 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
reg = <0x0 0xfee10000 0x0 0x100>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -9,6 +9,8 @@
@@ -8,6 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/ata/ahci.h>
/ {
compatible = "rockchip,rk3588";
@@ -1717,6 +1719,52 @@
@@ -1171,6 +1173,52 @@
};
};
+ sata0: sata@fe210000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe210000 0 0x1000>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
@@ -97,11 +86,11 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ sata2: sata@fe230000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe230000 0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;

22
target/linux/rockchip/patches-6.1/114-03-arm64-dts-rockchip-rk3588-evb1-add-SATA.patch → target/linux/rockchip/patches-6.1/051-03-v6.6-arm64-dts-rockchip-enable-SATA-on-rk3588-evb1.patch
View File

@@ -1,20 +1,23 @@
From 0af5c1ec425427c0c49b8185e2ca301262062ce2 Mon Sep 17 00:00:00 2001
From 9c7f24941927f8ca6760eef0309e00e260f0017a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 6 Apr 2023 17:32:02 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add SATA
Date: Tue, 11 Jul 2023 19:13:30 +0200
Subject: [PATCH] arm64: dts: rockchip: enable SATA on rk3588-evb1
Add support for the SATA0_0 port found on the RK3588 EVB1. The
second port (SATA0_1) does not work, which matches the downstream
behaviour.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230711171330.52535-1-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -843,6 +843,14 @@
@@ -49,6 +49,10 @@
};
};
@@ -22,10 +25,17 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -760,6 +764,10 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
&tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

65
target/linux/rockchip/patches-6.1/053-13-v6.6-arm64-dts-rockchip-Update-sound-card-label-on-rk3588-rock.patch Normal file
View File

@@ -0,0 +1,65 @@
From 7efcaf997ae624caeccd046b6266fc2b7c0b91dc Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Fri, 7 Jul 2023 19:28:22 +0300
Subject: [PATCH] arm64: dts: rockchip: Update sound card label on rk3588-rock-5b
The audio-graph-card driver uses the 'label' property to register the
sound card in the system, but the currently assigned string is too
generic and cannot be supported by alsa-project/alsa-ucm-conf:
card 0: Analog [Analog]
Use the more specific naming "rk3588-es8316", which is still generic
enough to be shared with other compatible boards, e.g. Rock 5A. The
audio card will be listed as:
card 0: rk3588es8316 [rk3588-es8316]
While at it, update also the DT node name, as there will be additional
sound related nodes available, i.e. for HDMI. Note that this involves
moving the node one position up, to preserve the alphabetical order.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230707162822.676024-1-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -18,17 +18,9 @@
stdout-path = "serial2:1500000n8";
};
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
- fan-supply = <&vcc5v0_sys>;
- pwms = <&pwm1 0 50000 0>;
- #cooling-cells = <2>;
- };
-
- sound {
+ analog-sound {
compatible = "audio-graph-card";
- label = "Analog";
+ label = "rk3588-es8316";
widgets = "Microphone", "Mic Jack",
"Headphone", "Headphones";
@@ -43,6 +35,14 @@
pinctrl-0 = <&hp_detect>;
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";

28
target/linux/rockchip/patches-6.1/110-02-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch
View File

@@ -17,15 +17,15 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
@@ -10,6 +10,7 @@
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3588";
@@ -16,6 +17,215 @@
@@ -18,6 +19,215 @@
#address-cells = <2>;
#size-cells = <2>;
@@ -241,7 +241,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -62,6 +272,7 @@
@@ -64,6 +274,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
@@ -249,7 +249,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -81,6 +292,7 @@
@@ -83,6 +294,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -257,7 +257,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -100,6 +312,7 @@
@@ -102,6 +314,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -265,7 +265,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -119,6 +332,7 @@
@@ -121,6 +334,7 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -273,7 +273,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -140,6 +354,7 @@
@@ -142,6 +356,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
@@ -281,7 +281,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -159,6 +374,7 @@
@@ -161,6 +376,7 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
@@ -289,7 +289,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -180,6 +396,7 @@
@@ -182,6 +398,7 @@
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
@@ -297,7 +297,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -199,6 +416,7 @@
@@ -201,6 +418,7 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
@@ -305,7 +305,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -351,6 +569,230 @@
@@ -353,6 +571,230 @@
#clock-cells = <0>;
};
@@ -536,7 +536,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -393,6 +835,16 @@
@@ -395,6 +837,16 @@
reg = <0x0 0xfd58c000 0x0 0x1000>;
};

6
target/linux/rockchip/patches-6.1/110-03-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch
View File

@@ -13,7 +13,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -81,6 +81,21 @@
@@ -85,6 +85,21 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
@@ -35,8 +35,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -760,6 +775,10 @@
};
@@ -768,6 +783,10 @@
status = "okay";
};
+&tsadc {

4
target/linux/rockchip/patches-6.1/112-07-arm64-dts-rockchip-rk3588-add-USB2-support.patch → target/linux/rockchip/patches-6.1/112-01-arm64-dts-rockchip-rk3588-add-USB2-support.patch
View File

@@ -1,4 +1,4 @@
From 734459837fe67a306f7fe63ab03c0c2c0042bf7c Mon Sep 17 00:00:00 2001
From c10b7b902f6d8d1b550c6b4ccd8615f407ca85a3 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 12 Jan 2023 19:20:37 +0100
Subject: [PATCH] arm64: dts: rockchip: rk3588: add USB2 support
@@ -13,7 +13,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -830,11 +830,105 @@
@@ -832,11 +832,105 @@
};
};

8
target/linux/rockchip/patches-6.1/112-08-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch → target/linux/rockchip/patches-6.1/112-02-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch
View File

@@ -1,4 +1,4 @@
From dc6a92371915067b5f8880bacae21498eaab69dd Mon Sep 17 00:00:00 2001
From 71c7890f2ecefdcd2fd4afeb0d1c0c0b97fe833d Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 12 Jan 2023 19:23:27 +0100
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add USB2
@@ -52,8 +52,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
};
&cpu_b0 {
@@ -96,6 +130,40 @@
&combphy0_ps {
@@ -100,6 +134,40 @@
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
@@ -94,7 +94,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -783,3 +851,11 @@
@@ -791,3 +859,11 @@
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

2
target/linux/rockchip/patches-6.1/112-09-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch → target/linux/rockchip/patches-6.1/112-03-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch
View File

@@ -1,4 +1,4 @@
From ec584a8d73148b9c936edbea13b4badc1de41069 Mon Sep 17 00:00:00 2001
From 8c64d17408c023fcb23133bd74c436f991a6f4f9 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 30 Mar 2023 15:44:36 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-rock5b: add USB2

14
target/linux/rockchip/patches-6.1/115-01-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch
View File

@@ -1,4 +1,4 @@
From b14fea6eb11e6e11c1747e54110c7223d102b0ed Mon Sep 17 00:00:00 2001
From 9afd072bbcb97efccf1be82515cbe4ba682cce38 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 17 Apr 2023 20:03:08 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588: add PCIe2 support
@@ -6,12 +6,8 @@ Subject: [PATCH] arm64: dts: rockchip: rk3588: add PCIe2 support
Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588
also has two PCIe3 IP blocks, that will be handled separately.
TODO: FIXME: this is not compliant with the DT binding. There is
one additional clock ("pipe"), one additional reset line, the
interrupt-names do not match
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 54 +++++++++++
@@ -60,7 +56,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
+ <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ reg = <0xa 0x40800000 0x0 0x00400000>,
+ <0x0 0xfe170000 0x0 0x00010000>,
+ <0x0 0xf2000000 0x0 0x00100000>;
@@ -123,7 +119,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
+ <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ reg = <0xa 0x40c00000 0x0 0x00400000>,
+ <0x0 0xfe180000 0x0 0x00010000>,
+ <0x0 0xf3000000 0x0 0x00100000>;
@@ -177,7 +173,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+ <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ reg = <0xa 0x41000000 0x0 0x00400000>,
+ <0x0 0xfe190000 0x0 0x00010000>,
+ <0x0 0xf4000000 0x0 0x00100000>;

12
target/linux/rockchip/patches-6.1/115-02-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-support.patch → target/linux/rockchip/patches-6.1/115-02-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network.patch
View File

@@ -1,13 +1,11 @@
From 871085534221b58ff5ed26c5852618decd83a1a4 Mon Sep 17 00:00:00 2001
From ee48c5b7edb4ff3b8a23e7c32cbf33ae892e7cc1 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 17 Apr 2023 21:13:03 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add PCIe2 support
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add PCIe2 network
controller
The RK3588 EVB1 has a second network card, which is connected
via a PCIe2 block. This adds support for that.
The patch also enables the first PCIe2 block. I did not test
its functionality, but the board boots up properly.
via PCIe2. This adds support for that.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
@@ -42,7 +40,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
};
&cpu_b0 {
&combphy0_ps {
@@ -860,10 +880,27 @@
status = "okay";
};

26
target/linux/rockchip/patches-6.1/115-03-arm64-dts-rockchip-RK3588s-Enable-PCIE2-0x1-fe190000.patch → target/linux/rockchip/patches-6.1/115-03-arm64-dts-rockchip-rock-5b-add-PCIe-network-controller.patch
View File

@@ -1,24 +1,23 @@
From 43227cd535520a31510c9db45e96686575bfb1e1 Mon Sep 17 00:00:00 2001
From: Lucas Tanure <lucas.tanure@collabora.com>
From 3a0dbc8a3fc183503f847fc21976026044021285 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 28 Feb 2023 14:40:59 +0000
Subject: [PATCH] arm64: dts: rockchip: RK3588s: Enable PCIE2.0x1 @fe190000
Subject: [PATCH] arm64: dts: rockchip: rock-5b: add PCIe network controller
Enable PCIE2.0x1 @fe190000 for RTL8125 network controller in
Rock 5B board.
Enable the RTL8125 network controller, which is connected via
PCIe.
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -76,6 +76,15 @@
pinctrl-0 = <&vcc5v0_host_en>;
@@ -63,6 +63,15 @@
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 {
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
@@ -26,9 +25,10 @@ Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
};
&cpu_b0 {
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -623,3 +632,14 @@
};
};

81
target/linux/rockchip/patches-6.1/117-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch Normal file
View File

@@ -0,0 +1,81 @@
From 80094450f857ce8e5e00c1952f072eede3902f64 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:19:48 +0200
Subject: [PATCH] clk: divider: Fix divisor masking on 64 bit platforms
The clock framework handles clock rates as "unsigned long", so u32 on
32-bit architectures and u64 on 64-bit architectures.
The current code casts the dividend to u64 on 32-bit to avoid a
potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000)
= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been
introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow
when dividing large clock rates").
On 64 bit platforms this masks the divisor, so that only the lower
32 bit are used. Thus requesting a frequency >= 4.3GHz results
in incorrect values. For example requesting 4300000000 (4.3 GHz) will
effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
is a bit of a special case, since that still returns correct values as
long as the parent clock is below 8.5 GHz.
Fix this by introducing a new helper, which avoids the overflow
by using a modulo operation instead of math tricks. This avoids
any requirements on the arguments (except that divisor should not
be 0 obviously).
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/clk-divider.c | 6 +++---
include/linux/math.h | 11 +++++++++++
2 files changed, 14 insertions(+), 3 deletions(-)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl
unsigned long parent_rate, unsigned long rate,
unsigned long flags)
{
- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
if (flags & CLK_DIVIDER_POWER_OF_TWO)
div = __roundup_pow_of_two(div);
@@ -237,7 +237,7 @@ static int _div_round_closest(const stru
int up, down;
unsigned long up_rate, down_rate;
- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
down = parent_rate / rate;
if (flags & CLK_DIVIDER_POWER_OF_TWO) {
@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate,
{
unsigned int div, value;
- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
if (!_is_valid_div(table, div, flags))
return -EINVAL;
--- a/include/linux/math.h
+++ b/include/linux/math.h
@@ -36,6 +36,17 @@
#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+/**
+ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up
+ * @n: numerator / dividend
+ * @d: denominator / divisor
+ *
+ * This functions does the same as DIV_ROUND_UP, but internally uses a
+ * division and a modulo operation instead of math tricks. This way it
+ * avoids overflowing when handling big numbers.
+ */
+#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d)))
+
#define DIV_ROUND_DOWN_ULL(ll, d) \
({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })

52
target/linux/rockchip/patches-6.1/117-02-clk-divider-Fix-divisions.patch
View File

@@ -1,52 +0,0 @@
From dd6d843b8fbad84cc585a1379bffd99004c83b79 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 May 2023 05:19:48 +0200
Subject: [PATCH] clk: divider: Fix divisions
The clock framework handles clock rates as "unsigned long", so u32 on
32-bit architectures and u64 on 64-bit architectures.
The current code pointlessly casts the dividend to u64 on 32-bit
architectures and thus pointlessly reducing the performance.
On the other hand on 64-bit architectures the divisor is masked and only
the lower 32-bit are used. Thus requesting a frequency >= 4.3GHz results
in incorrect values. For example requesting 4300000000 (4.3 GHz) will
effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
is a bit of a special case, since that still returns correct values as
long as the parent clock is below 8.5 GHz.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/clk-divider.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl
unsigned long parent_rate, unsigned long rate,
unsigned long flags)
{
- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ int div = DIV_ROUND_UP(parent_rate, rate);
if (flags & CLK_DIVIDER_POWER_OF_TWO)
div = __roundup_pow_of_two(div);
@@ -237,7 +237,7 @@ static int _div_round_closest(const stru
int up, down;
unsigned long up_rate, down_rate;
- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ up = DIV_ROUND_UP(parent_rate, rate);
down = parent_rate / rate;
if (flags & CLK_DIVIDER_POWER_OF_TWO) {
@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate,
{
unsigned int div, value;
- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ div = DIV_ROUND_UP(parent_rate, rate);
if (!_is_valid_div(table, div, flags))
return -EINVAL;

72
target/linux/rockchip/patches-6.1/117-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch Normal file
View File

@@ -0,0 +1,72 @@
From a5f467748264d9a337cb40083efde04c748d8c3e Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 13 Jun 2023 16:45:05 +0200
Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
Currently pclk_vo1grf is not exposed, but it should be referenced
from the vo1_grf syscon, which needs it enabled. That syscon will
be required for HDMI-RX functionality among other things.
Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
and need the VO's hclk enabled in addition to their parent clock.
No Fixes tag has been added, since the logic requiring these clocks
is not yet upstream anyways.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 11 +++++------
include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++-
2 files changed, 7 insertions(+), 7 deletions(-)
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
RK3588_CLKGATE_CON(56), 0, GFLAGS),
GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 1, GFLAGS),
- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
- RK3588_CLKGATE_CON(55), 10, GFLAGS),
COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(56), 11, GFLAGS),
@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
RK3588_CLKGATE_CON(60), 9, GFLAGS),
GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(60), 10, GFLAGS),
- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
- RK3588_CLKGATE_CON(59), 12, GFLAGS),
GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(59), 14, GFLAGS),
GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
@@ -2447,12 +2443,15 @@ static struct rockchip_clk_branch rk3588
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
+
};
static void __init rk3588_clk_init(struct device_node *np)
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
@@ -733,8 +733,9 @@
#define ACLK_AV1_PRE 718
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
+#define PCLK_VO1GRF 721
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+#define CLK_NR_CLKS (PCLK_VO1GRF + 1)
/* scmi-clocks indices */

27
target/linux/rockchip/patches-6.1/119-01-phy-rockchip-add-usbdp-combo-phy-driver.patch
View File

@@ -1,7 +1,7 @@
From 7575bee7ee718cae56720eb1cd137df3aea65c73 Mon Sep 17 00:00:00 2001
From 76dce9a4e101c5f961f91a3ddef99660081cadd5 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Tue, 25 Apr 2023 15:55:54 +0200
Subject: [PATCH 80/85] phy: rockchip: add usbdp combo phy driver
Subject: [PATCH] phy: rockchip: add usbdp combo phy driver
This adds a new USBDP combo PHY with Samsung IP block driver.
@@ -12,21 +12,21 @@ the property "rockchip,dp-lane-mux" provide the DP mux and mapping info.
When do DP link training, need to set lane number, link rate, swing, and
pre-emphasis via PHY configure interface.
Co-Developed-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Co-developed-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Co-Developed-by: Frank Wang <frank.wang@rock-chips.com>
Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Kconfig | 12 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 1728 +++++++++++++++++++++
3 files changed, 1738 insertions(+)
3 files changed, 1741 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -107,3 +107,12 @@ config PHY_ROCKCHIP_USB
@@ -107,3 +107,15 @@ config PHY_ROCKCHIP_USB
select GENERIC_PHY
help
Enable this to support the Rockchip USB 2.0 PHY.
@@ -37,8 +37,11 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ select GENERIC_PHY
+ select TYPEC
+ help
+ Enable this to support the Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
+ Enable this to support the Rockchip USB3.0/DP combo PHY with
+ Samsung IP block. This is required for USB3 support on RK3588.
+
+ To compile this driver as a module, choose M here: the module
+ will be called phy-rockchip-usbdp
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-
@@ -1308,7 +1311,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ id = 0;
+ udphy->id = id;
+
+ phy_cfgs = of_device_get_match_data(dev);
+ phy_cfgs = device_get_match_data(dev);
+ if (!phy_cfgs) {
+ dev_err(dev, "no OF data can be matched with %p node\n", np);
+ return -EINVAL;
@@ -1347,7 +1350,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ return ret;
+ }
+
+ if (device_property_present(dev, "svid")) {
+ if (device_property_present(dev, "mode-switch")) {
+ ret = udphy_setup_typec_mux(udphy);
+ if (ret)
+ return ret;
@@ -1776,4 +1779,4 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
+MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_LICENSE("GPL");

4
target/linux/rockchip/patches-6.1/119-02-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
View File

@@ -1,7 +1,7 @@
From 131f987dd64516874607913481c8b124e129c3a3 Mon Sep 17 00:00:00 2001
From 15e8ed9380726e7f27c886faa43df7be484f61e8 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 17:49:04 +0200
Subject: [PATCH 81/85] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes
Add both USB3-Displayport PHYs from RK3588.

66
target/linux/rockchip/patches-6.1/119-03-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch
View File

@@ -1,30 +1,32 @@
From 05f5bff9db6d1c8a8513ccd588102a758d13ec37 Mon Sep 17 00:00:00 2001
From c062260a0e652da798f7130ec25c6452957456d5 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 18:17:19 +0200
Subject: [PATCH 82/85] arm64: dts: rockchip: rk3588s: Add USB3 controllers
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 controllers
Add all USB3 controllers.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 29 +++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 62 +++++++++++++++++++++++
2 files changed, 91 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 29 ++++++++++-
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 60 ++++++++++++++++++++++-
2 files changed, 87 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,35 @@
@@ -7,6 +7,34 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ usbdrd3_1: usbdrd3_1 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ usbdrd3_1: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref", "suspend", "bus";
+ ranges;
+ resets = <&cru SRST_A_USB3OTG1>;
+ reset-names = "usb3-otg";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_1: usb@fc400000 {
@@ -32,8 +34,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ reset-names = "usb3-otg";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
@@ -42,27 +42,36 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+ };
+
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -34,7 +62,6 @@
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
#clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy1_otg: otg-port {
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -832,6 +832,38 @@
@@ -832,6 +832,36 @@
};
};
+ usbdrd3_0: usbdrd3_0 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ usbdrd3_0: usb@fc000000 {
+ compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref", "suspend", "bus";
+ ranges;
+ resets = <&cru SRST_A_USB3OTG0>;
+ reset-names = "usb3-otg";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_0: usb@fc000000 {
@@ -70,8 +79,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ reset-names = "usb3-otg";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
@@ -82,35 +89,33 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ quirk-skip-phy-init;
+ status = "disabled";
+ };
+ };
+
usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -876,6 +908,36 @@
@@ -876,6 +906,35 @@
status = "disabled";
};
+ usbhost3_0: usbhost3_0 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ usbhost3_0: usb@fcd00000 {
+ compatible = "rockchip,rk3588-dwc3-host", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
+ <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
+ clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
+ ranges;
+ resets = <&cru SRST_A_USB3OTG2>;
+ reset-names = "usb3-host";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbhost_dwc3_0: usb@fcd00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfcd00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_A_USB3OTG2>;
+ reset-names = "usb3-host";
+ dr_mode = "host";
+ phys = <&combphy2_psu PHY_TYPE_USB3>;
+ phy-names = "usb3-phy";
@@ -120,10 +125,17 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+ };
+
sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -898,7 +957,6 @@
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
#clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy0_otg: otg-port {

187
target/linux/rockchip/patches-6.1/119-04-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch Normal file
View File

@@ -0,0 +1,187 @@
From 3b53c3be9599f04e6ac116ea89bd2c93a420b00b Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 26 Apr 2023 21:18:43 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add USB3
Add support for the boards USB3 type A, as well as its Type-C
connector.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 149 ++++++++++++++++++
1 file changed, 149 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
#include "rk3588.dtsi"
/ {
@@ -101,6 +102,18 @@
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
};
&combphy0_ps {
@@ -899,8 +912,144 @@
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&combphy2_psu {
status = "okay";
};
+
+&usbdp_phy0 {
+ orientation-switch;
+ mode-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ rockchip,dp-lane-mux = <2 3>;
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&i2c2 {
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+ status = "okay";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_role_sw: endpoint {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+};

2
target/linux/rockchip/patches-6.1/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch
View File

@@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2029,6 +2029,17 @@
@@ -2025,6 +2025,17 @@
status = "disabled";
};

2
target/linux/rockchip/patches-6.1/801-06-arm64-dts-rockchip-rk3588s-rng-use-scmi_clk.patch
View File

@@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2033,7 +2033,7 @@
@@ -2029,7 +2029,7 @@
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;