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rockchip: refreshed rk3588 patchset

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- Added PCIe3/USB3 support for Rock 5B
- Updated sdmmc properties for Rock 5A/5B

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-07-27 04:19:54 +08:00
parent c467b5601a
commit 60e6e250cb
19 changed files with 433 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

155
target/linux/rockchip/patches-6.1/050-20-v6.6-arm64-dts-rockchip-add-PCIe3-support-for-rk3588.patch Normal file
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@@ -0,0 +1,155 @@
From 0acf4fa7f187cd7e3dad93f1ee14e9509687621e Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 17 Jul 2023 19:35:12 +0200
Subject: [PATCH] arm64: dts: rockchip: add PCIe3 support for rk3588
Add both PCIe3 controllers together with the shared PHY.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230717173512.65169-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
1 file changed, 120 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ pcie30_phy_grf: syscon@fd5b8000 {
+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
+ };
+
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -80,6 +85,108 @@
status = "disabled";
};
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0x0f>;
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+ <0 0 0 2 &pcie3x4_intc 1>,
+ <0 0 0 3 &pcie3x4_intc 2>,
+ <0 0 0 4 &pcie3x4_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <3>;
+ msi-map = <0x0000 &its1 0x0000 0x1000>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+ reg = <0xa 0x40000000 0x0 0x00400000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x0 0xf0000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+
+ pcie3x4_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
+ pcie3x2: pcie@fe160000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x10 0x1f>;
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+ <0 0 0 2 &pcie3x2_intc 1>,
+ <0 0 0 3 &pcie3x2_intc 2>,
+ <0 0 0 4 &pcie3x2_intc 3>;
+ linux,pci-domain = <1>;
+ max-link-speed = <3>;
+ msi-map = <0x1000 &its1 0x1000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ reg = <0xa 0x40400000 0x0 0x00400000>,
+ <0x0 0xfe160000 0x0 0x00010000>,
+ <0x0 0xf1000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+
+ pcie3x2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
@@ -167,4 +274,17 @@
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
status = "disabled";
};
+
+ pcie30phy: phy@fee80000 {
+ compatible = "rockchip,rk3588-pcie3-phy";
+ reg = <0x0 0xfee80000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+ clock-names = "pclk";
+ resets = <&cru SRST_PCIE30_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
};

55
target/linux/rockchip/patches-6.1/053-15-v6.6-arm64-dts-rockchip-fix-update-sdmmc-properties-for-rock-5.patch Normal file
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@@ -0,0 +1,55 @@
From c75b725ea6dd518beeebd693e4bfc02eb15e3b75 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Sat, 22 Jul 2023 21:11:50 +0900
Subject: [PATCH] arm64: dts: rockchip: fix/update sdmmc properties for rock-5a
and -5b
add alias for sdmmc as mmc1.
make card detect work.
Fixes: ea3e66e7ad0d ("arm64: dts: rockchip: add SD card support to rock-5a")
Fixes: 2a6d4af5f157 ("arm64: dts: rockchip: Add SD card support to rock-5b")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20230722121150.130126-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 ++
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 ++
2 files changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -11,6 +11,7 @@
aliases {
mmc0 = &sdhci;
+ mmc1 = &sdmmc;
serial2 = &uart2;
};
@@ -250,6 +251,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -13,6 +13,7 @@
aliases {
mmc0 = &sdhci;
+ mmc1 = &sdmmc;
serial2 = &uart2;
};
@@ -362,6 +363,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;

8
target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
View File

@@ -347,9 +347,9 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
#include "rk3588.dtsi"
/ {
@@ -12,6 +14,11 @@
aliases {
@@ -13,6 +15,11 @@
mmc0 = &sdhci;
mmc1 = &sdmmc;
serial2 = &uart2;
+
+ led-boot = &status_led;
@@ -359,7 +359,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
};
chosen {
@@ -57,6 +64,17 @@
@@ -58,6 +65,17 @@
vin-supply = <&vcc5v0_sys>;
};
@@ -377,7 +377,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -210,6 +228,12 @@
@@ -211,6 +229,12 @@
};
};

0
target/linux/rockchip/patches-6.1/110-01-cpufreq-rockchip-Introduce-driver-for-rk3588.patch → target/linux/rockchip/patches-6.1/110-cpufreq-rockchip-Introduce-driver-for-rk3588.patch
View File

0
target/linux/rockchip/patches-6.1/117-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch → target/linux/rockchip/patches-6.1/111-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch
View File

2
target/linux/rockchip/patches-6.1/117-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch → target/linux/rockchip/patches-6.1/111-02-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
View File

@@ -1,4 +1,4 @@
From a5f467748264d9a337cb40083efde04c748d8c3e Mon Sep 17 00:00:00 2001
From a8dc483b1653a2b99f9b63803b4575ba4a91d8d8 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 13 Jun 2023 16:45:05 +0200
Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf

2
target/linux/rockchip/patches-6.1/119-01-phy-rockchip-add-usbdp-combo-phy-driver.patch → target/linux/rockchip/patches-6.1/112-phy-rockchip-add-usbdp-combo-phy-driver.patch
View File

@@ -1,4 +1,4 @@
From 76dce9a4e101c5f961f91a3ddef99660081cadd5 Mon Sep 17 00:00:00 2001
From 3a68da76b9f07f81f59e61e4c21d405373bbd1fa Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Tue, 25 Apr 2023 15:55:54 +0200
Subject: [PATCH] phy: rockchip: add usbdp combo phy driver

0
target/linux/rockchip/patches-6.1/110-02-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch → target/linux/rockchip/patches-6.1/120-01-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch
View File

4
target/linux/rockchip/patches-6.1/115-01-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch → target/linux/rockchip/patches-6.1/120-02-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch
View File

@@ -16,8 +16,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -80,6 +80,60 @@
status = "disabled";
@@ -187,6 +187,60 @@
};
};
+ pcie2x1l0: pcie@fe170000 {

4
target/linux/rockchip/patches-6.1/119-02-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch → target/linux/rockchip/patches-6.1/120-03-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
View File

@@ -13,7 +13,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -12,6 +12,38 @@
@@ -17,6 +17,38 @@
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
@@ -52,7 +52,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -206,6 +238,37 @@
@@ -313,6 +345,37 @@
};
};

8
target/linux/rockchip/patches-6.1/119-03-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch → target/linux/rockchip/patches-6.1/120-04-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch
View File

@@ -45,10 +45,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
+ };
+
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -34,7 +62,6 @@
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x10000>;
@@ -39,7 +67,6 @@
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
#clock-cells = <0>;

0
target/linux/rockchip/patches-6.1/110-03-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch → target/linux/rockchip/patches-6.1/121-01-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch
View File

0
target/linux/rockchip/patches-6.1/115-02-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network.patch → target/linux/rockchip/patches-6.1/121-02-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network.patch
View File

0
target/linux/rockchip/patches-6.1/119-04-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch → target/linux/rockchip/patches-6.1/121-03-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch
View File

97
target/linux/rockchip/patches-6.1/121-04-arm64-dts-rockchip-rk3588-evb1-add-PCIe3-bus.patch Normal file
View File

@@ -0,0 +1,97 @@
From a32960824f10bab122fa0f4cdadce8a2f6a6286c Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 11 Jul 2023 17:20:47 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add PCIe3 bus
Enable PCIe3 support, which is exposed via a PCIe3 connector.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -30,6 +30,26 @@
pwms = <&pwm2 0 25000 0>;
};
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -39,6 +59,19 @@
regulator-max-microvolt = <12000000>;
};
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie30_en>;
+ };
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -222,6 +255,18 @@
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_reset>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
&pinctrl {
rtl8111 {
rtl8111_isolate: rtl8111-isolate {
@@ -242,6 +287,16 @@
};
};
+ pcie3 {
+ pcie3_reset: pcie3-reset {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v3_pcie30_en: vcc3v3-pcie30-en {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;

4
target/linux/rockchip/patches-6.1/115-03-arm64-dts-rockchip-rock-5b-add-PCIe-network-controller.patch → target/linux/rockchip/patches-6.1/123-01-arm64-dts-rockchip-rock-5b-add-PCIe-network-controller.patch
View File

@@ -13,7 +13,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -50,6 +50,15 @@
@@ -51,6 +51,15 @@
#cooling-cells = <2>;
};
@@ -29,7 +29,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -644,3 +653,14 @@
@@ -646,3 +655,14 @@
&usb_host1_ohci {
status = "okay";
};

71
target/linux/rockchip/patches-6.1/123-02-arm64-dts-rockchip-rock-5b-add-PCIe-3x4-support.patch Normal file
View File

@@ -0,0 +1,71 @@
From 72ec5f3a720b860f62d43a82924e75ea5e3cacb0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 14 Jul 2023 19:19:29 +0200
Subject: [PATCH] arm64: dts: rockchip: rock-5b: add PCIe 3x4 support
The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector
on the board's back.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -60,6 +60,19 @@
vin-supply = <&vcc_3v3_s3>;
};
+ vcc3v3_pcie30: vcc3v3-pcie30 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_vcc3v3_en>;
+ };
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -231,6 +244,18 @@
};
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_rst>;
+ status = "okay";
+};
+
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
@@ -250,6 +275,16 @@
};
};
+ pcie3 {
+ pcie3_rst: pcie3-rst {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;

38
target/linux/rockchip/patches-6.1/123-04-arm64-dts-rockchip-rk3588-rock5b-add-USB3-host.patch Normal file
View File

@@ -0,0 +1,38 @@
From 2dc513256933639c4ffef827244379375179ecbb Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 19 Jul 2023 15:56:42 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-rock5b: add USB3 host
Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds
USB3 for the upper USB3 port (the one further away from the PCB).
The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588
USB TypeC host controller, which use a different PHY that is not yet
supported upstream.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -118,6 +118,10 @@
};
};
+&combphy2_psu {
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -701,3 +705,7 @@
status = "okay";
};
+
+&usbhost3_0 {
+ status = "okay";
+};

2
target/linux/rockchip/patches-6.1/801-07-arm64-dts-rockchip-enable-hwrng-for-rockchip-boards.patch
View File

@@ -52,7 +52,7 @@
status = "okay";
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -260,6 +260,10 @@
@@ -300,6 +300,10 @@
status = "okay";
};