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rockchip: nanopi r6s: fix boot from eMMC

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-06-02 15:47:27 +08:00
parent 03e1f2cc2a
commit 6a9aea21ed
12 changed files with 166 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
package/boot/uboot-rockchip/Makefile
View File

@@ -5,13 +5,9 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2023.07-rc3
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/u-boot/u-boot.git
PKG_SOURCE_DATE:=2023-05-19
PKG_SOURCE_VERSION:=62df7a39442902a71259568c13a4d496d5a514f4
PKG_MIRROR_HASH:=08f18ab9a855e4af5301a9390288960a52a4ce89669d425abc674b7e7d05e6d9
PKG_HASH:=42ec083674bd30fa4c16e78c3f5f453c08d9f737595a77b5dda595ac3a09d82f
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>

10
package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
View File

@@ -6,11 +6,17 @@
#include "rk3588s-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc;
mmc1 = &sdhci;
};
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
&rng {
status = "okay";
};
@@ -22,7 +28,9 @@
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
};

2
package/boot/uboot-rockchip/src/arch/arm/dts/rk3588s-nanopi-r6s.dts
View File

@@ -23,7 +23,7 @@
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc;
mmc2 = &sdhci;
mmc1 = &sdhci;
serial2 = &uart2;
};

6
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@@ -56,12 +56,12 @@ rockchip_setup_macs()
friendlyarm,nanopi-r2c-plus|\
friendlyarm,nanopi-r4s|\
friendlyarm,nanopi-r5c|\
friendlyarm,nanopi-r5s)
friendlyarm,nanopi-r5s|\
friendlyarm,nanopi-r6s)
wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
friendlyarm,nanopi-r4se|\
friendlyarm,nanopi-r6s)
friendlyarm,nanopi-r4se)
wan_mac=$(macaddr_generate_from_mmc_cid mmcblk2)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;

3
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
View File

@@ -24,7 +24,7 @@
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc;
mmc2 = &sdhci;
mmc1 = &sdhci;
serial2 = &uart2;
led-boot = &power_led;
@@ -354,6 +354,7 @@
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
no-sdio;
no-sd;

34
target/linux/rockchip/patches-6.1/120-01-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-emmc.patch Normal file
View File

@@ -0,0 +1,34 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, lucas.tanure@collabora.com,
kever.yang@rock-chips.com, yifeng.zhao@rock-chips.com,
sebastian.reichel@collabora.com, andyshrk@163.com,
jagan@amarulasolutions.com, heiko@sntech.de, conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
broonie@kernel.org, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V2 1/5] arm64: dts: rockchip: add default pinctrl for rk3588 emmc
Date: Wed, 31 May 2023 11:12:16 -0500 [thread overview]
Message-ID: <20230531161220.280744-2-macroalpha82@gmail.com> (raw)
In-Reply-To: <20230531161220.280744-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add a default pinctrl definition for the rk3588 emmc.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2004,6 +2004,9 @@
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_data_strobe>;
+ pinctrl-names = "default";
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;

46
target/linux/rockchip/patches-6.1/120-02-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch Normal file
View File

@@ -0,0 +1,46 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, lucas.tanure@collabora.com,
kever.yang@rock-chips.com, yifeng.zhao@rock-chips.com,
sebastian.reichel@collabora.com, andyshrk@163.com,
jagan@amarulasolutions.com, heiko@sntech.de, conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
broonie@kernel.org, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V2 2/5] arm64: dts: rockchip: Add sdio node to rk3588
Date: Wed, 31 May 2023 11:12:17 -0500 [thread overview]
Message-ID: <20230531161220.280744-3-macroalpha82@gmail.com> (raw)
In-Reply-To: <20230531161220.280744-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add SDIO node for rk3588/rk3588s.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1993,6 +1993,21 @@
status = "disabled";
};
+ sdio: mmc@fe2d0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x00 0xfe2d0000 0x00 0x4000>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>;
+ power-domains = <&power RK3588_PD_SDIO>;
+ status = "disabled";
+ };
+
sdhci: mmc@fe2e0000 {
compatible = "rockchip,rk3588-dwcmshc";
reg = <0x0 0xfe2e0000 0x0 0x10000>;

85
target/linux/rockchip/patches-6.1/702-arm64-dts-rockchip-rk356x-Fix-PCIe-register-and-range-map.patch
View File

@@ -1,36 +1,79 @@
From: Andrew Powers-Holmes <aholmes@omnom.net>
To: linux-rockchip@lists.infradead.org
Cc: "Ondřej Jirman" <megi@xff.cz>, "Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Peter Geis" <pgwipeout@gmail.com>,
"Frank Wunderlich" <frank-w@public-files.de>,
"Michael Riesch" <michael.riesch@wolfvision.net>,
"Yifeng Zhao" <yifeng.zhao@rock-chips.com>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Nicolas Frattaroli" <frattaroli.nicolas@gmail.com>,
"Chris Morgan" <macromorgan@hotmail.com>,
"Ezequiel Garcia" <ezequiel@vanguardiasur.com.ar>,
"Robin Murphy" <robin.murphy@arm.com>,
"Mark Kettenis" <mark.kettenis@xs4all.nl>,
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Peter Geis <pgwipeout@gmail.com>
Cc: Andrew Powers-Holmes <aholmes@omnom.net>,
Ondrej Jirman <megi@xff.cz>,
stable@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>,
Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/1] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings
Date: Sat, 12 Nov 2022 22:41:26 +1100 [thread overview]
Message-ID: <20221112114125.1637543-2-aholmes@omnom.net> (raw)
In-Reply-To: <20221112114125.1637543-1-aholmes@omnom.net>
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings
Date: Thu, 1 Jun 2023 15:25:16 +0200 [thread overview]
Message-ID: <20230601132516.153934-1-frattaroli.nicolas@gmail.com> (raw)
From: Andrew Powers-Holmes <aholmes@omnom.net>
The register and range mappings for the PCIe controller in Rockchip's
RK356x SoCs are incorrect. Replace them with corrected values from the
vendor BSP sources, updated to match current DT schema.
Tested-by: Ondrej Jirman <megi@xff.cz>
These values are also used in u-boot.
Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
Cc: stable@vger.kernel.org
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
Since nobody else was gonna submit this fix on a fix, I decided
to do it myself, based on the u-boot patch Jonas Karlman wrote.
Please test that this does not break the PCIe 3 controller on
RK3568 hardware, I don't have the right setup to easily test it
on there.
Changes since v1:
- Fix copy-paste error on second reg property from 0xf2000000
to 0xf0000000
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
2 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -94,9 +94,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
- <0x3 0x7f000000 0x0 0x01000000>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
- <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
+ <0x0 0xf2000000 0x0 0x00100000>;
+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@@ -146,9 +147,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
- <0x3 0xbf000000 0x0 0x01000000>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
- <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
+ <0x0 0xf0000000 0x0 0x00100000>;
+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -951,7 +951,7 @@

4
target/linux/rockchip/patches-6.1/703-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
View File

@@ -18,7 +18,7 @@
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -116,7 +116,7 @@
@@ -117,7 +117,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
@@ -27,7 +27,7 @@
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
@@ -139,7 +139,7 @@
@@ -140,7 +140,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;

2
target/linux/rockchip/patches-6.1/801-04-arm64-dts-rockchip-rk3568-add-rng-node.patch
View File

@@ -11,7 +11,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -211,6 +211,16 @@
@@ -213,6 +213,16 @@
};
};

2
target/linux/rockchip/patches-6.1/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch
View File

@@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2011,6 +2011,17 @@
@@ -2029,6 +2029,17 @@
status = "disabled";
};

2
target/linux/rockchip/patches-6.1/801-06-arm64-dts-rockchip-rk3588s-rng-use-scmi_clk.patch
View File

@@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2015,7 +2015,7 @@
@@ -2033,7 +2033,7 @@
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;