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rockchip: refresh upstreamed patches

Browse Source 
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2023-06-08 17:58:31 +08:00
parent 15c26a9e78
commit dae139a209
24 changed files with 622 additions and 508 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
target/linux/rockchip/patches-6.1/702-arm64-dts-rockchip-rk356x-Fix-PCIe-register-and-range-map.patch → target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Fix-rk356x-PCIe-register-and-range-map.patch
View File

@@ -1,20 +1,7 @@
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Peter Geis <pgwipeout@gmail.com>
Cc: Andrew Powers-Holmes <aholmes@omnom.net>,
Ondrej Jirman <megi@xff.cz>,
stable@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>,
Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings
Date: Thu, 1 Jun 2023 15:25:16 +0200 [thread overview]
Message-ID: <20230601132516.153934-1-frattaroli.nicolas@gmail.com> (raw)
From 568a67e742dfa90b19a23305317164c5c350b71e Mon Sep 17 00:00:00 2001
From: Andrew Powers-Holmes <aholmes@omnom.net>
Date: Thu, 1 Jun 2023 15:25:16 +0200
Subject: [PATCH] arm64: dts: rockchip: Fix rk356x PCIe register and range mappings
The register and range mappings for the PCIe controller in Rockchip's
RK356x SoCs are incorrect. Replace them with corrected values from the
@@ -27,19 +14,10 @@ Cc: stable@vger.kernel.org
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Tested-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20230601132516.153934-1-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
Since nobody else was gonna submit this fix on a fix, I decided
to do it myself, based on the u-boot patch Jonas Karlman wrote.
Please test that this does not break the PCIe 3 controller on
RK3568 hardware, I don't have the right setup to easily test it
on there.
Changes since v1:
- Fix copy-paste error on second reg property from 0xf2000000
to 0xf0000000
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
2 files changed, 12 insertions(+), 9 deletions(-)

33
target/linux/rockchip/patches-6.1/118-01-iio-adc-rockchip_saradc-Add-callback-functions.patch → target/linux/rockchip/patches-6.1/037-01-v6.5-iio-adc-rockchip_saradc-Add-callback-functions.patch
View File

@@ -1,20 +1,7 @@
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
Simon Xue <xxm@rock-chips.com>
Subject: [PATCH v3 1/8] iio: adc: rockchip_saradc: Add callback functions
Date: Sun, 4 Jun 2023 00:23:33 +0530 [thread overview]
Message-ID: <20230603185340.13838-2-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
From fb1c13d595857ccff49cbb69ddcdc08594a832e7 Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Sun, 4 Jun 2023 00:23:33 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Add callback functions
Add start, read and power_down callback functions,
which will help in adding new rockchip device support
@@ -22,17 +9,11 @@ cleanly.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230603185340.13838-2-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- no change
Changes in v2
- Add a from address.
- Create a separate patch for changes done in the code for old
devices.
drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++------
drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++++++++--------
1 file changed, 52 insertions(+), 12 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c

44
target/linux/rockchip/patches-6.1/118-02-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch → target/linux/rockchip/patches-6.1/037-02-v6.5-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch
View File

@@ -1,43 +1,19 @@
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
Simon Xue <xxm@rock-chips.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 2/8] iio: adc: rockchip_saradc: Add support for RK3588
Date: Sun, 4 Jun 2023 00:23:34 +0530 [thread overview]
Message-ID: <20230603185340.13838-3-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
From 757953f8ec6916084e0c22218d1d0482e9fc6682 Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Sun, 4 Jun 2023 00:23:34 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Add support for RK3588
Add new start and read functions to support rk3588 device.
Also, add a device compatible string for the same.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230603185340.13838-3-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- Add bitfield.h header file.
- Add a Reviewed-by tag.
Changes in v2
- Add a from address.
- Create separate patches for adding new device support and changes to
the old device code.
- Make use of FIELD_PREP.
drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++
drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
--- a/drivers/iio/adc/rockchip_saradc.c
@@ -55,9 +31,9 @@ Changes in v2
#define SARADC_MAX_CHANNELS 8
+/* v2 registers */
+#define SARADC2_CONV_CON 0x0
+#define SARADC_T_PD_SOC 0x4
+#define SARADC_T_DAS_SOC 0xc
+#define SARADC2_CONV_CON 0x000
+#define SARADC_T_PD_SOC 0x004
+#define SARADC_T_DAS_SOC 0x00c
+#define SARADC2_END_INT_EN 0x104
+#define SARADC2_ST_CON 0x108
+#define SARADC2_STATUS 0x10c

30
target/linux/rockchip/patches-6.1/118-03-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_enabled.patch → target/linux/rockchip/patches-6.1/037-03-v6.5-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_enabled.patch
View File

@@ -1,33 +1,17 @@
From 97ad10bb2901738b87b02a8fbf02215f1f198bdb Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH v3 3/8] iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled
Date: Sun, 4 Jun 2023 00:23:35 +0530 [thread overview]
Message-ID: <20230603185340.13838-4-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:35 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled
Use devm_clk_get_enabled() to avoid manually disabling the
clock.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230603185340.13838-4-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- Do not remove clock enabling and disabling from the suspend and
resume functions respectively.
Changes in v2
- No need to enable the clocks earlier than the original code.
Move the enablement of clocks at it's original position.
drivers/iio/adc/rockchip_saradc.c | 56 +++++--------------------------
drivers/iio/adc/rockchip_saradc.c | 56 ++++++---------------------------------
1 file changed, 8 insertions(+), 48 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c

28
target/linux/rockchip/patches-6.1/118-04-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch → target/linux/rockchip/patches-6.1/037-04-v6.5-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch
View File

@@ -1,32 +1,16 @@
From 47902344c8c35c1c08147df08879ef75a3ff86c1 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 4/8] iio: adc: rockchip_saradc: Use of_device_get_match_data
Date: Sun, 4 Jun 2023 00:23:36 +0530 [thread overview]
Message-ID: <20230603185340.13838-5-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:36 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Use of_device_get_match_data
Use of_device_get_match_data() to simplify the code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230603185340.13838-5-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- No change
Changes in v2
- Add a Reviewed-by tag.
drivers/iio/adc/rockchip_saradc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

28
target/linux/rockchip/patches-6.1/118-05-iio-adc-rockchip_saradc-Match-alignment-with-open-parenth.patch → target/linux/rockchip/patches-6.1/037-05-v6.5-iio-adc-rockchip_saradc-Match-alignment-with-open-parenth.patch
View File

@@ -1,33 +1,17 @@
From 10bec68f51ee1564fc2b6dcc25ccec22a01b22f9 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 5/8] iio: adc: rockchip_saradc: Match alignment with open parenthesis
Date: Sun, 4 Jun 2023 00:23:37 +0530 [thread overview]
Message-ID: <20230603185340.13838-6-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:37 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Match alignment with open parenthesis
Match alignment with open parenthesis for improving the code
readability.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230603185340.13838-6-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- No change
Changes in v2
- Add a Reviewed-by tag.
drivers/iio/adc/rockchip_saradc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)

28
target/linux/rockchip/patches-6.1/118-06-iio-adc-rockchip_saradc-Use-dev_err_probe.patch → target/linux/rockchip/patches-6.1/037-06-v6.5-iio-adc-rockchip_saradc-Use-dev_err_probe.patch
View File

@@ -1,32 +1,18 @@
From 5e63d7a260ea5536c22fda7b852f54eeee6d7c98 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH v3 6/8] iio: adc: rockchip_saradc: Use dev_err_probe
Date: Sun, 4 Jun 2023 00:23:38 +0530 [thread overview]
Message-ID: <20230603185340.13838-7-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:38 +0530
Subject: [PATCH] iio: adc: rockchip_saradc: Use dev_err_probe
Use dev_err_probe instead of dev_err in probe function,
which simplifies code a little bit and prints the error
code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230603185340.13838-7-shreeya.patel@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes in v3
- No change
Changes in v2
- No change
drivers/iio/adc/rockchip_saradc.c | 45 ++++++++++++++-----------------
drivers/iio/adc/rockchip_saradc.c | 45 +++++++++++++++++----------------------
1 file changed, 20 insertions(+), 25 deletions(-)
--- a/drivers/iio/adc/rockchip_saradc.c

35
target/linux/rockchip/patches-6.1/050-14-v6.5-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK3588.patch Normal file
View File

@@ -0,0 +1,35 @@
From ec084cbddbbe3a778ee06ccc0c59cee23b5cbaf4 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:39 +0530
Subject: [PATCH] arm64: dts: rockchip: Add DT node for ADC support in RK3588
Add DT node for ADC support in RK3588.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20230603185340.13838-8-shreeya.patel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1784,6 +1784,18 @@
status = "disabled";
};
+ saradc: adc@fec10000 {
+ compatible = "rockchip,rk3588-saradc";
+ reg = <0x0 0xfec10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
i2c6: i2c@fec80000 {
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfec80000 0x0 0x1000>;

27
target/linux/rockchip/patches-6.1/050-15-v6.5-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-emmc.patch Normal file
View File

@@ -0,0 +1,27 @@
From 47ecb3905715a73b336103cc8d225877ab50143e Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:16 -0500
Subject: [PATCH] arm64: dts: rockchip: add default pinctrl for rk3588 emmc
Add a default pinctrl definition for the rk3588 emmc.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230531161220.280744-2-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1187,6 +1187,9 @@
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_data_strobe>;
+ pinctrl-names = "default";
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;

21
target/linux/rockchip/patches-6.1/120-02-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch → target/linux/rockchip/patches-6.1/050-16-v6.5-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch
View File

@@ -1,28 +1,21 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, lucas.tanure@collabora.com,
kever.yang@rock-chips.com, yifeng.zhao@rock-chips.com,
sebastian.reichel@collabora.com, andyshrk@163.com,
jagan@amarulasolutions.com, heiko@sntech.de, conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
broonie@kernel.org, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V2 2/5] arm64: dts: rockchip: Add sdio node to rk3588
Date: Wed, 31 May 2023 11:12:17 -0500 [thread overview]
Message-ID: <20230531161220.280744-3-macroalpha82@gmail.com> (raw)
In-Reply-To: <20230531161220.280744-1-macroalpha82@gmail.com>
From 725c47d78ddefd04a94391fafa5f99414c7f88db Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:17 -0500
Subject: [PATCH] arm64: dts: rockchip: Add sdio node to rk3588
Add SDIO node for rk3588/rk3588s.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230531161220.280744-3-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1993,6 +1993,21 @@
@@ -1176,6 +1176,21 @@
status = "disabled";
};

214
target/linux/rockchip/patches-6.1/110-04-arm64-dts-rockchip-rk3588-evb1-add-pmic.patch → target/linux/rockchip/patches-6.1/051-02-v6.5-arm64-dts-rockchip-add-PMIC-to-rk3588-evb1.patch
View File

@@ -1,20 +1,61 @@
From e7b9bfa6608f131c2575094b3e9c65394227b115 Mon Sep 17 00:00:00 2001
From ec5d218e1e443dd6fea7e77983c3f97b9e09a74a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 12 Jul 2022 15:17:33 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add pmic
Date: Fri, 26 May 2023 19:22:55 +0200
Subject: [PATCH] arm64: dts: rockchip: add PMIC to rk3588-evb1
This adds PMIC support for the RK3588 EVB.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230526172255.68236-1-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 740 ++++++++++++++++++
1 file changed, 740 insertions(+)
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 637 ++++++++++++++++++
1 file changed, 637 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -123,6 +123,746 @@
@@ -49,6 +49,38 @@
};
};
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -123,6 +155,611 @@
status = "okay";
};
@@ -26,15 +67,15 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-power-off";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-1 = <&rk806_dvs1_pwrdn>;
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
@@ -52,88 +93,21 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: dvs1-slp-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: dvs1-rst-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_slp: dvs2-slp-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: dvs2-rst-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: dvs2-dvs-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: dvs2-gpio-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_slp: dvs3-slp-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: dvs3-rst-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: dvs3-dvs-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: dvs3-gpio-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
@@ -396,15 +370,15 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+
+ pmic@1 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x01>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-sleep";
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
+ pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
+ <&rk806_slave_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
@@ -422,89 +396,21 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_slave_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs1_slp: dvs1-slp-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs1_pwrdn: dvs1-pwrdn-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs1_rst: dvs1-rst-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_slp: dvs2-slp-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs2_pwrdn: dvs2-pwrdn-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs2_rst: dvs2-rst-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_dvs: dvs2-dvs-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs2_gpio: dvs2-gpio-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_slave_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_slp: dvs3-slp-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs3_pwrdn: dvs3-pwrdn-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs3_rst: dvs3-rst-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs3_dvs: dvs3-dvs-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs3_gpio: dvs3-gpio-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: dcdc-reg1 {
+ regulator-always-on;

389
target/linux/rockchip/patches-6.1/053-09-v6.5-arm64-dts-rockchip-add-PMIC-to-rock-5b.patch Normal file
View File

@@ -0,0 +1,389 @@
From db242e8240b5dc8bd3709dceb194bd49cd3aac2e Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 29 May 2023 19:05:31 +0200
Subject: [PATCH] arm64: dts: rockchip: add PMIC to rock-5b
This adds PMIC support for the Radxa ROCK 5B
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230529170532.59804-1-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 350 ++++++++++++++++++++++++
1 file changed, 350 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -51,6 +51,16 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu_b0 {
@@ -69,6 +79,22 @@
cpu-supply = <&vdd_cpu_big1_s0>;
};
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -190,6 +216,330 @@
status = "okay";
};
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";

38
target/linux/rockchip/patches-6.1/053-10-v6.5-arm64-dts-rockchip-Add-SD-card-support-to-rock-5b.patch Normal file
View File

@@ -0,0 +1,38 @@
From 2a6d4af5f157b1540e7a49f7fdbbf517b0d0d5b7 Mon Sep 17 00:00:00 2001
From: Lucas Tanure <lucas.tanure@collabora.com>
Date: Mon, 29 May 2023 19:05:32 +0200
Subject: [PATCH] arm64: dts: rockchip: Add SD card support to rock-5b
Add sdmmc support for Rock Pi 5B board.
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230529170532.59804-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -216,6 +216,20 @@
status = "okay";
};
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;

6
target/linux/rockchip/patches-6.1/110-05-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch
View File

@@ -13,8 +13,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -49,6 +49,21 @@
};
@@ -81,6 +81,21 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&cpu_l0 {
@@ -35,7 +35,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -863,6 +878,10 @@
@@ -760,6 +775,10 @@
};
};

6
target/linux/rockchip/patches-6.1/112-08-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch
View File

@@ -52,8 +52,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
};
&cpu_l0 {
@@ -64,6 +98,40 @@
&cpu_b0 {
@@ -96,6 +130,40 @@
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
@@ -94,7 +94,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -886,3 +954,11 @@
@@ -783,3 +851,11 @@
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

8
target/linux/rockchip/patches-6.1/112-09-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch
View File

@@ -25,9 +25,9 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
#include "rk3588.dtsi"
/ {
@@ -51,6 +52,20 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -61,6 +62,20 @@
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc5v0_host: vcc5v0-host-regulator {
@@ -46,7 +46,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
};
&cpu_b0 {
@@ -194,3 +209,46 @@
@@ -558,3 +573,46 @@
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

2
target/linux/rockchip/patches-6.1/113-01-arm64-dts-rockchip-rk3588-add-combo-PHYs.patch
View File

@@ -79,7 +79,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2450,6 +2460,38 @@
@@ -2480,6 +2490,38 @@
#dma-cells = <1>;
};

2
target/linux/rockchip/patches-6.1/114-03-arm64-dts-rockchip-rk3588-evb1-add-SATA.patch
View File

@@ -14,7 +14,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -946,6 +946,14 @@
@@ -843,6 +843,14 @@
};
};

4
target/linux/rockchip/patches-6.1/115-02-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-support.patch
View File

@@ -42,8 +42,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
};
&cpu_l0 {
@@ -963,10 +983,27 @@
&cpu_b0 {
@@ -860,10 +880,27 @@
status = "okay";
};

4
target/linux/rockchip/patches-6.1/115-03-arm64-dts-rockchip-RK3588s-Enable-PCIE2-0x1-fe190000.patch
View File

@@ -13,7 +13,7 @@ Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -66,6 +66,15 @@
@@ -76,6 +76,15 @@
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
@@ -29,7 +29,7 @@ Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
};
&cpu_b0 {
@@ -252,3 +261,14 @@
@@ -616,3 +625,14 @@
};
};
};

63
target/linux/rockchip/patches-6.1/116-03-arm64-dts-rockchip-rock-5b-Add-SD-card-support.patch
View File

@@ -1,63 +0,0 @@
From 80b7c355e8db615dcdfec83ad0412761f3078279 Mon Sep 17 00:00:00 2001
From: Lucas Tanure <lucas.tanure@collabora.com>
Date: Tue, 21 Feb 2023 16:17:19 +0000
Subject: [PATCH] arm64: dts: rockchip: rock-5b: Add SD card support
Add sdmmc node and it's regulators for sd card support
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
+#include "rk3588-rk806-single.dtsi"
/ {
model = "Radxa ROCK 5 Model B";
@@ -75,6 +76,16 @@
startup-delay-us = <5000>;
vin-supply = <&vcc_3v3_s3>;
};
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu_b0 {
@@ -214,6 +225,22 @@
status = "okay";
};
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";

50
target/linux/rockchip/patches-6.1/118-07-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK3588.patch
View File

@@ -1,50 +0,0 @@
From: Shreeya Patel <shreeya.patel@collabora.com>
To: jic23@kernel.org, lars@metafoo.de, heiko@sntech.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
gustavo.padovan@collabora.com, kernel@collabora.com,
serge.broslavsky@collabora.com,
Shreeya Patel <shreeya.patel@collabora.com>
Subject: [PATCH v3 7/8] arm64: dts: rockchip: Add DT node for ADC support in RK3588
Date: Sun, 4 Jun 2023 00:23:39 +0530 [thread overview]
Message-ID: <20230603185340.13838-8-shreeya.patel@collabora.com> (raw)
In-Reply-To: <20230603185340.13838-1-shreeya.patel@collabora.com>
Add DT node for ADC support in RK3588.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
Changes in v3
- No change
Changes in v2
- No change
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2648,6 +2648,18 @@
status = "disabled";
};
+ saradc: saradc@fec10000 {
+ compatible = "rockchip,rk3588-saradc";
+ reg = <0x0 0xfec10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
system_sram2: sram@ff001000 {
compatible = "mmio-sram";
reg = <0x0 0xff001000 0x0 0xef000>;

2
target/linux/rockchip/patches-6.1/119-02-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
View File

@@ -156,7 +156,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2616,6 +2659,37 @@
@@ -2646,6 +2689,37 @@
#dma-cells = <1>;
};

34
target/linux/rockchip/patches-6.1/120-01-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-emmc.patch
View File

@@ -1,34 +0,0 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org, lucas.tanure@collabora.com,
kever.yang@rock-chips.com, yifeng.zhao@rock-chips.com,
sebastian.reichel@collabora.com, andyshrk@163.com,
jagan@amarulasolutions.com, heiko@sntech.de, conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
broonie@kernel.org, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V2 1/5] arm64: dts: rockchip: add default pinctrl for rk3588 emmc
Date: Wed, 31 May 2023 11:12:16 -0500 [thread overview]
Message-ID: <20230531161220.280744-2-macroalpha82@gmail.com> (raw)
In-Reply-To: <20230531161220.280744-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add a default pinctrl definition for the rk3588 emmc.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2004,6 +2004,9 @@
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_data_strobe>;
+ pinctrl-names = "default";
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;