Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
2023-08-08 07:48:59 +08:00
parent d4e8ac52ea ad2fa6bc9c
commit f853776af6
80 changed files with 10935 additions and 755 deletions
--- a/package/boot/arm-trusted-firmware-mediatek/Makefile
+++ b/package/boot/arm-trusted-firmware-mediatek/Makefile
@@ -1,6 +1,6 @@
 #
 # Copyright (C) 2017 Hauke Mehrtens
-# Copyright (C) 2021 Daniel Golle
+# Copyright (C) 2021-2023 Daniel Golle
 #
 # This is free software, licensed under the GNU General Public License v2.
 # See /LICENSE for more information.
@@ -13,9 +13,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git
-PKG_SOURCE_DATE:=2022-08-31
-PKG_SOURCE_VERSION:=7539348480af57c6d0db95aba6381f3ee7483779
-PKG_MIRROR_HASH:=125090124d77753acc379b3b124100978c1ecb3da37c4983ba9644b433b7eb08
+PKG_SOURCE_DATE:=2023-07-24
+PKG_SOURCE_VERSION:=00ac6db375b76e57e1f5e9e9bffa033e907c3581
+PKG_MIRROR_HASH:=74fc18395532c4292f530da8d00fa1873ada4e05e600c0077a7b7f85ace0d913

 PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>

@@ -31,6 +31,7 @@ define Trusted-Firmware-A/Default
  DDR_TYPE:=
  NAND_TYPE:=
  BOARD_QFN:=
+  DRAM_USE_COMB:=
 endef

 define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -214,6 +215,126 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr3
  DDR_TYPE:=ddr3
 endef

+define Trusted-Firmware-A/mt7988-nor-ddr3
+  NAME:=MediaTek MT7988 (SPI-NOR, DDR3)
+  BOOT_DEVICE:=nor
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr3
+endef
+
+define Trusted-Firmware-A/mt7988-emmc-ddr3
+  NAME:=MediaTek MT7988 (eMMC, DDR3)
+  BOOT_DEVICE:=emmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr3
+endef
+
+define Trusted-Firmware-A/mt7988-sdmmc-ddr3
+  NAME:=MediaTek MT7988 (SD card, DDR3)
+  BOOT_DEVICE:=sdmmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr3
+endef
+
+define Trusted-Firmware-A/mt7988-snand-ddr3
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR3)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr3
+endef
+
+define Trusted-Firmware-A/mt7988-spim-nand-ddr3
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR3)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr3
+endef
+
+define Trusted-Firmware-A/mt7988-nor-ddr4
+  NAME:=MediaTek MT7988 (SPI-NOR, DDR4)
+  BOOT_DEVICE:=nor
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr4
+endef
+
+define Trusted-Firmware-A/mt7988-emmc-ddr4
+  NAME:=MediaTek MT7988 (eMMC, DDR4)
+  BOOT_DEVICE:=emmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr4
+endef
+
+define Trusted-Firmware-A/mt7988-sdmmc-ddr4
+  NAME:=MediaTek MT7988 (SD card, DDR4)
+  BOOT_DEVICE:=sdmmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr4
+endef
+
+define Trusted-Firmware-A/mt7988-snand-ddr4
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR4)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr4
+endef
+
+define Trusted-Firmware-A/mt7988-spim-nand-ddr4
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR4)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DDR_TYPE:=ddr4
+endef
+
+define Trusted-Firmware-A/mt7988-nor-comb
+  NAME:=MediaTek MT7988 (SPI-NOR)
+  BOOT_DEVICE:=nor
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+endef
+
+define Trusted-Firmware-A/mt7988-emmc-comb
+  NAME:=MediaTek MT7988 (eMMC)
+  BOOT_DEVICE:=emmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+endef
+
+define Trusted-Firmware-A/mt7988-sdmmc-comb
+  NAME:=MediaTek MT7988 (SD card)
+  BOOT_DEVICE:=sdmmc
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+endef
+
+define Trusted-Firmware-A/mt7988-snand-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+endef
+
+define Trusted-Firmware-A/mt7988-spim-nand-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+endef
+
 TFA_TARGETS:= \
 	mt7622-nor-1ddr \
 	mt7622-nor-2ddr \
@@ -237,7 +358,22 @@ TFA_TARGETS:= \
 	mt7986-nor-ddr4 \
 	mt7986-sdmmc-ddr4 \
 	mt7986-snand-ddr4 \
-	mt7986-spim-nand-ddr4
+	mt7986-spim-nand-ddr4 \
+	mt7988-emmc-ddr3 \
+	mt7988-nor-ddr3 \
+	mt7988-sdmmc-ddr3 \
+	mt7988-snand-ddr3 \
+	mt7988-spim-nand-ddr3 \
+	mt7988-emmc-ddr4 \
+	mt7988-nor-ddr4 \
+	mt7988-sdmmc-ddr4 \
+	mt7988-snand-ddr4 \
+	mt7988-spim-nand-ddr4 \
+	mt7988-emmc-comb \
+	mt7988-nor-comb \
+	mt7988-sdmmc-comb \
+	mt7988-snand-comb \
+	mt7988-spim-nand-comb

 TFA_MAKE_FLAGS += \
 	BOOT_DEVICE=$(BOOT_DEVICE) \
@@ -247,6 +383,7 @@ TFA_MAKE_FLAGS += \
 	$(if $(NAND_TYPE),NAND_TYPE=$(NAND_TYPE)) \
 	HAVE_DRAM_OBJ_FILE=yes \
 	$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
+	$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
 	all

 define Package/trusted-firmware-a/install
--- a/package/boot/arm-trusted-firmware-tools/Makefile
+++ b/package/boot/arm-trusted-firmware-tools/Makefile
@@ -8,9 +8,9 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=arm-trusted-firmware-tools
-PKG_VERSION:=2.7
+PKG_VERSION:=2.9
 PKG_RELEASE:=1
-PKG_HASH:=53422dc649153838e03820330ba17cb10afe3e330ecde0db11e4d5f1361a33e6
+PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b

 PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
 PKG_HOST_ONLY:=1
--- a/package/boot/uboot-envtools/files/mediatek_filogic
+++ b/package/boot/uboot-envtools/files/mediatek_filogic
@@ -52,6 +52,8 @@ mercusys,mr90x-v1)
 netgear,wax220)
 	ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x20000" "0x20000"
 	;;
+xiaomi,mi-router-wr30u-112m-nmbm|\
+xiaomi,mi-router-wr30u-stock|\
 xiaomi,redmi-router-ax6000|\
 xiaomi,redmi-router-ax6000-stock)
 	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000"
@@ -62,6 +64,7 @@ qihoo,360t7|\
 tplink,tl-xdr4288|\
 tplink,tl-xdr6086|\
 tplink,tl-xdr6088|\
+xiaomi,mi-router-wr30u-ubootmod|\
 xiaomi,redmi-router-ax6000-ubootmod)
 	. /lib/upgrade/nand.sh
 	local envubi=$(nand_find_ubi ubi)
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk

-PKG_VERSION:=2023.04
-PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
+PKG_VERSION:=2023.07.02
+PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host

 include $(INCLUDE_DIR)/u-boot.mk
@@ -200,6 +200,18 @@ define U-Boot/mt7981_qihoo_360t7
  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
 endef

+define U-Boot/mt7981_xiaomi_mi-router-wr30u
+  NAME:=Xiaomi Router WR30U
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=xiaomi_mi-router-wr30u-ubootmod
+  UBOOT_CONFIG:=mt7981_xiaomi_mi-router-wr30u
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand
+  BL2_SOC:=mt7981
+  BL2_DDRTYPE:=ddr3
+  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
+endef
+
 define U-Boot/mt7986_rfb
  NAME:=MT7986 Reference Board
  BUILD_SUBTARGET:=filogic
@@ -309,6 +321,66 @@ define U-Boot/mt7986_xiaomi_redmi-router-ax6000
  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
 endef

+define U-Boot/mt7988_rfb-spim-nand
+  NAME:=MT7988 Reference Board
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
+  UBOOT_CONFIG:=mt7988_rfb
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ddr4
+endef
+
+define U-Boot/mt7988_rfb-snand
+  NAME:=MT7988 Reference Board
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
+  UBOOT_CONFIG:=mt7988_rfb
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=snand
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7988-snand-ddr4
+endef
+
+define U-Boot/mt7988_rfb-nor
+  NAME:=MT7988 Reference Board
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
+  UBOOT_CONFIG:=mt7988_rfb
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=nor
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7988-nor-ddr4
+endef
+
+define U-Boot/mt7988_rfb-emmc
+  NAME:=MT7988 Reference Board
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
+  UBOOT_CONFIG:=mt7988_rfb
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=emmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7988-emmc-ddr4
+endef
+
+define U-Boot/mt7988_rfb-sd
+  NAME:=MT7988 Reference Board
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
+  UBOOT_CONFIG:=mt7988_sd_rfb
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=sdmmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=ddr4
+  DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-ddr4
+endef
+
 UBOOT_TARGETS := \
 	mt7620_mt7530_rfb \
 	mt7620_rfb \
@@ -327,6 +399,7 @@ UBOOT_TARGETS := \
 	mt7629_rfb \
 	mt7981_h3c_magic-nx30-pro \
 	mt7981_qihoo_360t7 \
+	mt7981_xiaomi_mi-router-wr30u \
 	mt7986_bananapi_bpi-r3-emmc \
 	mt7986_bananapi_bpi-r3-sdmmc \
 	mt7986_bananapi_bpi-r3-snand \
@@ -335,7 +408,12 @@ UBOOT_TARGETS := \
 	mt7986_tplink_tl-xdr6086 \
 	mt7986_tplink_tl-xdr6088 \
 	mt7986_xiaomi_redmi-router-ax6000 \
-	mt7986_rfb
+	mt7986_rfb \
+	mt7988_rfb-spim-nand \
+	mt7988_rfb-snand \
+	mt7988_rfb-nor \
+	mt7988_rfb-emmc \
+	mt7988_rfb-sd

 ifdef CONFIG_TARGET_mediatek
 UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin)
--- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
+++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
@@ -21,7 +21,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 CONFIG_SYS_PROMPT="MT7622> "
 CONFIG_DEBUG_UART_BASE=0x11002000
 CONFIG_DEBUG_UART_CLOCK=25000000
-@@ -24,6 +26,9 @@ CONFIG_CMD_SF_TEST=y
+@@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SMC=y
 CONFIG_ENV_OVERWRITE=y
--- a/package/boot/uboot-mediatek/patches/001-pinctrl-mediatek-set-R1-R0-in-case-pullen-pullsel-su.patch
+++ b/package/boot/uboot-mediatek/patches/001-pinctrl-mediatek-set-R1-R0-in-case-pullen-pullsel-su.patch
@@ -1,88 +0,0 @@
-From patchwork Wed Apr 12 20:36:43 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 1768270
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@legolas.ozlabs.org
-Date: Wed, 12 Apr 2023 21:36:43 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: u-boot@lists.denx.de, Sam Shih <sam.shih@mediatek.com>,
- GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
- Chunfeng Yun <chunfeng.yun@mediatek.com>,
- Weijie Gao <weijie.gao@mediatek.com>, Ryder Lee <ryder.lee@mediatek.com>,
- Frank Wunderlich <frank-w@public-files.de>
-Cc: Steven Liu =?utf-8?b?KOWKieS6uuixqik=?= <steven.liu@mediatek.com>,
- John Crispin <john@phrozen.org>
-Subject: [PATCH] pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
-Message-ID: <ZDcWW7kLSLn1GMZ1@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-
-Commit dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
-related functions") changed the logic deciding to set R0 and R1
-registers for V1 devices.
-
-Before:
-	/* Also set PUPD/R0/R1 if the pin has them */
-	err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
-	if (err != -EINVAL) {
-		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
-		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
-	}
-
-After:
-	/* try pupd_r1_r0 if pullen_pullsel return error */
-	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
-						  val);
-	if (err)
-		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
-						       pullup, val);
-
-Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
-always either returns 0 in case of success or -EINVAL in case any error
-has occurred. Hence the logic responsible of the decision to program R0
-and R1 has been inverted.
-
-This leads to problems on BananaPi R2 (MT7623N) when booting from
-SDMMC, it turns out accessing eMMC no longer works since
-U-Boot 2022.07:
-
-MT7623> mmc dev 0
-Card did not respond to voltage select! : -110
-
-The problem wasn't detected for a long time as both eMMC and SDMMC work
-fine if they are used to boot from, and hence R0 and R1 were already
-setup by the bootrom and/or preloader.
-
-Fix the logic to restore the originally intended and correct behavior
-and also change the descriptive comment accordingly.
-
-Fixes: dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -349,10 +349,10 @@ int mtk_pinconf_bias_set_v1(struct udevi
- {
- 	int err;
- 
-	/* try pupd_r1_r0 if pullen_pullsel return error */
-+	/* set pupd_r1_r0 if pullen_pullsel succeeded */
- 	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
- 						  val);
-	if (err)
-+	if (!err)
- 		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
- 						       pullup, val);
- 
--- a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
+++ b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
@@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config SYS_NAND_MAX_OOBFREE
 --- a/drivers/mtd/Makefile
 +++ b/drivers/mtd/Makefile
-@@ -38,3 +38,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR
+@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR
 obj-$(CONFIG_SPL_UBI) += ubispl/
 
 endif
--- a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch
+++ b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch
@@ -31,16 +31,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mtd/Kconfig
 +++ b/drivers/mtd/Kconfig
-@@ -272,4 +272,6 @@ source "drivers/mtd/spi/Kconfig"
+@@ -274,4 +274,6 @@ source "drivers/mtd/ubi/Kconfig"
 
- source "drivers/mtd/ubi/Kconfig"
+ source "drivers/mtd/nvmxip/Kconfig"
 
 +source "drivers/mtd/nmbm/Kconfig"
 +
 endmenu
 --- a/drivers/mtd/Makefile
 +++ b/drivers/mtd/Makefile
-@@ -40,3 +40,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/
+@@ -41,3 +41,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/
 endif
 
 obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/
--- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
+++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
@@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 #if defined(CONFIG_CMD_ONENAND)
 /* go init the NAND */
 static int initr_onenand(void)
-@@ -703,6 +717,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_CMD_ONENAND
 	initr_onenand,
 #endif
--- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
+++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1352,6 +1352,12 @@ config CMD_NAND_TORTURE
+@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE
 
 endif # CMD_NAND
 
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	depends on NVME
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -123,6 +123,7 @@ obj-y += legacy-mtd-utils.o
+@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
 endif
 obj-$(CONFIG_CMD_MUX) += mux.o
 obj-$(CONFIG_CMD_NAND) += nand.o
--- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
+++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
@@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1352,6 +1352,14 @@ config CMD_NAND_TORTURE
+@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE
 
 endif # CMD_NAND
 
@@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	bool "nmbm"
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -123,6 +123,7 @@ obj-y += legacy-mtd-utils.o
+@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
 endif
 obj-$(CONFIG_CMD_MUX) += mux.o
 obj-$(CONFIG_CMD_NAND) += nand.o
--- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -2818,6 +2818,100 @@ static int spi_nor_init_params(struct sp
+@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp
 	return 0;
 }
 
@@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
 {
 	size_t i;
-@@ -3930,6 +4024,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor)
 	nor->write = spi_nor_write_data;
 	nor->read_reg = spi_nor_read_reg;
 	nor->write_reg = spi_nor_write_reg;
--- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
+++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
@@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -40,3 +40,11 @@
 &snfi {
- 	u-boot,dm-pre-reloc;
+ 	bootph-all;
 };
 +
 +&pinctrl {
--- a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch
+++ b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch
@@ -55,7 +55,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 		reg = <0x11014000 0x1000>;
 --- a/configs/mt7622_rfb_defconfig
 +++ b/configs/mt7622_rfb_defconfig
-@@ -21,6 +21,7 @@ CONFIG_SYS_MAXARGS=8
+@@ -22,6 +22,7 @@ CONFIG_SYS_MAXARGS=8
 CONFIG_SYS_PBSIZE=1049
 CONFIG_CMD_BOOTMENU=y
 CONFIG_CMD_MMC=y
@@ -63,7 +63,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_PING=y
-@@ -40,6 +41,10 @@ CONFIG_SYSCON=y
+@@ -41,6 +42,10 @@ CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_MTK=y
--- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
+++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
@@ -18,14 +18,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1288,6 +1288,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb \
 	mt7981-rfb.dtb \
 +	mt7981-snfi-nand-rfb.dtb \
 	mt7981-emmc-rfb.dtb \
 	mt7981-sd-rfb.dtb \
- 	mt7986a-rfb.dtb \
+ 	mt7986a-bpi-r3-sd.dtb \
 --- /dev/null
 +++ b/arch/arm/dts/mt7981-snfi-nand-rfb.dts
@@ -0,0 +1,132 @@
--- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
+++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -672,6 +672,7 @@ static int set_4byte(struct spi_nor *nor
+@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor
 	case SNOR_MFR_ISSI:
 	case SNOR_MFR_MACRONIX:
 	case SNOR_MFR_WINBOND:
--- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
@@ -207,8 +207,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 -	ret = spinand_manufacturer_detect(spinand);
 +	ret = spinand_id_detect(spinand);
 	if (ret) {
- 		dev_err(spinand->slave->dev, "unknown raw ID %*phN\n",
- 			SPINAND_MAX_ID_LEN, spinand->id.data);
+ 		dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
+ 			spinand->id.data[0], spinand->id.data[1],
 --- a/drivers/mtd/nand/spi/gigadevice.c
 +++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -22,8 +22,13 @@
--- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
+++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -823,6 +823,14 @@ config MMC_MTK
+@@ -820,6 +820,14 @@ config MMC_MTK
 	  This is needed if support for any SD/SDIO/MMC devices is required.
 	  If unsure, say N.
 
@@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
 obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
 obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
 obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
--- a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
+++ b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
@@ -0,0 +1,297 @@
+From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:15:41 +0800
+Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for
+ armv8 platform
+
+Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node
+and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed.
+
+Also, since mt7622 always passes fdt to linux kernel, there's no need to
+assign value to gd->bd->bi_boot_params.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/mt7981-emmc-rfb.dts     |  5 +++++
+ arch/arm/dts/mt7981-rfb.dts          |  5 +++++
+ arch/arm/dts/mt7981-sd-rfb.dts       |  5 +++++
+ arch/arm/dts/mt7986a-bpi-r3-sd.dts   |  5 +++++
+ arch/arm/dts/mt7986a-rfb.dts         |  5 +++++
+ arch/arm/dts/mt7986a-sd-rfb.dts      |  5 +++++
+ arch/arm/dts/mt7986b-rfb.dts         |  5 +++++
+ arch/arm/dts/mt7986b-sd-rfb.dts      |  5 +++++
+ arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++----
+ arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++--
+ arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++--
+ board/mediatek/mt7622/mt7622_rfb.c   |  1 -
+ include/configs/mt7622.h             | 10 ----------
+ include/configs/mt7981.h             |  9 ---------
+ include/configs/mt7986.h             |  9 ---------
+ 15 files changed, 67 insertions(+), 37 deletions(-)
+
+--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
+@@ -18,6 +18,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		  compatible = "regulator-fixed";
+ 		  regulator-name = "fixed-3.3V";
+--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
+@@ -17,6 +17,11 @@
+ 		stdout-path = &uart0;
+ 		tick-timer = &timer0;
+ 	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+ };
+ 
+ &uart0 {
+--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
+@@ -18,6 +18,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		  compatible = "regulator-fixed";
+ 		  regulator-name = "fixed-3.3V";
+--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+@@ -19,6 +19,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x80000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-3.3V";
+--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
+@@ -18,6 +18,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_1p8v: regulator-1p8v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-1.8V";
+--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
+@@ -19,6 +19,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-3.3V";
+--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
+@@ -18,6 +18,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-3.3V";
+--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
+@@ -19,6 +19,11 @@
+ 		tick-timer = &timer0;
+ 	};
+ 
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+ 	reg_3p3v: regulator-3p3v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-3.3V";
+--- a/arch/arm/mach-mediatek/mt7622/init.c
+++ b/arch/arm/mach-mediatek/mt7622/init.c
+@@ -4,11 +4,14 @@
+  * Author: Sam Shih <sam.shih@mediatek.com>
+  */
+ 
+-#include <common.h>
+ #include <fdtdec.h>
+ #include <init.h>
+ #include <asm/armv8/mmu.h>
+-#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+ 
+ int print_cpuinfo(void)
+ {
+@@ -20,11 +23,13 @@ int dram_init(void)
+ {
+ 	int ret;
+ 
+-	ret = fdtdec_setup_memory_banksize();
+	ret = fdtdec_setup_mem_size_base();
+ 	if (ret)
+ 		return ret;
+-	return fdtdec_setup_mem_size_base();
+ 
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
+
+	return 0;
+ }
+ 
+ void reset_cpu(void)
+--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
+@@ -4,18 +4,25 @@
+  * Author: Sam Shih <sam.shih@mediatek.com>
+  */
+ 
+-#include <cpu_func.h>
+#include <fdtdec.h>
+ #include <init.h>
+ #include <asm/armv8/mmu.h>
+ #include <asm/system.h>
+ #include <asm/global_data.h>
+#include <asm/u-boot.h>
+ #include <linux/sizes.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int dram_init(void)
+ {
+-	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
+ 
+ 	return 0;
+ }
+--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
+@@ -4,18 +4,25 @@
+  * Author: Sam Shih <sam.shih@mediatek.com>
+  */
+ 
+-#include <cpu_func.h>
+#include <fdtdec.h>
+ #include <init.h>
+ #include <asm/armv8/mmu.h>
+ #include <asm/system.h>
+ #include <asm/global_data.h>
+#include <asm/u-boot.h>
+ #include <linux/sizes.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int dram_init(void)
+ {
+-	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
+ 
+ 	return 0;
+ }
+--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
+@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int board_init(void)
+ {
+-	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+ 	return 0;
+ }
+ 
+--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
+@@ -9,14 +9,4 @@
+ #ifndef __MT7622_H
+ #define __MT7622_H
+ 
+-/* Uboot definition */
+-#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
+-
+-/* SPL -> Uboot */
+-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+-/* DRAM */
+-#define CFG_SYS_SDRAM_BASE		0x40000000
+-
+-/* Ethernet */
+-
+ #endif
+--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
+@@ -9,13 +9,4 @@
+ #ifndef __MT7981_H
+ #define __MT7981_H
+ 
+-/* Uboot definition */
+-#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+-
+-/* SPL -> Uboot */
+-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+-
+-/* DRAM */
+-#define CFG_SYS_SDRAM_BASE		0x40000000
+-
+ #endif
+--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
+@@ -9,13 +9,4 @@
+ #ifndef __MT7986_H
+ #define __MT7986_H
+ 
+-/* Uboot definition */
+-#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+-
+-/* SPL -> Uboot */
+-#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+-
+-/* DRAM */
+-#define CFG_SYS_SDRAM_BASE		0x40000000
+-
+ #endif
--- a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
+++ b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
@@ -0,0 +1,129 @@
+From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:15:47 +0800
+Subject: [PATCH 02/29] board: mediatek: update config headers
+
+Remove unused information from include/configs/mtxxxx.h
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ include/configs/mt7620.h |  3 +--
+ include/configs/mt7621.h |  6 ++----
+ include/configs/mt7623.h |  8 --------
+ include/configs/mt7628.h |  5 ++---
+ include/configs/mt7629.h | 13 +------------
+ 5 files changed, 6 insertions(+), 29 deletions(-)
+
+--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
+@@ -10,10 +10,9 @@
+ 
+ #define CFG_SYS_SDRAM_BASE		0x80000000
+ 
+-#define CFG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET		0x400000
+ 
+ /* SPL */
+-
+ #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+ 
+ /* Dummy value */
+--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
+@@ -12,13 +12,11 @@
+ 
+ #define CFG_MAX_MEM_MAPPED		0x1c000000
+ 
+-#define CFG_SYS_INIT_SP_OFFSET	0x800000
+#define CFG_SYS_INIT_SP_OFFSET		0x800000
+ 
+ /* MMC */
+ #define MMC_SUPPORTS_TUNING
+ 
+-/* NAND */
+-
+ /* Serial SPL */
+ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
+ #define CFG_SYS_NS16550_CLK		50000000
+@@ -26,7 +24,7 @@
+ #endif
+ 
+ /* Serial common */
+-#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
+ 					  230400, 460800, 921600 }
+ 
+ /* Dummy value */
+--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
+@@ -11,12 +11,6 @@
+ 
+ #include <linux/sizes.h>
+ 
+-/* Miscellaneous configurable options */
+-
+-/* Environment */
+-
+-/* Preloader -> Uboot */
+-
+ /* MMC */
+ #define MMC_SUPPORTS_TUNING
+ 
+@@ -32,8 +26,6 @@
+ 	"fdt_addr_r=" FDT_HIGH "\0"			\
+ 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
+ 
+-/* Ethernet */
+-
+ #ifdef CONFIG_DISTRO_DEFAULTS
+ 
+ #define BOOT_TARGET_DEVICES(func)	\
+--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
+@@ -10,7 +10,7 @@
+ 
+ #define CFG_SYS_SDRAM_BASE		0x80000000
+ 
+-#define CFG_SYS_INIT_SP_OFFSET	0x80000
+#define CFG_SYS_INIT_SP_OFFSET		0x80000
+ 
+ /* Serial SPL */
+ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
+@@ -19,11 +19,10 @@
+ #endif
+ 
+ /* Serial common */
+-#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
+ 					  230400, 460800, 921600 }
+ 
+ /* SPL */
+-
+ #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+ 
+ /* Dummy value */
+--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
+@@ -9,21 +9,10 @@
+ #ifndef __MT7629_H
+ #define __MT7629_H
+ 
+-#include <linux/sizes.h>
+-
+-/* Miscellaneous configurable options */
+-
+-/* Environment */
+-
+/* SPL */
+ #define CFG_SYS_UBOOT_BASE		(0x30000000 + CONFIG_SPL_PAD_TO)
+ 
+-/* SPL -> Uboot */
+-
+-/* UBoot -> Kernel */
+-
+ /* DRAM */
+ #define CFG_SYS_SDRAM_BASE		0x40000000
+ 
+-/* Ethernet */
+-
+ #endif
--- a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
+++ b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
@@ -0,0 +1,84 @@
+From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:15:54 +0800
+Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
+
+We don't really need to switch clk rate during operating SPIM controller.
+Get clk rate only once at driver probing.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
+---
+ drivers/spi/mtk_spim.c | 21 +++++++++++++--------
+ 1 file changed, 13 insertions(+), 8 deletions(-)
+
+--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
+@@ -137,6 +137,8 @@ struct mtk_spim_capability {
+  * @state:		Controller state
+  * @sel_clk:		Pad clock
+  * @spi_clk:		Core clock
+ * @pll_clk_rate:	Controller's PLL source clock rate, which is different
+ *			from SPI bus clock rate
+  * @xfer_len:		Current length of data for transfer
+  * @hw_cap:		Controller capabilities
+  * @tick_dly:		Used to postpone SPI sampling time
+@@ -149,6 +151,7 @@ struct mtk_spim_priv {
+ 	void __iomem *base;
+ 	u32 state;
+ 	struct clk sel_clk, spi_clk;
+	u32 pll_clk_rate;
+ 	u32 xfer_len;
+ 	struct mtk_spim_capability hw_cap;
+ 	u32 tick_dly;
+@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
+ static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
+ 				      u32 speed_hz)
+ {
+-	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
+	u32 div, sck_time, cs_time, reg_val;
+ 
+-	spi_clk_hz = clk_get_rate(&priv->spi_clk);
+-	if (speed_hz <= spi_clk_hz / 4)
+-		div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
+	if (speed_hz <= priv->pll_clk_rate / 4)
+		div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
+ 	else
+ 		div = 4;
+ 
+@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
+ {
+ 	struct udevice *bus = dev_get_parent(slave->dev);
+ 	struct mtk_spim_priv *priv = dev_get_priv(bus);
+-	u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
+	u32 sck_l, sck_h, clk_count, reg;
+ 	ulong us = 1;
+ 	int ret = 0;
+ 
+@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
+ 	else
+ 		clk_count = op->data.nbytes;
+ 
+-	spi_bus_clk = clk_get_rate(&priv->spi_clk);
+ 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
+ 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
+-	do_div(spi_bus_clk, sck_l + sck_h + 2);
+	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
+ 
+-	us = CLK_TO_US(spi_bus_clk, clk_count * 8);
+	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
+ 	us += 1000 * 1000; /* 1s tolerance */
+ 
+ 	if (us > UINT_MAX)
+@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
+ 	clk_enable(&priv->sel_clk);
+ 	clk_enable(&priv->spi_clk);
+ 
+	priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
+	if (priv->pll_clk_rate == 0)
+		return -EINVAL;
+
+ 	return 0;
+ }
+ 
--- a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
+++ b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
@@ -0,0 +1,35 @@
+From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:02 +0800
+Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits
+
+In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
+
+However these IRQ enable bits may be set in previous boot stage (BootROM).
+
+If we leave these bits not cleared, although u-boot has disabled IRQ and
+nothing will happen, the linux kernel may encounter panic during
+initializing the spim driver due to IRQ event happens before IRQ handler
+is properly setup.
+
+This patch clear IRQ bits to prevent this from happening.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
+---
+ drivers/spi/mtk_spim.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
+@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s
+ 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
+ 	}
+ 
+	/* Disable interrupt enable for pause mode & normal mode */
+	reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
+
+ 	/* disable dma mode */
+ 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
+ 
--- a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
+++ b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
@@ -0,0 +1,25 @@
+From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:07 +0800
+Subject: [PATCH 05/29] serial: mtk: initial priv data before using
+
+This patch ensures driver private data being fully initialized in
+_debug_uart_init which is not covered by .priv_auto ops.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+Reviewed-by: Stefan Roese <sr@denx.de>
+---
+ drivers/serial/serial_mtk.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
+@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void
+ {
+ 	struct mtk_serial_priv priv;
+ 
+	memset(&priv, 0, sizeof(struct mtk_serial_priv));
+ 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
+ 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
+ 
--- a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
+++ b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
@@ -0,0 +1,26 @@
+From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:11 +0800
+Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use
+
+This patch add missing return value check for allocating the driver's
+private data. -ENOMEM will be returned if malloc() fails.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/reset/reset-mediatek.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/reset/reset-mediatek.c
+++ b/drivers/reset/reset-mediatek.c
+@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice *
+ 		return ret;
+ 
+ 	priv = malloc(sizeof(struct mediatek_reset_priv));
+	if (!priv)
+		return -ENOMEM;
+
+ 	priv->regofs = regofs;
+ 	priv->nr_resets = num_regs * 32;
+ 	dev_set_priv(rst_dev, priv);
--- a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
+++ b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
@@ -0,0 +1,125 @@
+From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:15 +0800
+Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981
+
+MT7981 actually uses MediaTek I2C controller v3 instead of v1.
+This patch adds support for I2C controller v3 fix fixes the I2C usability
+for MT7981.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 43 insertions(+), 2 deletions(-)
+
+--- a/drivers/i2c/mtk_i2c.c
+++ b/drivers/i2c/mtk_i2c.c
+@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
+ 	[REG_DCM_EN] = 0xf88,
+ };
+ 
+static const uint mt_i2c_regs_v3[] = {
+	[REG_PORT] = 0x0,
+	[REG_INTR_MASK] = 0x8,
+	[REG_INTR_STAT] = 0xc,
+	[REG_CONTROL] = 0x10,
+	[REG_TRANSFER_LEN] = 0x14,
+	[REG_TRANSAC_LEN] = 0x18,
+	[REG_DELAY_LEN] = 0x1c,
+	[REG_TIMING] = 0x20,
+	[REG_START] = 0x24,
+	[REG_EXT_CONF] = 0x28,
+	[REG_LTIMING] = 0x2c,
+	[REG_HS] = 0x30,
+	[REG_IO_CONFIG] = 0x34,
+	[REG_FIFO_ADDR_CLR] = 0x38,
+	[REG_TRANSFER_LEN_AUX] = 0x44,
+	[REG_CLOCK_DIV] = 0x48,
+	[REG_SOFTRESET] = 0x50,
+	[REG_SLAVE_ADDR] = 0x94,
+	[REG_DEBUGSTAT] = 0xe4,
+	[REG_DEBUGCTRL] = 0xe8,
+	[REG_FIFO_STAT] = 0xf4,
+	[REG_FIFO_THRESH] = 0xf8,
+	[REG_DCM_EN] = 0xf88,
+};
+
+ struct mtk_i2c_soc_data {
+ 	const uint *regs;
+ 	uint dma_sync: 1;
+	uint ltiming_adjust: 1;
+ };
+ 
+ struct mtk_i2c_priv {
+@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev
+ 				(sample_cnt << HS_SAMPLE_OFFSET) |
+ 				(step_cnt << HS_STEP_OFFSET);
+ 		i2c_writel(priv, REG_HS, high_speed_reg);
+		if (priv->soc_data->ltiming_adjust) {
+			timing_reg = (sample_cnt << 12) | (step_cnt << 9);
+			i2c_writel(priv, REG_LTIMING, timing_reg);
+		}
+ 	} else {
+ 		ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
+ 					      &step_cnt, &sample_cnt);
+@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev
+ 		high_speed_reg = I2C_TIME_CLR_VALUE;
+ 		i2c_writel(priv, REG_TIMING, timing_reg);
+ 		i2c_writel(priv, REG_HS, high_speed_reg);
+		if (priv->soc_data->ltiming_adjust) {
+			timing_reg = (sample_cnt << 6) | step_cnt;
+			i2c_writel(priv, REG_LTIMING, timing_reg);
+		}
+ 	}
+
+ exit:
+ 	if (mtk_i2c_clk_disable(priv))
+ 		return log_msg_ret("set_speed disable clk", -1);
+@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice
+ 		return log_msg_ret("probe enable clk", -1);
+ 
+ 	mtk_i2c_init_hw(priv);
+-
+ 	if (mtk_i2c_clk_disable(priv))
+ 		return log_msg_ret("probe disable clk", -1);
+ 
+@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic
+ static const struct mtk_i2c_soc_data mt76xx_soc_data = {
+ 	.regs = mt_i2c_regs_v1,
+ 	.dma_sync = 0,
+	.ltiming_adjust = 0,
+ };
+ 
+ static const struct mtk_i2c_soc_data mt7981_soc_data = {
+-	.regs = mt_i2c_regs_v1,
+	.regs = mt_i2c_regs_v3,
+ 	.dma_sync = 1,
+	.ltiming_adjust = 1,
+ };
+ 
+ static const struct mtk_i2c_soc_data mt7986_soc_data = {
+ 	.regs = mt_i2c_regs_v1,
+ 	.dma_sync = 1,
+	.ltiming_adjust = 0,
+ };
+ 
+ static const struct mtk_i2c_soc_data mt8183_soc_data = {
+ 	.regs = mt_i2c_regs_v2,
+ 	.dma_sync = 1,
+	.ltiming_adjust = 0,
+ };
+ 
+ static const struct mtk_i2c_soc_data mt8518_soc_data = {
+ 	.regs = mt_i2c_regs_v1,
+ 	.dma_sync = 0,
+	.ltiming_adjust = 0,
+ };
+ 
+ static const struct mtk_i2c_soc_data mt8512_soc_data = {
+ 	.regs = mt_i2c_regs_v1,
+ 	.dma_sync = 1,
+	.ltiming_adjust = 0,
+ };
+ 
+ static const struct dm_i2c_ops mtk_i2c_ops = {
--- a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
+++ b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
@@ -0,0 +1,36 @@
+From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:19 +0800
+Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981
+
+This patch enables i2c support for MediaTek MT7981
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
+@@ -181,6 +181,20 @@
+ 		status = "disabled";
+ 	};
+ 
+	i2c0: i2c@11007000 {
+		compatible = "mediatek,mt7981-i2c";
+		reg = <0x11007000 0x1000>,
+		      <0x10217080 0x80>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
+			 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+ 	uart0: serial@11002000 {
+ 		compatible = "mediatek,hsuart";
+ 		reg = <0x11002000 0x400>;
--- a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
+++ b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
@@ -0,0 +1,34 @@
+From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:24 +0800
+Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC
+
+This patch adds PWM support for MediaTek MT7988 SoC.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/pwm/pwm-mtk.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
+@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d
+ 	.reg_ver = PWM_REG_V1,
+ };
+ 
+static const struct mtk_pwm_soc mt7988_data = {
+	.num_pwms = 8,
+	.pwm45_fixup = false,
+	.reg_ver = PWM_REG_V2,
+};
+
+ static const struct udevice_id mtk_pwm_ids[] = {
+ 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
+ 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
+ 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
+ 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
+ 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
+ 	{ }
+ };
+ 
--- a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
+++ b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
--- a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
+++ b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
@@ -0,0 +1,49 @@
+From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:33 +0800
+Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek
+ MT7988 SoC
+
+This patch adds reset bits for MediaTek MT7988
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mt7988-reset.h
+
+--- /dev/null
+++ b/include/dt-bindings/reset/mt7988-reset.h
+@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* ETHDMA Subsystem resets */
+#define ETHDMA_FE_RST			6
+#define ETHDMA_PMTR_RST			8
+#define ETHDMA_GMAC_RST			23
+#define ETHDMA_WDMA0_RST		24
+#define ETHDMA_WDMA1_RST		25
+#define ETHDMA_WDMA2_RST		26
+#define ETHDMA_PPE0_RST			29
+#define ETHDMA_PPE1_RST			30
+#define ETHDMA_PPE2_RST			31
+
+/* ETHWARP Subsystem resets */
+#define ETHWARP_GSW_RST			9
+#define ETHWARP_EIP197_RST		10
+#define ETHWARP_WOCPU0_RST		32
+#define ETHWARP_WOCPU1_RST		33
+#define ETHWARP_WOCPU2_RST		34
+#define ETHWARP_WOX_NET_MUX_RST		35
+#define ETHWARP_WED0_RST		36
+#define ETHWARP_WED1_RST		37
+#define ETHWARP_WED2_RST		38
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
--- a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
+++ b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
--- a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
+++ b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
@@ -0,0 +1,37 @@
+From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:42 +0800
+Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving
+ configuration functions
+
+The original mediatek pinctrl functions for driving configuration
+'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input
+parameters are not supported.
+This patch fixes the return value in those functions.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev
+ 			return err;
+ 	}
+ 
+-	return 0;
+	return err;
+ }
+ 
+ int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
+@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev
+ 			return err;
+ 	}
+ 
+-	return 0;
+	return err;
+ }
+ 
+ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
--- a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
+++ b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
@@ -0,0 +1,43 @@
+From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:46 +0800
+Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support
+
+This patch adds pinmux_set ops for mediatek pinctrl framework
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+@@ -304,6 +304,19 @@ static const char *mtk_get_function_name
+ 	return priv->soc->funcs[selector].name;
+ }
+ 
+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+			  unsigned int func_selector)
+{
+	int err;
+
+	err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
+			       func_selector);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+ static int mtk_pinmux_group_set(struct udevice *dev,
+ 				unsigned int group_selector,
+ 				unsigned int func_selector)
+@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops
+ 	.get_group_name = mtk_get_group_name,
+ 	.get_functions_count = mtk_get_functions_count,
+ 	.get_function_name = mtk_get_function_name,
+	.pinmux_set = mtk_pinmux_set,
+ 	.pinmux_group_set = mtk_pinmux_group_set,
+ #if CONFIG_IS_ENABLED(PINCONF)
+ 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
--- a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
+++ b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
--- a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
+++ b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
@@ -0,0 +1,138 @@
+From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:54 +0800
+Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting
+ eth is requested
+
+So far the switch is initialized in probe stage and is connected to PSE
+unconditionally. This will cause all packets being flooded to PSE and may
+cause PSE hang before entering linux.
+
+This patch changes the connection between switch and PSE:
+- Still initialize switch in probe stage, but disconnect it with PSE
+- Connect switch with PSE on eth start
+- Disconnect on eth stop
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 41 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -123,8 +123,10 @@ struct mtk_eth_priv {
+ 
+ 	enum mtk_switch sw;
+ 	int (*switch_init)(struct mtk_eth_priv *priv);
+	void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
+ 	u32 mt753x_smi_addr;
+ 	u32 mt753x_phy_base;
+	u32 mt753x_pmcr;
+ 
+ 	struct gpio_desc rst_gpio;
+ 	int mcm;
+@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m
+ 	return 0;
+ }
+ 
+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
+ static int mt7530_setup(struct mtk_eth_priv *priv)
+ {
+ 	u16 phy_addr, phy_val;
+@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p
+ 	      FORCE_DPX | FORCE_LINK;
+ 
+ 	/* MT7530 Port6: Forced 1000M/FD, FC disabled */
+-	mt753x_reg_write(priv, PMCR_REG(6), val);
+	priv->mt753x_pmcr = val;
+ 
+ 	/* MT7530 Port5: Forced link down */
+ 	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
+ 
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
+
+ 	/* MT7530 Port6: Set to RGMII */
+ 	mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
+ 
+@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt
+ 	}
+ }
+ 
+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE_LNK;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
+ static int mt7531_setup(struct mtk_eth_priv *priv)
+ {
+ 	u16 phy_addr, phy_val;
+@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p
+ 	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
+ 	       FORCE_LINK;
+ 
+-	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
+-	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+	priv->mt753x_pmcr = pmcr;
+
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
+ 
+ 	/* Turn on PHYs */
+ 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice
+ 
+ 	mtk_eth_fifo_init(priv);
+ 
+	if (priv->switch_mac_control)
+		priv->switch_mac_control(priv, true);
+
+ 	/* Start PHY */
+ 	if (priv->sw == SW_NONE) {
+ 		ret = mtk_phy_start(priv);
+@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice
+ {
+ 	struct mtk_eth_priv *priv = dev_get_priv(dev);
+ 
+	if (priv->switch_mac_control)
+		priv->switch_mac_control(priv, false);
+
+ 	mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
+ 		     TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
+ 	udelay(500);
+@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude
+ 	/* check for switch first, otherwise phy will be used */
+ 	priv->sw = SW_NONE;
+ 	priv->switch_init = NULL;
+	priv->switch_mac_control = NULL;
+ 	str = dev_read_string(dev, "mediatek,switch");
+ 
+ 	if (str) {
+ 		if (!strcmp(str, "mt7530")) {
+ 			priv->sw = SW_MT7530;
+ 			priv->switch_init = mt7530_setup;
+			priv->switch_mac_control = mt7530_mac_control;
+ 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ 		} else if (!strcmp(str, "mt7531")) {
+ 			priv->sw = SW_MT7531;
+ 			priv->switch_init = mt7531_setup;
+			priv->switch_mac_control = mt7531_mac_control;
+ 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ 		} else {
+ 			printf("error: unsupported switch\n");
--- a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
+++ b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
@@ -0,0 +1,56 @@
+From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:16:59 +0800
+Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait
+ time
+
+Not all switches requires 1 second delay after deasserting reset.
+MT7531 requires only maximum 200ms.
+
+This patch defines dedicated reset wait time for each switch chip, and will
+significantly improve the boot time for boards using MT7531.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -127,6 +127,7 @@ struct mtk_eth_priv {
+ 	u32 mt753x_smi_addr;
+ 	u32 mt753x_phy_base;
+ 	u32 mt753x_pmcr;
+	u32 mt753x_reset_wait_time;
+ 
+ 	struct gpio_desc rst_gpio;
+ 	int mcm;
+@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr
+ 		reset_assert(&priv->rst_mcm);
+ 		udelay(1000);
+ 		reset_deassert(&priv->rst_mcm);
+-		mdelay(1000);
+		mdelay(priv->mt753x_reset_wait_time);
+ 	} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
+ 		dm_gpio_set_value(&priv->rst_gpio, 0);
+ 		udelay(1000);
+ 		dm_gpio_set_value(&priv->rst_gpio, 1);
+-		mdelay(1000);
+		mdelay(priv->mt753x_reset_wait_time);
+ 	}
+ 
+ 	ret = priv->switch_init(priv);
+@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude
+ 			priv->switch_init = mt7530_setup;
+ 			priv->switch_mac_control = mt7530_mac_control;
+ 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 1000;
+ 		} else if (!strcmp(str, "mt7531")) {
+ 			priv->sw = SW_MT7531;
+ 			priv->switch_init = mt7531_setup;
+ 			priv->switch_mac_control = mt7531_mac_control;
+ 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 200;
+ 		} else {
+ 			printf("error: unsupported switch\n");
+ 			return -EINVAL;
--- a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
+++ b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
@@ -0,0 +1,34 @@
+From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:03 +0800
+Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC
+
+The original direct MDIO clause 45 access via SoC is missing the
+data output. This patch adds it back to ensure MDIO clause 45 can
+work properly for external PHYs.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
+ 	      (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
+ 	      (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
+ 
+-	if (cmd == MDIO_CMD_WRITE)
+	if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
+ 		val |= data & MDIO_RW_DATA_M;
+ 
+ 	mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
+@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
+ 		return ret;
+ 	}
+ 
+-	if (cmd == MDIO_CMD_READ) {
+	if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
+ 		val = mtk_gmac_read(priv, GMAC_PIAC_REG);
+ 		return val & MDIO_RW_DATA_M;
+ 	}
--- a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
+++ b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
@@ -0,0 +1,36 @@
+From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:07 +0800
+Subject: [PATCH 19/29] net: mediatek: add missing static qualifier
+
+mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
+Since they're not used outside this file, we should add them back.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+fixup to add static qualifier
+---
+ drivers/net/mtk_eth.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m
+ 			     MDIO_ST_C22);
+ }
+ 
+-int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+			       u16 reg)
+ {
+ 	u8 phy_addr;
+ 	int ret;
+@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p
+ 	return 0;
+ }
+ 
+-int mt753x_switch_init(struct mtk_eth_priv *priv)
+static int mt753x_switch_init(struct mtk_eth_priv *priv)
+ {
+ 	int ret;
+ 	int i;
--- a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
+++ b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
@@ -0,0 +1,149 @@
+From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:13 +0800
+Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps
+ auto-negotiation mode
+
+Existing SGMII support of mtk-eth is actually a MediaTek-specific
+2.5Gbps high-speed SGMII (HSGMII) which does not support
+auto-negotiation mode.
+
+This patch adds SGMII 1Gbps auto-negotiation mode and rename the
+existing HSGMII to 2500basex.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------
+ drivers/net/mtk_eth.h |  2 ++
+ 2 files changed, 42 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p
+ 		if (!port5_sgmii)
+ 			mt7531_port_rgmii_init(priv, 5);
+ 		break;
+-	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_2500BASEX:
+ 		mt7531_port_sgmii_init(priv, 6);
+ 		if (port5_sgmii)
+ 			mt7531_port_sgmii_init(priv, 5);
+@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m
+ 	      (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
+ 	      MAC_MODE | FORCE_MODE |
+ 	      MAC_TX_EN | MAC_RX_EN |
+	      DEL_RXFIFO_CLR |
+ 	      BKOFF_EN | BACKPR_EN;
+ 
+ 	switch (priv->phydev->speed) {
+@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m
+ 		mcr |= (SPEED_100M << FORCE_SPD_S);
+ 		break;
+ 	case SPEED_1000:
+	case SPEED_2500:
+ 		mcr |= (SPEED_1000M << FORCE_SPD_S);
+ 		break;
+ 	};
+@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_
+ 		return 0;
+ 	}
+ 
+-	mtk_phy_link_adjust(priv);
+	if (!priv->force_mode)
+		mtk_phy_link_adjust(priv);
+ 
+ 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
+ 	      (phydev->duplex) ? "full" : "half",
+@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice
+ 	return 0;
+ }
+ 
+-static void mtk_sgmii_init(struct mtk_eth_priv *priv)
+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
+{
+	/* Set SGMII GEN1 speed(1G) */
+	clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+			SGMSYS_SPEED_2500, 0);
+
+	/* Enable SGMII AN */
+	setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
+		     SGMII_AN_ENABLE);
+
+	/* SGMII AN mode setting */
+	writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
+
+	/* SGMII PN SWAP setting */
+	if (priv->pn_swap) {
+		setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
+			     SGMII_PN_SWAP_TX_RX);
+	}
+
+	/* Release PHYA power down state */
+	clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
+			SGMII_PHYA_PWD, 0);
+}
+
+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
+ {
+ 	/* Set SGMII GEN2 speed(2.5G) */
+ 	setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_
+ 		ge_mode = GE_MODE_RGMII;
+ 		break;
+ 	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_2500BASEX:
+ 		ge_mode = GE_MODE_RGMII;
+ 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
+ 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
+-		mtk_sgmii_init(priv);
+		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
+			mtk_sgmii_an_init(priv);
+		else
+			mtk_sgmii_force_init(priv);
+ 		break;
+ 	case PHY_INTERFACE_MODE_MII:
+ 	case PHY_INTERFACE_MODE_GMII:
+@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_
+ 			mcr |= SPEED_100M << FORCE_SPD_S;
+ 			break;
+ 		case SPEED_1000:
+		case SPEED_2500:
+ 			mcr |= SPEED_1000M << FORCE_SPD_S;
+ 			break;
+ 		}
+@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude
+ 		priv->duplex = ofnode_read_bool(subnode, "full-duplex");
+ 
+ 		if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
+-		    priv->speed != SPEED_1000) {
+		    priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
+		    priv->speed != SPEED_10000) {
+ 			printf("error: no valid speed set in fixed-link\n");
+ 			return -EINVAL;
+ 		}
+ 	}
+ 
+-	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+	    priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ 		/* get corresponding sgmii phandle */
+ 		ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
+ 						 NULL, 0, 0, &args);
+--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
+@@ -69,6 +69,7 @@ enum mkt_eth_capabilities {
+ #define SGMII_AN_RESTART		BIT(9)
+ 
+ #define SGMSYS_SGMII_MODE		0x20
+#define SGMII_AN_MODE			0x31120103
+ #define SGMII_FORCE_MODE		0x31120019
+ 
+ #define SGMSYS_QPHY_PWR_STATE_CTRL	0xe8
+@@ -168,6 +169,7 @@ enum mkt_eth_capabilities {
+ #define FORCE_MODE			BIT(15)
+ #define MAC_TX_EN			BIT(14)
+ #define MAC_RX_EN			BIT(13)
+#define DEL_RXFIFO_CLR			BIT(12)
+ #define BKOFF_EN			BIT(9)
+ #define BACKPR_EN			BIT(8)
+ #define FORCE_RX_FC			BIT(5)
--- a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
+++ b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
@@ -0,0 +1,214 @@
+From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:18 +0800
+Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to
+ 2500base-x
+
+Now that individual 2.5Gbps SGMII support has been added to
+mtk-eth, all boards that use 2.5Gbps link with mt7531 must be
+converted to use "2500base-x" instead of "sgmii".
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+[also convert BPi-R3]
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++--
+ arch/arm/dts/mt7622-rfb.dts              | 4 ++--
+ arch/arm/dts/mt7629-rfb.dts              | 4 ++--
+ arch/arm/dts/mt7981-emmc-rfb.dts         | 4 ++--
+ arch/arm/dts/mt7981-rfb.dts              | 4 ++--
+ arch/arm/dts/mt7981-sd-rfb.dts           | 4 ++--
+ arch/arm/dts/mt7986a-bpi-r3-sd.dts       | 4 ++--
+ arch/arm/dts/mt7986a-rfb.dts             | 4 ++--
+ arch/arm/dts/mt7986a-sd-rfb.dts          | 4 ++--
+ arch/arm/dts/mt7986b-rfb.dts             | 4 ++--
+ arch/arm/dts/mt7986b-sd-rfb.dts          | 4 ++--
+ 11 files changed, 22 insertions(+), 22 deletions(-)
+
+--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+@@ -224,12 +224,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
+@@ -240,12 +240,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
+@@ -25,12 +25,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
+@@ -46,12 +46,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
+@@ -37,12 +37,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
+@@ -46,12 +46,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+@@ -76,12 +76,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
+@@ -55,12 +55,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
+@@ -47,12 +47,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
+@@ -46,12 +46,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
+--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
+@@ -47,12 +47,12 @@
+ &eth {
+ 	status = "okay";
+ 	mediatek,gmac-id = <0>;
+-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
+ 	mediatek,switch = "mt7531";
+ 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ 
+ 	fixed-link {
+-		speed = <1000>;
+		speed = <2500>;
+ 		full-duplex;
+ 	};
+ };
--- a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
+++ b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
@@ -0,0 +1,138 @@
+From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:22 +0800
+Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
+ for MT7981
+
+MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
+register must be set to connect the SGMII phy to GMAC2.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
+ drivers/net/mtk_eth.h | 16 ++++++++++++++++
+ 2 files changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -103,6 +103,8 @@ struct mtk_eth_priv {
+ 
+ 	struct regmap *ethsys_regmap;
+ 
+	struct regmap *infra_regmap;
+
+ 	struct mii_dev *mdio_bus;
+ 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
+ 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
+@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
+ 	regmap_write(priv->ethsys_regmap, reg, val);
+ }
+ 
+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+			  u32 set)
+{
+	uint val;
+
+	regmap_read(priv->infra_regmap, reg, &val);
+	val &= ~clr;
+	val |= set;
+	regmap_write(priv->infra_regmap, reg, val);
+}
+
+ /* Direct MDIO clause 22/45 access via SoC */
+ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
+ 		      u32 cmd, u32 st)
+@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
+ 		break;
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
+			mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
+				      SGMII_QPHY_SEL);
+		}
+
+ 		ge_mode = GE_MODE_RGMII;
+ 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
+ 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
+@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
+ 	if (IS_ERR(priv->ethsys_regmap))
+ 		return PTR_ERR(priv->ethsys_regmap);
+ 
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
+		/* get corresponding infracfg phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
+						 NULL, 0, 0, &args);
+
+		if (ret)
+			return ret;
+
+		priv->infra_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->infra_regmap))
+			return PTR_ERR(priv->infra_regmap);
+	}
+
+ 	/* Reset controllers */
+ 	ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
+ 	if (ret) {
+@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
+ };
+ 
+ static const struct mtk_soc_data mt7981_data = {
+-	.caps = MT7986_CAPS,
+	.caps = MT7981_CAPS,
+ 	.ana_rgc3 = 0x128,
+ 	.pdma_base = PDMA_V2_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma_v2),
+--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
+@@ -15,27 +15,38 @@
+ enum mkt_eth_capabilities {
+ 	MTK_TRGMII_BIT,
+ 	MTK_TRGMII_MT7621_CLK_BIT,
+	MTK_U3_COPHY_V2_BIT,
+	MTK_INFRA_BIT,
+ 	MTK_NETSYS_V2_BIT,
+ 
+ 	/* PATH BITS */
+ 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
+ };
+ 
+ #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
+ #define MTK_TRGMII_MT7621_CLK		BIT(MTK_TRGMII_MT7621_CLK_BIT)
+#define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
+#define MTK_INFRA			BIT(MTK_INFRA_BIT)
+ #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
+ 
+ /* Supported path present on SoCs */
+ #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
+ 
+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+
+ #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
+ 
+#define MTK_GMAC2_U3_QPHY	(MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
+
+ #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
+ 
+ #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
+ 
+ #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
+ 
+#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
+
+ #define MT7986_CAPS  (MTK_NETSYS_V2)
+ 
+ /* Frame Engine Register Bases */
+@@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
+ #define ETHSYS_CLKCFG0_REG		0x2c
+ #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
+ 
+/* Top misc registers */
+#define USB_PHY_SWITCH_REG		0x218
+#define QPHY_SEL_MASK			0x3
+#define SGMII_QPHY_SEL			0x2
+
+ /* SYSCFG0_GE_MODE: GE Modes */
+ #define GE_MODE_RGMII			0
+ #define GE_MODE_MII			1
--- a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
+++ b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
@@ -0,0 +1,36 @@
+From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:27 +0800
+Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support
+ GMAC/USB3 Co-PHY
+
+This patch adds infracfg to eth node to support enabling GMAC2.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/mt7981.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
+@@ -266,6 +266,7 @@
+ 		reset-names = "fe";
+ 		mediatek,ethsys = <&ethsys>;
+ 		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,infracfg = <&topmisc>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -284,6 +285,12 @@
+ 		#clock-cells = <1>;
+ 	};
+ 
+	topmisc: topmisc@11d10000 {
+		compatible = "mediatek,mt7981-topmisc", "syscon";
+		reg = <0x11d10000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+ 	spi0: spi@1100a000 {
+ 		compatible = "mediatek,ipm-spi";
+ 		reg = <0x1100a000 0x100>;
--- a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
+++ b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
@@ -0,0 +1,341 @@
+From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:31 +0800
+Subject: [PATCH 24/29] net: mediatek: add USXGMII support
+
+This patch adds support for USXGMII of SoC.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++-
+ drivers/net/mtk_eth.h |  24 +++++
+ 2 files changed, 251 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -105,6 +105,11 @@ struct mtk_eth_priv {
+ 
+ 	struct regmap *infra_regmap;
+ 
+	struct regmap *usxgmii_regmap;
+	struct regmap *xfi_pextp_regmap;
+	struct regmap *xfi_pll_regmap;
+	struct regmap *toprgu_regmap;
+
+ 	struct mii_dev *mdio_bus;
+ 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
+ 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
+@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk
+ 	return 0;
+ }
+ 
+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
+{
+	u16 lcl_adv = 0, rmt_adv = 0;
+	u8 flowctrl;
+	u32 mcr;
+
+	mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
+	mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
+
+	if (priv->phydev->duplex) {
+		if (priv->phydev->pause)
+			rmt_adv = LPA_PAUSE_CAP;
+		if (priv->phydev->asym_pause)
+			rmt_adv |= LPA_PAUSE_ASYM;
+
+		if (priv->phydev->advertising & ADVERTISED_Pause)
+			lcl_adv |= ADVERTISE_PAUSE_CAP;
+		if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
+			lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+		if (flowctrl & FLOW_CTRL_TX)
+			mcr |= XGMAC_FORCE_TX_FC;
+		if (flowctrl & FLOW_CTRL_RX)
+			mcr |= XGMAC_FORCE_RX_FC;
+
+		debug("rx pause %s, tx pause %s\n",
+		      flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
+		      flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
+	}
+
+	mcr &= ~(XGMAC_TRX_DISABLE);
+	mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
+}
+
+ static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
+ {
+ 	u16 lcl_adv = 0, rmt_adv = 0;
+@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_
+ 		return 0;
+ 	}
+ 
+-	if (!priv->force_mode)
+-		mtk_phy_link_adjust(priv);
+	if (!priv->force_mode) {
+		if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+			mtk_xphy_link_adjust(priv);
+		else
+			mtk_phy_link_adjust(priv);
+	}
+ 
+ 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
+ 	      (phydev->duplex) ? "full" : "half",
+@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct
+ 			SGMII_PHYA_PWD, 0);
+ }
+ 
+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
+{
+	u32 val = 0;
+
+	/* Add software workaround for USXGMII PLL TCL issue */
+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
+		     RG_XFI_PLL_ANA_SWWA);
+
+	regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
+	val |= RG_XFI_PLL_EN;
+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
+}
+
+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
+{
+	switch (priv->gmac_id) {
+	case 1:
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+		break;
+	case 2:
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+		break;
+	}
+
+	mdelay(10);
+}
+
+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
+{
+	regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
+	regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
+	ndelay(1020);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
+	ndelay(1020);
+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
+
+	regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+	regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+	regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+	regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+	regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+	regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+	regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+	regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+	regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+	regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+	regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+	regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+	regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+	regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+	regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+	regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+	regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+	regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+	regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+	regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+	regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+	regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+	regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+	regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+	regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
+	regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
+	regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
+	regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+	regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+	regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+	udelay(150);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+	udelay(15);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+	ndelay(1020);
+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+	udelay(100);
+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+	regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+	udelay(400);
+}
+
+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
+{
+	mtk_xfi_pll_enable(priv);
+	mtk_usxgmii_reset(priv);
+	mtk_usxgmii_setup_phya_an_10000(priv);
+}
+
+ static void mtk_mac_init(struct mtk_eth_priv *priv)
+ {
+ 	int i, ge_mode = 0;
+@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_
+ 	}
+ }
+ 
+static void mtk_xmac_init(struct mtk_eth_priv *priv)
+{
+	u32 sts;
+
+	switch (priv->phy_interface) {
+	case PHY_INTERFACE_MODE_USXGMII:
+		mtk_usxgmii_an_init(priv);
+		break;
+	default:
+		break;
+	}
+
+	/* Set GMAC to the correct mode */
+	mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
+		       SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+		       0);
+
+	if (priv->gmac_id == 1) {
+		mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
+			      NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
+	} else if (priv->gmac_id == 2) {
+		sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
+		sts |= XGMAC_FORCE_LINK;
+		mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
+	}
+
+	/* Force GMAC link down */
+	mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
+}
+
+ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
+ {
+ 	char *pkt_base = priv->pkt_pool;
+@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice
+ 				ARCH_DMA_MINALIGN);
+ 
+ 	/* Set MAC mode */
+-	mtk_mac_init(priv);
+	if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+		mtk_xmac_init(priv);
+	else
+		mtk_mac_init(priv);
+ 
+ 	/* Probe phy if switch is not specified */
+ 	if (priv->sw == SW_NONE)
+@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude
+ 		}
+ 
+ 		priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
+	} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+		/* get corresponding usxgmii phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->usxgmii_regmap))
+			return PTR_ERR(priv->usxgmii_regmap);
+
+		/* get corresponding xfi_pextp phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->xfi_pextp_regmap))
+			return PTR_ERR(priv->xfi_pextp_regmap);
+
+		/* get corresponding xfi_pll phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->xfi_pll_regmap))
+			return PTR_ERR(priv->xfi_pll_regmap);
+
+		/* get corresponding toprgu phandle */
+		ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
+						 NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		priv->toprgu_regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(priv->toprgu_regmap))
+			return PTR_ERR(priv->toprgu_regmap);
+ 	}
+ 
+ 	/* check for switch first, otherwise phy will be used */
+--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
+@@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
+ #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
+ 
+ /* Top misc registers */
+#define TOPMISC_NETSYS_PCS_MUX		0x84
+#define NETSYS_PCS_MUX_MASK		GENMASK(1, 0)
+#define MUX_G2_USXGMII_SEL		BIT(1)
+#define MUX_HSGMII1_G1_SEL		BIT(0)
+
+ #define USB_PHY_SWITCH_REG		0x218
+ #define QPHY_SEL_MASK			0x3
+ #define SGMII_QPHY_SEL			0x2
+@@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
+ #define SGMSYS_GEN2_SPEED_V2		0x128
+ #define SGMSYS_SPEED_2500		BIT(2)
+ 
+/* USXGMII subsystem config registers */
+/* Register to control USXGMII XFI PLL digital */
+#define XFI_PLL_DIG_GLB8		0x08
+#define RG_XFI_PLL_EN			BIT(31)
+
+/* Register to control USXGMII XFI PLL analog */
+#define XFI_PLL_ANA_GLB8		0x108
+#define RG_XFI_PLL_ANA_SWWA		0x02283248
+
+ /* Frame Engine Registers */
+ #define FE_GLO_MISC_REG			0x124
+ #define PDMA_VER_V2			BIT(4)
+@@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
+ #define TD_DM_DRVP_S			0
+ #define TD_DM_DRVP_M			0x0f
+ 
+/* XGMAC Status Registers */
+#define XGMAC_STS(x)			(((x) == 2) ? 0x001C : 0x000C)
+#define XGMAC_FORCE_LINK		BIT(15)
+
+/* XGMAC Registers */
+#define XGMAC_PORT_MCR(x)		(0x2000 + (((x) - 1) * 0x1000))
+#define XGMAC_TRX_DISABLE		0xf
+#define XGMAC_FORCE_TX_FC		BIT(5)
+#define XGMAC_FORCE_RX_FC		BIT(4)
+
+ /* MT7530 Registers */
+ 
+ #define PCR_REG(p)			(0x2004 + (p) * 0x100)
--- a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
+++ b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
@@ -0,0 +1,221 @@
+From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:37 +0800
+Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3
+
+This patch adds support for NETSYS v3 hardware.
+Comparing to NETSYS v2, NETSYS v3 has three GMACs.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++-----------
+ drivers/net/mtk_eth.h |  7 +++++++
+ 2 files changed, 44 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -76,6 +76,7 @@ enum mtk_switch {
+  * @caps			Flags shown the extra capability for the SoC
+  * @ana_rgc3:			The offset for register ANA_RGC3 related to
+  *				sgmiisys syscon
+ * @gdma_count:			Number of GDMAs
+  * @pdma_base:			Register base of PDMA block
+  * @txd_size:			Tx DMA descriptor size.
+  * @rxd_size:			Rx DMA descriptor size.
+@@ -83,6 +84,7 @@ enum mtk_switch {
+ struct mtk_soc_data {
+ 	u32 caps;
+ 	u32 ana_rgc3;
+	u32 gdma_count;
+ 	u32 pdma_base;
+ 	u32 txd_size;
+ 	u32 rxd_size;
+@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et
+ {
+ 	u32 gdma_base;
+ 
+-	if (no == 1)
+	if (no == 2)
+		gdma_base = GDMA3_BASE;
+	else if (no == 1)
+ 		gdma_base = GDMA2_BASE;
+ 	else
+ 		gdma_base = GDMA1_BASE;
+@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk
+ 		txd->txd1 = virt_to_phys(pkt_base);
+ 		txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
+ 
+-		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
+							   15 : priv->gmac_id + 1);
+		else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ 			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
+ 		else
+ 			txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
+@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk
+ 
+ 		rxd->rxd1 = virt_to_phys(pkt_base);
+ 
+-		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+		    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ 			rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
+ 		else
+ 			rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
+@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk
+ static int mtk_eth_start(struct udevice *dev)
+ {
+ 	struct mtk_eth_priv *priv = dev_get_priv(dev);
+-	int ret;
+	int i, ret;
+ 
+ 	/* Reset FE */
+ 	reset_assert(&priv->rst_fe);
+@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice
+ 	reset_deassert(&priv->rst_fe);
+ 	mdelay(10);
+ 
+-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ 		setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
+ 
+ 	/* Packets forward to PDMA */
+ 	mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
+ 
+-	if (priv->gmac_id == 0)
+-		mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+-	else
+-		mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+	for (i = 0; i < priv->soc->gdma_count; i++) {
+		if (i == priv->gmac_id)
+			continue;
+
+		mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+	}
+
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
+		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+			       GDMA_CPU_BRIDGE_EN);
+	}
+ 
+ 	udelay(500);
+ 
+@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *
+ 	flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
+ 			   roundup(length, ARCH_DMA_MINALIGN));
+ 
+-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
+ 	else
+ 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
+@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *
+ 		return -EAGAIN;
+ 	}
+ 
+-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ 		length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
+ 	else
+ 		length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
+@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi
+ 
+ 	rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
+ 
+-	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ 		rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
+ 	else
+ 		rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
+@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude
+ static const struct mtk_soc_data mt7986_data = {
+ 	.caps = MT7986_CAPS,
+ 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V2_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
+@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_
+ static const struct mtk_soc_data mt7981_data = {
+ 	.caps = MT7981_CAPS,
+ 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V2_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
+@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_
+ 
+ static const struct mtk_soc_data mt7629_data = {
+ 	.ana_rgc3 = 0x128,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V1_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma),
+ 	.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_
+ 
+ static const struct mtk_soc_data mt7623_data = {
+ 	.caps = MT7623_CAPS,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V1_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma),
+ 	.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_
+ 
+ static const struct mtk_soc_data mt7622_data = {
+ 	.ana_rgc3 = 0x2028,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V1_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma),
+ 	.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_
+ 
+ static const struct mtk_soc_data mt7621_data = {
+ 	.caps = MT7621_CAPS,
+	.gdma_count = 2,
+ 	.pdma_base = PDMA_V1_BASE,
+ 	.txd_size = sizeof(struct mtk_tx_dma),
+ 	.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
+@@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
+ 	MTK_U3_COPHY_V2_BIT,
+ 	MTK_INFRA_BIT,
+ 	MTK_NETSYS_V2_BIT,
+	MTK_NETSYS_V3_BIT,
+ 
+ 	/* PATH BITS */
+ 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
+@@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
+ #define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
+ #define MTK_INFRA			BIT(MTK_INFRA_BIT)
+ #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
+#define MTK_NETSYS_V3			BIT(MTK_NETSYS_V3_BIT)
+ 
+ /* Supported path present on SoCs */
+ #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
+@@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
+ /* Frame Engine Register Bases */
+ #define PDMA_V1_BASE			0x0800
+ #define PDMA_V2_BASE			0x6000
+#define PDMA_V3_BASE			0x6800
+ #define GDMA1_BASE			0x0500
+ #define GDMA2_BASE			0x1500
+#define GDMA3_BASE			0x0540
+ #define GMAC_BASE			0x10000
+ 
+ /* Ethernet subsystem registers */
+@@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
+ #define UN_DP_S				0
+ #define UN_DP_M				0x0f
+ 
+#define GDMA_EG_CTRL_REG		0x004
+#define GDMA_CPU_BRIDGE_EN		BIT(31)
+
+ #define GDMA_MAC_LSB_REG		0x008
+ 
+ #define GDMA_MAC_MSB_REG		0x00c
--- a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
@@ -0,0 +1,327 @@
+From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:41 +0800
+Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC
+
+This patch adds support for MediaTek MT7988.
+
+MT7988 features MediaTek NETSYS v3, including three GMACs, and two
+of them supports 10Gbps USXGMII.
+
+MT7988 embeds a MT7531 switch (not MCM) which supports accessing
+internal registers through MMIO instead of MDIO.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++-
+ drivers/net/mtk_eth.h |  20 ++++++
+ 2 files changed, 177 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
+@@ -54,6 +54,16 @@
+ 	(DP_PDMA << MC_DP_S) | \
+ 	(DP_PDMA << UN_DP_S))
+ 
+#define GDMA_BRIDGE_TO_CPU \
+	(0xC0000000 | \
+	GDM_ICS_EN | \
+	GDM_TCS_EN | \
+	GDM_UCS_EN | \
+	(DP_PDMA << MYMAC_DP_S) | \
+	(DP_PDMA << BC_DP_S) | \
+	(DP_PDMA << MC_DP_S) | \
+	(DP_PDMA << UN_DP_S))
+
+ #define GDMA_FWD_DISCARD \
+ 	(0x20000000 | \
+ 	GDM_ICS_EN | \
+@@ -68,7 +78,8 @@
+ enum mtk_switch {
+ 	SW_NONE,
+ 	SW_MT7530,
+-	SW_MT7531
+	SW_MT7531,
+	SW_MT7988,
+ };
+ 
+ /* struct mtk_soc_data -	This is the structure holding all differences
+@@ -102,6 +113,7 @@ struct mtk_eth_priv {
+ 	void __iomem *fe_base;
+ 	void __iomem *gmac_base;
+ 	void __iomem *sgmii_base;
+	void __iomem *gsw_base;
+ 
+ 	struct regmap *ethsys_regmap;
+ 
+@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et
+ 	writel(val, priv->fe_base + gdma_base + reg);
+ }
+ 
+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
+{
+	clrsetbits_le32(priv->fe_base + reg, clr, set);
+}
+
+ static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
+ {
+ 	return readl(priv->gmac_base + reg);
+@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth
+ 	regmap_write(priv->infra_regmap, reg, val);
+ }
+ 
+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
+{
+	return readl(priv->gsw_base + reg);
+}
+
+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+	writel(val, priv->gsw_base + reg);
+}
+
+ /* Direct MDIO clause 22/45 access via SoC */
+ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
+ 		      u32 cmd, u32 st)
+@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et
+ {
+ 	int ret, low_word, high_word;
+ 
+	if (priv->sw == SW_MT7988) {
+		*data = mtk_gsw_read(priv, reg);
+		return 0;
+	}
+
+ 	/* Write page address */
+ 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
+ 	if (ret)
+@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e
+ {
+ 	int ret;
+ 
+	if (priv->sw == SW_MT7988) {
+		mtk_gsw_write(priv, reg, data);
+		return 0;
+	}
+
+ 	/* Write page address */
+ 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
+ 	if (ret)
+@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev
+ 		priv->mmd_write = mtk_mmd_ind_write;
+ 		break;
+ 	case SW_MT7531:
+	case SW_MT7988:
+ 		priv->mii_read = mt7531_mii_ind_read;
+ 		priv->mii_write = mt7531_mii_ind_write;
+ 		priv->mmd_read = mt7531_mmd_ind_read;
+@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p
+ 	return 0;
+ }
+ 
+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
+{
+	u16 val;
+	u32 i;
+
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		/* Enable HW auto downshift */
+		priv->mii_write(priv, i, 0x1f, 0x1);
+		val = priv->mii_read(priv, i, PHY_EXT_REG_14);
+		val |= PHY_EN_DOWN_SHFIT;
+		priv->mii_write(priv, i, PHY_EXT_REG_14, val);
+
+		/* PHY link down power saving enable */
+		val = priv->mii_read(priv, i, PHY_EXT_REG_17);
+		val |= PHY_LINKDOWN_POWER_SAVING_EN;
+		priv->mii_write(priv, i, PHY_EXT_REG_17, val);
+	}
+}
+
+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+	u32 pmcr = FORCE_MODE_LNK;
+
+	if (enable)
+		pmcr = priv->mt753x_pmcr;
+
+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
+static int mt7988_setup(struct mtk_eth_priv *priv)
+{
+	u16 phy_addr, phy_val;
+	u32 pmcr;
+	int i;
+
+	priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
+
+	priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
+				MT753X_SMI_ADDR_MASK;
+
+	/* Turn off PHYs */
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+		phy_val |= BMCR_PDOWN;
+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+	}
+
+	switch (priv->phy_interface) {
+	case PHY_INTERFACE_MODE_USXGMII:
+		/* Use CPU bridge instead of actual USXGMII path */
+
+		/* Set GDM1 no drop */
+		mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
+
+		/* Enable GDM1 to GSW CPU bridge */
+		mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
+
+		/* XGMAC force link up */
+		mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
+
+		/* Setup GSW CPU bridge IPG */
+		mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
+			     (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
+		break;
+	default:
+		printf("Error: MT7988 GSW does not support %s interface\n",
+		       phy_string_for_interface(priv->phy_interface));
+		break;
+	}
+
+	pmcr = MT7988_FORCE_MODE |
+	       (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
+	       MAC_MODE | MAC_TX_EN | MAC_RX_EN |
+	       BKOFF_EN | BACKPR_EN |
+	       FORCE_RX_FC | FORCE_TX_FC |
+	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
+	       FORCE_LINK;
+
+	priv->mt753x_pmcr = pmcr;
+
+	/* Keep MAC link down before starting eth */
+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
+
+	/* Turn on PHYs */
+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+		phy_val &= ~BMCR_PDOWN;
+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+	}
+
+	mt7988_phy_setting(priv);
+
+	return 0;
+}
+
+ static int mt753x_switch_init(struct mtk_eth_priv *priv)
+ {
+ 	int ret;
+@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
+		if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
+			mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
+				       GDMA_BRIDGE_TO_CPU);
+		}
+
+ 		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ 			       GDMA_CPU_BRIDGE_EN);
+ 	}
+@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude
+ 			priv->switch_mac_control = mt7531_mac_control;
+ 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ 			priv->mt753x_reset_wait_time = 200;
+		} else if (!strcmp(str, "mt7988")) {
+			priv->sw = SW_MT7988;
+			priv->switch_init = mt7988_setup;
+			priv->switch_mac_control = mt7988_mac_control;
+			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+			priv->mt753x_reset_wait_time = 50;
+ 		} else {
+ 			printf("error: unsupported switch\n");
+ 			return -EINVAL;
+@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude
+ 	return 0;
+ }
+ 
+static const struct mtk_soc_data mt7988_data = {
+	.caps = MT7988_CAPS,
+	.ana_rgc3 = 0x128,
+	.gdma_count = 3,
+	.pdma_base = PDMA_V3_BASE,
+	.txd_size = sizeof(struct mtk_tx_dma_v2),
+	.rxd_size = sizeof(struct mtk_rx_dma_v2),
+};
+
+ static const struct mtk_soc_data mt7986_data = {
+ 	.caps = MT7986_CAPS,
+ 	.ana_rgc3 = 0x128,
+@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_
+ };
+ 
+ static const struct udevice_id mtk_eth_ids[] = {
+	{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
+ 	{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
+ 	{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
+ 	{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
+--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
+@@ -51,6 +51,8 @@ enum mkt_eth_capabilities {
+ 
+ #define MT7986_CAPS  (MTK_NETSYS_V2)
+ 
+#define MT7988_CAPS  (MTK_NETSYS_V3 | MTK_INFRA)
+
+ /* Frame Engine Register Bases */
+ #define PDMA_V1_BASE			0x0800
+ #define PDMA_V2_BASE			0x6000
+@@ -59,6 +61,7 @@ enum mkt_eth_capabilities {
+ #define GDMA2_BASE			0x1500
+ #define GDMA3_BASE			0x0540
+ #define GMAC_BASE			0x10000
+#define GSW_BASE			0x20000
+ 
+ /* Ethernet subsystem registers */
+ 
+@@ -117,6 +120,9 @@ enum mkt_eth_capabilities {
+ #define RG_XFI_PLL_ANA_SWWA		0x02283248
+ 
+ /* Frame Engine Registers */
+#define PSE_NO_DROP_CFG_REG		0x108
+#define PSE_NO_DROP_GDM1		BIT(1)
+
+ #define FE_GLO_MISC_REG			0x124
+ #define PDMA_VER_V2			BIT(4)
+ 
+@@ -187,6 +193,17 @@ enum mkt_eth_capabilities {
+ #define MDIO_RW_DATA_S			0
+ #define MDIO_RW_DATA_M			0xffff
+ 
+#define GMAC_XGMAC_STS_REG		0x000c
+#define P1_XGMAC_FORCE_LINK		BIT(15)
+
+#define GMAC_MAC_MISC_REG		0x0010
+
+#define GMAC_GSW_CFG_REG		0x0080
+#define GSWTX_IPG_M			0xF0000
+#define GSWTX_IPG_S			16
+#define GSWRX_IPG_M			0xF
+#define GSWRX_IPG_S			0
+
+ /* MDIO_CMD: MDIO commands */
+ #define MDIO_CMD_ADDR			0
+ #define MDIO_CMD_WRITE			1
+@@ -285,6 +302,9 @@ enum mkt_eth_capabilities {
+ 					FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
+ 					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
+ 					FORCE_MODE_LNK
+#define MT7988_FORCE_MODE		FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
+					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
+					FORCE_MODE_LNK
+ 
+ /* MT7531 SGMII Registers */
+ #define MT7531_SGMII_REG_BASE		0x5000
--- a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
+++ b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
@@ -0,0 +1,55 @@
+From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:45 +0800
+Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and
+ version
+
+This patch converts magic and version fields of ghf common header
+to one field with the type of uint32_t to make this header flexible
+for futher updates.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ tools/mtk_image.c | 10 ++++++----
+ tools/mtk_image.h |  6 +++---
+ 2 files changed, 9 insertions(+), 7 deletions(-)
+
+--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
+@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc
+ 	hdr->type = cpu_to_le32(type);
+ }
+ 
+-static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
+-				  int type, int ver)
+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
+				  uint16_t type, uint8_t ver)
+ {
+-	memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
+-	gfh->version = ver;
+	uint32_t magic_version = GFH_HEADER_MAGIC |
+				 (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
+
+	gfh->magic_version = cpu_to_le32(magic_version);
+ 	gfh->size = cpu_to_le16(size);
+ 	gfh->type = cpu_to_le16(type);
+ }
+--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
+@@ -63,13 +63,13 @@ struct gen_device_header {
+ 
+ /* BootROM header definitions */
+ struct gfh_common_header {
+-	uint8_t magic[3];
+-	uint8_t version;
+	uint32_t magic_version;
+ 	uint16_t size;
+ 	uint16_t type;
+ };
+ 
+-#define GFH_HEADER_MAGIC	"MMM"
+#define GFH_HEADER_MAGIC		0x4D4D4D
+#define GFH_HEADER_VERSION_SHIFT	24
+ 
+ #define GFH_TYPE_FILE_INFO	0
+ #define GFH_TYPE_BL_INFO	1
--- a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
@@ -0,0 +1,606 @@
+From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:49 +0800
+Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
+
+This patch adds basic support for MediaTek MT7988 SoC.
+This includes files that will initialize the SoC after boot and
+its device tree.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/mt7988-u-boot.dtsi               |  25 ++
+ arch/arm/dts/mt7988.dtsi                      | 391 ++++++++++++++++++
+ arch/arm/mach-mediatek/Kconfig                |  13 +-
+ arch/arm/mach-mediatek/Makefile               |   1 +
+ arch/arm/mach-mediatek/mt7988/Makefile        |   4 +
+ arch/arm/mach-mediatek/mt7988/init.c          |  63 +++
+ arch/arm/mach-mediatek/mt7988/lowlevel_init.S |  30 ++
+ 7 files changed, 526 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
+ create mode 100644 arch/arm/dts/mt7988.dtsi
+ create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
+ create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
+ create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
+
+--- /dev/null
+++ b/arch/arm/dts/mt7988-u-boot.dtsi
+@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&system_clk {
+	bootph-all;
+};
+
+&spi_clk {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&uart1 {
+	bootph-all;
+};
+
+&uart2 {
+	bootph-all;
+};
+--- /dev/null
+++ b/arch/arm/dts/mt7988.dtsi
+@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <dt-bindings/reset/mt7988-reset.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "mediatek,mt7988-rfb";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			mediatek,hwver = <&hwver>;
+		};
+	};
+
+	system_clk: dummy40m {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		#clock-cells = <0>;
+	};
+
+	spi_clk: dummy208m {
+		compatible = "fixed-clock";
+		clock-frequency = <208000000>;
+		#clock-cells = <0>;
+	};
+
+	hwver: hwver {
+		compatible = "mediatek,hwver", "syscon";
+		reg = <0 0x8000000 0 0x1000>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		clock-frequency = <13000000>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	watchdog: watchdog@1001c000 {
+		compatible = "mediatek,mt7622-wdt",
+			     "mediatek,mt6589-wdt",
+			     "syscon";
+		reg = <0 0x1001c000 0 0x1000>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		#reset-cells = <1>;
+	};
+
+	gic: interrupt-controller@c000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		interrupt-controller;
+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+		      <0 0x0c080000 0 0x200000>; /* GICR */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&infracfg_ao>;
+		#clock-cells = <1>;
+	};
+
+	apmixedsys: apmixedsys@1001e000 {
+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
+		reg = <0 0x1001e000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	topckgen: topckgen@1001b000 {
+		compatible = "mediatek,mt7988-topckgen", "syscon";
+		reg = <0 0x1001b000 0 0x1000>;
+		clock-parent = <&apmixedsys>;
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl@1001f000 {
+		compatible = "mediatek,mt7988-pinctrl";
+		reg = <0 0x1001f000 0 0x1000>,
+		      <0 0x11c10000 0 0x1000>,
+		      <0 0x11d00000 0 0x1000>,
+		      <0 0x11d20000 0 0x1000>,
+		      <0 0x11e00000 0 0x1000>,
+		      <0 0x11f00000 0 0x1000>,
+		      <0 0x1000b000 0 0x1000>;
+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+			    "eint";
+		gpio: gpio-controller {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
+	sgmiisys0: syscon@10060000 {
+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
+		reg = <0 0x10060000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	sgmiisys1: syscon@10070000 {
+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
+		reg = <0 0x10070000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys0: syscon@10080000 {
+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
+		reg = <0 0x10080000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys1: syscon@10081000 {
+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
+		reg = <0 0x10081000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp0: syscon@11f20000 {
+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
+		reg = <0 0x11f20000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp1: syscon@11f30000 {
+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
+		reg = <0 0x11f30000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pll: syscon@11f40000 {
+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
+		reg = <0 0x11f40000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	topmisc: topmisc@11d10000 {
+		compatible = "mediatek,mt7988-topmisc", "syscon",
+			     "mediatek,mt7988-power-controller";
+		reg = <0 0x11d10000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	infracfg_ao: infracfg@10001000 {
+		compatible = "mediatek,mt7988-infracfg", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@11000000 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000000 0 0x100>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O0>;
+		status = "disabled";
+	};
+
+	uart1: serial@11000100 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000100 0 0x100>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O1>;
+		status = "disabled";
+	};
+
+	uart2: serial@11000200 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000200 0 0x100>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O2>;
+		status = "disabled";
+	};
+
+	i2c0: i2c@11003000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11003000 0 0x1000>,
+		      <0 0x10217080 0 0x80>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@11004000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11004000 0 0x1000>,
+		      <0 0x10217100 0 0x80>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@11005000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11005000 0 0x1000>,
+		      <0 0x10217180 0 0x80>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	pwm: pwm@10048000 {
+		compatible = "mediatek,mt7988-pwm";
+		reg = <0 0x10048000 0 0x1000>;
+		#pwm-cells = <2>;
+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
+		status = "disabled";
+	};
+
+	snand: snand@11001000 {
+		compatible = "mediatek,mt7988-snand",
+			     "mediatek,mt7986-snand";
+		reg = <0 0x11001000 0 0x1000>,
+		      <0 0x11002000 0 0x1000>;
+		reg-names = "nfi", "ecc";
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
+			 <&infracfg_ao CK_INFRA_NFI>,
+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+				  <&topckgen CK_TOP_NFI1X_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
+					 <&topckgen CK_TOP_CB_M_D8>;
+		status = "disabled";
+	};
+
+	spi0: spi@1100a000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11007000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi1: spi@1100b000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11008000 0 0x100>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi2: spi@11009000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11009000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	mmc0: mmc@11230000 {
+		compatible = "mediatek,mt7988-mmc",
+			     "mediatek,mt7986-mmc";
+		reg = <0 0x11230000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+		clock-names = "source", "hclk", "source_cg", "axi_cg";
+		status = "disabled";
+	};
+
+	ethdma: syscon@15000000 {
+		compatible = "mediatek,mt7988-ethdma", "syscon";
+		reg = <0 0x15000000 0 0x20000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	ethwarp: syscon@15031000 {
+		compatible = "mediatek,mt7988-ethwarp", "syscon";
+		reg = <0 0x15031000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	eth: ethernet@15100000 {
+		compatible = "mediatek,mt7988-eth", "syscon";
+		reg = <0 0x15100000 0 0x20000>;
+		mediatek,ethsys = <&ethdma>;
+		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,usxgmiisys = <&usxgmiisys0>;
+		mediatek,xfi_pextp = <&xfi_pextp0>;
+		mediatek,xfi_pll = <&xfi_pll>;
+		mediatek,infracfg = <&topmisc>;
+		mediatek,toprgu = <&watchdog>;
+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
+		reset-names = "fe", "mcm";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mediatek,mcm;
+		status = "disabled";
+	};
+};
+--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
+@@ -58,6 +58,15 @@ config TARGET_MT7986
+ 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+ 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
+ 
+config TARGET_MT7988
+	bool "MediaTek MT7988 SoC"
+	select ARM64
+	select CPU
+	help
+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+	  10 Gigabit Ethernet , I2C, and PCIe.
+
+ config TARGET_MT8183
+ 	bool "MediaTek MT8183 SoC"
+ 	select ARM64
+@@ -104,6 +113,7 @@ config SYS_BOARD
+ 	default "mt7629" if TARGET_MT7629
+ 	default "mt7981" if TARGET_MT7981
+ 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
+ 	default "mt8183" if TARGET_MT8183
+ 	default "mt8512" if TARGET_MT8512
+ 	default "mt8516" if TARGET_MT8516
+@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
+ 	default "mt7629" if TARGET_MT7629
+ 	default "mt7981" if TARGET_MT7981
+ 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
+ 	default "mt8183" if TARGET_MT8183
+ 	default "mt8512" if TARGET_MT8512
+ 	default "mt8516" if TARGET_MT8516
+@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
+ 	string
+ 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
+ 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+-	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
+ 	default "lk=1" if TARGET_MT7623
+ 
+ source "board/mediatek/mt7629/Kconfig"
+--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
+ obj-$(CONFIG_TARGET_MT7629) += mt7629/
+ obj-$(CONFIG_TARGET_MT7981) += mt7981/
+ obj-$(CONFIG_TARGET_MT7986) += mt7986/
+obj-$(CONFIG_TARGET_MT7988) += mt7988/
+ obj-$(CONFIG_TARGET_MT8183) += mt8183/
+ obj-$(CONFIG_TARGET_MT8516) += mt8516/
+ obj-$(CONFIG_TARGET_MT8518) += mt8518/
+--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/Makefile
+@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
+--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/init.c
+@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SZ_8G				_AC(0x200000000, ULL)
+
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = gd->ram_base;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+static struct mm_region mt7988_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x200000000ULL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = mt7988_mem_map;
+--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
+@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+	mov     x3, x2
+	mov     x2, x1
+	mov     x1, x4
+	mov	x4, #0
+	ldr x0, =0x82000200
+	SMC #0
+	ret
--- a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
+++ b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
@@ -0,0 +1,575 @@
+From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 19 Jul 2023 17:17:54 +0800
+Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
+
+This patch adds general board files based on MT7988 SoCs.
+
+MT7988 uses one mmc controller for booting from both SD and eMMC,
+and the pins of mmc controller booting from SD are also shared with
+one of spi controllers.
+So two configs are need for these boot types:
+
+1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
+2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/Makefile              |   2 +
+ arch/arm/dts/mt7988-rfb.dts        | 182 +++++++++++++++++++++++++++++
+ arch/arm/dts/mt7988-sd-rfb.dts     | 134 +++++++++++++++++++++
+ board/mediatek/mt7988/MAINTAINERS  |   7 ++
+ board/mediatek/mt7988/Makefile     |   3 +
+ board/mediatek/mt7988/mt7988_rfb.c |  10 ++
+ configs/mt7988_rfb_defconfig       |  83 +++++++++++++
+ configs/mt7988_sd_rfb_defconfig    |  71 +++++++++++
+ include/configs/mt7988.h           |  14 +++
+ 9 files changed, 506 insertions(+)
+ create mode 100644 arch/arm/dts/mt7988-rfb.dts
+ create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
+ create mode 100644 board/mediatek/mt7988/MAINTAINERS
+ create mode 100644 board/mediatek/mt7988/Makefile
+ create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
+ create mode 100644 configs/mt7988_rfb_defconfig
+ create mode 100644 configs/mt7988_sd_rfb_defconfig
+ create mode 100644 include/configs/mt7988.h
+
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ 	mt7986b-sd-rfb.dtb \
+ 	mt7986a-emmc-rfb.dtb \
+ 	mt7986b-emmc-rfb.dtb \
+	mt7988-rfb.dtb \
+	mt7988-sd-rfb.dtb \
+ 	mt8183-pumpkin.dtb \
+ 	mt8512-bm1-emmc.dtb \
+ 	mt8516-pumpkin.dtb \
+--- /dev/null
+++ b/arch/arm/dts/mt7988-rfb.dts
+@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "mt7988-rfb";
+	compatible = "mediatek,mt7988-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "usxgmii";
+	mediatek,switch = "mt7988";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&pinctrl {
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+				 "pwm5", "pwm6", "pwm7";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+	};
+
+	mmc0_pins_default: mmc0default {
+		mux {
+			function = "flash";
+			groups =  "emmc_51";
+		};
+
+		conf-cmd-dat {
+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+			input-enable;
+		};
+
+		conf-clk {
+			pins = "EMMC_CK";
+		};
+
+		conf-dsl {
+			pins = "EMMC_DSL";
+		};
+
+		conf-rst {
+			pins = "EMMC_RSTB";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	max-frequency = <52000000>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
+@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "mt7988-rfb";
+	compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "usxgmii";
+	mediatek,switch = "mt7988";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&pinctrl {
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+				 "pwm5", "pwm6", "pwm7";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	mmc1_pins_default: mmc1default {
+		mux {
+			function = "flash";
+			groups =  "emmc_45";
+		};
+
+		conf-cmd-dat {
+			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
+			       "SPI2_CLK", "SPI2_HOLD";
+			input-enable;
+		};
+
+		conf-clk {
+			pins = "SPI2_WP";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_default>;
+	max-frequency = <52000000>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
+--- /dev/null
+++ b/board/mediatek/mt7988/MAINTAINERS
+@@ -0,0 +1,7 @@
+MT7988
+M:	Sam Shih <sam.shih@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7988
+F:	include/configs/mt7988.h
+F:	configs/mt7988_rfb_defconfig
+F:	configs/mt7988_sd_rfb_defconfig
+--- /dev/null
+++ b/board/mediatek/mt7988/Makefile
+@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= mt7988_rfb.o
+--- /dev/null
+++ b/board/mediatek/mt7988/mt7988_rfb.c
+@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
+--- /dev/null
+++ b/configs/mt7988_rfb_defconfig
+@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
+--- /dev/null
+++ b/configs/mt7988_sd_rfb_defconfig
+@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
+--- /dev/null
+++ b/include/configs/mt7988.h
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7988 SoC
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7988_H
+#define __MT7988_H
+
+#define CFG_MAX_MEM_MAPPED		0xC0000000
+
+#endif
--- a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
+++ b/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
@@ -0,0 +1,47 @@
+From 4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7 Mon Sep 17 00:00:00 2001
+Message-ID: <4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7.1690828424.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 31 Jul 2023 19:25:04 +0100
+Subject: [PATCH] ram: mediatek: include <linux/sizes.h> for SZ_* macros
+To: Ryder Lee <ryder.lee@mediatek.com>,
+    Weijie Gao <weijie.gao@mediatek.com>,
+    Chunfeng Yun <chunfeng.yun@mediatek.com>,
+    GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
+    u-boot@lists.denx.de
+
+Something between U-Boot 2023.04 and 2023.07.02 resulted in no longer
+implicitely including <linux/sizes.h> in the DDR3 RAM driver for the
+MT7929 SoC. The result is a build failure:
+drivers/ram/mediatek/ddr3-mt7629.c: In function 'mtk_ddr3_get_info':
+drivers/ram/mediatek/ddr3-mt7629.c:734:30: error: 'SZ_128M' undeclared (first use in this function)
+  734 |                 info->size = SZ_128M;
+      |                              ^~~~~~~
+drivers/ram/mediatek/ddr3-mt7629.c:734:30: note: each undeclared identifier is reported only once for each function it appears in
+drivers/ram/mediatek/ddr3-mt7629.c:737:30: error: 'SZ_256M' undeclared (first use in this function)
+  737 |                 info->size = SZ_256M;
+      |                              ^~~~~~~
+drivers/ram/mediatek/ddr3-mt7629.c:740:30: error: 'SZ_512M' undeclared (first use in this function)
+  740 |                 info->size = SZ_512M;
+      |                              ^~~~~~~
+drivers/ram/mediatek/ddr3-mt7629.c:743:30: error: 'SZ_1G' undeclared (first use in this function)
+  743 |                 info->size = SZ_1G;
+      |                              ^~~~~
+
+Include <linux/sizes.h> so SZ_* is defined.
+
+Reported-by: Tianling Shen <cnsztl@immortalwrt.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/ram/mediatek/ddr3-mt7629.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/ram/mediatek/ddr3-mt7629.c
+++ b/drivers/ram/mediatek/ddr3-mt7629.c
+@@ -14,6 +14,7 @@
+ #include <asm/io.h>
+ #include <linux/bitops.h>
+ #include <linux/delay.h>
+#include <linux/sizes.h>
+ 
+ /* EMI */
+ #define EMI_CONA			0x000
--- a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
@@ -0,0 +1,33 @@
+--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
+@@ -61,6 +61,30 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
+	psci {
+		compatible  = "arm,psci-0.2";
+		method      = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 64 KiB reserved for ramoops/pstore */
+		ramoops@42ff0000 {
+			compatible = "ramoops";
+			reg = <0 0x42ff0000 0 0x10000>;
+			record-size = <0x1000>;
+		};
+
+		/* 320 KiB reserved for ARM Trusted Firmware (BL31+BL32) */
+		secmon_reserved: secmon@43000000 {
+			reg = <0 0x43000000 0 0x50000>;
+			no-map;
+		};
+	};
+
+ 	hwver: hwver {
+ 		compatible = "mediatek,hwver", "syscon";
+ 		reg = <0 0x8000000 0 0x1000>;
--- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
+++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
@@ -1,6 +1,6 @@
 --- a/tools/Makefile
 +++ b/tools/Makefile
-@@ -115,7 +115,6 @@ dumpimage-mkimage-objs := aisimage.o \
+@@ -116,7 +116,6 @@ dumpimage-mkimage-objs := aisimage.o \
 			imximage.o \
 			imx8image.o \
 			imx8mimage.o \
--- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
+++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -1067,7 +1067,7 @@ quiet_cmd_pad_cat = CAT     $@
+@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
 
 quiet_cmd_lzma = LZMA    $@
--- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
+++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
@@ -122,7 +122,7 @@
 		   int arch, int ph_type, int bootstage_id,
 --- a/include/image.h
 +++ b/include/image.h
-@@ -1046,6 +1046,7 @@ int fit_parse_subimage(const char *spec,
+@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec,
 		ulong *addr, const char **image_name);
 
 int fit_get_subimage_count(const void *fit, int images_noffset);
--- a/package/boot/uboot-mediatek/patches/212-cmd-bootmenu-hack-restore-ansi.patch
+++ b/package/boot/uboot-mediatek/patches/212-cmd-bootmenu-hack-restore-ansi.patch
@@ -1,11 +0,0 @@
--- a/common/menu.c
-+++ b/common/menu.c
-@@ -15,7 +15,7 @@
- 
- #include "menu.h"
- 
-#define ansi 0
-+#define ansi 1
- 
- /*
-  * Internally, each item in a menu is represented by a struct menu_item.
--- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
+++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
@@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -601,6 +601,12 @@ config CMD_ENV_EXISTS
+@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS
 	  Check if a variable is defined in the environment for use in
 	  shell scripting.
 
@@ -76,7 +76,7 @@
 #if defined(CONFIG_CMD_ENV_CALLBACK)
 static int print_static_binding(const char *var_name, const char *callback_name,
 				void *priv)
-@@ -1231,6 +1285,9 @@ static struct cmd_tbl cmd_env_sub[] = {
+@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = {
 	U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
 #endif
 	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
@@ -86,7 +86,7 @@
 #if defined(CONFIG_CMD_RUN)
 	U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
 #endif
-@@ -1322,6 +1379,9 @@ static char env_help_text[] =
+@@ -1319,6 +1376,9 @@ static char env_help_text[] =
 #if defined(CONFIG_CMD_NVEDIT_EFI)
 	"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
 #endif
@@ -96,7 +96,7 @@
 #if defined(CONFIG_CMD_RUN)
 	"env run var [...] - run commands in an environment variable\n"
 #endif
-@@ -1431,6 +1491,17 @@ U_BOOT_CMD(
+@@ -1428,6 +1488,17 @@ U_BOOT_CMD(
 );
 #endif
 
--- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
+++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
@@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com>

 --- a/boot/image-fdt.c
 +++ b/boot/image-fdt.c
-@@ -636,6 +636,12 @@ int image_setup_libfdt(struct bootm_head
+@@ -637,6 +637,12 @@ int image_setup_libfdt(struct bootm_head
 					images->fit_uname_cfg,
 					strlen(images->fit_uname_cfg) + 1, 1);
 
--- a/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch
+++ b/package/boot/uboot-mediatek/patches/300-force-pylibfdt-build.patch
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -2000,26 +2000,7 @@ endif
+@@ -2006,26 +2006,7 @@ endif
 # Check dtc and pylibfdt, if DTC is provided, else build them
 PHONY += scripts_dtc
 scripts_dtc: scripts_basic
--- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
+++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
@@ -17,7 +17,7 @@
 
 #include <mtd.h>
 #include <linux/mtd/mtd.h>
-@@ -25,7 +32,22 @@ int board_init(void)
+@@ -24,7 +31,22 @@ int board_init(void)
 
 int board_late_init(void)
 {
@@ -43,7 +43,7 @@
 }
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -140,4 +140,11 @@ config MTK_BROM_HEADER_INFO
+@@ -151,4 +151,11 @@ config MTK_BROM_HEADER_INFO
 
 source "board/mediatek/mt7629/Kconfig"
 
--- a/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch
+++ b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch
@@ -0,0 +1,46 @@
+--- a/board/mediatek/mt7988/mt7988_rfb.c
+++ b/board/mediatek/mt7988/mt7988_rfb.c
+@@ -4,7 +4,43 @@
+  * Author: Sam Shih <sam.shih@mediatek.com>
+  */
+ 
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <button.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#ifndef CONFIG_RESET_BUTTON_LABEL
+#define CONFIG_RESET_BUTTON_LABEL "reset"
+#endif
+
+ int board_init(void)
+ {
+ 	return 0;
+ }
+
+int board_late_init(void)
+{
+	gd->env_valid = 1; //to load environment variable from persistent store
+	struct udevice *dev;
+
+	gd->env_valid = ENV_VALID;
+	if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {
+		puts("reset button found\n");
+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY
+		if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) {
+			button_get_state(dev);
+			mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY);
+		}
+#endif
+		if (button_get_state(dev) == BUTTON_ON) {
+			puts("button pushed, resetting environment\n");
+			gd->env_valid = ENV_INVALID;
+		}
+	}
+	env_relocate();
+	return 0;
+}
--- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
+++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
@@ -20,14 +20,14 @@
 +&snand {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&snfi_pins>;
+	quad-spi;
 	status = "okay";
 -
 -	spi-flash@0{
 -		compatible = "jedec,spi-nor";
 -		reg = <0>;
-		u-boot,dm-pre-reloc;
+-		bootph-all;
 -	};
-+	quad-spi;
 };
 
 &uart0 {
--- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
+++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
@@ -323,12 +323,12 @@
 +&eth {
 +	status = "okay";
 +	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 +	mediatek,switch = "mt7531";
 +	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 +
 +	fixed-link {
-+		speed = <1000>;
+		speed = <2500>;
 +		full-duplex;
 +	};
 +};
@@ -344,7 +344,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1285,6 +1285,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1305,6 +1305,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7622-bananapi-bpi-r64.dtb \
--- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
+++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
@@ -150,7 +150,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts
-@@ -0,0 +1,188 @@
+@@ -0,0 +1,193 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2019 MediaTek Inc.
@@ -173,6 +173,11 @@
 +		tick-timer = &timer0;
 +	};
 +
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x20000000>;
+	};
+
 +	aliases {
 +		spi0 = &snor;
 +	};
@@ -320,11 +325,11 @@
 +	pinctrl-0 = <&eth_pins>;
 +
 +	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 +	phy-handle = <&gphy>;
 +
 +	fixed-link {
-+		speed = <1000>;
+		speed = <2500>;
 +		full-duplex;
 +	};
 +
@@ -341,7 +346,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1286,6 +1286,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1306,6 +1306,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7622-linksys-e8450-ubi.dtb \
@@ -433,7 +438,7 @@
 #ifdef CONFIG_MMC
 static int initr_mmc(void)
 {
-@@ -720,6 +735,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -713,6 +728,9 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_NMBM_MTD
 	initr_nmbm,
 #endif
--- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
+++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
@@ -1,14 +1,3 @@
--- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -1293,6 +1293,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt7981-snfi-nand-rfb.dtb \
- 	mt7981-emmc-rfb.dtb \
- 	mt7981-sd-rfb.dtb \
-+	mt7986a-bpi-r3-sd.dtb \
-+	mt7986a-bpi-r3-emmc.dtb \
- 	mt7986a-rfb.dtb \
- 	mt7986b-rfb.dtb \
- 	mt7986a-sd-rfb.dtb \
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-emmc_defconfig
@@ -0,0 +1,196 @@
@@ -806,317 +795,6 @@
 +CONFIG_USE_SERVERIP=y
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
-+++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts
-@@ -0,0 +1,33 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7986a-bpi-r3-sd.dts"
-+#include <dt-bindings/gpio/gpio.h>
-+/ {
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	cap-mmc-highspeed;
-+	cap-mmc-hw-reset;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	status = "okay";
-+};
-+
--- /dev/null
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -0,0 +1,272 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/input/linux-event-codes.h>
-+#include "mt7986.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+	model = "BananaPi BPi-R3";
-+	compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+		tick-timer = &timer0;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	keys {
-+		compatible = "gpio-keys";
-+/*
-+		factory {
-+			label = "reset";
-+			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
-+		};
-+*/
-+		wps {
-+			label = "reset";
-+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+		};
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led_status_green: green {
-+			label = "green:status";
-+			gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led_status_blue: blue {
-+			label = "blue:status";
-+			gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+
-+};
-+
-+&uart0 {
-+	mediatek,force-highspeed;
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "disabled";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
-+	mediatek,switch = "mt7531";
-+	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+	};
-+};
-+
-+&pinctrl {
-+	spic_pins: spi1-pins-func-1 {
-+		mux {
-+			function = "spi";
-+			groups = "spi1_2";
-+		};
-+	};
-+
-+	uart1_pins: spi1-pins-func-3 {
-+		mux {
-+			function = "uart";
-+			groups = "uart1_2";
-+		};
-+	};
-+
-+	pwm_pins: pwm0-pins-func-1 {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_51";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <MTK_DRIVE_6mA>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+
-+		conf-dsl {
-+			pins = "EMMC_DSL";
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+	};
-+
-+	spi_flash_pins: spi0-pins-func-1 {
-+		mux {
-+			function = "flash";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+
-+		conf-pu {
-+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-+			drive-strength = <MTK_DRIVE_8mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
-+		};
-+
-+		conf-pd {
-+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-+			drive-strength = <MTK_DRIVE_8mA>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi_flash_pins>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <1>;
-+	sample_sel = <0>;
-+
-+	spi_nor@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x40000>;
-+			};
-+
-+			partition@40000 {
-+				label = "u-boot-env";
-+				reg = <0x40000 0x40000>;
-+			};
-+
-+			partition@80000 {
-+				label = "reserved";
-+				reg = <0x80000 0x80000>;
-+			};
-+
-+			partition@100000 {
-+				label = "fip";
-+				reg = <0x100000 0x80000>;
-+			};
-+
-+			partition@180000 {
-+				label = "recovery";
-+				reg = <0x180000 0xa80000>;
-+			};
-+
-+			partition@c00000 {
-+				label = "fit";
-+				reg = <0xc00000 0x1400000>;
-+			};
-+		};
-+	};
-+
-+	spi_nand@1 {
-+		compatible = "spi-nand";
-+		reg = <1>;
-+		spi-max-frequency = <52000000>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+			};
-+
-+			partition@80000 {
-+				label = "factory";
-+				reg = <0x80000 0x300000>;
-+			};
-+
-+			partition@380000 {
-+				label = "fip";
-+				reg = <0x380000 0x200000>;
-+			};
-+
-+			partition@580000 {
-+				label = "ubi";
-+				reg = <0x580000 0x7a80000>;
-+			};
-+		};
-+	};
-+};
-+
-+&watchdog {
-+	status = "disabled";
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	bus-width = <4>;
-+	max-frequency = <52000000>;
-+	cap-sd-highspeed;
-+	r_smpl = <1>;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_3p3v>;
-+	status = "okay";
-+};
-+
--- /dev/null
 +++ b/bananapi_bpi-r3_sdmmc_env
@@ -0,0 +1,80 @@
 +ipaddr=192.168.1.1
--- a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch
+++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch
@@ -182,7 +182,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/arch/arm/dts/mt7986a-xiaomi_redmi-ax6000.dts
-@@ -0,0 +1,156 @@
+@@ -0,0 +1,161 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2021 MediaTek Inc.
@@ -205,6 +205,11 @@
 +		tick-timer = &timer0;
 +	};
 +
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x20000000>;
+	};
+
 +	keys {
 +		compatible = "gpio-keys";
 +		factory {
--- a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch
+++ b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch
@@ -555,7 +555,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/arch/arm/dts/mt7986a-tplink-tl-xdr608x.dts
-@@ -0,0 +1,191 @@
+@@ -0,0 +1,196 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2021 MediaTek Inc.
@@ -578,6 +578,11 @@
 +		tick-timer = &timer0;
 +	};
 +
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x20000000>;
+	};
+
 +	keys {
 +		compatible = "gpio-keys";
 +
@@ -634,12 +639,12 @@
 +&eth {
 +	status = "okay";
 +	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 +	mediatek,switch = "mt7531";
 +	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 +
 +	fixed-link {
-+		speed = <1000>;
+		speed = <2500>;
 +		full-duplex;
 +	};
 +};
--- a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch
+++ b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch
@@ -178,7 +178,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/arch/arm/dts/mt7981_qihoo-360t7.dts
-@@ -0,0 +1,180 @@
+@@ -0,0 +1,185 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2022 MediaTek Inc.
@@ -201,6 +201,11 @@
 +		tick-timer = &timer0;
 +	};
 +
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 +	keys {
 +		compatible = "gpio-keys";
 +
@@ -246,12 +251,12 @@
 +&eth {
 +	status = "okay";
 +	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 +	mediatek,switch = "mt7531";
 +	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 +
 +	fixed-link {
-+		speed = <1000>;
+		speed = <2500>;
 +		full-duplex;
 +	};
 +};
--- a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch
+++ b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch
@@ -0,0 +1,461 @@
+--- /dev/null
+++ b/configs/mt7981_xiaomi_mi-router-wr30u_defconfig
+@@ -0,0 +1,175 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7981=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-wr30u"
+CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-wr30u_env"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-wr30u.dtb"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_BOOTDELAY=30
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_PROMPT="MT7981> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+# CONFIG_CMD_MBR is not set
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PHY_FIXED=y
+CONFIG_MTK_AHCI=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCI=y
+# CONFIG_MMC is not set
+# CONFIG_DM_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_ENV_SIZE_REDUND=0x1f000
+CONFIG_ENV_UBI_VOLUME="ubootenv"
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7981=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_HEXDUMP=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTK_SPIM=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_LMB_MAX_REGIONS=64
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
+++ b/arch/arm/dts/mt7981_xiaomi_mi-router-wr30u.dts
+@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7981.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Xiaomi Router WR30U";
+	compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer0;
+	};
+
+	config {
+		blink_led = "yellow:network";
+		system_led = "yellow:system";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		mesh {
+			label = "mesh";
+			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_9>;
+			linux,input-type = <EV_SW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue {
+			label = "blue:system";
+			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led_system_yellow {
+			label = "yellow:system";
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led_network_blue {
+			label = "blue:network";
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led_network_yellow {
+			label = "yellow:network";
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	mediatek,force-highspeed;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "disabled";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "sgmii";
+	mediatek,switch = "mt7531";
+	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&pinctrl {
+	spi_flash_pins: spi0-pins-func-1 {
+		mux {
+			function = "flash";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+	spic_pins: spi1-pins-func-1 {
+		mux {
+			function = "spi";
+			groups = "spi1_1";
+		};
+	};
+
+	uart1_pins: spi1-pins-func-3 {
+		mux {
+			function = "uart";
+			groups = "uart1_2";
+		};
+	};
+
+	pwm_pins: pwm0-pins-func-1 {
+		mux {
+			function = "pwm";
+			groups = "pwm0_1", "pwm1_0";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <2>;
+	sample_sel = <0>;
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x00 0x100000>;
+			};
+
+			partition@100000 {
+				label = "Nvram";
+				reg = <0x100000 0x40000>;
+			};
+
+			partition@140000 {
+				label = "Bdata";
+				reg = <0x140000 0x40000>;
+			};
+
+			partition@180000 {
+				label = "factory";
+				reg = <0x180000 0x200000>;
+			};
+
+			partition@380000 {
+				label = "fip";
+				reg = <0x380000 0x200000>;
+			};
+
+			partition@580000 {
+				label = "crash";
+				reg = <0x580000 0x40000>;
+			};
+
+			partition@5c0000 {
+				label = "crash_log";
+				reg = <0x5c0000 0x40000>;
+			};
+
+			partition@600000 {
+				label = "ubi";
+				reg = <0x600000 0x7000000>;
+			};
+
+			partition@7600000 {
+				label = "KF";
+				reg = <0x7600000 0x40000>;
+			};
+		};
+	};
+};
+
+&watchdog {
+	status = "disabled";
+};
+--- /dev/null
+++ b/xiaomi_mi-router-wr30u_env
+@@ -0,0 +1,56 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
+bootconf=config-1
+bootdelay=0
+bootfile=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-initramfs-recovery.itb
+bootfile_bl2=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-preloader.bin
+bootfile_fip=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-bl31-uboot.fip
+bootfile_upg=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-squashfs-sysupgrade.itb
+bootled_pwr=yellow:system
+bootled_rec=yellow:network
+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
+bootmenu_default=0
+bootmenu_delay=0
+bootmenu_title=      [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )
+bootmenu_0=Initialize environment.=run _firstboot
+bootmenu_0d=Run default boot command.=run boot_default
+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
+bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
+bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
+bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
+bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
+bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
+bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
+bootmenu_8=Reboot.=reset
+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
+boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
+boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
+boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever
+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
+part_default=production
+part_recovery=recovery
+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format
+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
+_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       [33m$ver[0m"
--- a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch
+++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch
@@ -178,7 +178,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/arch/arm/dts/mt7981_h3c_magic-nx30-pro.dts
-@@ -0,0 +1,200 @@
+@@ -0,0 +1,205 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2022 MediaTek Inc.
@@ -201,6 +201,11 @@
 +		tick-timer = &timer0;
 +	};
 +
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
 +	keys {
 +		compatible = "gpio-keys";
 +
@@ -246,12 +251,12 @@
 +&eth {
 +	status = "okay";
 +	mediatek,gmac-id = <0>;
-+	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 +	mediatek,switch = "mt7531";
 +	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 +
 +	fixed-link {
-+		speed = <1000>;
+		speed = <2500>;
 +		full-duplex;
 +	};
 +};
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -307,6 +307,24 @@ endef

 $(eval $(call KernelPackage,phy-marvell))

+define KernelPackage/phy-marvell-10g
+   SUBMENU:=$(NETWORK_DEVICES_MENU)
+   TITLE:=Marvell 10 Gigabit Ethernet PHY driver
+   KCONFIG:=CONFIG_MARVELL_10G_PHY
+   DEPENDS:=+kmod-libphy
+   FILES:=$(LINUX_DIR)/drivers/net/phy/marvell10g.ko
+   AUTOLOAD:=$(call AutoLoad,18,marvell10g)
+endef
+
+define KernelPackage/phy-marvell/description
+   Supports Marvell 10 Gigabit Ethernet PHYs:
+   * 88E2110
+   * 88E2111
+   * 88x3310
+   * 88x3340
+endef
+
+$(eval $(call KernelPackage,phy-marvell-10g))

 define KernelPackage/phy-realtek
   SUBMENU:=$(NETWORK_DEVICES_MENU)
--- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-112m-nmbm.dts
+++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-112m-nmbm.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include "mt7981b-xiaomi-mi-router-wr30u.dtsi"
+
+/ {
+	model = "Xiaomi Mi Router WR30U (112M UBI with NMBM-Enabled layout)";
+	compatible = "xiaomi,mi-router-wr30u-112m-nmbm", "mediatek,mt7981";
+};
+
+&spi_nand {
+	mediatek,nmbm;
+	mediatek,bmt-max-ratio = <1>;
+	mediatek,bmt-max-reserved-blocks = <64>;
+};
+
+&partitions {
+	partition@600000 {
+		label = "ubi";
+		reg = <0x600000 0x7000000>;
+	};
+};
--- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts
+++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include "mt7981b-xiaomi-mi-router-wr30u.dtsi"
+
+/ {
+	model = "Xiaomi Mi Router WR30U (stock layout)";
+	compatible = "xiaomi,mi-router-wr30u-stock", "mediatek,mt7981";
+};
+
+&spi_nand {
+	mediatek,nmbm;
+	mediatek,bmt-max-ratio = <1>;
+	mediatek,bmt-max-reserved-blocks = <64>;
+};
+
+&partitions {
+	// ubi_kernel is the ubi partition in stock.
+	partition@600000 {
+		label = "ubi_kernel";
+		reg = <0x600000 0x2200000>;
+	};
+
+	/* ubi is the result of squashing
+	 * consecutive stock partitions:
+	 * - ubi1
+	 * - overlay
+	 * - data
+	 */
+	partition@2800000 {
+		label = "ubi";
+		reg = <0x2800000 0x4e00000>;
+	};
+};
--- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include "mt7981b-xiaomi-mi-router-wr30u.dtsi"
+
+/ {
+	model = "Xiaomi Mi Router WR30U (OpenWrt U-Boot layout)";
+	compatible = "xiaomi,mi-router-wr30u-ubootmod", "mediatek,mt7981";
+};
+
+&partitions {
+	partition@600000 {
+		label = "ubi";
+		reg = <0x600000 0x7000000>;
+	};
+};
--- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi
+++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7981.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_system_yellow;
+		led-failsafe = &led_system_yellow;
+		led-running = &led_system_blue;
+		led-upgrade = &led_system_yellow;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		mesh {
+			label = "mesh";
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_9>;
+			linux,input-type = <EV_SW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue: system_blue {
+			label = "blue:system";
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led_system_yellow: system_yellow {
+			label = "yellow:system";
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led_network_blue {
+			label = "blue:network";
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led_network_yellow {
+			label = "yellow:network";
+			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		nvmem-cells = <&macaddr_factory_4>;
+		nvmem-cell-names = "mac-address";
+		mac-address-increment = <(-1)>;
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+};
+
+&mdio_bus {
+	switch: switch@0 {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "wan";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+		};
+
+		port@6 {
+			reg = <6>;
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+
+		partitions: partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x00 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "Nvram";
+				reg = <0x100000 0x40000>;
+			};
+
+			partition@140000 {
+				label = "Bdata";
+				reg = <0x140000 0x40000>;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x200000>;
+				read-only;
+
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_factory_4: macaddr@4 {
+					reg = <0x4 0x6>;
+				};
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x380000 0x200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "crash";
+				reg = <0x580000 0x40000>;
+				read-only;
+			};
+
+			partition@5c0000 {
+				label = "crash_log";
+				reg = <0x5c0000 0x40000>;
+				read-only;
+			};
+
+			partition@7600000 {
+				label = "KF";
+				reg = <0x7600000 0x40000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	mediatek,mtd-eeprom = <&factory 0x0>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 #include "mt7988a-rfb-spim-nand.dtsi"
 #include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/leds/common.h>

 / {
 	model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
@@ -29,173 +30,105 @@
 	pinctrl-0 = <&mdio0_pins>;
 	pinctrl-names = "default";
 	status = "okay";
+};

-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "internal";
+	phy-connection-type = "internal";
+	phy = <&int_2p5g_phy>;
+};
+
+&gmac2 {
+	status = "okay";
+	phy-mode = "usxgmii";
+	phy-connection-type = "usxgmii";
+	phy = <&phy8>;
+};
+
+&mdio_bus {
+	/* external Aquantia AQR113C */
+	phy0: ethernet-phy@0 {
 		reg = <0>;
-		phy-mode = "internal";
-
-		fixed-link {
-			speed = <10000>;
-			full-duplex;
-			pause;
-		};
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reset-gpios = <&pio 72 1>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <221000>;
 	};

-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "internal";
-		phy-connection-type = "internal";
-		phy = <&phy15>;
+	/* external Aquantia AQR113C */
+	phy8: ethernet-phy@8 {
+		reg = <8>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reset-gpios = <&pio 71 1>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <221000>;
 	};

-	gmac2: mac@2 {
-		compatible = "mediatek,eth-mac";
-		reg = <2>;
-		phy-mode = "10gbase-kr";
-		phy-connection-type = "10gbase-kr";
-		phy = <&phy8>;
+	/* external Maxlinear GPY211C */
+	phy5: ethernet-phy@5 {
+		reg = <5>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		phy-mode = "2500base-x";
 	};

-	mdio0: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* external Aquantia AQR113C */
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-			compatible = "ethernet-phy-ieee802.3-c45";
-			reset-gpios = <&pio 72 1>;
-			reset-assert-us = <100000>;
-			reset-deassert-us = <221000>;
-		};
-
-		/* external Aquantia AQR113C */
-		phy8: ethernet-phy@8 {
-			reg = <8>;
-			compatible = "ethernet-phy-ieee802.3-c45";
-			reset-gpios = <&pio 71 1>;
-			reset-assert-us = <100000>;
-			reset-deassert-us = <221000>;
-		};
-
-		/* external Maxlinear GPY211C */
-		phy5: ethernet-phy@5 {
-			reg = <5>;
-			compatible = "ethernet-phy-ieee802.3-c45";
-			phy-mode = "2500base-x";
-		};
-
-		/* external Maxlinear GPY211C */
-		phy13: ethernet-phy@13 {
-			reg = <13>;
-			compatible = "ethernet-phy-ieee802.3-c45";
-			phy-mode = "2500base-x";
-		};
-
-		/* internal 2.5G PHY */
-		phy15: ethernet-phy@15 {
-			reg = <15>;
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-			compatible = "ethernet-phy-ieee802.3-c45";
-			phy-mode = "internal";
-		};
+	/* external Maxlinear GPY211C */
+	phy13: ethernet-phy@13 {
+		reg = <13>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		phy-mode = "2500base-x";
 	};
 };

+&int_2p5g_phy {
+	pinctrl-names = "i2p5gbe-led";
+	pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
+
 &switch {
 	status = "okay";
-
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan0";
-			phy-mode = "internal";
-			phy-handle = <&gsw_phy0>;
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan1";
-			phy-mode = "internal";
-			phy-handle = <&gsw_phy1>;
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan2";
-			phy-mode = "internal";
-			phy-handle = <&gsw_phy2>;
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan3";
-			phy-mode = "internal";
-			phy-handle = <&gsw_phy3>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "internal";
-
-			fixed-link {
-				speed = <10000>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		mediatek,pio = <&pio>;
-
-		gsw_phy0: ethernet-phy@0 {
-			compatible = "ethernet-phy-id03a2.9481";
-			reg = <0>;
-			phy-mode = "internal";
-			pinctrl-names = "gbe-led";
-			pinctrl-0 = <&gbe0_led0_pins>;
-			nvmem-cells = <&phy_calibration_p0>;
-			nvmem-cell-names = "phy-cal-data";
-		};
-
-		gsw_phy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-id03a2.9481";
-			reg = <1>;
-			phy-mode = "internal";
-			pinctrl-names = "gbe-led";
-			pinctrl-0 = <&gbe1_led0_pins>;
-			nvmem-cells = <&phy_calibration_p1>;
-			nvmem-cell-names = "phy-cal-data";
-		};
-
-		gsw_phy2: ethernet-phy@2 {
-			compatible = "ethernet-phy-id03a2.9481";
-			reg = <2>;
-			phy-mode = "internal";
-			pinctrl-names = "gbe-led";
-			pinctrl-0 = <&gbe2_led0_pins>;
-			nvmem-cells = <&phy_calibration_p2>;
-			nvmem-cell-names = "phy-cal-data";
-		};
-
-		gsw_phy3: ethernet-phy@3 {
-			compatible = "ethernet-phy-id03a2.9481";
-			reg = <3>;
-			phy-mode = "internal";
-			pinctrl-names = "gbe-led";
-			pinctrl-0 = <&gbe3_led0_pins>;
-			nvmem-cells = <&phy_calibration_p3>;
-			nvmem-cell-names = "phy-cal-data";
-		};
-	};
+};
+
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
 };
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -4,12 +4,13 @@
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/reset/ti-syscon.h>
 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/ti-syscon.h>
 #include <dt-bindings/thermal/thermal.h>

 / {
@@ -144,9 +145,9 @@
 		#size-cells = <2>;
 		ranges;

-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
 		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
+			reg = <0 0x43000000 0 0x50000>;
 			no-map;
 		};
 	};
@@ -228,7 +229,7 @@
 				    "iocfg_lb_base", "iocfg_tl_base", "eint";
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 83>;
+			gpio-ranges = <&pio 0 0 84>;
 			interrupt-controller;
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
@@ -260,47 +261,131 @@
 				};
 			};

-			i2c2_pins: i2c2-pins-g0 {
+			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
+				mux {
+					function = "i2c";
+					groups = "i2c1_sfp";
+				};
+			};
+
+			i2c2_pins: i2c2-pins {
+				mux {
+					function = "i2c";
+					groups = "i2c2";
+				};
+			};
+
+			i2c2_0_pins: i2c2-pins-g0 {
+				mux {
+					function = "i2c";
+					groups = "i2c2_0";
+				};
+			};
+
+			i2c2_1_pins: i2c2-pins-g1 {
 				mux {
 					function = "i2c";
 					groups = "i2c2_1";
 				};
 			};

-			gbe0_led0_pins: gbe0-pins {
+			gbe0_led0_pins: gbe0-led0-pins {
 				mux {
 					function = "led";
 					groups = "gbe0_led0";
 				};
 			};

-			gbe1_led0_pins: gbe1-pins {
+			gbe1_led0_pins: gbe1-led0-pins {
 				mux {
 					function = "led";
 					groups = "gbe1_led0";
 				};
 			};

-			gbe2_led0_pins: gbe2-pins {
+			gbe2_led0_pins: gbe2-led0-pins {
 				mux {
 					function = "led";
 					groups = "gbe2_led0";
 				};
 			};

-			gbe3_led0_pins: gbe3-pins {
+			gbe3_led0_pins: gbe3-led0-pins {
 				mux {
 					function = "led";
 					groups = "gbe3_led0";
 				};
 			};

-			i2p5gbe_led0_pins: 2p5gbe-pins {
+			gbe0_led1_pins: gbe0-led1-pins {
+				mux {
+					function = "led";
+					groups = "gbe0_led1";
+				};
+			};
+
+			gbe1_led1_pins: gbe1-led1-pins {
+				mux {
+					function = "led";
+					groups = "gbe1_led1";
+				};
+			};
+
+			gbe2_led1_pins: gbe2-led1-pins {
+				mux {
+					function = "led";
+					groups = "gbe2_led1";
+				};
+			};
+
+			gbe3_led1_pins: gbe3-led1-pins {
+				mux {
+					function = "led";
+					groups = "gbe3_led1";
+				};
+			};
+
+			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
 				mux {
 					function = "led";
 					groups = "2p5gbe_led0";
 				};
 			};
+
+			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
+				mux {
+					function = "led";
+					groups = "2p5gbe_led1";
+				};
+			};
+
+			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
+				mux {
+					function = "flash";
+					groups = "emmc_45";
+				};
+			};
+
+			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
+				mux {
+					function = "flash";
+					groups = "emmc_51";
+				};
+			};
+
+			mmc0_pins_sdcard: mmc0-pins-sdcard {
+				mux {
+					function = "flash";
+					groups = "sdcard";
+				};
+			};
+
+			uart0_pins: uart0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart0";
+				};
+			};
 		};

 		sgmiisys0: syscon@10060000 {
@@ -380,6 +465,8 @@
 					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
 			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 						 <&topckgen CLK_TOP_UART_SEL>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
 			status = "disabled";
 		};

@@ -645,6 +732,29 @@
 			status = "disabled";
 		};

+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt7986-mmc",
+				     "mediatek,mt7981-mmc";
+			reg = <0 0x11230000 0 0x1000>,
+			      <0 0x11D60000 0 0x1000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_MSDC400>,
+				 <&infracfg CLK_INFRA_MSDC2_HCK>,
+				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
+			clock-names = "source",
+				      "hclk",
+				      "axi_cg",
+				      "ahb_cg";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		tphy: tphy@11c50000 {
 			compatible = "mediatek,mt7988",
 				     "mediatek,generic-tphy-v2";
@@ -747,6 +857,157 @@
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&ethrst 0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "lan0";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy0>;
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "lan1";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy1>;
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "lan2";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy2>;
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "lan3";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy3>;
+				};
+
+				port@6 {
+					reg = <6>;
+					ethernet = <&gmac0>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <10000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mediatek,pio = <&pio>;
+
+				gsw_phy0: ethernet-phy@0 {
+					compatible = "ethernet-phy-id03a2.9481";
+					reg = <0>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p0>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy0_led0: gsw-phy0-led0@0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy0_led1: gsw-phy0-led1@1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-id03a2.9481";
+					reg = <1>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p1>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy1_led0: gsw-phy1-led0@0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy1_led1: gsw-phy1-led1@1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-id03a2.9481";
+					reg = <2>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p2>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy2_led0: gsw-phy2-led0@0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy2_led1: gsw-phy2-led1@1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-id03a2.9481";
+					reg = <3>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p3>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy3_led0: gsw-phy3-led0@0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy3_led1: gsw-phy3-led1@1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+			};
 		};

 		ethwarp: syscon@15031000 {
@@ -843,6 +1104,40 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
+
+			gmac0: mac@0 {
+				compatible = "mediatek,eth-mac";
+				reg = <0>;
+				phy-mode = "internal";
+
+				fixed-link {
+					speed = <10000>;
+					full-duplex;
+					pause;
+				};
+			};
+
+			gmac1: mac@1 {
+				compatible = "mediatek,eth-mac";
+				reg = <1>;
+			};
+
+			gmac2: mac@2 {
+				compatible = "mediatek,eth-mac";
+				reg = <2>;
+			};
+
+			mdio_bus: mdio-bus {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* internal 2.5G PHY */
+				int_2p5g_phy: ethernet-phy@15 {
+					reg = <15>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+					phy-mode = "internal";
+				};
+			};
 		};
 	};
 };
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
 };

 static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1),
-	PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
+	PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
+	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
 	PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
+
 	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
 	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
 	PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
 	PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
+
 	PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
 	PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
+	PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
 	PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
 	PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
 	PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
 	PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
 	PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
 	PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
 	PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
 	PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
 	PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
 	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
 	PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
 	PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
 	PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
 	PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
 	PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
@@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
 	PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
 	PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
 	PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-	PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1),
+
+	PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
 	PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
 	PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
 	PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
 	PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
+	PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
+	PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
+	PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
+
 	PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
 	PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
 	PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
@@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
 	PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
 	PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
 	PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
+	PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
+	PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
+	PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
 };

 static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1),
-	PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1),
+	PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
+	PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
+	PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
 	PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1),
+	PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
+	PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
+
 	PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
 	PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
 	PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
 	PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
+
 	PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
 	PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1),
-	PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1),
-	PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
+
+	PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
+	PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
+	PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
+	PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
 	PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
 	PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
 	PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
 	PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
 	PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
 	PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
 	PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
 	PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
 	PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
 	PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
 	PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
 	PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
 	PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
 	PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
 	PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
@@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
 	PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
 	PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
 	PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-	PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1),
+
+	PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
 	PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
+	PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
+	PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
 	PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
 	PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
 	PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1),
-	PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1),
+	PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
+	PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
+	PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
+	PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
+
 	PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
 	PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
 	PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
@@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
 	PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
 	PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
 	PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-	PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1),
-	PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1),
+
+	PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
+	PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
+	PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
+	PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
 };

 static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
@@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
 	PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
 	PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
 	PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1),
+
+	PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
 	PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
+
 	PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
 	PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
 	PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
@@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
 	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
 	PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
 	PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1),
+
+	PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
+
+	PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
+
 	PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
+
 	PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
 	PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
 	PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
@@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
 };

 static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
+	PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
 	PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3),
+	PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
+	PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
+
 	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
 	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
 	PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
 	PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
+
 	PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
 	PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
+
 	PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
 	PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
+
 	PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
 	PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
 	PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
 	PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3),
+	PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
+	PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
 	PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3),
+	PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
+	PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
+	PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
 	PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
 	PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
 	PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
@@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
 	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
 	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
 	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
+	PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
 	PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
 	PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
 	PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
@@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
 	PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
 	PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3),
+	PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
+	PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
+	PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
 	PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3),
+
+	PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
+	PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
 	PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3),
+	PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
+	PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
+	PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
 	PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
 	PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
 	PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
+	PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
+	PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
+
+	PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
+	PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
+
 	PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
 	PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
 	PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
@@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
 	PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
 	PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
 	PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3),
+
+	PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
+	PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
+	PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
+	PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
 };

 static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
 	PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
 	PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
+
 	PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
 	PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
+
 	PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
 	PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
 	PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
 	PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
 	PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
 	PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
 	PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
 	PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
 	PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
 	PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
 	PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
 	PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
 	PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
 	PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
 	PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
@@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
 	PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
 	PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
 	PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-	PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
 	PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
 	PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
 	PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
+
 	PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
 	PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1),
+
+	PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
 };

 static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
 	PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
 	PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
+
 	PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
 	PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
+
 	PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
 	PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
 	PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
 	PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
 	PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
 	PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
 	PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
 	PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
 	PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
 	PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
 	PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
 	PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
 	PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
 	PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
 	PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
@@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
 	PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
 	PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
 	PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
 	PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
 	PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
 	PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
+
 	PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
 	PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1),
+
+	PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
 };

 static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1),
+	PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
+	PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
+	PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
+	PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
 	PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
+
 	PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
 	PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
+
 	PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
 	PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
+
 	PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
 	PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
 	PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
 	PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
 	PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
+	PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
+	PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
 	PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
 	PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
 	PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
 	PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
 	PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
 	PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
 	PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
 	PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
 	PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
 	PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
@@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
 	PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
 	PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
 	PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
 	PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-	PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1),
+
+	PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
 	PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
+	PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
 	PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
 	PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
+	PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
+	PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
+	PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
+	PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
+
+	PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
+
 	PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
 	PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1),
+
+	PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
+	PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
+	PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
+	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
 };

 static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
@@ -26,6 +26,11 @@ netgear,wax220)
 	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"
 	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0"
 	;;
+xiaomi,mi-router-wr30u-112m-nmbm|\
+xiaomi,mi-router-wr30u-stock|\
+xiaomi,mi-router-wr30u-ubootmod)
+	ucidef_set_led_netdev "wan" "wan" "blue:network" "wan"
+	;;
 xiaomi,redmi-router-ax6000|\
 xiaomi,redmi-router-ax6000-stock|\
 xiaomi,redmi-router-ax6000-ubootmod)
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -55,6 +55,9 @@ mediatek_setup_interfaces()
 	tplink,tl-xdr6086)
 		ucidef_set_interfaces_lan_wan "lan1 lan2" eth1
 		;;
+	xiaomi,mi-router-wr30u-112m-nmbm|\
+	xiaomi,mi-router-wr30u-stock|\
+	xiaomi,mi-router-wr30u-ubootmod|\
 	xiaomi,redmi-router-ax6000|\
 	xiaomi,redmi-router-ax6000-stock|\
 	xiaomi,redmi-router-ax6000-ubootmod)
@@ -101,6 +104,9 @@ mediatek_setup_macs()
 		wan_mac=$(macaddr_add "$lan_mac" 1)
 		label_mac=$wan_mac
 		;;
+	xiaomi,mi-router-wr30u-112m-nmbm|\
+	xiaomi,mi-router-wr30u-stock|\
+	xiaomi,mi-router-wr30u-ubootmod|\
 	xiaomi,redmi-router-ax6000|\
 	xiaomi,redmi-router-ax6000-stock|\
 	xiaomi,redmi-router-ax6000-ubootmod)
--- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
@@ -1,6 +1,6 @@
 REQUIRE_IMAGE_METADATA=1

-redmi_ax6000_initial_setup()
+xiaomi_initial_setup()
 {
 	# initialize UBI and setup uboot-env if it's running on initramfs
 	[ "$(rootfs_type)" = "tmpfs" ] || return 0
@@ -35,7 +35,16 @@ redmi_ax6000_initial_setup()
 	fw_setenv flag_boot_success 1
 	fw_setenv flag_try_sys1_failed 8
 	fw_setenv flag_try_sys2_failed 8
-	fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),30720k(ubi),30720k(ubi1),51200k(overlay)"
+
+	local board=$(board_name)
+	case "$board" in
+	xiaomi,mi-router-wr30u-stock)
+		fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),34816k(ubi),34816k(ubi1),32768k(overlay),12288k(data),256k(KF)"
+		;;
+	xiaomi,redmi-router-ax6000-stock)
+		fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),30720k(ubi),30720k(ubi1),51200k(overlay)"
+		;;
+	esac
 }

 platform_do_upgrade() {
@@ -84,10 +93,13 @@ platform_do_upgrade() {
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6086|\
 	tplink,tl-xdr6088|\
+	xiaomi,mi-router-wr30u-112m-nmbm|\
+	xiaomi,mi-router-wr30u-ubootmod|\
 	xiaomi,redmi-router-ax6000-ubootmod)
 		CI_KERNPART="fit"
 		nand_do_upgrade "$1"
 		;;
+	xiaomi,mi-router-wr30u-stock|\
 	xiaomi,redmi-router-ax6000-stock)
 		CI_KERN_UBIPART=ubi_kernel
 		CI_ROOT_UBIPART=ubi
@@ -140,8 +152,9 @@ platform_pre_upgrade() {
 	local board=$(board_name)

 	case "$board" in
+	xiaomi,mi-router-wr30u-stock|\
 	xiaomi,redmi-router-ax6000-stock)
-		redmi_ax6000_initial_setup
+		xiaomi_initial_setup
 		;;
 	esac
 }
--- a/target/linux/mediatek/filogic/config-5.15
+++ b/target/linux/mediatek/filogic/config-5.15
@@ -306,7 +306,7 @@ CONFIG_PHYLINK=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PHY_MTK_TPHY=y
 # CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
+CONFIG_PHY_MTK_XSPHY=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_MT2712 is not set
 # CONFIG_PINCTRL_MT6765 is not set
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -478,6 +478,68 @@ define Device/tplink_tl-xdr6088
 endef
 TARGET_DEVICES += tplink_tl-xdr6088

+define Device/xiaomi_mi-router-wr30u-112m-nmbm
+  DEVICE_VENDOR := Xiaomi
+  DEVICE_MODEL := Mi Router WR30U (custom U-Boot layout)
+  DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-112m-nmbm
+  DEVICE_DTS_DIR := ../dts
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+  ARTIFACTS := initramfs-factory.ubi
+  ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
+endif
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += xiaomi_mi-router-wr30u-112m-nmbm
+
+define Device/xiaomi_mi-router-wr30u-stock
+  DEVICE_VENDOR := Xiaomi
+  DEVICE_MODEL := Mi Router WR30U (stock layout)
+  DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-stock
+  DEVICE_DTS_DIR := ../dts
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+  ARTIFACTS := initramfs-factory.ubi
+  ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
+endif
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += xiaomi_mi-router-wr30u-stock
+
+define Device/xiaomi_mi-router-wr30u-ubootmod
+  DEVICE_VENDOR := Xiaomi
+  DEVICE_MODEL := Mi Router WR30U (OpenWrt U-Boot layout)
+  DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-ubootmod
+  DEVICE_DTS_DIR := ../dts
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  KERNEL_IN_UBI := 1
+  UBOOTENV_IN_UBI := 1
+  IMAGES := sysupgrade.itb
+  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  KERNEL := kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+        fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGE/sysupgrade.itb := append-kernel | \
+        fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
+  ARTIFACTS := preloader.bin bl31-uboot.fip
+  ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
+  ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot xiaomi_mi-router-wr30u
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+  ARTIFACTS += initramfs-factory.ubi
+  ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel
+endif
+endef
+TARGET_DEVICES += xiaomi_mi-router-wr30u-ubootmod
+
 define Device/xiaomi_redmi-router-ax6000
  DEVICE_VENDOR := Xiaomi
  DEVICE_MODEL := Redmi Router AX6000 (custom U-Boot layout)