OpenWrt v24.10.0: adjust config defaults

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

feeds.conf.default

@@ -1,4 +1,4 @@
-src-git packages https://git.openwrt.org/feed/packages.git^cf301cd92c4c501271cf6c1caf19eabef3ce0c09
-src-git luci https://git.openwrt.org/project/luci.git^bdf1db5fb536b155d4b035f3bbf9590782e41cf7
+src-git packages https://git.openwrt.org/feed/packages.git^201fd099b80a2931b7326ce20b0cbb824296c99f
+src-git luci https://git.openwrt.org/project/luci.git^7b0663a5557118499dc3b3d44550efc1b6fa3feb
 src-git routing https://git.openwrt.org/feed/routing.git^e87b55c6a642947ad7e24cd5054a637df63d5dbe
 src-git telephony https://git.openwrt.org/feed/telephony.git^fd605af7143165a2490681ec1752f259873b9147

include/version.mk

@@ -23,13 +23,13 @@ PKG_CONFIG_DEPENDS += \
 sanitize = $(call tolower,$(subst _,-,$(subst $(space),-,$(1))))
 
 VERSION_NUMBER:=$(call qstrip,$(CONFIG_VERSION_NUMBER))
-VERSION_NUMBER:=$(if $(VERSION_NUMBER),$(VERSION_NUMBER),24.10.0-rc7)
+VERSION_NUMBER:=$(if $(VERSION_NUMBER),$(VERSION_NUMBER),24.10.0)
 
 VERSION_CODE:=$(call qstrip,$(CONFIG_VERSION_CODE))
-VERSION_CODE:=$(if $(VERSION_CODE),$(VERSION_CODE),r28417-daef29c75d)
+VERSION_CODE:=$(if $(VERSION_CODE),$(VERSION_CODE),r28427-6df0e3d02a)
 
 VERSION_REPO:=$(call qstrip,$(CONFIG_VERSION_REPO))
-VERSION_REPO:=$(if $(VERSION_REPO),$(VERSION_REPO),https://downloads.openwrt.org/releases/24.10.0-rc7)
+VERSION_REPO:=$(if $(VERSION_REPO),$(VERSION_REPO),https://downloads.openwrt.org/releases/24.10.0)
 
 VERSION_DIST:=$(call qstrip,$(CONFIG_VERSION_DIST))
 VERSION_DIST:=$(if $(VERSION_DIST),$(VERSION_DIST),OpenWrt)

package/base-files/image-config.in

@@ -190,7 +190,7 @@ if VERSIONOPT
 	config VERSION_REPO
 		string
 		prompt "Release repository"
-		default "https://downloads.openwrt.org/releases/24.10.0-rc7"
+		default "https://downloads.openwrt.org/releases/24.10.0"
 		help
 			This is the repository address embedded in the image, it defaults
 			to the trunk snapshot repo; the url may contain the following placeholders:

target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts

@@ -68,6 +68,8 @@
 	status = "okay";
 
 	led-controller@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "sercomm,msp430-leds";
 		reg = <1>;
 		spi-max-frequency = <500000>;

target/linux/generic/pending-6.6/720-04-net-phy-realtek-introduce-rtl822x_aldps_probe.patch

@@ -1,104 +0,0 @@
-From 9155098547fb1172d4fa536f3f6bc9d42f59d08c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 22 Apr 2023 03:26:01 +0100
-Subject: [PATCH] net: phy: realtek: setup ALDPS on RTL822x
-
-Setup Link Down Power Saving Mode according the DTS property
-just like for RTL821x 1GE PHYs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/realtek/realtek_main.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/drivers/net/phy/realtek/realtek_main.c
-+++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -82,6 +82,10 @@
- 
- #define RTL822X_VND2_GANLPAR				0xa414
- 
-+#define RTL8221B_PHYCR1				0xa430
-+#define RTL8221B_PHYCR1_ALDPS_EN		BIT(2)
-+#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN	BIT(12)
-+
- #define RTL8366RB_POWER_SAVE			0x15
- #define RTL8366RB_POWER_SAVE_ON			BIT(12)
- 
-@@ -1207,6 +1211,25 @@ static int rtl8251b_c45_match_phy_device
- 	return rtlgen_is_c45_match(phydev, RTL_8251B, true);
- }
- 
-+static int rtl822x_aldps_probe(struct phy_device *phydev)
-+{
-+	struct device *dev = &phydev->mdio.dev;
-+	int val;
-+
-+	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1);
-+	if (val < 0)
-+		return val;
-+
-+	if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
-+		val |= RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
-+	else
-+		val &= ~(RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1, val);
-+
-+	return rtl822x_probe(phydev);
-+}
-+
- static int rtlgen_resume(struct phy_device *phydev)
- {
- 	int ret = genphy_resume(phydev);
-@@ -1478,6 +1501,7 @@ static struct phy_driver realtek_drvs[]
- 	}, {
- 		PHY_ID_MATCH_EXACT(0x001cc838),
- 		.name           = "RTL8226-CG 2.5Gbps PHY",
-+		.probe          = rtl822x_aldps_probe,
- 		.soft_reset     = genphy_soft_reset,
- 		.get_features   = rtl822x_get_features,
- 		.config_aneg    = rtl822x_config_aneg,
-@@ -1489,6 +1513,7 @@ static struct phy_driver realtek_drvs[]
- 	}, {
- 		PHY_ID_MATCH_EXACT(0x001cc848),
- 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
-+		.probe          = rtl822x_aldps_probe,
- 		.soft_reset     = genphy_soft_reset,
- 		.get_features   = rtl822x_get_features,
- 		.config_aneg    = rtl822x_config_aneg,
-@@ -1503,7 +1528,7 @@ static struct phy_driver realtek_drvs[]
- 		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
- 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
- 		.soft_reset     = genphy_soft_reset,
--		.probe		= rtl822x_probe,
-+		.probe          = rtl822x_aldps_probe,
- 		.get_features   = rtl822x_get_features,
- 		.config_aneg    = rtl822x_config_aneg,
- 		.config_init    = rtl822xb_config_init,
-@@ -1517,7 +1542,7 @@ static struct phy_driver realtek_drvs[]
- 		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
- 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
- 		.soft_reset     = genphy_soft_reset,
--		.probe		= rtl822x_probe,
-+		.probe          = rtl822x_aldps_probe,
- 		.config_init    = rtl822xb_config_init,
- 		.get_rate_matching = rtl822xb_get_rate_matching,
- 		.get_features   = rtl822x_c45_get_features,
-@@ -1529,7 +1554,7 @@ static struct phy_driver realtek_drvs[]
- 		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
- 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
- 		.soft_reset     = genphy_soft_reset,
--		.probe		= rtl822x_probe,
-+		.probe          = rtl822x_aldps_probe,
- 		.get_features   = rtl822x_get_features,
- 		.config_aneg    = rtl822x_config_aneg,
- 		.config_init    = rtl822xb_config_init,
-@@ -1543,7 +1568,7 @@ static struct phy_driver realtek_drvs[]
- 		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
- 		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
- 		.soft_reset     = genphy_soft_reset,
--		.probe		= rtl822x_probe,
-+		.probe          = rtl822x_aldps_probe,
- 		.config_init    = rtl822xb_config_init,
- 		.get_rate_matching = rtl822xb_get_rate_matching,
- 		.get_features   = rtl822x_c45_get_features,

target/linux/generic/pending-6.6/720-04-net-phy-realtek-setup-aldps.patch

@@ -0,0 +1,42 @@
+From 9155098547fb1172d4fa536f3f6bc9d42f59d08c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 22 Apr 2023 03:26:01 +0100
+Subject: [PATCH] net: phy: realtek: setup ALDPS on RTL822x
+
+Setup Link Down Power Saving Mode according the DTS property
+just like for RTL821x 1GE PHYs.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/realtek/realtek_main.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -82,6 +82,10 @@
+ 
+ #define RTL822X_VND2_GANLPAR				0xa414
+ 
++#define RTL8221B_PHYCR1				0xa430
++#define RTL8221B_PHYCR1_ALDPS_EN		BIT(2)
++#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN	BIT(12)
++
+ #define RTL8366RB_POWER_SAVE			0x15
+ #define RTL8366RB_POWER_SAVE_ON			BIT(12)
+ 
+@@ -889,6 +893,15 @@ static int rtl822xb_config_init(struct p
+ 	if (ret < 0)
+ 		return ret;
+ 
++	if (of_property_read_bool(phydev->mdio.dev.of_node, "realtek,aldps-enable"))
++		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
++				 RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
++	else
++		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
++				   RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
++	if (ret < 0)
++		return ret;
++
+ 	/* Disable SGMII AN */
+ 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x7588, 0x2);
+ 	if (ret < 0)

target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch

@@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1157,10 +1157,32 @@ static int rtl8226_match_phy_device(stru
+@@ -1166,10 +1166,32 @@ static int rtl8226_match_phy_device(stru
  static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
  			       bool is_c45)
  {

target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch

@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1387,6 +1387,51 @@ static irqreturn_t rtl9000a_handle_inter
+@@ -1377,6 +1377,51 @@ static irqreturn_t rtl9000a_handle_inter
  	return IRQ_HANDLED;
  }
  
@@ -64,39 +64,39 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1549,6 +1594,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1537,6 +1582,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
 +		.config_intr	= rtl8221b_config_intr,
 +		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
- 		.probe          = rtl822x_aldps_probe,
+ 		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1563,6 +1610,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1551,6 +1598,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
 +		.config_intr	= rtl8221b_config_intr,
 +		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
- 		.probe          = rtl822x_aldps_probe,
+ 		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,
-@@ -1575,6 +1624,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1563,6 +1612,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
 +		.config_intr	= rtl8221b_config_intr,
 +		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
- 		.probe          = rtl822x_aldps_probe,
+ 		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1589,6 +1640,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1577,6 +1628,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
 +		.config_intr	= rtl8221b_config_intr,
 +		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
- 		.probe          = rtl822x_aldps_probe,
+ 		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,

target/linux/generic/pending-6.6/720-07-net-phy-realtek-mark-existing-MMDs-as-present.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1034,6 +1034,9 @@ static int rtl822x_c45_get_features(stru
+@@ -1043,6 +1043,9 @@ static int rtl822x_c45_get_features(stru
  	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
  			 phydev->supported);
  

target/linux/generic/pending-6.6/720-08-net-phy-realtek-work-around-broken-serdes.patch

@@ -0,0 +1,58 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 30 Jan 2025 05:33:12 +0000
+Subject: [PATCH] net: phy: realtek: work around broken SerDes
+
+For still unknown reasons the SerDes init sequence may sometimes
+time out because a self-clearing bit never clears, indicating the
+PHY has entered an unrecoverable error state.
+
+Work-around the issue by triggering a hardware reset and retry the
+setup sequence while warning the user that this has happened.
+This is really more of a work-around than a fix, and should be
+replaced by a better actual fix in future (hopefully).
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -923,6 +923,22 @@ static int rtl822xb_config_init(struct p
+ 	return 0;
+ }
+ 
++static int rtl822xb_config_init_war(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = rtl822xb_config_init(phydev);
++
++	if (ret == -ETIMEDOUT) {
++		phydev_warn(phydev, "SerDes setup timed out, retrying\n");
++		phy_device_reset(phydev, 1);
++		phy_device_reset(phydev, 0);
++		ret = rtl822xb_config_init(phydev);
++	}
++
++	return ret;
++}
++
+ static int rtl822xb_get_rate_matching(struct phy_device *phydev,
+ 				      phy_interface_t iface)
+ {
+@@ -1605,7 +1621,7 @@ static struct phy_driver realtek_drvs[]
+ 		.handle_interrupt = rtl8221b_handle_interrupt,
+ 		.soft_reset     = genphy_soft_reset,
+ 		.probe		= rtl822x_probe,
+-		.config_init    = rtl822xb_config_init,
++		.config_init    = rtl822xb_config_init_war,
+ 		.get_rate_matching = rtl822xb_get_rate_matching,
+ 		.get_features   = rtl822x_c45_get_features,
+ 		.config_aneg    = rtl822x_c45_config_aneg,
+@@ -1635,7 +1651,7 @@ static struct phy_driver realtek_drvs[]
+ 		.handle_interrupt = rtl8221b_handle_interrupt,
+ 		.soft_reset     = genphy_soft_reset,
+ 		.probe		= rtl822x_probe,
+-		.config_init    = rtl822xb_config_init,
++		.config_init    = rtl822xb_config_init_war,
+ 		.get_rate_matching = rtl822xb_get_rate_matching,
+ 		.get_features   = rtl822x_c45_get_features,
+ 		.config_aneg    = rtl822x_c45_config_aneg,

target/linux/generic/pending-6.6/720-09-net-phy-realtek-disable-MDIO-broadcast.patch

@@ -0,0 +1,27 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 30 Jan 2025 05:38:31 +0000
+Subject: [PATCH] net: phy: realtek: disable MDIO broadcast
+
+RealTek's PHYs by default also listen on MDIO address 0 which is defined
+as broadcast address. This can lead to problems if there is an actual PHY
+(such as MT7981 built-in PHY) present at this address, as accessing that
+PHY may then confuse the RealTek PHY.
+
+Disabled listening on the MDIO broadcast address to avoid such problems.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -849,6 +849,11 @@ static int rtl822xb_config_init(struct p
+ 			     phydev->host_interfaces) ||
+ 		    phydev->interface == PHY_INTERFACE_MODE_SGMII;
+ 
++	/* disable listening on MDIO broadcast address (0) */
++	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 0xa430, BIT(13));
++	if (ret < 0)
++		return ret;
++
+ 	/* fill in possible interfaces */
+ 	__assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
+ 		     has_2500);

target/linux/ipq806x/base-files/etc/board.d/02_network

@@ -81,12 +81,12 @@ ipq806x_setup_macs()
 		linksys,ea7500-v1)
 			hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 			ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
-			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
+			ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 1)"
 		;;
 		linksys,ea8500)
 			hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 			ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
-			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
+			ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 1)"
 		;;
 		linksys,e8350-v1 |\
 		zyxel,nbg6817)
@@ -98,7 +98,7 @@ ipq806x_setup_macs()
 			hw_mac_addr=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address)
 			ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
 			hw_mac_addr=$(mtd_get_mac_ascii hwconfig HW.WAN.MAC.Address)
-			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
+			ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 1)"
 		;;
 	esac
 }

target/linux/mediatek/patches-6.6/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch

@@ -0,0 +1,33 @@
+From 4c4baed29b168e9bf39545a945a9523ea280cb44 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 1 Feb 2025 04:24:17 +0000
+Subject: [PATCH 1/2] Revert "arm64: dts: mediatek: fix t-phy unit name"
+
+This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f.
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi  | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -908,7 +908,7 @@
+ 		status = "disabled";
+ 	};
+ 
+-	sata_phy: t-phy {
++	sata_phy: t-phy@1a243000 {
+ 		compatible = "mediatek,mt7622-tphy",
+ 			     "mediatek,generic-tphy-v1";
+ 		#address-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -428,7 +428,7 @@
+ 			};
+ 		};
+ 
+-		pcie_phy: t-phy {
++		pcie_phy: t-phy@11c00000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";
+ 			ranges;

target/linux/mediatek/patches-6.6/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch

@@ -0,0 +1,33 @@
+From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 28 Jun 2024 12:55:40 +0200
+Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys
+ node
+
+Sata node reference the pciesys with the property mediatek,phy-node
+and that is used as a syscon to access the pciesys regs.
+
+Readd the syscon compatible to pciesys node to restore correct
+functionality of the SATA interface.
+
+Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
+Reported-by: Frank Wunderlich <frank-w@public-files.de>
+Co-developed-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Cc: stable@vger.kernel.org
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -798,7 +798,7 @@
+ 	};
+ 
+ 	pciesys: clock-controller@1a100800 {
+-		compatible = "mediatek,mt7622-pciesys";
++		compatible = "mediatek,mt7622-pciesys", "syscon";
+ 		reg = <0 0x1a100800 0 0x1000>;
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;

target/linux/ramips/dts/rt3883.dtsi

@@ -51,7 +51,7 @@
 			compatible = "ralink,rt2880-timer";
 			reg = <0x100 0x20>;
 
-			clocks = <&sysc 5>;
+			clocks = <&sysc 4>;
 
 			interrupt-parent = <&intc>;
 			interrupts = <1>;
@@ -61,7 +61,7 @@
 			compatible = "ralink,rt2880-wdt";
 			reg = <0x120 0x10>;
 
-			clocks = <&sysc 6>;
+			clocks = <&sysc 5>;
 
 			resets = <&sysc 8>;
 			reset-names = "wdt";
@@ -93,7 +93,7 @@
 			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0x500 0x100>;
 
-			clocks = <&sysc 7>;
+			clocks = <&sysc 6>;
 
 			resets = <&sysc 12>;
 
@@ -187,7 +187,7 @@
 			compatible = "ralink,rt2880-i2c";
 			reg = <0x900 0x100>;
 
-			clocks = <&sysc 8>;
+			clocks = <&sysc 7>;
 
 			resets = <&sysc 16>;
 			reset-names = "i2c";
@@ -205,7 +205,7 @@
 			compatible = "ralink,rt3883-i2s";
 			reg = <0xa00 0x100>;
 
-			clocks = <&sysc 9>;
+			clocks = <&sysc 8>;
 
 			resets = <&sysc 17>;
 			reset-names = "i2s";
@@ -229,7 +229,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			clocks = <&sysc 10>;
+			clocks = <&sysc 9>;
 
 			resets = <&sysc 18>;
 			reset-names = "spi";
@@ -246,7 +246,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			clocks = <&sysc 11>;
+			clocks = <&sysc 10>;
 
 			resets = <&sysc 18>;
 			reset-names = "spi";
@@ -261,7 +261,7 @@
 			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
-			clocks = <&sysc 12>;
+			clocks = <&sysc 11>;
 
 			resets = <&sysc 19>;
 
@@ -343,7 +343,7 @@
 		#size-cells = <0>;
 		reg = <0x10100000 0x10000>;
 
-		clocks = <&sysc 13>;
+		clocks = <&sysc 12>;
 
 		resets = <&sysc 21>;
 		reset-names = "fe";
@@ -463,7 +463,7 @@
 		compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
 		reg = <0x10180000 0x40000>;
 
-		clocks = <&sysc 14>;
+		clocks = <&sysc 13>;
 
 		interrupt-parent = <&cpuintc>;
 		interrupts = <6>;

target/linux/ramips/mt7620/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom

@@ -34,12 +34,12 @@ case "$FIRMWARE" in
 		wan_mac=$(jboot_config_read -m -i $(find_mtd_part "config") -o 0xE000)
 		wifi_mac=$(macaddr_add "$wan_mac" 1)
 		jboot_eeprom_extract "config" 0xE000
-		caldata_patch_data "${wifi_mac//:/}" 0x4
+		caldata_patch_mac $wifi_mac 0x4
 		;;
 	dovado,tiny-ac)
 		wifi_mac=$(mtd_get_mac_ascii u-boot-env INIC_MAC_ADDR)
 		caldata_extract "factory" 0x0 0x200
-		caldata_patch_data "${wifi_mac//:/}" 0x4
+		caldata_patch_mac $wifi_mac 0x4
 		;;
 	*)
 		caldata_die "Please define mtd-eeprom in $board DTS file!"

target/linux/ramips/patches-6.6/003-v6.14-clk-ralink-mtmips-remove-duplicated-xtal-clock-for-Ralink.patch

@@ -0,0 +1,28 @@
+From 830d8062d25581cf0beaa334486eea06834044da Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Wed, 8 Jan 2025 10:36:36 +0100
+Subject: [PATCH] clk: ralink: mtmips: remove duplicated 'xtal' clock for
+ Ralink SoC RT3883
+
+Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
+need to redefine it again in fixed clocks section. Hence, remove the duplicate
+one from there.
+
+Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/ralink/clk-mtmips.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/clk/ralink/clk-mtmips.c
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -266,7 +266,6 @@ err_clk_unreg:
+ 	}
+ 
+ static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
+-	CLK_FIXED("xtal", NULL, 40000000),
+ 	CLK_FIXED("periph", "xtal", 40000000)
+ };
+ 

target/linux/ramips/patches-6.6/100-mips-ralink-update-CPU-clock-index.patch

@@ -0,0 +1,58 @@
+From ef57412d070fe663a66a5473ffc708bd89671259 Mon Sep 17 00:00:00 2001
+From: Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Date: Sun, 2 Feb 2025 17:10:14 +0800
+Subject: [PATCH] mips: ralink: update CPU clock index
+
+Some clock indexes have been reorganized in commit d34db686a3d7
+("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs").
+Update CPU clock index to match the clock driver changes.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
+---
+ arch/mips/ralink/clk.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -19,27 +19,22 @@
+ 
+ static const char *clk_cpu(int *idx)
+ {
++	*idx = 1;
++
+ 	switch (ralink_soc) {
+ 	case RT2880_SOC:
+-		*idx = 0;
+ 		return "ralink,rt2880-sysc";
+ 	case RT3883_SOC:
+-		*idx = 0;
+ 		return "ralink,rt3883-sysc";
+ 	case RT305X_SOC_RT3050:
+-		*idx = 0;
+ 		return "ralink,rt3050-sysc";
+ 	case RT305X_SOC_RT3052:
+-		*idx = 0;
+ 		return "ralink,rt3052-sysc";
+ 	case RT305X_SOC_RT3350:
+-		*idx = 1;
+ 		return "ralink,rt3350-sysc";
+ 	case RT305X_SOC_RT3352:
+-		*idx = 1;
+ 		return "ralink,rt3352-sysc";
+ 	case RT305X_SOC_RT5350:
+-		*idx = 1;
+ 		return "ralink,rt5350-sysc";
+ 	case MT762X_SOC_MT7620A:
+ 		*idx = 2;
+@@ -48,10 +43,8 @@ static const char *clk_cpu(int *idx)
+ 		*idx = 2;
+ 		return "ralink,mt7620-sysc";
+ 	case MT762X_SOC_MT7628AN:
+-		*idx = 1;
+ 		return "ralink,mt7628-sysc";
+ 	case MT762X_SOC_MT7688:
+-		*idx = 1;
+ 		return "ralink,mt7688-sysc";
+ 	default:
+ 		*idx = -1;

target/linux/ramips/patches-6.6/809-pinctrl-mtmips-allow-mux-SDXC-pins-for-mt76x8.patch

@@ -0,0 +1,105 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 1 Jan 2025 13:30:11 +0800
+Subject: [PATCH] pinctrl: mtmips: allow mux SDXC pins for mt76x8
+
+This is a hack to supprot two types of mt76x8 SDXC pinmaps:
+
+a) Use ethernet phy pins as SDXC IO.
+
+&pinctrl {
+	ephy-digital;
+
+	sdxc_iot_mode: sdxc_iot_mode {
+		esd {
+			groups = "esd";
+			function = "iot";
+		};
+
+		sdxc {
+			groups = "sdmode";
+			function = "sdxc";
+		};
+	};
+};
+
+b) Use I2S/I2C/GPIO0/UART1 pins as SDXC IO.
+
+&pinctrl {
+	ephy-analog;
+
+	sdxc_router_mode: sdxc_router_mode {
+		groups = "esd", "gpio", "i2c", "i2s", "sdmode", "uart1";
+		function = "gpio";
+	};
+};
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt76x8.c | 24 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c
+@@ -1,10 +1,13 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ 
++#include <asm/mach-ralink/ralink_regs.h>
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
+ #include "pinctrl-mtmips.h"
+ 
++#define SYSC_REG_AGPIO_CFG		0x3c
++
+ #define MT76X8_GPIO_MODE_MASK		0x3
+ 
+ #define MT76X8_GPIO_MODE_P4LED_KN	58
+@@ -26,6 +29,7 @@
+ #define MT76X8_GPIO_MODE_I2C		20
+ #define MT76X8_GPIO_MODE_REFCLK		18
+ #define MT76X8_GPIO_MODE_PERST		16
++#define MT76X8_GPIO_MODE_ESD		15
+ #define MT76X8_GPIO_MODE_WDT		14
+ #define MT76X8_GPIO_MODE_SPI		12
+ #define MT76X8_GPIO_MODE_SDMODE		10
+@@ -74,6 +78,12 @@ static struct mtmips_pmx_func refclk_grp
+ static struct mtmips_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) };
+ static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) };
+ static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) };
++/*
++ * "esd" (Ethernet SDXC) group supports two mode:
++ * "gpio" - SDXC mux to I2S/I2C/GPIO0/UART1 pins with "gpio" mode
++ * "iot"  - SDXC mux to EPHY pins, eth p1-p4 pad must be set to "digital"
++ */
++static struct mtmips_pmx_func esd_grp[] = { FUNC("iot", 0, 47, 1) };
+ 
+ static struct mtmips_pmx_func sd_mode_grp[] = {
+ 	FUNC("jtag", 3, 22, 8),
+@@ -216,6 +226,7 @@ static struct mtmips_pmx_group mt76x8_pi
+ 	GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST),
+ 	GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT),
+ 	GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI),
++	GRP("esd", esd_grp, 1, MT76X8_GPIO_MODE_ESD),
+ 	GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK,
+ 				1, MT76X8_GPIO_MODE_SDMODE),
+ 	GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK,
+@@ -257,7 +268,18 @@ static struct mtmips_pmx_group mt76x8_pi
+ 
+ static int mt76x8_pinctrl_probe(struct platform_device *pdev)
+ {
+-	return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data);
++	int ret;
++
++	ret = mtmips_pinctrl_init(pdev, mt76x8_pinmux_data);
++	if (ret)
++		return ret;
++
++	if (of_property_present(pdev->dev.of_node, "ephy-analog"))
++		rt_sysc_m32(0xf << 17, 0, SYSC_REG_AGPIO_CFG);
++	else if (of_property_present(pdev->dev.of_node, "ephy-digital"))
++		rt_sysc_m32(0xf << 17, 0xf << 17, SYSC_REG_AGPIO_CFG);
++
++	return ret;
+ }
+ 
+ static const struct of_device_id mt76x8_pinctrl_match[] = {

target/linux/x86/image/64.mk

@@ -4,7 +4,7 @@ define Device/generic
   DEVICE_PACKAGES += \
 	kmod-amazon-ena kmod-amd-xgbe kmod-bnx2 kmod-dwmac-intel kmod-e1000e kmod-e1000 \
 	kmod-forcedeth kmod-fs-vfat kmod-igb kmod-igc kmod-ixgbe kmod-r8169 \
-	kmod-tg3
+	kmod-tg3 kmod-drm-i915
   GRUB2_VARIANT := generic
 endef
 TARGET_DEVICES += generic

target/linux/x86/image/generic.mk

@@ -3,7 +3,8 @@ define Device/generic
   DEVICE_MODEL := x86
   DEVICE_PACKAGES += kmod-3c59x kmod-8139too kmod-e100 kmod-e1000 kmod-natsemi \
 	kmod-ne2k-pci kmod-pcnet32 kmod-r8169 kmod-sis900 kmod-tg3 \
-	kmod-via-rhine kmod-via-velocity kmod-forcedeth kmod-fs-vfat
+	kmod-via-rhine kmod-via-velocity kmod-forcedeth kmod-fs-vfat \
+	kmod-drm-i915
   GRUB2_VARIANT := generic
 endef
 TARGET_DEVICES += generic

target/linux/x86/image/legacy.mk

@@ -3,7 +3,8 @@ define Device/generic
   DEVICE_MODEL := x86/legacy
   DEVICE_PACKAGES += kmod-3c59x kmod-8139too kmod-e100 kmod-e1000 \
 	kmod-natsemi kmod-ne2k-pci kmod-pcnet32 kmod-r8169 kmod-sis900 \
-	kmod-tg3 kmod-via-rhine kmod-via-velocity kmod-forcedeth
+	kmod-tg3 kmod-via-rhine kmod-via-velocity kmod-forcedeth \
+	kmod-drm-i915
   GRUB2_VARIANT := legacy
 endef
 TARGET_DEVICES += generic

version

@@ -1 +1 @@
-r28417-daef29c75d
+r28427-6df0e3d02a

version.date

@@ -1 +1 @@
-1738018409
+1738624177