rockchip: move upstreamed drivers to files-5.15
faedfa5b40f095 arm64: dts: rockchip: Add PCIe v3 nodes to rk3568 2e9bffc4f713db phy: rockchip: Support PCIe v3 Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
@@ -42,6 +42,128 @@
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reg = <0x0 0xfe190200 0x0 0x20>;
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};
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pcie30_phy_grf: syscon@fdcb8000 {
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compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfdcb8000 0x0 0x10000>;
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};
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pcie30phy: phy@fe8c0000 {
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compatible = "rockchip,rk3568-pcie3-phy";
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reg = <0x0 0xfe8c0000 0x0 0x20000>;
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#phy-cells = <0>;
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clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
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<&cru PCLK_PCIE30PHY>;
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clock-names = "refclk_m", "refclk_n", "pclk";
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resets = <&cru SRST_PCIE30PHY>;
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reset-names = "phy";
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rockchip,phy-grf = <&pcie30_phy_grf>;
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status = "disabled";
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};
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pcie3x1: pcie@fe270000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
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<0 0 0 2 &pcie3x1_intc 1>,
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<0 0 0 3 &pcie3x1_intc 2>,
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<0 0 0 4 &pcie3x1_intc 3>;
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linux,pci-domain = <1>;
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x1000 0x1000>;
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num-lanes = <1>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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reg = <0x3 0xc0400000 0x0 0x00400000>,
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<0x0 0xfe270000 0x0 0x00010000>,
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<0x3 0x7f000000 0x0 0x01000000>;
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ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
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<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE30X1_POWERUP>;
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reset-names = "pipe";
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/* bifurcation; lane1 when using 1+1 */
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status = "disabled";
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pcie3x1_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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<0 0 0 2 &pcie3x2_intc 1>,
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<0 0 0 3 &pcie3x2_intc 2>,
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<0 0 0 4 &pcie3x2_intc 3>;
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linux,pci-domain = <2>;
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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reg = <0x3 0xc0800000 0x0 0x00400000>,
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<0x0 0xfe280000 0x0 0x00010000>,
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<0x3 0xbf000000 0x0 0x01000000>;
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ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
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<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE30X2_POWERUP>;
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reset-names = "pipe";
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/* bifurcation; lane0 when using 1+1 */
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status = "disabled";
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pcie3x2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
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};
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};
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gmac0: ethernet@fe2a0000 {
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compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe2a0000 0x0 0x10000>;
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@@ -2,7 +2,7 @@
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/*
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* Rockchip PCIE3.0 phy driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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@@ -20,10 +20,11 @@
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/* Register for RK3568 */
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#define GRF_PCIE30PHY_CON1 0x4
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#define GRF_PCIE30PHY_CON4 0x10
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
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#define GRF_PCIE30PHY_STATUS0 0x80
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#define GRF_PCIE30PHY_WR_EN (0xf << 16)
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#define SRAM_INIT_DONE(reg) (reg & BIT(14))
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#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
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@@ -62,10 +63,6 @@ struct rockchip_p3phy_ops {
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int (*phy_init)(struct rockchip_p3phy_priv *priv);
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};
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static u16 phy_fw[] = {
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#include "p3phy.fw"
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};
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static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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@@ -91,13 +88,12 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
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struct phy *phy = priv->phy;
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bool bifurcation = false;
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int ret;
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int i;
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u32 reg;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
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for (i = 0; i < priv->num_lanes; i++) {
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for (int i = 0; i < priv->num_lanes; i++) {
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dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
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if (priv->lanes[i] > 1)
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bifurcation = true;
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@@ -107,44 +103,25 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
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if (bifurcation) {
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dev_info(&phy->dev, "bifurcation enabled\n");
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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(0xf << 16) | RK3568_BIFURCATION_LANE_0_1);
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GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
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BIT(15) | BIT(31));
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GRF_PCIE30PHY_DA_OCM);
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} else {
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dev_info(&phy->dev, "bifurcation disabled\n");
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dev_dbg(&phy->dev, "bifurcation disabled\n");
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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(0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1);
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GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
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reset_control_deassert(priv->p30phy);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_STATUS0,
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reg, SRAM_INIT_DONE(reg),
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0, 500);
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if (ret) {
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if (ret)
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dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
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__func__, reg);
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return ret;
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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(0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
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for (i = 0; i < 8192; i++)
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writel(phy_fw[i], priv->mmio + (i<<2));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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(0x0 << 8) | (0x3 << (8 + 16)));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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(0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
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return 0;
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return ret;
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}
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static const struct rockchip_p3phy_ops rk3568_ops = {
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@@ -156,13 +133,12 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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u32 reg = 0;
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u8 mode = 0;
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int ret;
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int i;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
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/* Set bifurcation if needed */
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for (i = 0; i < priv->num_lanes; i++) {
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for (int i = 0; i < priv->num_lanes; i++) {
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if (!priv->lanes[i])
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mode |= (BIT(i) << 3);
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@@ -201,8 +177,8 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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reg, RK3588_SRAM_INIT_DONE(reg),
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0, 500);
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if (ret)
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pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
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__func__, reg);
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dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
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reg);
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return ret;
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}
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@@ -217,7 +193,7 @@ static int rochchip_p3phy_init(struct phy *phy)
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ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
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if (ret) {
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pr_err("failed to enable PCIe bulk clks %d\n", ret);
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dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
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return ret;
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}
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@@ -271,7 +247,7 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
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priv->ops = of_device_get_match_data(&pdev->dev);
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if (!priv->ops) {
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dev_err(&pdev->dev, "no of match data provided\n");
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dev_err(dev, "no of match data provided\n");
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return -EINVAL;
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}
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@@ -1,174 +0,0 @@
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From: Frank Wunderlich <linux@fw-web.de>
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To: linux-rockchip@lists.infradead.org
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Cc: Frank Wunderlich <frank-w@public-files.de>,
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Kishon Vijay Abraham I <kishon@ti.com>,
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Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Heiko Stuebner <heiko@sntech.de>,
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Philipp Zabel <p.zabel@pengutronix.de>,
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Johan Jonker <jbx6244@gmail.com>,
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Yifeng Zhao <yifeng.zhao@rock-chips.com>,
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Peter Geis <pgwipeout@gmail.com>,
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Michael Riesch <michael.riesch@wolfvision.net>,
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Liang Chen <cl@rock-chips.com>, Simon Xue <xxm@rock-chips.com>,
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Shawn Lin <shawn.lin@rock-chips.com>,
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linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org,
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linux-kernel@vger.kernel.org
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Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
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Date: Sun, 19 Jun 2022 10:26:04 +0200 [thread overview]
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Message-ID: <20220619082605.7935-5-linux@fw-web.de> (raw)
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In-Reply-To: <20220619082605.7935-1-linux@fw-web.de>
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From: Frank Wunderlich <frank-w@public-files.de>
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Add nodes to rk356x devicetree to support PCIe v3.
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Co-developed-by: Peter Geis <pgwipeout@gmail.com>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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---
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v4:
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- update pcie3 reg/ranges
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v3:
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- fix from Peter: change bus-range and msi-map, msi-map needs
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to start from 0x0
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v2:
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- change to compatible with soc-part
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- change rockchip,bifurcation to vendor unspecific bifurcation
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
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1 file changed, 122 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -42,6 +42,128 @@
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reg = <0x0 0xfe190200 0x0 0x20>;
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};
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+ pcie30_phy_grf: syscon@fdcb8000 {
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+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
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+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
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+ };
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+
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+ pcie30phy: phy@fe8c0000 {
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+ compatible = "rockchip,rk3568-pcie3-phy";
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+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
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+ #phy-cells = <0>;
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+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
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+ <&cru PCLK_PCIE30PHY>;
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+ clock-names = "refclk_m", "refclk_n", "pclk";
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+ resets = <&cru SRST_PCIE30PHY>;
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+ reset-names = "phy";
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+ rockchip,phy-grf = <&pcie30_phy_grf>;
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+ status = "disabled";
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+ };
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+
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+ pcie3x1: pcie@fe270000 {
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+ compatible = "rockchip,rk3568-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x0 0xf>;
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+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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+ <&cru CLK_PCIE30X1_AUX_NDFT>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk", "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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+ #interrupt-cells = <1>;
|
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
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+ <0 0 0 2 &pcie3x1_intc 1>,
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+ <0 0 0 3 &pcie3x1_intc 2>,
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+ <0 0 0 4 &pcie3x1_intc 3>;
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+ linux,pci-domain = <1>;
|
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+ num-ib-windows = <6>;
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||||
+ num-ob-windows = <2>;
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+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0400000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe270000 0x0 0x00010000>,
|
||||
+ <0x3 0x7f000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane1 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x1_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie3x2: pcie@fe280000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
+ <0 0 0 2 &pcie3x2_intc 1>,
|
||||
+ <0 0 0 3 &pcie3x2_intc 2>,
|
||||
+ <0 0 0 4 &pcie3x2_intc 3>;
|
||||
+ linux,pci-domain = <2>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ num-lanes = <2>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0800000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe280000 0x0 0x00010000>,
|
||||
+ <0x3 0xbf000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane0 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x2_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gmac0: ethernet@fe2a0000 {
|
||||
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
@@ -0,0 +1,76 @@
|
||||
From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
|
||||
From: Kever Yang <kever.yang@rock-chips.com>
|
||||
Date: Mon, 11 Jul 2022 20:35:52 +0800
|
||||
Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
|
||||
|
||||
This fw fix some RX issue:
|
||||
1. connect detect error;
|
||||
2. transfer error in ssd huge data write(more than 10GB).
|
||||
|
||||
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
|
||||
---
|
||||
drivers/phy/phy-rockchip-snps-pcie3.c | 36 +-
|
||||
drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
|
||||
2 files changed, 8225 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
/* Register for RK3568 */
|
||||
#define GRF_PCIE30PHY_CON1 0x4
|
||||
+#define GRF_PCIE30PHY_CON4 0x10
|
||||
#define GRF_PCIE30PHY_CON6 0x18
|
||||
#define GRF_PCIE30PHY_CON9 0x24
|
||||
#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops {
|
||||
int (*phy_init)(struct rockchip_p3phy_priv *priv);
|
||||
};
|
||||
|
||||
+static u16 phy_fw[] = {
|
||||
+ #include "p3phy.fw"
|
||||
+};
|
||||
+
|
||||
static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
@@ -112,16 +117,35 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
|
||||
GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
}
|
||||
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
|
||||
+
|
||||
reset_control_deassert(priv->p30phy);
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
GRF_PCIE30PHY_STATUS0,
|
||||
reg, SRAM_INIT_DONE(reg),
|
||||
0, 500);
|
||||
- if (ret)
|
||||
+ if (ret) {
|
||||
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
|
||||
__func__, reg);
|
||||
- return ret;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
|
||||
+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
|
||||
+ for (int i = 0; i < 8192; i++)
|
||||
+ writel(phy_fw[i], priv->mmio + (i<<2));
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
|
||||
+ (0x0 << 8) | (0x3 << (8 + 16)));
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
|
||||
+
|
||||
+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
Reference in New Issue
Block a user